Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Alex Deucher |
| 23 | */ |
| 24 | #ifndef CIK_H |
| 25 | #define CIK_H |
| 26 | |
| 27 | #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 |
| 28 | |
| 29 | #define CIK_RB_BITMAP_WIDTH_PER_SH 2 |
| 30 | |
Alex Deucher | 1c49165 | 2013-04-09 12:45:26 -0400 | [diff] [blame] | 31 | #define VGA_HDP_CONTROL 0x328 |
| 32 | #define VGA_MEMORY_DISABLE (1 << 4) |
| 33 | |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 34 | #define DMIF_ADDR_CALC 0xC00 |
| 35 | |
Alex Deucher | 1c49165 | 2013-04-09 12:45:26 -0400 | [diff] [blame] | 36 | #define SRBM_GFX_CNTL 0xE44 |
| 37 | #define PIPEID(x) ((x) << 0) |
| 38 | #define MEID(x) ((x) << 2) |
| 39 | #define VMID(x) ((x) << 4) |
| 40 | #define QUEUEID(x) ((x) << 8) |
| 41 | |
Alex Deucher | 6f2043c | 2013-04-09 12:43:41 -0400 | [diff] [blame] | 42 | #define SRBM_STATUS2 0xE4C |
| 43 | #define SRBM_STATUS 0xE50 |
| 44 | |
Alex Deucher | 1c49165 | 2013-04-09 12:45:26 -0400 | [diff] [blame] | 45 | #define VM_L2_CNTL 0x1400 |
| 46 | #define ENABLE_L2_CACHE (1 << 0) |
| 47 | #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) |
| 48 | #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) |
| 49 | #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) |
| 50 | #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) |
| 51 | #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) |
| 52 | #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) |
| 53 | #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) |
| 54 | #define VM_L2_CNTL2 0x1404 |
| 55 | #define INVALIDATE_ALL_L1_TLBS (1 << 0) |
| 56 | #define INVALIDATE_L2_CACHE (1 << 1) |
| 57 | #define INVALIDATE_CACHE_MODE(x) ((x) << 26) |
| 58 | #define INVALIDATE_PTE_AND_PDE_CACHES 0 |
| 59 | #define INVALIDATE_ONLY_PTE_CACHES 1 |
| 60 | #define INVALIDATE_ONLY_PDE_CACHES 2 |
| 61 | #define VM_L2_CNTL3 0x1408 |
| 62 | #define BANK_SELECT(x) ((x) << 0) |
| 63 | #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) |
| 64 | #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) |
| 65 | #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) |
| 66 | #define VM_L2_STATUS 0x140C |
| 67 | #define L2_BUSY (1 << 0) |
| 68 | #define VM_CONTEXT0_CNTL 0x1410 |
| 69 | #define ENABLE_CONTEXT (1 << 0) |
| 70 | #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) |
Alex Deucher | a00024b | 2012-09-18 16:06:01 -0400 | [diff] [blame] | 71 | #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) |
Alex Deucher | 1c49165 | 2013-04-09 12:45:26 -0400 | [diff] [blame] | 72 | #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) |
Alex Deucher | a00024b | 2012-09-18 16:06:01 -0400 | [diff] [blame] | 73 | #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) |
| 74 | #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) |
| 75 | #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) |
| 76 | #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) |
| 77 | #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) |
| 78 | #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) |
| 79 | #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) |
| 80 | #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) |
| 81 | #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) |
| 82 | #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) |
Alex Deucher | 1c49165 | 2013-04-09 12:45:26 -0400 | [diff] [blame] | 83 | #define VM_CONTEXT1_CNTL 0x1414 |
| 84 | #define VM_CONTEXT0_CNTL2 0x1430 |
| 85 | #define VM_CONTEXT1_CNTL2 0x1434 |
| 86 | #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 |
| 87 | #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c |
| 88 | #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 |
| 89 | #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 |
| 90 | #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 |
| 91 | #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c |
| 92 | #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 |
| 93 | #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 |
| 94 | |
| 95 | #define VM_INVALIDATE_REQUEST 0x1478 |
| 96 | #define VM_INVALIDATE_RESPONSE 0x147c |
| 97 | |
| 98 | #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 |
| 99 | #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c |
| 100 | |
| 101 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c |
| 102 | #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 |
| 103 | #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 |
| 104 | #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 |
| 105 | #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c |
| 106 | #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 |
| 107 | #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 |
| 108 | #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 |
| 109 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c |
| 110 | #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 |
| 111 | |
| 112 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C |
| 113 | #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 |
| 114 | |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 115 | #define MC_SHARED_CHMAP 0x2004 |
| 116 | #define NOOFCHAN_SHIFT 12 |
| 117 | #define NOOFCHAN_MASK 0x0000f000 |
| 118 | #define MC_SHARED_CHREMAP 0x2008 |
| 119 | |
Alex Deucher | 1c49165 | 2013-04-09 12:45:26 -0400 | [diff] [blame] | 120 | #define CHUB_CONTROL 0x1864 |
| 121 | #define BYPASS_VM (1 << 0) |
| 122 | |
| 123 | #define MC_VM_FB_LOCATION 0x2024 |
| 124 | #define MC_VM_AGP_TOP 0x2028 |
| 125 | #define MC_VM_AGP_BOT 0x202C |
| 126 | #define MC_VM_AGP_BASE 0x2030 |
| 127 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 |
| 128 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 |
| 129 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C |
| 130 | |
| 131 | #define MC_VM_MX_L1_TLB_CNTL 0x2064 |
| 132 | #define ENABLE_L1_TLB (1 << 0) |
| 133 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) |
| 134 | #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) |
| 135 | #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) |
| 136 | #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) |
| 137 | #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) |
| 138 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) |
| 139 | #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) |
| 140 | #define MC_VM_FB_OFFSET 0x2068 |
| 141 | |
Alex Deucher | bc8273f | 2012-06-29 19:44:04 -0400 | [diff] [blame] | 142 | #define MC_SHARED_BLACKOUT_CNTL 0x20ac |
| 143 | |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 144 | #define MC_ARB_RAMCFG 0x2760 |
| 145 | #define NOOFBANK_SHIFT 0 |
| 146 | #define NOOFBANK_MASK 0x00000003 |
| 147 | #define NOOFRANK_SHIFT 2 |
| 148 | #define NOOFRANK_MASK 0x00000004 |
| 149 | #define NOOFROWS_SHIFT 3 |
| 150 | #define NOOFROWS_MASK 0x00000038 |
| 151 | #define NOOFCOLS_SHIFT 6 |
| 152 | #define NOOFCOLS_MASK 0x000000C0 |
| 153 | #define CHANSIZE_SHIFT 8 |
| 154 | #define CHANSIZE_MASK 0x00000100 |
| 155 | #define NOOFGROUPS_SHIFT 12 |
| 156 | #define NOOFGROUPS_MASK 0x00001000 |
| 157 | |
Alex Deucher | bc8273f | 2012-06-29 19:44:04 -0400 | [diff] [blame] | 158 | #define MC_SEQ_SUP_CNTL 0x28c8 |
| 159 | #define RUN_MASK (1 << 0) |
| 160 | #define MC_SEQ_SUP_PGM 0x28cc |
| 161 | |
| 162 | #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 |
| 163 | #define TRAIN_DONE_D0 (1 << 30) |
| 164 | #define TRAIN_DONE_D1 (1 << 31) |
| 165 | |
| 166 | #define MC_IO_PAD_CNTL_D0 0x29d0 |
| 167 | #define MEM_FALL_OUT_CMD (1 << 8) |
| 168 | |
| 169 | #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 |
| 170 | #define MC_SEQ_IO_DEBUG_DATA 0x2a48 |
| 171 | |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 172 | #define HDP_HOST_PATH_CNTL 0x2C00 |
| 173 | #define HDP_NONSURFACE_BASE 0x2C04 |
| 174 | #define HDP_NONSURFACE_INFO 0x2C08 |
| 175 | #define HDP_NONSURFACE_SIZE 0x2C0C |
| 176 | |
| 177 | #define HDP_ADDR_CONFIG 0x2F48 |
| 178 | #define HDP_MISC_CNTL 0x2F4C |
| 179 | #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) |
| 180 | |
Alex Deucher | 1c49165 | 2013-04-09 12:45:26 -0400 | [diff] [blame] | 181 | #define CONFIG_MEMSIZE 0x5428 |
| 182 | |
| 183 | #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 |
| 184 | |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 185 | #define BIF_FB_EN 0x5490 |
| 186 | #define FB_READ_EN (1 << 0) |
| 187 | #define FB_WRITE_EN (1 << 1) |
| 188 | |
Alex Deucher | 1c49165 | 2013-04-09 12:45:26 -0400 | [diff] [blame] | 189 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
| 190 | |
Alex Deucher | 2cae3bc | 2012-07-05 11:45:40 -0400 | [diff] [blame^] | 191 | #define GPU_HDP_FLUSH_REQ 0x54DC |
| 192 | #define GPU_HDP_FLUSH_DONE 0x54E0 |
| 193 | #define CP0 (1 << 0) |
| 194 | #define CP1 (1 << 1) |
| 195 | #define CP2 (1 << 2) |
| 196 | #define CP3 (1 << 3) |
| 197 | #define CP4 (1 << 4) |
| 198 | #define CP5 (1 << 5) |
| 199 | #define CP6 (1 << 6) |
| 200 | #define CP7 (1 << 7) |
| 201 | #define CP8 (1 << 8) |
| 202 | #define CP9 (1 << 9) |
| 203 | #define SDMA0 (1 << 10) |
| 204 | #define SDMA1 (1 << 11) |
| 205 | |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 206 | #define GRBM_CNTL 0x8000 |
| 207 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) |
| 208 | |
Alex Deucher | 6f2043c | 2013-04-09 12:43:41 -0400 | [diff] [blame] | 209 | #define GRBM_STATUS2 0x8008 |
| 210 | #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F |
| 211 | #define ME0PIPE1_CF_RQ_PENDING (1 << 4) |
| 212 | #define ME0PIPE1_PF_RQ_PENDING (1 << 5) |
| 213 | #define ME1PIPE0_RQ_PENDING (1 << 6) |
| 214 | #define ME1PIPE1_RQ_PENDING (1 << 7) |
| 215 | #define ME1PIPE2_RQ_PENDING (1 << 8) |
| 216 | #define ME1PIPE3_RQ_PENDING (1 << 9) |
| 217 | #define ME2PIPE0_RQ_PENDING (1 << 10) |
| 218 | #define ME2PIPE1_RQ_PENDING (1 << 11) |
| 219 | #define ME2PIPE2_RQ_PENDING (1 << 12) |
| 220 | #define ME2PIPE3_RQ_PENDING (1 << 13) |
| 221 | #define RLC_RQ_PENDING (1 << 14) |
| 222 | #define RLC_BUSY (1 << 24) |
| 223 | #define TC_BUSY (1 << 25) |
| 224 | #define CPF_BUSY (1 << 28) |
| 225 | #define CPC_BUSY (1 << 29) |
| 226 | #define CPG_BUSY (1 << 30) |
| 227 | |
| 228 | #define GRBM_STATUS 0x8010 |
| 229 | #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F |
| 230 | #define SRBM_RQ_PENDING (1 << 5) |
| 231 | #define ME0PIPE0_CF_RQ_PENDING (1 << 7) |
| 232 | #define ME0PIPE0_PF_RQ_PENDING (1 << 8) |
| 233 | #define GDS_DMA_RQ_PENDING (1 << 9) |
| 234 | #define DB_CLEAN (1 << 12) |
| 235 | #define CB_CLEAN (1 << 13) |
| 236 | #define TA_BUSY (1 << 14) |
| 237 | #define GDS_BUSY (1 << 15) |
| 238 | #define WD_BUSY_NO_DMA (1 << 16) |
| 239 | #define VGT_BUSY (1 << 17) |
| 240 | #define IA_BUSY_NO_DMA (1 << 18) |
| 241 | #define IA_BUSY (1 << 19) |
| 242 | #define SX_BUSY (1 << 20) |
| 243 | #define WD_BUSY (1 << 21) |
| 244 | #define SPI_BUSY (1 << 22) |
| 245 | #define BCI_BUSY (1 << 23) |
| 246 | #define SC_BUSY (1 << 24) |
| 247 | #define PA_BUSY (1 << 25) |
| 248 | #define DB_BUSY (1 << 26) |
| 249 | #define CP_COHERENCY_BUSY (1 << 28) |
| 250 | #define CP_BUSY (1 << 29) |
| 251 | #define CB_BUSY (1 << 30) |
| 252 | #define GUI_ACTIVE (1 << 31) |
| 253 | #define GRBM_STATUS_SE0 0x8014 |
| 254 | #define GRBM_STATUS_SE1 0x8018 |
| 255 | #define GRBM_STATUS_SE2 0x8038 |
| 256 | #define GRBM_STATUS_SE3 0x803C |
| 257 | #define SE_DB_CLEAN (1 << 1) |
| 258 | #define SE_CB_CLEAN (1 << 2) |
| 259 | #define SE_BCI_BUSY (1 << 22) |
| 260 | #define SE_VGT_BUSY (1 << 23) |
| 261 | #define SE_PA_BUSY (1 << 24) |
| 262 | #define SE_TA_BUSY (1 << 25) |
| 263 | #define SE_SX_BUSY (1 << 26) |
| 264 | #define SE_SPI_BUSY (1 << 27) |
| 265 | #define SE_SC_BUSY (1 << 29) |
| 266 | #define SE_DB_BUSY (1 << 30) |
| 267 | #define SE_CB_BUSY (1 << 31) |
| 268 | |
| 269 | #define GRBM_SOFT_RESET 0x8020 |
| 270 | #define SOFT_RESET_CP (1 << 0) /* All CP blocks */ |
| 271 | #define SOFT_RESET_RLC (1 << 2) /* RLC */ |
| 272 | #define SOFT_RESET_GFX (1 << 16) /* GFX */ |
| 273 | #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */ |
| 274 | #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */ |
| 275 | #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */ |
| 276 | |
| 277 | #define CP_MEC_CNTL 0x8234 |
| 278 | #define MEC_ME2_HALT (1 << 28) |
| 279 | #define MEC_ME1_HALT (1 << 30) |
| 280 | |
Alex Deucher | 841cf44 | 2012-12-18 21:47:44 -0500 | [diff] [blame] | 281 | #define CP_MEC_CNTL 0x8234 |
| 282 | #define MEC_ME2_HALT (1 << 28) |
| 283 | #define MEC_ME1_HALT (1 << 30) |
| 284 | |
Alex Deucher | 6f2043c | 2013-04-09 12:43:41 -0400 | [diff] [blame] | 285 | #define CP_ME_CNTL 0x86D8 |
| 286 | #define CP_CE_HALT (1 << 24) |
| 287 | #define CP_PFP_HALT (1 << 26) |
| 288 | #define CP_ME_HALT (1 << 28) |
| 289 | |
Alex Deucher | 841cf44 | 2012-12-18 21:47:44 -0500 | [diff] [blame] | 290 | #define CP_RB0_RPTR 0x8700 |
| 291 | #define CP_RB_WPTR_DELAY 0x8704 |
| 292 | |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 293 | #define CP_MEQ_THRESHOLDS 0x8764 |
| 294 | #define MEQ1_START(x) ((x) << 0) |
| 295 | #define MEQ2_START(x) ((x) << 8) |
| 296 | |
| 297 | #define VGT_VTX_VECT_EJECT_REG 0x88B0 |
| 298 | |
| 299 | #define VGT_CACHE_INVALIDATION 0x88C4 |
| 300 | #define CACHE_INVALIDATION(x) ((x) << 0) |
| 301 | #define VC_ONLY 0 |
| 302 | #define TC_ONLY 1 |
| 303 | #define VC_AND_TC 2 |
| 304 | #define AUTO_INVLD_EN(x) ((x) << 6) |
| 305 | #define NO_AUTO 0 |
| 306 | #define ES_AUTO 1 |
| 307 | #define GS_AUTO 2 |
| 308 | #define ES_AND_GS_AUTO 3 |
| 309 | |
| 310 | #define VGT_GS_VERTEX_REUSE 0x88D4 |
| 311 | |
| 312 | #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc |
| 313 | #define INACTIVE_CUS_MASK 0xFFFF0000 |
| 314 | #define INACTIVE_CUS_SHIFT 16 |
| 315 | #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 |
| 316 | |
| 317 | #define PA_CL_ENHANCE 0x8A14 |
| 318 | #define CLIP_VTX_REORDER_ENA (1 << 0) |
| 319 | #define NUM_CLIP_SEQ(x) ((x) << 1) |
| 320 | |
| 321 | #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 |
| 322 | #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) |
| 323 | #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) |
| 324 | |
| 325 | #define PA_SC_FIFO_SIZE 0x8BCC |
| 326 | #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) |
| 327 | #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) |
| 328 | #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) |
| 329 | #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) |
| 330 | |
| 331 | #define PA_SC_ENHANCE 0x8BF0 |
| 332 | #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0) |
| 333 | #define DISABLE_PA_SC_GUIDANCE (1 << 13) |
| 334 | |
| 335 | #define SQ_CONFIG 0x8C00 |
| 336 | |
Alex Deucher | 1c49165 | 2013-04-09 12:45:26 -0400 | [diff] [blame] | 337 | #define SH_MEM_BASES 0x8C28 |
| 338 | /* if PTR32, these are the bases for scratch and lds */ |
| 339 | #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ |
| 340 | #define SHARED_BASE(x) ((x) << 16) /* LDS */ |
| 341 | #define SH_MEM_APE1_BASE 0x8C2C |
| 342 | /* if PTR32, this is the base location of GPUVM */ |
| 343 | #define SH_MEM_APE1_LIMIT 0x8C30 |
| 344 | /* if PTR32, this is the upper limit of GPUVM */ |
| 345 | #define SH_MEM_CONFIG 0x8C34 |
| 346 | #define PTR32 (1 << 0) |
| 347 | #define ALIGNMENT_MODE(x) ((x) << 2) |
| 348 | #define SH_MEM_ALIGNMENT_MODE_DWORD 0 |
| 349 | #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 |
| 350 | #define SH_MEM_ALIGNMENT_MODE_STRICT 2 |
| 351 | #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 |
| 352 | #define DEFAULT_MTYPE(x) ((x) << 4) |
| 353 | #define APE1_MTYPE(x) ((x) << 7) |
| 354 | |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 355 | #define SX_DEBUG_1 0x9060 |
| 356 | |
| 357 | #define SPI_CONFIG_CNTL 0x9100 |
| 358 | |
| 359 | #define SPI_CONFIG_CNTL_1 0x913C |
| 360 | #define VTX_DONE_DELAY(x) ((x) << 0) |
| 361 | #define INTERP_ONE_PRIM_PER_ROW (1 << 4) |
| 362 | |
| 363 | #define TA_CNTL_AUX 0x9508 |
| 364 | |
| 365 | #define DB_DEBUG 0x9830 |
| 366 | #define DB_DEBUG2 0x9834 |
| 367 | #define DB_DEBUG3 0x9838 |
| 368 | |
| 369 | #define CC_RB_BACKEND_DISABLE 0x98F4 |
| 370 | #define BACKEND_DISABLE(x) ((x) << 16) |
| 371 | #define GB_ADDR_CONFIG 0x98F8 |
| 372 | #define NUM_PIPES(x) ((x) << 0) |
| 373 | #define NUM_PIPES_MASK 0x00000007 |
| 374 | #define NUM_PIPES_SHIFT 0 |
| 375 | #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) |
| 376 | #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 |
| 377 | #define PIPE_INTERLEAVE_SIZE_SHIFT 4 |
| 378 | #define NUM_SHADER_ENGINES(x) ((x) << 12) |
| 379 | #define NUM_SHADER_ENGINES_MASK 0x00003000 |
| 380 | #define NUM_SHADER_ENGINES_SHIFT 12 |
| 381 | #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) |
| 382 | #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 |
| 383 | #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 |
| 384 | #define ROW_SIZE(x) ((x) << 28) |
| 385 | #define ROW_SIZE_MASK 0x30000000 |
| 386 | #define ROW_SIZE_SHIFT 28 |
| 387 | |
| 388 | #define GB_TILE_MODE0 0x9910 |
| 389 | # define ARRAY_MODE(x) ((x) << 2) |
| 390 | # define ARRAY_LINEAR_GENERAL 0 |
| 391 | # define ARRAY_LINEAR_ALIGNED 1 |
| 392 | # define ARRAY_1D_TILED_THIN1 2 |
| 393 | # define ARRAY_2D_TILED_THIN1 4 |
| 394 | # define ARRAY_PRT_TILED_THIN1 5 |
| 395 | # define ARRAY_PRT_2D_TILED_THIN1 6 |
| 396 | # define PIPE_CONFIG(x) ((x) << 6) |
| 397 | # define ADDR_SURF_P2 0 |
| 398 | # define ADDR_SURF_P4_8x16 4 |
| 399 | # define ADDR_SURF_P4_16x16 5 |
| 400 | # define ADDR_SURF_P4_16x32 6 |
| 401 | # define ADDR_SURF_P4_32x32 7 |
| 402 | # define ADDR_SURF_P8_16x16_8x16 8 |
| 403 | # define ADDR_SURF_P8_16x32_8x16 9 |
| 404 | # define ADDR_SURF_P8_32x32_8x16 10 |
| 405 | # define ADDR_SURF_P8_16x32_16x16 11 |
| 406 | # define ADDR_SURF_P8_32x32_16x16 12 |
| 407 | # define ADDR_SURF_P8_32x32_16x32 13 |
| 408 | # define ADDR_SURF_P8_32x64_32x32 14 |
| 409 | # define TILE_SPLIT(x) ((x) << 11) |
| 410 | # define ADDR_SURF_TILE_SPLIT_64B 0 |
| 411 | # define ADDR_SURF_TILE_SPLIT_128B 1 |
| 412 | # define ADDR_SURF_TILE_SPLIT_256B 2 |
| 413 | # define ADDR_SURF_TILE_SPLIT_512B 3 |
| 414 | # define ADDR_SURF_TILE_SPLIT_1KB 4 |
| 415 | # define ADDR_SURF_TILE_SPLIT_2KB 5 |
| 416 | # define ADDR_SURF_TILE_SPLIT_4KB 6 |
| 417 | # define MICRO_TILE_MODE_NEW(x) ((x) << 22) |
| 418 | # define ADDR_SURF_DISPLAY_MICRO_TILING 0 |
| 419 | # define ADDR_SURF_THIN_MICRO_TILING 1 |
| 420 | # define ADDR_SURF_DEPTH_MICRO_TILING 2 |
| 421 | # define ADDR_SURF_ROTATED_MICRO_TILING 3 |
| 422 | # define SAMPLE_SPLIT(x) ((x) << 25) |
| 423 | # define ADDR_SURF_SAMPLE_SPLIT_1 0 |
| 424 | # define ADDR_SURF_SAMPLE_SPLIT_2 1 |
| 425 | # define ADDR_SURF_SAMPLE_SPLIT_4 2 |
| 426 | # define ADDR_SURF_SAMPLE_SPLIT_8 3 |
| 427 | |
| 428 | #define GB_MACROTILE_MODE0 0x9990 |
| 429 | # define BANK_WIDTH(x) ((x) << 0) |
| 430 | # define ADDR_SURF_BANK_WIDTH_1 0 |
| 431 | # define ADDR_SURF_BANK_WIDTH_2 1 |
| 432 | # define ADDR_SURF_BANK_WIDTH_4 2 |
| 433 | # define ADDR_SURF_BANK_WIDTH_8 3 |
| 434 | # define BANK_HEIGHT(x) ((x) << 2) |
| 435 | # define ADDR_SURF_BANK_HEIGHT_1 0 |
| 436 | # define ADDR_SURF_BANK_HEIGHT_2 1 |
| 437 | # define ADDR_SURF_BANK_HEIGHT_4 2 |
| 438 | # define ADDR_SURF_BANK_HEIGHT_8 3 |
| 439 | # define MACRO_TILE_ASPECT(x) ((x) << 4) |
| 440 | # define ADDR_SURF_MACRO_ASPECT_1 0 |
| 441 | # define ADDR_SURF_MACRO_ASPECT_2 1 |
| 442 | # define ADDR_SURF_MACRO_ASPECT_4 2 |
| 443 | # define ADDR_SURF_MACRO_ASPECT_8 3 |
| 444 | # define NUM_BANKS(x) ((x) << 6) |
| 445 | # define ADDR_SURF_2_BANK 0 |
| 446 | # define ADDR_SURF_4_BANK 1 |
| 447 | # define ADDR_SURF_8_BANK 2 |
| 448 | # define ADDR_SURF_16_BANK 3 |
| 449 | |
| 450 | #define CB_HW_CONTROL 0x9A10 |
| 451 | |
| 452 | #define GC_USER_RB_BACKEND_DISABLE 0x9B7C |
| 453 | #define BACKEND_DISABLE_MASK 0x00FF0000 |
| 454 | #define BACKEND_DISABLE_SHIFT 16 |
| 455 | |
| 456 | #define TCP_CHAN_STEER_LO 0xac0c |
| 457 | #define TCP_CHAN_STEER_HI 0xac10 |
| 458 | |
Alex Deucher | 1c49165 | 2013-04-09 12:45:26 -0400 | [diff] [blame] | 459 | #define TC_CFG_L1_LOAD_POLICY0 0xAC68 |
| 460 | #define TC_CFG_L1_LOAD_POLICY1 0xAC6C |
| 461 | #define TC_CFG_L1_STORE_POLICY 0xAC70 |
| 462 | #define TC_CFG_L2_LOAD_POLICY0 0xAC74 |
| 463 | #define TC_CFG_L2_LOAD_POLICY1 0xAC78 |
| 464 | #define TC_CFG_L2_STORE_POLICY0 0xAC7C |
| 465 | #define TC_CFG_L2_STORE_POLICY1 0xAC80 |
| 466 | #define TC_CFG_L2_ATOMIC_POLICY 0xAC84 |
| 467 | #define TC_CFG_L1_VOLATILE 0xAC88 |
| 468 | #define TC_CFG_L2_VOLATILE 0xAC8C |
| 469 | |
Alex Deucher | 841cf44 | 2012-12-18 21:47:44 -0500 | [diff] [blame] | 470 | #define CP_RB0_BASE 0xC100 |
| 471 | #define CP_RB0_CNTL 0xC104 |
| 472 | #define RB_BUFSZ(x) ((x) << 0) |
| 473 | #define RB_BLKSZ(x) ((x) << 8) |
| 474 | #define BUF_SWAP_32BIT (2 << 16) |
| 475 | #define RB_NO_UPDATE (1 << 27) |
| 476 | #define RB_RPTR_WR_ENA (1 << 31) |
| 477 | |
| 478 | #define CP_RB0_RPTR_ADDR 0xC10C |
| 479 | #define RB_RPTR_SWAP_32BIT (2 << 0) |
| 480 | #define CP_RB0_RPTR_ADDR_HI 0xC110 |
| 481 | #define CP_RB0_WPTR 0xC114 |
| 482 | |
| 483 | #define CP_DEVICE_ID 0xC12C |
| 484 | #define CP_ENDIAN_SWAP 0xC140 |
| 485 | #define CP_RB_VMID 0xC144 |
| 486 | |
| 487 | #define CP_PFP_UCODE_ADDR 0xC150 |
| 488 | #define CP_PFP_UCODE_DATA 0xC154 |
| 489 | #define CP_ME_RAM_RADDR 0xC158 |
| 490 | #define CP_ME_RAM_WADDR 0xC15C |
| 491 | #define CP_ME_RAM_DATA 0xC160 |
| 492 | |
| 493 | #define CP_CE_UCODE_ADDR 0xC168 |
| 494 | #define CP_CE_UCODE_DATA 0xC16C |
| 495 | #define CP_MEC_ME1_UCODE_ADDR 0xC170 |
| 496 | #define CP_MEC_ME1_UCODE_DATA 0xC174 |
| 497 | #define CP_MEC_ME2_UCODE_ADDR 0xC178 |
| 498 | #define CP_MEC_ME2_UCODE_DATA 0xC17C |
| 499 | |
| 500 | #define CP_MAX_CONTEXT 0xC2B8 |
| 501 | |
| 502 | #define CP_RB0_BASE_HI 0xC2C4 |
| 503 | |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 504 | #define PA_SC_RASTER_CONFIG 0x28350 |
| 505 | # define RASTER_CONFIG_RB_MAP_0 0 |
| 506 | # define RASTER_CONFIG_RB_MAP_1 1 |
| 507 | # define RASTER_CONFIG_RB_MAP_2 2 |
| 508 | # define RASTER_CONFIG_RB_MAP_3 3 |
| 509 | |
Alex Deucher | 2cae3bc | 2012-07-05 11:45:40 -0400 | [diff] [blame^] | 510 | #define VGT_EVENT_INITIATOR 0x28a90 |
| 511 | # define SAMPLE_STREAMOUTSTATS1 (1 << 0) |
| 512 | # define SAMPLE_STREAMOUTSTATS2 (2 << 0) |
| 513 | # define SAMPLE_STREAMOUTSTATS3 (3 << 0) |
| 514 | # define CACHE_FLUSH_TS (4 << 0) |
| 515 | # define CACHE_FLUSH (6 << 0) |
| 516 | # define CS_PARTIAL_FLUSH (7 << 0) |
| 517 | # define VGT_STREAMOUT_RESET (10 << 0) |
| 518 | # define END_OF_PIPE_INCR_DE (11 << 0) |
| 519 | # define END_OF_PIPE_IB_END (12 << 0) |
| 520 | # define RST_PIX_CNT (13 << 0) |
| 521 | # define VS_PARTIAL_FLUSH (15 << 0) |
| 522 | # define PS_PARTIAL_FLUSH (16 << 0) |
| 523 | # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) |
| 524 | # define ZPASS_DONE (21 << 0) |
| 525 | # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) |
| 526 | # define PERFCOUNTER_START (23 << 0) |
| 527 | # define PERFCOUNTER_STOP (24 << 0) |
| 528 | # define PIPELINESTAT_START (25 << 0) |
| 529 | # define PIPELINESTAT_STOP (26 << 0) |
| 530 | # define PERFCOUNTER_SAMPLE (27 << 0) |
| 531 | # define SAMPLE_PIPELINESTAT (30 << 0) |
| 532 | # define SO_VGT_STREAMOUT_FLUSH (31 << 0) |
| 533 | # define SAMPLE_STREAMOUTSTATS (32 << 0) |
| 534 | # define RESET_VTX_CNT (33 << 0) |
| 535 | # define VGT_FLUSH (36 << 0) |
| 536 | # define BOTTOM_OF_PIPE_TS (40 << 0) |
| 537 | # define DB_CACHE_FLUSH_AND_INV (42 << 0) |
| 538 | # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) |
| 539 | # define FLUSH_AND_INV_DB_META (44 << 0) |
| 540 | # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) |
| 541 | # define FLUSH_AND_INV_CB_META (46 << 0) |
| 542 | # define CS_DONE (47 << 0) |
| 543 | # define PS_DONE (48 << 0) |
| 544 | # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) |
| 545 | # define THREAD_TRACE_START (51 << 0) |
| 546 | # define THREAD_TRACE_STOP (52 << 0) |
| 547 | # define THREAD_TRACE_FLUSH (54 << 0) |
| 548 | # define THREAD_TRACE_FINISH (55 << 0) |
| 549 | # define PIXEL_PIPE_STAT_CONTROL (56 << 0) |
| 550 | # define PIXEL_PIPE_STAT_DUMP (57 << 0) |
| 551 | # define PIXEL_PIPE_STAT_RESET (58 << 0) |
| 552 | |
Alex Deucher | 841cf44 | 2012-12-18 21:47:44 -0500 | [diff] [blame] | 553 | #define SCRATCH_REG0 0x30100 |
| 554 | #define SCRATCH_REG1 0x30104 |
| 555 | #define SCRATCH_REG2 0x30108 |
| 556 | #define SCRATCH_REG3 0x3010C |
| 557 | #define SCRATCH_REG4 0x30110 |
| 558 | #define SCRATCH_REG5 0x30114 |
| 559 | #define SCRATCH_REG6 0x30118 |
| 560 | #define SCRATCH_REG7 0x3011C |
| 561 | |
| 562 | #define SCRATCH_UMSK 0x30140 |
| 563 | #define SCRATCH_ADDR 0x30144 |
| 564 | |
| 565 | #define CP_SEM_WAIT_TIMER 0x301BC |
| 566 | |
| 567 | #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8 |
| 568 | |
Alex Deucher | 2cae3bc | 2012-07-05 11:45:40 -0400 | [diff] [blame^] | 569 | #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0 |
| 570 | |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 571 | #define GRBM_GFX_INDEX 0x30800 |
| 572 | #define INSTANCE_INDEX(x) ((x) << 0) |
| 573 | #define SH_INDEX(x) ((x) << 8) |
| 574 | #define SE_INDEX(x) ((x) << 16) |
| 575 | #define SH_BROADCAST_WRITES (1 << 29) |
| 576 | #define INSTANCE_BROADCAST_WRITES (1 << 30) |
| 577 | #define SE_BROADCAST_WRITES (1 << 31) |
| 578 | |
| 579 | #define VGT_ESGS_RING_SIZE 0x30900 |
| 580 | #define VGT_GSVS_RING_SIZE 0x30904 |
| 581 | #define VGT_PRIMITIVE_TYPE 0x30908 |
| 582 | #define VGT_INDEX_TYPE 0x3090C |
| 583 | |
| 584 | #define VGT_NUM_INDICES 0x30930 |
| 585 | #define VGT_NUM_INSTANCES 0x30934 |
| 586 | #define VGT_TF_RING_SIZE 0x30938 |
| 587 | #define VGT_HS_OFFCHIP_PARAM 0x3093C |
| 588 | #define VGT_TF_MEMORY_BASE 0x30940 |
| 589 | |
| 590 | #define PA_SU_LINE_STIPPLE_VALUE 0x30a00 |
| 591 | #define PA_SC_LINE_STIPPLE_STATE 0x30a04 |
| 592 | |
| 593 | #define SQC_CACHES 0x30d20 |
| 594 | |
| 595 | #define CP_PERFMON_CNTL 0x36020 |
| 596 | |
| 597 | #define CGTS_TCC_DISABLE 0x3c00c |
| 598 | #define CGTS_USER_TCC_DISABLE 0x3c010 |
| 599 | #define TCC_DISABLE_MASK 0xFFFF0000 |
| 600 | #define TCC_DISABLE_SHIFT 16 |
| 601 | |
Alex Deucher | 841cf44 | 2012-12-18 21:47:44 -0500 | [diff] [blame] | 602 | /* |
| 603 | * PM4 |
| 604 | */ |
| 605 | #define PACKET_TYPE0 0 |
| 606 | #define PACKET_TYPE1 1 |
| 607 | #define PACKET_TYPE2 2 |
| 608 | #define PACKET_TYPE3 3 |
| 609 | |
| 610 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) |
| 611 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) |
| 612 | #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) |
| 613 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
| 614 | #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ |
| 615 | (((reg) >> 2) & 0xFFFF) | \ |
| 616 | ((n) & 0x3FFF) << 16) |
| 617 | #define CP_PACKET2 0x80000000 |
| 618 | #define PACKET2_PAD_SHIFT 0 |
| 619 | #define PACKET2_PAD_MASK (0x3fffffff << 0) |
| 620 | |
| 621 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) |
| 622 | |
| 623 | #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ |
| 624 | (((op) & 0xFF) << 8) | \ |
| 625 | ((n) & 0x3FFF) << 16) |
| 626 | |
| 627 | #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) |
| 628 | |
| 629 | /* Packet 3 types */ |
| 630 | #define PACKET3_NOP 0x10 |
| 631 | #define PACKET3_SET_BASE 0x11 |
| 632 | #define PACKET3_BASE_INDEX(x) ((x) << 0) |
| 633 | #define CE_PARTITION_BASE 3 |
| 634 | #define PACKET3_CLEAR_STATE 0x12 |
| 635 | #define PACKET3_INDEX_BUFFER_SIZE 0x13 |
| 636 | #define PACKET3_DISPATCH_DIRECT 0x15 |
| 637 | #define PACKET3_DISPATCH_INDIRECT 0x16 |
| 638 | #define PACKET3_ATOMIC_GDS 0x1D |
| 639 | #define PACKET3_ATOMIC_MEM 0x1E |
| 640 | #define PACKET3_OCCLUSION_QUERY 0x1F |
| 641 | #define PACKET3_SET_PREDICATION 0x20 |
| 642 | #define PACKET3_REG_RMW 0x21 |
| 643 | #define PACKET3_COND_EXEC 0x22 |
| 644 | #define PACKET3_PRED_EXEC 0x23 |
| 645 | #define PACKET3_DRAW_INDIRECT 0x24 |
| 646 | #define PACKET3_DRAW_INDEX_INDIRECT 0x25 |
| 647 | #define PACKET3_INDEX_BASE 0x26 |
| 648 | #define PACKET3_DRAW_INDEX_2 0x27 |
| 649 | #define PACKET3_CONTEXT_CONTROL 0x28 |
| 650 | #define PACKET3_INDEX_TYPE 0x2A |
| 651 | #define PACKET3_DRAW_INDIRECT_MULTI 0x2C |
| 652 | #define PACKET3_DRAW_INDEX_AUTO 0x2D |
| 653 | #define PACKET3_NUM_INSTANCES 0x2F |
| 654 | #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 |
| 655 | #define PACKET3_INDIRECT_BUFFER_CONST 0x33 |
| 656 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 |
| 657 | #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 |
| 658 | #define PACKET3_DRAW_PREAMBLE 0x36 |
| 659 | #define PACKET3_WRITE_DATA 0x37 |
Alex Deucher | 2cae3bc | 2012-07-05 11:45:40 -0400 | [diff] [blame^] | 660 | #define WRITE_DATA_DST_SEL(x) ((x) << 8) |
| 661 | /* 0 - register |
| 662 | * 1 - memory (sync - via GRBM) |
| 663 | * 2 - gl2 |
| 664 | * 3 - gds |
| 665 | * 4 - reserved |
| 666 | * 5 - memory (async - direct) |
| 667 | */ |
| 668 | #define WR_ONE_ADDR (1 << 16) |
| 669 | #define WR_CONFIRM (1 << 20) |
| 670 | #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) |
| 671 | /* 0 - LRU |
| 672 | * 1 - Stream |
| 673 | */ |
| 674 | #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) |
| 675 | /* 0 - me |
| 676 | * 1 - pfp |
| 677 | * 2 - ce |
| 678 | */ |
Alex Deucher | 841cf44 | 2012-12-18 21:47:44 -0500 | [diff] [blame] | 679 | #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 |
| 680 | #define PACKET3_MEM_SEMAPHORE 0x39 |
Alex Deucher | 2cae3bc | 2012-07-05 11:45:40 -0400 | [diff] [blame^] | 681 | # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) |
| 682 | # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ |
| 683 | # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ |
| 684 | # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) |
| 685 | # define PACKET3_SEM_SEL_WAIT (0x7 << 29) |
Alex Deucher | 841cf44 | 2012-12-18 21:47:44 -0500 | [diff] [blame] | 686 | #define PACKET3_COPY_DW 0x3B |
| 687 | #define PACKET3_WAIT_REG_MEM 0x3C |
Alex Deucher | 2cae3bc | 2012-07-05 11:45:40 -0400 | [diff] [blame^] | 688 | #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) |
| 689 | /* 0 - always |
| 690 | * 1 - < |
| 691 | * 2 - <= |
| 692 | * 3 - == |
| 693 | * 4 - != |
| 694 | * 5 - >= |
| 695 | * 6 - > |
| 696 | */ |
| 697 | #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) |
| 698 | /* 0 - reg |
| 699 | * 1 - mem |
| 700 | */ |
| 701 | #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) |
| 702 | /* 0 - wait_reg_mem |
| 703 | * 1 - wr_wait_wr_reg |
| 704 | */ |
| 705 | #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) |
| 706 | /* 0 - me |
| 707 | * 1 - pfp |
| 708 | */ |
Alex Deucher | 841cf44 | 2012-12-18 21:47:44 -0500 | [diff] [blame] | 709 | #define PACKET3_INDIRECT_BUFFER 0x3F |
Alex Deucher | 2cae3bc | 2012-07-05 11:45:40 -0400 | [diff] [blame^] | 710 | #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) |
| 711 | #define INDIRECT_BUFFER_VALID (1 << 23) |
| 712 | #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) |
| 713 | /* 0 - LRU |
| 714 | * 1 - Stream |
| 715 | * 2 - Bypass |
| 716 | */ |
Alex Deucher | 841cf44 | 2012-12-18 21:47:44 -0500 | [diff] [blame] | 717 | #define PACKET3_COPY_DATA 0x40 |
| 718 | #define PACKET3_PFP_SYNC_ME 0x42 |
| 719 | #define PACKET3_SURFACE_SYNC 0x43 |
| 720 | # define PACKET3_DEST_BASE_0_ENA (1 << 0) |
| 721 | # define PACKET3_DEST_BASE_1_ENA (1 << 1) |
| 722 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
| 723 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) |
| 724 | # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) |
| 725 | # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) |
| 726 | # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) |
| 727 | # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) |
| 728 | # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) |
| 729 | # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) |
| 730 | # define PACKET3_DB_DEST_BASE_ENA (1 << 14) |
| 731 | # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) |
| 732 | # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ |
| 733 | # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ |
| 734 | # define PACKET3_DEST_BASE_2_ENA (1 << 19) |
| 735 | # define PACKET3_DEST_BASE_3_ENA (1 << 21) |
| 736 | # define PACKET3_TCL1_ACTION_ENA (1 << 22) |
| 737 | # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ |
| 738 | # define PACKET3_CB_ACTION_ENA (1 << 25) |
| 739 | # define PACKET3_DB_ACTION_ENA (1 << 26) |
| 740 | # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) |
| 741 | # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) |
| 742 | # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) |
| 743 | #define PACKET3_COND_WRITE 0x45 |
| 744 | #define PACKET3_EVENT_WRITE 0x46 |
| 745 | #define EVENT_TYPE(x) ((x) << 0) |
| 746 | #define EVENT_INDEX(x) ((x) << 8) |
| 747 | /* 0 - any non-TS event |
| 748 | * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* |
| 749 | * 2 - SAMPLE_PIPELINESTAT |
| 750 | * 3 - SAMPLE_STREAMOUTSTAT* |
| 751 | * 4 - *S_PARTIAL_FLUSH |
| 752 | * 5 - EOP events |
| 753 | * 6 - EOS events |
| 754 | */ |
| 755 | #define PACKET3_EVENT_WRITE_EOP 0x47 |
| 756 | #define EOP_TCL1_VOL_ACTION_EN (1 << 12) |
| 757 | #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ |
| 758 | #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ |
| 759 | #define EOP_TCL1_ACTION_EN (1 << 16) |
| 760 | #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ |
Alex Deucher | 2cae3bc | 2012-07-05 11:45:40 -0400 | [diff] [blame^] | 761 | #define EOP_CACHE_POLICY(x) ((x) << 25) |
Alex Deucher | 841cf44 | 2012-12-18 21:47:44 -0500 | [diff] [blame] | 762 | /* 0 - LRU |
| 763 | * 1 - Stream |
| 764 | * 2 - Bypass |
| 765 | */ |
Alex Deucher | 2cae3bc | 2012-07-05 11:45:40 -0400 | [diff] [blame^] | 766 | #define EOP_TCL2_VOLATILE (1 << 27) |
Alex Deucher | 841cf44 | 2012-12-18 21:47:44 -0500 | [diff] [blame] | 767 | #define DATA_SEL(x) ((x) << 29) |
| 768 | /* 0 - discard |
| 769 | * 1 - send low 32bit data |
| 770 | * 2 - send 64bit data |
| 771 | * 3 - send 64bit GPU counter value |
| 772 | * 4 - send 64bit sys counter value |
| 773 | */ |
| 774 | #define INT_SEL(x) ((x) << 24) |
| 775 | /* 0 - none |
| 776 | * 1 - interrupt only (DATA_SEL = 0) |
| 777 | * 2 - interrupt when data write is confirmed |
| 778 | */ |
| 779 | #define DST_SEL(x) ((x) << 16) |
| 780 | /* 0 - MC |
| 781 | * 1 - TC/L2 |
| 782 | */ |
| 783 | #define PACKET3_EVENT_WRITE_EOS 0x48 |
| 784 | #define PACKET3_RELEASE_MEM 0x49 |
| 785 | #define PACKET3_PREAMBLE_CNTL 0x4A |
| 786 | # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) |
| 787 | # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) |
| 788 | #define PACKET3_DMA_DATA 0x50 |
| 789 | #define PACKET3_AQUIRE_MEM 0x58 |
| 790 | #define PACKET3_REWIND 0x59 |
| 791 | #define PACKET3_LOAD_UCONFIG_REG 0x5E |
| 792 | #define PACKET3_LOAD_SH_REG 0x5F |
| 793 | #define PACKET3_LOAD_CONFIG_REG 0x60 |
| 794 | #define PACKET3_LOAD_CONTEXT_REG 0x61 |
| 795 | #define PACKET3_SET_CONFIG_REG 0x68 |
| 796 | #define PACKET3_SET_CONFIG_REG_START 0x00008000 |
| 797 | #define PACKET3_SET_CONFIG_REG_END 0x0000b000 |
| 798 | #define PACKET3_SET_CONTEXT_REG 0x69 |
| 799 | #define PACKET3_SET_CONTEXT_REG_START 0x00028000 |
| 800 | #define PACKET3_SET_CONTEXT_REG_END 0x00029000 |
| 801 | #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 |
| 802 | #define PACKET3_SET_SH_REG 0x76 |
| 803 | #define PACKET3_SET_SH_REG_START 0x0000b000 |
| 804 | #define PACKET3_SET_SH_REG_END 0x0000c000 |
| 805 | #define PACKET3_SET_SH_REG_OFFSET 0x77 |
| 806 | #define PACKET3_SET_QUEUE_REG 0x78 |
| 807 | #define PACKET3_SET_UCONFIG_REG 0x79 |
Alex Deucher | 2cae3bc | 2012-07-05 11:45:40 -0400 | [diff] [blame^] | 808 | #define PACKET3_SET_UCONFIG_REG_START 0x00030000 |
| 809 | #define PACKET3_SET_UCONFIG_REG_END 0x00031000 |
Alex Deucher | 841cf44 | 2012-12-18 21:47:44 -0500 | [diff] [blame] | 810 | #define PACKET3_SCRATCH_RAM_WRITE 0x7D |
| 811 | #define PACKET3_SCRATCH_RAM_READ 0x7E |
| 812 | #define PACKET3_LOAD_CONST_RAM 0x80 |
| 813 | #define PACKET3_WRITE_CONST_RAM 0x81 |
| 814 | #define PACKET3_DUMP_CONST_RAM 0x83 |
| 815 | #define PACKET3_INCREMENT_CE_COUNTER 0x84 |
| 816 | #define PACKET3_INCREMENT_DE_COUNTER 0x85 |
| 817 | #define PACKET3_WAIT_ON_CE_COUNTER 0x86 |
| 818 | #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 |
Alex Deucher | 2cae3bc | 2012-07-05 11:45:40 -0400 | [diff] [blame^] | 819 | #define PACKET3_SWITCH_BUFFER 0x8B |
Alex Deucher | 841cf44 | 2012-12-18 21:47:44 -0500 | [diff] [blame] | 820 | |
Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 821 | #endif |