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Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001/*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
Charulatha V1a5d8192011-02-02 17:52:14 +05306 * Juha Yrj�l� <juha.yrjola@nokia.com>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/device.h>
29#include <linux/delay.h>
30#include <linux/dma-mapping.h>
Russell King53741ed2012-04-23 13:51:48 +010031#include <linux/dmaengine.h>
32#include <linux/omap-dma.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070033#include <linux/platform_device.h>
34#include <linux/err.h>
35#include <linux/clk.h>
36#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090037#include <linux/slab.h>
Govindraj.R1f1a4382011-02-02 17:52:15 +053038#include <linux/pm_runtime.h>
Benoit Coussond5a80032012-02-15 18:37:34 +010039#include <linux/of.h>
40#include <linux/of_device.h>
Matt Porterec155af2012-09-18 08:01:25 -040041#include <linux/pinctrl/consumer.h>
42#include <linux/err.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070043
44#include <linux/spi/spi.h>
45
Arnd Bergmann22037472012-08-24 15:21:06 +020046#include <linux/platform_data/spi-omap2-mcspi.h>
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070047
48#define OMAP2_MCSPI_MAX_FREQ 48000000
Shubhrajyoti D27b52842012-03-26 17:04:22 +053049#define SPI_AUTOSUSPEND_TIMEOUT 2000
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070050
51#define OMAP2_MCSPI_REVISION 0x00
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070052#define OMAP2_MCSPI_SYSSTATUS 0x14
53#define OMAP2_MCSPI_IRQSTATUS 0x18
54#define OMAP2_MCSPI_IRQENABLE 0x1c
55#define OMAP2_MCSPI_WAKEUPENABLE 0x20
56#define OMAP2_MCSPI_SYST 0x24
57#define OMAP2_MCSPI_MODULCTRL 0x28
58
59/* per-channel banks, 0x14 bytes each, first is: */
60#define OMAP2_MCSPI_CHCONF0 0x2c
61#define OMAP2_MCSPI_CHSTAT0 0x30
62#define OMAP2_MCSPI_CHCTRL0 0x34
63#define OMAP2_MCSPI_TX0 0x38
64#define OMAP2_MCSPI_RX0 0x3c
65
66/* per-register bitmasks: */
67
Jouni Hogander7a8fa722009-09-22 16:45:58 -070068#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
69#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
70#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070071
Jouni Hogander7a8fa722009-09-22 16:45:58 -070072#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
73#define OMAP2_MCSPI_CHCONF_POL BIT(1)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070074#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
Jouni Hogander7a8fa722009-09-22 16:45:58 -070075#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070076#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
Jouni Hogander7a8fa722009-09-22 16:45:58 -070077#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
78#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070079#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
Jouni Hogander7a8fa722009-09-22 16:45:58 -070080#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
81#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
82#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
83#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
84#define OMAP2_MCSPI_CHCONF_IS BIT(18)
85#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
86#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070087
Jouni Hogander7a8fa722009-09-22 16:45:58 -070088#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
89#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
90#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070091
Jouni Hogander7a8fa722009-09-22 16:45:58 -070092#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070093
Jouni Hogander7a8fa722009-09-22 16:45:58 -070094#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -070095
96/* We have 2 DMA channels per CS, one for RX and one for TX */
97struct omap2_mcspi_dma {
Russell King53741ed2012-04-23 13:51:48 +010098 struct dma_chan *dma_tx;
99 struct dma_chan *dma_rx;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700100
101 int dma_tx_sync_dev;
102 int dma_rx_sync_dev;
103
104 struct completion dma_tx_completion;
105 struct completion dma_rx_completion;
106};
107
108/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
109 * cache operations; better heuristics consider wordsize and bitrate.
110 */
Roman Tereshonkov8b66c132010-04-12 09:07:54 +0000111#define DMA_MIN_BYTES 160
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700112
113
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530114/*
115 * Used for context save and restore, structure members to be updated whenever
116 * corresponding registers are modified.
117 */
118struct omap2_mcspi_regs {
119 u32 modulctrl;
120 u32 wakeupenable;
121 struct list_head cs;
122};
123
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700124struct omap2_mcspi {
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700125 struct spi_master *master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700126 /* Virtual base address of the controller */
127 void __iomem *base;
Russell Kinge5480b732008-09-01 21:51:50 +0100128 unsigned long phys;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700129 /* SPI1 has 4 channels, while SPI2 has 2 */
130 struct omap2_mcspi_dma *dma_channels;
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530131 struct device *dev;
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530132 struct omap2_mcspi_regs ctx;
Daniel Mack0384e902012-10-07 18:19:44 +0200133 unsigned int pin_dir:1;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700134};
135
136struct omap2_mcspi_cs {
137 void __iomem *base;
Russell Kinge5480b732008-09-01 21:51:50 +0100138 unsigned long phys;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700139 int word_len;
Tero Kristo89c05372009-09-22 16:46:17 -0700140 struct list_head node;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700141 /* Context save and restore shadow register */
142 u32 chconf0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700143};
144
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700145static inline void mcspi_write_reg(struct spi_master *master,
146 int idx, u32 val)
147{
148 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
149
150 __raw_writel(val, mcspi->base + idx);
151}
152
153static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
154{
155 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
156
157 return __raw_readl(mcspi->base + idx);
158}
159
160static inline void mcspi_write_cs_reg(const struct spi_device *spi,
161 int idx, u32 val)
162{
163 struct omap2_mcspi_cs *cs = spi->controller_state;
164
165 __raw_writel(val, cs->base + idx);
166}
167
168static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
169{
170 struct omap2_mcspi_cs *cs = spi->controller_state;
171
172 return __raw_readl(cs->base + idx);
173}
174
Hemanth Va41ae1a2009-09-22 16:46:16 -0700175static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
176{
177 struct omap2_mcspi_cs *cs = spi->controller_state;
178
179 return cs->chconf0;
180}
181
182static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
183{
184 struct omap2_mcspi_cs *cs = spi->controller_state;
185
186 cs->chconf0 = val;
187 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
Roman Tereshonkova330ce22010-03-15 09:06:28 +0000188 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700189}
190
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700191static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
192 int is_read, int enable)
193{
194 u32 l, rw;
195
Hemanth Va41ae1a2009-09-22 16:46:16 -0700196 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700197
198 if (is_read) /* 1 is read, 0 write */
199 rw = OMAP2_MCSPI_CHCONF_DMAR;
200 else
201 rw = OMAP2_MCSPI_CHCONF_DMAW;
202
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +0530203 if (enable)
204 l |= rw;
205 else
206 l &= ~rw;
207
Hemanth Va41ae1a2009-09-22 16:46:16 -0700208 mcspi_write_chconf0(spi, l);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700209}
210
211static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
212{
213 u32 l;
214
215 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
216 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000217 /* Flash post-writes */
218 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700219}
220
221static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
222{
223 u32 l;
224
Hemanth Va41ae1a2009-09-22 16:46:16 -0700225 l = mcspi_cached_chconf0(spi);
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +0530226 if (cs_active)
227 l |= OMAP2_MCSPI_CHCONF_FORCE;
228 else
229 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
230
Hemanth Va41ae1a2009-09-22 16:46:16 -0700231 mcspi_write_chconf0(spi, l);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700232}
233
234static void omap2_mcspi_set_master_mode(struct spi_master *master)
235{
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530236 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
237 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700238 u32 l;
239
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530240 /*
241 * Setup when switching from (reset default) slave mode
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700242 * to single-channel master mode
243 */
244 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +0530245 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
246 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700247 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700248
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530249 ctx->modulctrl = l;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700250}
251
252static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
253{
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530254 struct spi_master *spi_cntrl = mcspi->master;
255 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
256 struct omap2_mcspi_cs *cs;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700257
258 /* McSPI: context restore */
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530259 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
260 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700261
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530262 list_for_each_entry(cs, &ctx->cs, node)
Tero Kristo89c05372009-09-22 16:46:17 -0700263 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700264}
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700265
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530266static int omap2_prepare_transfer(struct spi_master *master)
267{
268 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
269
270 pm_runtime_get_sync(mcspi->dev);
271 return 0;
272}
273
274static int omap2_unprepare_transfer(struct spi_master *master)
275{
276 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
277
278 pm_runtime_mark_last_busy(mcspi->dev);
279 pm_runtime_put_autosuspend(mcspi->dev);
280 return 0;
281}
282
Ilkka Koskinen2764c502010-10-19 17:07:31 +0300283static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
284{
285 unsigned long timeout;
286
287 timeout = jiffies + msecs_to_jiffies(1000);
288 while (!(__raw_readl(reg) & bit)) {
289 if (time_after(jiffies, timeout))
290 return -1;
291 cpu_relax();
292 }
293 return 0;
294}
295
Russell King53741ed2012-04-23 13:51:48 +0100296static void omap2_mcspi_rx_callback(void *data)
297{
298 struct spi_device *spi = data;
299 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
300 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
301
302 complete(&mcspi_dma->dma_rx_completion);
303
304 /* We must disable the DMA RX request */
305 omap2_mcspi_set_dma_req(spi, 1, 0);
306}
307
308static void omap2_mcspi_tx_callback(void *data)
309{
310 struct spi_device *spi = data;
311 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
312 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
313
314 complete(&mcspi_dma->dma_tx_completion);
315
316 /* We must disable the DMA TX request */
317 omap2_mcspi_set_dma_req(spi, 0, 0);
318}
319
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530320static void omap2_mcspi_tx_dma(struct spi_device *spi,
321 struct spi_transfer *xfer,
322 struct dma_slave_config cfg)
323{
324 struct omap2_mcspi *mcspi;
325 struct omap2_mcspi_dma *mcspi_dma;
326 unsigned int count;
327 u8 * rx;
328 const u8 * tx;
329 void __iomem *chstat_reg;
330 struct omap2_mcspi_cs *cs = spi->controller_state;
331
332 mcspi = spi_master_get_devdata(spi->master);
333 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
334 count = xfer->len;
335
336 rx = xfer->rx_buf;
337 tx = xfer->tx_buf;
338 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
339
340 if (mcspi_dma->dma_tx) {
341 struct dma_async_tx_descriptor *tx;
342 struct scatterlist sg;
343
344 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
345
346 sg_init_table(&sg, 1);
347 sg_dma_address(&sg) = xfer->tx_dma;
348 sg_dma_len(&sg) = xfer->len;
349
350 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
351 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
352 if (tx) {
353 tx->callback = omap2_mcspi_tx_callback;
354 tx->callback_param = spi;
355 dmaengine_submit(tx);
356 } else {
357 /* FIXME: fall back to PIO? */
358 }
359 }
360 dma_async_issue_pending(mcspi_dma->dma_tx);
361 omap2_mcspi_set_dma_req(spi, 0, 1);
362
363 wait_for_completion(&mcspi_dma->dma_tx_completion);
364 dma_unmap_single(mcspi->dev, xfer->tx_dma, count,
365 DMA_TO_DEVICE);
366
367 /* for TX_ONLY mode, be sure all words have shifted out */
368 if (rx == NULL) {
369 if (mcspi_wait_for_reg_bit(chstat_reg,
370 OMAP2_MCSPI_CHSTAT_TXS) < 0)
371 dev_err(&spi->dev, "TXS timed out\n");
372 else if (mcspi_wait_for_reg_bit(chstat_reg,
373 OMAP2_MCSPI_CHSTAT_EOT) < 0)
374 dev_err(&spi->dev, "EOT timed out\n");
375 }
376}
377
378static unsigned
379omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
380 struct dma_slave_config cfg,
381 unsigned es)
382{
383 struct omap2_mcspi *mcspi;
384 struct omap2_mcspi_dma *mcspi_dma;
385 unsigned int count;
386 u32 l;
387 int elements = 0;
388 int word_len, element_count;
389 struct omap2_mcspi_cs *cs = spi->controller_state;
390 mcspi = spi_master_get_devdata(spi->master);
391 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
392 count = xfer->len;
393 word_len = cs->word_len;
394 l = mcspi_cached_chconf0(spi);
395
396 if (word_len <= 8)
397 element_count = count;
398 else if (word_len <= 16)
399 element_count = count >> 1;
400 else /* word_len <= 32 */
401 element_count = count >> 2;
402
403 if (mcspi_dma->dma_rx) {
404 struct dma_async_tx_descriptor *tx;
405 struct scatterlist sg;
406 size_t len = xfer->len - es;
407
408 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
409
410 if (l & OMAP2_MCSPI_CHCONF_TURBO)
411 len -= es;
412
413 sg_init_table(&sg, 1);
414 sg_dma_address(&sg) = xfer->rx_dma;
415 sg_dma_len(&sg) = len;
416
417 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
418 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
419 DMA_CTRL_ACK);
420 if (tx) {
421 tx->callback = omap2_mcspi_rx_callback;
422 tx->callback_param = spi;
423 dmaengine_submit(tx);
424 } else {
425 /* FIXME: fall back to PIO? */
426 }
427 }
428
429 dma_async_issue_pending(mcspi_dma->dma_rx);
430 omap2_mcspi_set_dma_req(spi, 1, 1);
431
432 wait_for_completion(&mcspi_dma->dma_rx_completion);
433 dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
434 DMA_FROM_DEVICE);
435 omap2_mcspi_set_enable(spi, 0);
436
437 elements = element_count - 1;
438
439 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
440 elements--;
441
442 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
443 & OMAP2_MCSPI_CHSTAT_RXS)) {
444 u32 w;
445
446 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
447 if (word_len <= 8)
448 ((u8 *)xfer->rx_buf)[elements++] = w;
449 else if (word_len <= 16)
450 ((u16 *)xfer->rx_buf)[elements++] = w;
451 else /* word_len <= 32 */
452 ((u32 *)xfer->rx_buf)[elements++] = w;
453 } else {
454 dev_err(&spi->dev, "DMA RX penultimate word empty");
455 count -= (word_len <= 8) ? 2 :
456 (word_len <= 16) ? 4 :
457 /* word_len <= 32 */ 8;
458 omap2_mcspi_set_enable(spi, 1);
459 return count;
460 }
461 }
462 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
463 & OMAP2_MCSPI_CHSTAT_RXS)) {
464 u32 w;
465
466 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
467 if (word_len <= 8)
468 ((u8 *)xfer->rx_buf)[elements] = w;
469 else if (word_len <= 16)
470 ((u16 *)xfer->rx_buf)[elements] = w;
471 else /* word_len <= 32 */
472 ((u32 *)xfer->rx_buf)[elements] = w;
473 } else {
474 dev_err(&spi->dev, "DMA RX last word empty");
475 count -= (word_len <= 8) ? 1 :
476 (word_len <= 16) ? 2 :
477 /* word_len <= 32 */ 4;
478 }
479 omap2_mcspi_set_enable(spi, 1);
480 return count;
481}
482
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700483static unsigned
484omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
485{
486 struct omap2_mcspi *mcspi;
487 struct omap2_mcspi_cs *cs = spi->controller_state;
488 struct omap2_mcspi_dma *mcspi_dma;
Russell King8c7494a2012-04-23 13:56:25 +0100489 unsigned int count;
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000490 u32 l;
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530491 u8 *rx;
492 const u8 *tx;
Russell King53741ed2012-04-23 13:51:48 +0100493 struct dma_slave_config cfg;
494 enum dma_slave_buswidth width;
495 unsigned es;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700496
497 mcspi = spi_master_get_devdata(spi->master);
498 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000499 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700500
Ilkka Koskinen2764c502010-10-19 17:07:31 +0300501
Russell King53741ed2012-04-23 13:51:48 +0100502 if (cs->word_len <= 8) {
503 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
504 es = 1;
505 } else if (cs->word_len <= 16) {
506 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
507 es = 2;
508 } else {
509 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
510 es = 4;
511 }
512
513 memset(&cfg, 0, sizeof(cfg));
514 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
515 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
516 cfg.src_addr_width = width;
517 cfg.dst_addr_width = width;
518 cfg.src_maxburst = 1;
519 cfg.dst_maxburst = 1;
520
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700521 rx = xfer->rx_buf;
522 tx = xfer->tx_buf;
523
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530524 count = xfer->len;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700525
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530526 if (tx != NULL)
527 omap2_mcspi_tx_dma(spi, xfer, cfg);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700528
Shubhrajyoti Dd7b43942012-09-11 12:13:20 +0530529 if (rx != NULL)
530 return omap2_mcspi_rx_dma(spi, xfer, cfg, es);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700531
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700532 return count;
533}
534
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700535static unsigned
536omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
537{
538 struct omap2_mcspi *mcspi;
539 struct omap2_mcspi_cs *cs = spi->controller_state;
540 unsigned int count, c;
541 u32 l;
542 void __iomem *base = cs->base;
543 void __iomem *tx_reg;
544 void __iomem *rx_reg;
545 void __iomem *chstat_reg;
546 int word_len;
547
548 mcspi = spi_master_get_devdata(spi->master);
549 count = xfer->len;
550 c = count;
551 word_len = cs->word_len;
552
Hemanth Va41ae1a2009-09-22 16:46:16 -0700553 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700554
555 /* We store the pre-calculated register addresses on stack to speed
556 * up the transfer loop. */
557 tx_reg = base + OMAP2_MCSPI_TX0;
558 rx_reg = base + OMAP2_MCSPI_RX0;
559 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
560
Michael Jonesadef6582011-02-25 16:55:11 +0100561 if (c < (word_len>>3))
562 return 0;
563
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700564 if (word_len <= 8) {
565 u8 *rx;
566 const u8 *tx;
567
568 rx = xfer->rx_buf;
569 tx = xfer->tx_buf;
570
571 do {
Kalle Valofeed9ba2008-01-24 14:00:40 -0800572 c -= 1;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700573 if (tx != NULL) {
574 if (mcspi_wait_for_reg_bit(chstat_reg,
575 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
576 dev_err(&spi->dev, "TXS timed out\n");
577 goto out;
578 }
Felipe Balbi079a1762010-09-29 17:31:29 +0900579 dev_vdbg(&spi->dev, "write-%d %02x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700580 word_len, *tx);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700581 __raw_writel(*tx++, tx_reg);
582 }
583 if (rx != NULL) {
584 if (mcspi_wait_for_reg_bit(chstat_reg,
585 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
586 dev_err(&spi->dev, "RXS timed out\n");
587 goto out;
588 }
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000589
590 if (c == 1 && tx == NULL &&
591 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
592 omap2_mcspi_set_enable(spi, 0);
593 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900594 dev_vdbg(&spi->dev, "read-%d %02x\n",
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000595 word_len, *(rx - 1));
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000596 if (mcspi_wait_for_reg_bit(chstat_reg,
597 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
598 dev_err(&spi->dev,
599 "RXS timed out\n");
600 goto out;
601 }
602 c = 0;
603 } else if (c == 0 && tx == NULL) {
604 omap2_mcspi_set_enable(spi, 0);
605 }
606
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700607 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900608 dev_vdbg(&spi->dev, "read-%d %02x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700609 word_len, *(rx - 1));
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700610 }
Jarkko Nikula95c5c3a2011-03-21 16:27:30 +0200611 } while (c);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700612 } else if (word_len <= 16) {
613 u16 *rx;
614 const u16 *tx;
615
616 rx = xfer->rx_buf;
617 tx = xfer->tx_buf;
618 do {
Kalle Valofeed9ba2008-01-24 14:00:40 -0800619 c -= 2;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700620 if (tx != NULL) {
621 if (mcspi_wait_for_reg_bit(chstat_reg,
622 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
623 dev_err(&spi->dev, "TXS timed out\n");
624 goto out;
625 }
Felipe Balbi079a1762010-09-29 17:31:29 +0900626 dev_vdbg(&spi->dev, "write-%d %04x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700627 word_len, *tx);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700628 __raw_writel(*tx++, tx_reg);
629 }
630 if (rx != NULL) {
631 if (mcspi_wait_for_reg_bit(chstat_reg,
632 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
633 dev_err(&spi->dev, "RXS timed out\n");
634 goto out;
635 }
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000636
637 if (c == 2 && tx == NULL &&
638 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
639 omap2_mcspi_set_enable(spi, 0);
640 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900641 dev_vdbg(&spi->dev, "read-%d %04x\n",
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000642 word_len, *(rx - 1));
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000643 if (mcspi_wait_for_reg_bit(chstat_reg,
644 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
645 dev_err(&spi->dev,
646 "RXS timed out\n");
647 goto out;
648 }
649 c = 0;
650 } else if (c == 0 && tx == NULL) {
651 omap2_mcspi_set_enable(spi, 0);
652 }
653
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700654 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900655 dev_vdbg(&spi->dev, "read-%d %04x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700656 word_len, *(rx - 1));
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700657 }
Jarkko Nikula95c5c3a2011-03-21 16:27:30 +0200658 } while (c >= 2);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700659 } else if (word_len <= 32) {
660 u32 *rx;
661 const u32 *tx;
662
663 rx = xfer->rx_buf;
664 tx = xfer->tx_buf;
665 do {
Kalle Valofeed9ba2008-01-24 14:00:40 -0800666 c -= 4;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700667 if (tx != NULL) {
668 if (mcspi_wait_for_reg_bit(chstat_reg,
669 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
670 dev_err(&spi->dev, "TXS timed out\n");
671 goto out;
672 }
Felipe Balbi079a1762010-09-29 17:31:29 +0900673 dev_vdbg(&spi->dev, "write-%d %08x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700674 word_len, *tx);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700675 __raw_writel(*tx++, tx_reg);
676 }
677 if (rx != NULL) {
678 if (mcspi_wait_for_reg_bit(chstat_reg,
679 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
680 dev_err(&spi->dev, "RXS timed out\n");
681 goto out;
682 }
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000683
684 if (c == 4 && tx == NULL &&
685 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
686 omap2_mcspi_set_enable(spi, 0);
687 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900688 dev_vdbg(&spi->dev, "read-%d %08x\n",
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000689 word_len, *(rx - 1));
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000690 if (mcspi_wait_for_reg_bit(chstat_reg,
691 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
692 dev_err(&spi->dev,
693 "RXS timed out\n");
694 goto out;
695 }
696 c = 0;
697 } else if (c == 0 && tx == NULL) {
698 omap2_mcspi_set_enable(spi, 0);
699 }
700
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700701 *rx++ = __raw_readl(rx_reg);
Felipe Balbi079a1762010-09-29 17:31:29 +0900702 dev_vdbg(&spi->dev, "read-%d %08x\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700703 word_len, *(rx - 1));
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700704 }
Jarkko Nikula95c5c3a2011-03-21 16:27:30 +0200705 } while (c >= 4);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700706 }
707
708 /* for TX_ONLY mode, be sure all words have shifted out */
709 if (xfer->rx_buf == NULL) {
710 if (mcspi_wait_for_reg_bit(chstat_reg,
711 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
712 dev_err(&spi->dev, "TXS timed out\n");
713 } else if (mcspi_wait_for_reg_bit(chstat_reg,
714 OMAP2_MCSPI_CHSTAT_EOT) < 0)
715 dev_err(&spi->dev, "EOT timed out\n");
Jason Wange1993ed2010-10-19 18:03:27 +0800716
717 /* disable chan to purge rx datas received in TX_ONLY transfer,
718 * otherwise these rx datas will affect the direct following
719 * RX_ONLY transfer.
720 */
721 omap2_mcspi_set_enable(spi, 0);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700722 }
723out:
Roman Tereshonkov4743a0f2010-04-13 10:41:51 +0000724 omap2_mcspi_set_enable(spi, 1);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700725 return count - c;
726}
727
Hannu Heikkinen57d9c102011-02-24 21:31:33 +0200728static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
729{
730 u32 div;
731
732 for (div = 0; div < 15; div++)
733 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
734 return div;
735
736 return 15;
737}
738
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700739/* called only when no transfer is active to this device */
740static int omap2_mcspi_setup_transfer(struct spi_device *spi,
741 struct spi_transfer *t)
742{
743 struct omap2_mcspi_cs *cs = spi->controller_state;
744 struct omap2_mcspi *mcspi;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700745 struct spi_master *spi_cntrl;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700746 u32 l = 0, div = 0;
747 u8 word_len = spi->bits_per_word;
Scott Ellis9bd45172010-03-10 14:23:13 -0700748 u32 speed_hz = spi->max_speed_hz;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700749
750 mcspi = spi_master_get_devdata(spi->master);
Hemanth Va41ae1a2009-09-22 16:46:16 -0700751 spi_cntrl = mcspi->master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700752
753 if (t != NULL && t->bits_per_word)
754 word_len = t->bits_per_word;
755
756 cs->word_len = word_len;
757
Scott Ellis9bd45172010-03-10 14:23:13 -0700758 if (t && t->speed_hz)
759 speed_hz = t->speed_hz;
760
Hannu Heikkinen57d9c102011-02-24 21:31:33 +0200761 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
762 div = omap2_mcspi_calc_divisor(speed_hz);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700763
Hemanth Va41ae1a2009-09-22 16:46:16 -0700764 l = mcspi_cached_chconf0(spi);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700765
766 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
767 * REVISIT: this controller could support SPI_3WIRE mode.
768 */
Daniel Mack2cd45172012-11-14 11:14:26 +0800769 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
Daniel Mack0384e902012-10-07 18:19:44 +0200770 l &= ~OMAP2_MCSPI_CHCONF_IS;
771 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
772 l |= OMAP2_MCSPI_CHCONF_DPE0;
773 } else {
774 l |= OMAP2_MCSPI_CHCONF_IS;
775 l |= OMAP2_MCSPI_CHCONF_DPE1;
776 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
777 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700778
779 /* wordlength */
780 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
781 l |= (word_len - 1) << 7;
782
783 /* set chipselect polarity; manage with FORCE */
784 if (!(spi->mode & SPI_CS_HIGH))
785 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
786 else
787 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
788
789 /* set clock divisor */
790 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
791 l |= div << 2;
792
793 /* set SPI mode 0..3 */
794 if (spi->mode & SPI_CPOL)
795 l |= OMAP2_MCSPI_CHCONF_POL;
796 else
797 l &= ~OMAP2_MCSPI_CHCONF_POL;
798 if (spi->mode & SPI_CPHA)
799 l |= OMAP2_MCSPI_CHCONF_PHA;
800 else
801 l &= ~OMAP2_MCSPI_CHCONF_PHA;
802
Hemanth Va41ae1a2009-09-22 16:46:16 -0700803 mcspi_write_chconf0(spi, l);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700804
805 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
Hannu Heikkinen57d9c102011-02-24 21:31:33 +0200806 OMAP2_MCSPI_MAX_FREQ >> div,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700807 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
808 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
809
810 return 0;
811}
812
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700813static int omap2_mcspi_request_dma(struct spi_device *spi)
814{
815 struct spi_master *master = spi->master;
816 struct omap2_mcspi *mcspi;
817 struct omap2_mcspi_dma *mcspi_dma;
Russell King53741ed2012-04-23 13:51:48 +0100818 dma_cap_mask_t mask;
819 unsigned sig;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700820
821 mcspi = spi_master_get_devdata(master);
822 mcspi_dma = mcspi->dma_channels + spi->chip_select;
823
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700824 init_completion(&mcspi_dma->dma_rx_completion);
825 init_completion(&mcspi_dma->dma_tx_completion);
826
Russell King53741ed2012-04-23 13:51:48 +0100827 dma_cap_zero(mask);
828 dma_cap_set(DMA_SLAVE, mask);
Russell King53741ed2012-04-23 13:51:48 +0100829 sig = mcspi_dma->dma_rx_sync_dev;
830 mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
831 if (!mcspi_dma->dma_rx) {
832 dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n");
833 return -EAGAIN;
834 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700835
Russell King53741ed2012-04-23 13:51:48 +0100836 sig = mcspi_dma->dma_tx_sync_dev;
837 mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
838 if (!mcspi_dma->dma_tx) {
839 dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n");
840 dma_release_channel(mcspi_dma->dma_rx);
841 mcspi_dma->dma_rx = NULL;
842 return -EAGAIN;
843 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700844
845 return 0;
846}
847
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700848static int omap2_mcspi_setup(struct spi_device *spi)
849{
850 int ret;
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530851 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
852 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700853 struct omap2_mcspi_dma *mcspi_dma;
854 struct omap2_mcspi_cs *cs = spi->controller_state;
855
David Brownell7d077192009-06-17 16:26:03 -0700856 if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700857 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
858 spi->bits_per_word);
859 return -EINVAL;
860 }
861
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700862 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
863
864 if (!cs) {
Russell King10aa5a32012-06-18 11:27:04 +0100865 cs = kzalloc(sizeof *cs, GFP_KERNEL);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700866 if (!cs)
867 return -ENOMEM;
868 cs->base = mcspi->base + spi->chip_select * 0x14;
Russell Kinge5480b732008-09-01 21:51:50 +0100869 cs->phys = mcspi->phys + spi->chip_select * 0x14;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700870 cs->chconf0 = 0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700871 spi->controller_state = cs;
Tero Kristo89c05372009-09-22 16:46:17 -0700872 /* Link this to context save list */
Benoit Cousson1bd897f82012-03-26 15:32:33 +0530873 list_add_tail(&cs->node, &ctx->cs);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700874 }
875
Russell King8c7494a2012-04-23 13:56:25 +0100876 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700877 ret = omap2_mcspi_request_dma(spi);
878 if (ret < 0)
879 return ret;
880 }
881
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +0530882 ret = pm_runtime_get_sync(mcspi->dev);
Govindraj.R1f1a4382011-02-02 17:52:15 +0530883 if (ret < 0)
884 return ret;
Hemanth Va41ae1a2009-09-22 16:46:16 -0700885
Kyungmin Park86eeb6f2007-10-16 01:27:45 -0700886 ret = omap2_mcspi_setup_transfer(spi, NULL);
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +0530887 pm_runtime_mark_last_busy(mcspi->dev);
888 pm_runtime_put_autosuspend(mcspi->dev);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700889
890 return ret;
891}
892
893static void omap2_mcspi_cleanup(struct spi_device *spi)
894{
895 struct omap2_mcspi *mcspi;
896 struct omap2_mcspi_dma *mcspi_dma;
Tero Kristo89c05372009-09-22 16:46:17 -0700897 struct omap2_mcspi_cs *cs;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700898
899 mcspi = spi_master_get_devdata(spi->master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700900
Scott Ellis5e774942010-03-10 14:22:45 -0700901 if (spi->controller_state) {
902 /* Unlink controller state from context save list */
903 cs = spi->controller_state;
904 list_del(&cs->node);
Tero Kristo89c05372009-09-22 16:46:17 -0700905
Russell King10aa5a32012-06-18 11:27:04 +0100906 kfree(cs);
Scott Ellis5e774942010-03-10 14:22:45 -0700907 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700908
Scott Ellis99f1a432010-05-24 14:20:27 +0000909 if (spi->chip_select < spi->master->num_chipselect) {
910 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
911
Russell King53741ed2012-04-23 13:51:48 +0100912 if (mcspi_dma->dma_rx) {
913 dma_release_channel(mcspi_dma->dma_rx);
914 mcspi_dma->dma_rx = NULL;
Scott Ellis99f1a432010-05-24 14:20:27 +0000915 }
Russell King53741ed2012-04-23 13:51:48 +0100916 if (mcspi_dma->dma_tx) {
917 dma_release_channel(mcspi_dma->dma_tx);
918 mcspi_dma->dma_tx = NULL;
Scott Ellis99f1a432010-05-24 14:20:27 +0000919 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700920 }
921}
922
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530923static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700924{
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700925
926 /* We only enable one channel at a time -- the one whose message is
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530927 * -- although this controller would gladly
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700928 * arbitrate among multiple channels. This corresponds to "single
929 * channel" master mode. As a side effect, we need to manage the
930 * chipselect with the FORCE bit ... CS != channel enable.
931 */
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700932
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530933 struct spi_device *spi;
934 struct spi_transfer *t = NULL;
935 int cs_active = 0;
936 struct omap2_mcspi_cs *cs;
937 struct omap2_mcspi_device_config *cd;
938 int par_override = 0;
939 int status = 0;
940 u32 chconf;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700941
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530942 spi = m->spi;
943 cs = spi->controller_state;
944 cd = spi->controller_data;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700945
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530946 omap2_mcspi_set_enable(spi, 1);
947 list_for_each_entry(t, &m->transfers, transfer_list) {
948 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
949 status = -EINVAL;
950 break;
951 }
952 if (par_override || t->speed_hz || t->bits_per_word) {
953 par_override = 1;
954 status = omap2_mcspi_setup_transfer(spi, t);
955 if (status < 0)
956 break;
957 if (!t->speed_hz && !t->bits_per_word)
958 par_override = 0;
959 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700960
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +0530961 if (!cs_active) {
962 omap2_mcspi_force_cs(spi, 1);
963 cs_active = 1;
964 }
965
966 chconf = mcspi_cached_chconf0(spi);
967 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
968 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
969
970 if (t->tx_buf == NULL)
971 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
972 else if (t->rx_buf == NULL)
973 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
974
975 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
976 /* Turbo mode is for more than one word */
977 if (t->len > ((cs->word_len + 7) >> 3))
978 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
979 }
980
981 mcspi_write_chconf0(spi, chconf);
982
983 if (t->len) {
984 unsigned count;
985
986 /* RX_ONLY mode needs dummy data in TX reg */
987 if (t->tx_buf == NULL)
988 __raw_writel(0, cs->base
989 + OMAP2_MCSPI_TX0);
990
991 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
992 count = omap2_mcspi_txrx_dma(spi, t);
993 else
994 count = omap2_mcspi_txrx_pio(spi, t);
995 m->actual_length += count;
996
997 if (count != t->len) {
998 status = -EIO;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -0700999 break;
1000 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001001 }
1002
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301003 if (t->delay_usecs)
1004 udelay(t->delay_usecs);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001005
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301006 /* ignore the "leave it on after last xfer" hint */
1007 if (t->cs_change) {
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001008 omap2_mcspi_force_cs(spi, 0);
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301009 cs_active = 0;
1010 }
1011 }
1012 /* Restore defaults if they were overriden */
1013 if (par_override) {
1014 par_override = 0;
1015 status = omap2_mcspi_setup_transfer(spi, NULL);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001016 }
1017
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301018 if (cs_active)
1019 omap2_mcspi_force_cs(spi, 0);
Govindraj.R1f1a4382011-02-02 17:52:15 +05301020
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301021 omap2_mcspi_set_enable(spi, 0);
1022
1023 m->status = status;
1024
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001025}
1026
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301027static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1028 struct spi_message *m)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001029{
1030 struct omap2_mcspi *mcspi;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001031 struct spi_transfer *t;
1032
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301033 mcspi = spi_master_get_devdata(master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001034 m->actual_length = 0;
1035 m->status = 0;
1036
1037 /* reject invalid messages and transfers */
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301038 if (list_empty(&m->transfers))
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001039 return -EINVAL;
1040 list_for_each_entry(t, &m->transfers, transfer_list) {
1041 const void *tx_buf = t->tx_buf;
1042 void *rx_buf = t->rx_buf;
1043 unsigned len = t->len;
1044
1045 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1046 || (len && !(rx_buf || tx_buf))
1047 || (t->bits_per_word &&
1048 ( t->bits_per_word < 4
1049 || t->bits_per_word > 32))) {
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301050 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001051 t->speed_hz,
1052 len,
1053 tx_buf ? "tx" : "",
1054 rx_buf ? "rx" : "",
1055 t->bits_per_word);
1056 return -EINVAL;
1057 }
Hannu Heikkinen57d9c102011-02-24 21:31:33 +02001058 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301059 dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
Hannu Heikkinen57d9c102011-02-24 21:31:33 +02001060 t->speed_hz,
1061 OMAP2_MCSPI_MAX_FREQ >> 15);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001062 return -EINVAL;
1063 }
1064
1065 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1066 continue;
1067
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001068 if (tx_buf != NULL) {
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301069 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001070 len, DMA_TO_DEVICE);
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301071 if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1072 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001073 'T', len);
1074 return -EINVAL;
1075 }
1076 }
1077 if (rx_buf != NULL) {
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301078 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001079 DMA_FROM_DEVICE);
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301080 if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1081 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001082 'R', len);
1083 if (tx_buf != NULL)
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301084 dma_unmap_single(mcspi->dev, t->tx_dma,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001085 len, DMA_TO_DEVICE);
1086 return -EINVAL;
1087 }
1088 }
1089 }
1090
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301091 omap2_mcspi_work(mcspi, m);
1092 spi_finalize_current_message(master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001093 return 0;
1094}
1095
Arnd Bergmann24ab32752012-07-20 16:01:43 +05301096static int __devinit omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001097{
1098 struct spi_master *master = mcspi->master;
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301099 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301100 int ret = 0;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001101
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301102 ret = pm_runtime_get_sync(mcspi->dev);
Govindraj.R1f1a4382011-02-02 17:52:15 +05301103 if (ret < 0)
1104 return ret;
Jouni Hoganderddb22192009-07-29 15:02:11 -07001105
Shubhrajyoti D39f80522012-03-29 22:11:07 +05301106 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1107 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1108 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001109
1110 omap2_mcspi_set_master_mode(master);
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301111 pm_runtime_mark_last_busy(mcspi->dev);
1112 pm_runtime_put_autosuspend(mcspi->dev);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001113 return 0;
1114}
1115
Govindraj.R1f1a4382011-02-02 17:52:15 +05301116static int omap_mcspi_runtime_resume(struct device *dev)
1117{
1118 struct omap2_mcspi *mcspi;
1119 struct spi_master *master;
1120
1121 master = dev_get_drvdata(dev);
1122 mcspi = spi_master_get_devdata(master);
1123 omap2_mcspi_restore_ctx(mcspi);
1124
1125 return 0;
1126}
1127
Benoit Coussond5a80032012-02-15 18:37:34 +01001128static struct omap2_mcspi_platform_config omap2_pdata = {
1129 .regs_offset = 0,
1130};
1131
1132static struct omap2_mcspi_platform_config omap4_pdata = {
1133 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1134};
1135
1136static const struct of_device_id omap_mcspi_of_match[] = {
1137 {
1138 .compatible = "ti,omap2-mcspi",
1139 .data = &omap2_pdata,
1140 },
1141 {
1142 .compatible = "ti,omap4-mcspi",
1143 .data = &omap4_pdata,
1144 },
1145 { },
1146};
1147MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
Girishccc7bae2008-02-06 01:38:16 -08001148
Felipe Balbi7d6b6d82012-03-14 11:18:30 +02001149static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001150{
1151 struct spi_master *master;
Uwe Kleine-König83a01e72012-05-21 21:57:39 +02001152 const struct omap2_mcspi_platform_config *pdata;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001153 struct omap2_mcspi *mcspi;
1154 struct resource *r;
1155 int status = 0, i;
Benoit Coussond5a80032012-02-15 18:37:34 +01001156 u32 regs_offset = 0;
1157 static int bus_num = 1;
1158 struct device_node *node = pdev->dev.of_node;
1159 const struct of_device_id *match;
Matt Porterec155af2012-09-18 08:01:25 -04001160 struct pinctrl *pinctrl;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001161
1162 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1163 if (master == NULL) {
1164 dev_dbg(&pdev->dev, "master allocation failed\n");
1165 return -ENOMEM;
1166 }
1167
David Brownelle7db06b2009-06-17 16:26:04 -07001168 /* the spi->mode bits understood by this driver: */
1169 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1170
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001171 master->setup = omap2_mcspi_setup;
Shubhrajyoti D5fda88f2012-05-10 18:27:45 +05301172 master->prepare_transfer_hardware = omap2_prepare_transfer;
1173 master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1174 master->transfer_one_message = omap2_mcspi_transfer_one_message;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001175 master->cleanup = omap2_mcspi_cleanup;
Benoit Coussond5a80032012-02-15 18:37:34 +01001176 master->dev.of_node = node;
1177
Daniel Mack0384e902012-10-07 18:19:44 +02001178 dev_set_drvdata(&pdev->dev, master);
1179
1180 mcspi = spi_master_get_devdata(master);
1181 mcspi->master = master;
1182
Benoit Coussond5a80032012-02-15 18:37:34 +01001183 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1184 if (match) {
1185 u32 num_cs = 1; /* default number of chipselect */
1186 pdata = match->data;
1187
1188 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1189 master->num_chipselect = num_cs;
1190 master->bus_num = bus_num++;
Daniel Mack2cd45172012-11-14 11:14:26 +08001191 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1192 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
Benoit Coussond5a80032012-02-15 18:37:34 +01001193 } else {
1194 pdata = pdev->dev.platform_data;
1195 master->num_chipselect = pdata->num_cs;
1196 if (pdev->id != -1)
1197 master->bus_num = pdev->id;
Daniel Mack0384e902012-10-07 18:19:44 +02001198 mcspi->pin_dir = pdata->pin_dir;
Benoit Coussond5a80032012-02-15 18:37:34 +01001199 }
1200 regs_offset = pdata->regs_offset;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001201
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001202 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1203 if (r == NULL) {
1204 status = -ENODEV;
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301205 goto free_master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001206 }
Shubhrajyoti D1458d162011-10-24 15:54:24 +05301207
Benoit Coussond5a80032012-02-15 18:37:34 +01001208 r->start += regs_offset;
1209 r->end += regs_offset;
Shubhrajyoti D1458d162011-10-24 15:54:24 +05301210 mcspi->phys = r->start;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001211
Shubhrajyoti D1a77b122012-03-17 12:44:01 +05301212 mcspi->base = devm_request_and_ioremap(&pdev->dev, r);
Russell King55c381e2008-09-04 14:07:22 +01001213 if (!mcspi->base) {
1214 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1215 status = -ENOMEM;
Shubhrajyoti D1a77b122012-03-17 12:44:01 +05301216 goto free_master;
Russell King55c381e2008-09-04 14:07:22 +01001217 }
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001218
Govindraj.R1f1a4382011-02-02 17:52:15 +05301219 mcspi->dev = &pdev->dev;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001220
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301221 INIT_LIST_HEAD(&mcspi->ctx.cs);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001222
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001223 mcspi->dma_channels = kcalloc(master->num_chipselect,
1224 sizeof(struct omap2_mcspi_dma),
1225 GFP_KERNEL);
1226
1227 if (mcspi->dma_channels == NULL)
Shubhrajyoti D1a77b122012-03-17 12:44:01 +05301228 goto free_master;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001229
Charulatha V1a5d8192011-02-02 17:52:14 +05301230 for (i = 0; i < master->num_chipselect; i++) {
1231 char dma_ch_name[14];
1232 struct resource *dma_res;
1233
1234 sprintf(dma_ch_name, "rx%d", i);
1235 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1236 dma_ch_name);
1237 if (!dma_res) {
1238 dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1239 status = -ENODEV;
1240 break;
1241 }
1242
Charulatha V1a5d8192011-02-02 17:52:14 +05301243 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1244 sprintf(dma_ch_name, "tx%d", i);
1245 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1246 dma_ch_name);
1247 if (!dma_res) {
1248 dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1249 status = -ENODEV;
1250 break;
1251 }
1252
Charulatha V1a5d8192011-02-02 17:52:14 +05301253 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001254 }
1255
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301256 if (status < 0)
1257 goto dma_chnl_free;
1258
Matt Porterec155af2012-09-18 08:01:25 -04001259 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1260 if (IS_ERR(pinctrl))
1261 dev_warn(&pdev->dev,
1262 "pins are not configured from the driver\n");
1263
Shubhrajyoti D27b52842012-03-26 17:04:22 +05301264 pm_runtime_use_autosuspend(&pdev->dev);
1265 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
Govindraj.R1f1a4382011-02-02 17:52:15 +05301266 pm_runtime_enable(&pdev->dev);
1267
1268 if (status || omap2_mcspi_master_setup(mcspi) < 0)
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301269 goto disable_pm;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001270
1271 status = spi_register_master(master);
1272 if (status < 0)
Shubhrajyoti D37a2d842012-08-02 16:41:25 +05301273 goto disable_pm;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001274
1275 return status;
1276
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301277disable_pm:
Shubhrajyoti D751c9252011-10-28 17:14:18 +05301278 pm_runtime_disable(&pdev->dev);
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301279dma_chnl_free:
Govindraj.R1f1a4382011-02-02 17:52:15 +05301280 kfree(mcspi->dma_channels);
Shubhrajyoti D39f1b562011-10-28 17:14:19 +05301281free_master:
Shubhrajyoti D37a2d842012-08-02 16:41:25 +05301282 spi_master_put(master);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001283 return status;
1284}
1285
Felipe Balbi7d6b6d82012-03-14 11:18:30 +02001286static int __devexit omap2_mcspi_remove(struct platform_device *pdev)
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001287{
1288 struct spi_master *master;
1289 struct omap2_mcspi *mcspi;
1290 struct omap2_mcspi_dma *dma_channels;
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001291
1292 master = dev_get_drvdata(&pdev->dev);
1293 mcspi = spi_master_get_devdata(master);
1294 dma_channels = mcspi->dma_channels;
1295
Shubhrajyoti Da93a2022012-08-22 11:35:14 +05301296 pm_runtime_put_sync(mcspi->dev);
Shubhrajyoti D751c9252011-10-28 17:14:18 +05301297 pm_runtime_disable(&pdev->dev);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001298
1299 spi_unregister_master(master);
1300 kfree(dma_channels);
1301
1302 return 0;
1303}
1304
Kay Sievers7e38c3c2008-04-10 21:29:20 -07001305/* work with hotplug and coldplug */
1306MODULE_ALIAS("platform:omap2_mcspi");
1307
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001308#ifdef CONFIG_SUSPEND
1309/*
1310 * When SPI wake up from off-mode, CS is in activate state. If it was in
1311 * unactive state when driver was suspend, then force it to unactive state at
1312 * wake up.
1313 */
1314static int omap2_mcspi_resume(struct device *dev)
1315{
1316 struct spi_master *master = dev_get_drvdata(dev);
1317 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301318 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1319 struct omap2_mcspi_cs *cs;
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001320
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301321 pm_runtime_get_sync(mcspi->dev);
Benoit Cousson1bd897f82012-03-26 15:32:33 +05301322 list_for_each_entry(cs, &ctx->cs, node) {
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001323 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001324 /*
1325 * We need to toggle CS state for OMAP take this
1326 * change in account.
1327 */
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +05301328 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001329 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
Shubhrajyoti Daf4e9442012-08-22 11:35:13 +05301330 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001331 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1332 }
1333 }
Shubhrajyoti D034d3dc2012-08-22 11:35:12 +05301334 pm_runtime_mark_last_busy(mcspi->dev);
1335 pm_runtime_put_autosuspend(mcspi->dev);
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001336 return 0;
1337}
1338#else
1339#define omap2_mcspi_resume NULL
1340#endif
1341
1342static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1343 .resume = omap2_mcspi_resume,
Govindraj.R1f1a4382011-02-02 17:52:15 +05301344 .runtime_resume = omap_mcspi_runtime_resume,
Gregory CLEMENT42ce7fd2010-12-29 11:52:53 +01001345};
1346
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001347static struct platform_driver omap2_mcspi_driver = {
1348 .driver = {
1349 .name = "omap2_mcspi",
1350 .owner = THIS_MODULE,
Benoit Coussond5a80032012-02-15 18:37:34 +01001351 .pm = &omap2_mcspi_pm_ops,
1352 .of_match_table = omap_mcspi_of_match,
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001353 },
Felipe Balbi7d6b6d82012-03-14 11:18:30 +02001354 .probe = omap2_mcspi_probe,
1355 .remove = __devexit_p(omap2_mcspi_remove),
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001356};
1357
Felipe Balbi9fdca9d2012-03-14 11:18:31 +02001358module_platform_driver(omap2_mcspi_driver);
Samuel Ortizccdc7bf2007-07-17 04:04:13 -07001359MODULE_LICENSE("GPL");