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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/pci.h>
David Brownell075c1772007-04-26 00:12:06 -070014#include <linux/pm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <linux/module.h>
16#include <linux/spinlock.h>
Tim Schmielau4e57b682005-10-30 15:03:48 -080017#include <linux/string.h>
vignesh babu229f5af2007-08-13 18:23:14 +053018#include <linux/log2.h>
Shaohua Li7d715a62008-02-25 09:46:41 +080019#include <linux/pci-aspm.h>
Stephen Rothwellc300bd2fb2008-07-10 02:16:44 +020020#include <linux/pm_wakeup.h>
Sheng Yang8dd7f802008-10-21 17:38:25 +080021#include <linux/interrupt.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <asm/dma.h> /* isa_dma_bridge_buggy */
Yuji Shimada32a9a6822009-03-16 17:13:39 +090023#include <linux/device.h>
24#include <asm/setup.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090025#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
Alan Stern00240c32009-04-27 13:33:16 -040027const char *pci_power_names[] = {
28 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
29};
30EXPORT_SYMBOL_GPL(pci_power_names);
31
Rafael J. Wysockiaa8c6c92009-01-16 21:54:43 +010032unsigned int pci_pm_d3_delay = PCI_PM_D3_WAIT;
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
Jeff Garzik32a2eea2007-10-11 16:57:27 -040034#ifdef CONFIG_PCI_DOMAINS
35int pci_domains_supported = 1;
36#endif
37
Atsushi Nemoto4516a612007-02-05 16:36:06 -080038#define DEFAULT_CARDBUS_IO_SIZE (256)
39#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
40/* pci=cbmemsize=nnM,cbiosize=nn can override this */
41unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
42unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
43
Eric W. Biederman28760482009-09-09 14:09:24 -070044#define DEFAULT_HOTPLUG_IO_SIZE (256)
45#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
46/* pci=hpmemsize=nnM,hpiosize=nn can override this */
47unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
48unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
49
Jesse Barnesac1aa472009-10-26 13:20:44 -070050/*
51 * The default CLS is used if arch didn't set CLS explicitly and not
52 * all pci devices agree on the same value. Arch can override either
53 * the dfl or actual value as it sees fit. Don't forget this is
54 * measured in 32-bit words, not bytes.
55 */
Tejun Heo98e724c2009-10-08 18:59:53 +090056u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
Jesse Barnesac1aa472009-10-26 13:20:44 -070057u8 pci_cache_line_size;
58
Linus Torvalds1da177e2005-04-16 15:20:36 -070059/**
60 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
61 * @bus: pointer to PCI bus structure to search
62 *
63 * Given a PCI bus, returns the highest PCI bus number present in the set
64 * including the given PCI bus and its list of child PCI buses.
65 */
Sam Ravnborg96bde062007-03-26 21:53:30 -080066unsigned char pci_bus_max_busnr(struct pci_bus* bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -070067{
68 struct list_head *tmp;
69 unsigned char max, n;
70
Kristen Accardib82db5c2006-01-17 16:56:56 -080071 max = bus->subordinate;
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 list_for_each(tmp, &bus->children) {
73 n = pci_bus_max_busnr(pci_bus_b(tmp));
74 if(n > max)
75 max = n;
76 }
77 return max;
78}
Kristen Accardib82db5c2006-01-17 16:56:56 -080079EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -070080
Andrew Morton1684f5d2008-12-01 14:30:30 -080081#ifdef CONFIG_HAS_IOMEM
82void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
83{
84 /*
85 * Make sure the BAR is actually a memory resource, not an IO resource
86 */
87 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
88 WARN_ON(1);
89 return NULL;
90 }
91 return ioremap_nocache(pci_resource_start(pdev, bar),
92 pci_resource_len(pdev, bar));
93}
94EXPORT_SYMBOL_GPL(pci_ioremap_bar);
95#endif
96
Kristen Accardib82db5c2006-01-17 16:56:56 -080097#if 0
Linus Torvalds1da177e2005-04-16 15:20:36 -070098/**
99 * pci_max_busnr - returns maximum PCI bus number
100 *
101 * Returns the highest PCI bus number present in the system global list of
102 * PCI buses.
103 */
104unsigned char __devinit
105pci_max_busnr(void)
106{
107 struct pci_bus *bus = NULL;
108 unsigned char max, n;
109
110 max = 0;
111 while ((bus = pci_find_next_bus(bus)) != NULL) {
112 n = pci_bus_max_busnr(bus);
113 if(n > max)
114 max = n;
115 }
116 return max;
117}
118
Adrian Bunk54c762f2005-12-22 01:08:52 +0100119#endif /* 0 */
120
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100121#define PCI_FIND_CAP_TTL 48
122
123static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
124 u8 pos, int cap, int *ttl)
Roland Dreier24a4e372005-10-28 17:35:34 -0700125{
126 u8 id;
Roland Dreier24a4e372005-10-28 17:35:34 -0700127
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100128 while ((*ttl)--) {
Roland Dreier24a4e372005-10-28 17:35:34 -0700129 pci_bus_read_config_byte(bus, devfn, pos, &pos);
130 if (pos < 0x40)
131 break;
132 pos &= ~3;
133 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
134 &id);
135 if (id == 0xff)
136 break;
137 if (id == cap)
138 return pos;
139 pos += PCI_CAP_LIST_NEXT;
140 }
141 return 0;
142}
143
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100144static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
145 u8 pos, int cap)
146{
147 int ttl = PCI_FIND_CAP_TTL;
148
149 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
150}
151
Roland Dreier24a4e372005-10-28 17:35:34 -0700152int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
153{
154 return __pci_find_next_cap(dev->bus, dev->devfn,
155 pos + PCI_CAP_LIST_NEXT, cap);
156}
157EXPORT_SYMBOL_GPL(pci_find_next_capability);
158
Michael Ellermand3bac112006-11-22 18:26:16 +1100159static int __pci_bus_find_cap_start(struct pci_bus *bus,
160 unsigned int devfn, u8 hdr_type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161{
162 u16 status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163
164 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
165 if (!(status & PCI_STATUS_CAP_LIST))
166 return 0;
167
168 switch (hdr_type) {
169 case PCI_HEADER_TYPE_NORMAL:
170 case PCI_HEADER_TYPE_BRIDGE:
Michael Ellermand3bac112006-11-22 18:26:16 +1100171 return PCI_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172 case PCI_HEADER_TYPE_CARDBUS:
Michael Ellermand3bac112006-11-22 18:26:16 +1100173 return PCI_CB_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174 default:
175 return 0;
176 }
Michael Ellermand3bac112006-11-22 18:26:16 +1100177
178 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179}
180
181/**
182 * pci_find_capability - query for devices' capabilities
183 * @dev: PCI device to query
184 * @cap: capability code
185 *
186 * Tell if a device supports a given PCI capability.
187 * Returns the address of the requested capability structure within the
188 * device's PCI configuration space or 0 in case the device does not
189 * support it. Possible values for @cap:
190 *
191 * %PCI_CAP_ID_PM Power Management
192 * %PCI_CAP_ID_AGP Accelerated Graphics Port
193 * %PCI_CAP_ID_VPD Vital Product Data
194 * %PCI_CAP_ID_SLOTID Slot Identification
195 * %PCI_CAP_ID_MSI Message Signalled Interrupts
196 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
197 * %PCI_CAP_ID_PCIX PCI-X
198 * %PCI_CAP_ID_EXP PCI Express
199 */
200int pci_find_capability(struct pci_dev *dev, int cap)
201{
Michael Ellermand3bac112006-11-22 18:26:16 +1100202 int pos;
203
204 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
205 if (pos)
206 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
207
208 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209}
210
211/**
212 * pci_bus_find_capability - query for devices' capabilities
213 * @bus: the PCI bus to query
214 * @devfn: PCI device to query
215 * @cap: capability code
216 *
217 * Like pci_find_capability() but works for pci devices that do not have a
218 * pci_dev structure set up yet.
219 *
220 * Returns the address of the requested capability structure within the
221 * device's PCI configuration space or 0 in case the device does not
222 * support it.
223 */
224int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
225{
Michael Ellermand3bac112006-11-22 18:26:16 +1100226 int pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227 u8 hdr_type;
228
229 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
230
Michael Ellermand3bac112006-11-22 18:26:16 +1100231 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
232 if (pos)
233 pos = __pci_find_next_cap(bus, devfn, pos, cap);
234
235 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236}
237
238/**
239 * pci_find_ext_capability - Find an extended capability
240 * @dev: PCI device to query
241 * @cap: capability code
242 *
243 * Returns the address of the requested extended capability structure
244 * within the device's PCI configuration space or 0 if the device does
245 * not support it. Possible values for @cap:
246 *
247 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
248 * %PCI_EXT_CAP_ID_VC Virtual Channel
249 * %PCI_EXT_CAP_ID_DSN Device Serial Number
250 * %PCI_EXT_CAP_ID_PWR Power Budgeting
251 */
252int pci_find_ext_capability(struct pci_dev *dev, int cap)
253{
254 u32 header;
Zhao, Yu557848c2008-10-13 19:18:07 +0800255 int ttl;
256 int pos = PCI_CFG_SPACE_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257
Zhao, Yu557848c2008-10-13 19:18:07 +0800258 /* minimum 8 bytes per capability */
259 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
260
261 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262 return 0;
263
264 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
265 return 0;
266
267 /*
268 * If we have no capabilities, this is indicated by cap ID,
269 * cap version and next pointer all being 0.
270 */
271 if (header == 0)
272 return 0;
273
274 while (ttl-- > 0) {
275 if (PCI_EXT_CAP_ID(header) == cap)
276 return pos;
277
278 pos = PCI_EXT_CAP_NEXT(header);
Zhao, Yu557848c2008-10-13 19:18:07 +0800279 if (pos < PCI_CFG_SPACE_SIZE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280 break;
281
282 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
283 break;
284 }
285
286 return 0;
287}
Brice Goglin3a720d72006-05-23 06:10:01 -0400288EXPORT_SYMBOL_GPL(pci_find_ext_capability);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100290static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
291{
292 int rc, ttl = PCI_FIND_CAP_TTL;
293 u8 cap, mask;
294
295 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
296 mask = HT_3BIT_CAP_MASK;
297 else
298 mask = HT_5BIT_CAP_MASK;
299
300 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
301 PCI_CAP_ID_HT, &ttl);
302 while (pos) {
303 rc = pci_read_config_byte(dev, pos + 3, &cap);
304 if (rc != PCIBIOS_SUCCESSFUL)
305 return 0;
306
307 if ((cap & mask) == ht_cap)
308 return pos;
309
Brice Goglin47a4d5b2007-01-10 23:15:29 -0800310 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
311 pos + PCI_CAP_LIST_NEXT,
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100312 PCI_CAP_ID_HT, &ttl);
313 }
314
315 return 0;
316}
317/**
318 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
319 * @dev: PCI device to query
320 * @pos: Position from which to continue searching
321 * @ht_cap: Hypertransport capability code
322 *
323 * To be used in conjunction with pci_find_ht_capability() to search for
324 * all capabilities matching @ht_cap. @pos should always be a value returned
325 * from pci_find_ht_capability().
326 *
327 * NB. To be 100% safe against broken PCI devices, the caller should take
328 * steps to avoid an infinite loop.
329 */
330int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
331{
332 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
333}
334EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
335
336/**
337 * pci_find_ht_capability - query a device's Hypertransport capabilities
338 * @dev: PCI device to query
339 * @ht_cap: Hypertransport capability code
340 *
341 * Tell if a device supports a given Hypertransport capability.
342 * Returns an address within the device's PCI configuration space
343 * or 0 in case the device does not support the request capability.
344 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
345 * which has a Hypertransport capability matching @ht_cap.
346 */
347int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
348{
349 int pos;
350
351 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
352 if (pos)
353 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
354
355 return pos;
356}
357EXPORT_SYMBOL_GPL(pci_find_ht_capability);
358
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359/**
360 * pci_find_parent_resource - return resource region of parent bus of given region
361 * @dev: PCI device structure contains resources to be searched
362 * @res: child resource record for which parent is sought
363 *
364 * For given resource region of given device, return the resource
365 * region of parent bus the given region is contained in or where
366 * it should be allocated from.
367 */
368struct resource *
369pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
370{
371 const struct pci_bus *bus = dev->bus;
372 int i;
373 struct resource *best = NULL;
374
375 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
376 struct resource *r = bus->resource[i];
377 if (!r)
378 continue;
379 if (res->start && !(res->start >= r->start && res->end <= r->end))
380 continue; /* Not contained */
381 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
382 continue; /* Wrong type */
383 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
384 return r; /* Exact match */
Linus Torvalds8c8def22009-11-09 12:04:32 -0800385 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
386 if (r->flags & IORESOURCE_PREFETCH)
387 continue;
388 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
389 if (!best)
390 best = r;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391 }
392 return best;
393}
394
395/**
John W. Linville064b53db2005-07-27 10:19:44 -0400396 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
397 * @dev: PCI device to have its BARs restored
398 *
399 * Restore the BAR values for a given device, so as to make it
400 * accessible by its driver.
401 */
Adrian Bunkad6685992007-10-27 03:06:22 +0200402static void
John W. Linville064b53db2005-07-27 10:19:44 -0400403pci_restore_bars(struct pci_dev *dev)
404{
Yu Zhaobc5f5a82008-11-22 02:40:00 +0800405 int i;
John W. Linville064b53db2005-07-27 10:19:44 -0400406
Yu Zhaobc5f5a82008-11-22 02:40:00 +0800407 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
Yu Zhao14add802008-11-22 02:38:52 +0800408 pci_update_resource(dev, i);
John W. Linville064b53db2005-07-27 10:19:44 -0400409}
410
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200411static struct pci_platform_pm_ops *pci_platform_pm;
412
413int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
414{
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +0200415 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
416 || !ops->sleep_wake || !ops->can_wakeup)
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200417 return -EINVAL;
418 pci_platform_pm = ops;
419 return 0;
420}
421
422static inline bool platform_pci_power_manageable(struct pci_dev *dev)
423{
424 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
425}
426
427static inline int platform_pci_set_power_state(struct pci_dev *dev,
428 pci_power_t t)
429{
430 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
431}
432
433static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
434{
435 return pci_platform_pm ?
436 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
437}
Randy Dunlap8f7020d2005-10-23 11:57:38 -0700438
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +0200439static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
440{
441 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
442}
443
444static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
445{
446 return pci_platform_pm ?
447 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
448}
449
John W. Linville064b53db2005-07-27 10:19:44 -0400450/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200451 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
452 * given PCI device
453 * @dev: PCI device to handle.
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200454 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455 *
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200456 * RETURN VALUE:
457 * -EINVAL if the requested state is invalid.
458 * -EIO if device does not support PCI PM or its PM capabilities register has a
459 * wrong version, or device doesn't support the requested state.
460 * 0 if device already is in the requested state.
461 * 0 if device's power state has been successfully changed.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700462 */
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100463static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200465 u16 pmcsr;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200466 bool need_restore = false;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700467
Rafael J. Wysocki4a865902009-03-16 22:40:36 +0100468 /* Check if we're already there */
469 if (dev->current_state == state)
470 return 0;
471
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200472 if (!dev->pm_cap)
Andrew Lunncca03de2007-07-09 11:55:58 -0700473 return -EIO;
474
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200475 if (state < PCI_D0 || state > PCI_D3hot)
476 return -EINVAL;
477
Linus Torvalds1da177e2005-04-16 15:20:36 -0700478 /* Validate current state:
479 * Can enter D0 from any state, but if we can only go deeper
480 * to sleep if we're already in a low power state
481 */
Rafael J. Wysocki4a865902009-03-16 22:40:36 +0100482 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200483 && dev->current_state > state) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600484 dev_err(&dev->dev, "invalid power transition "
485 "(from state %d to %d)\n", dev->current_state, state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700486 return -EINVAL;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200487 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489 /* check if this device supports the desired state */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200490 if ((state == PCI_D1 && !dev->d1_support)
491 || (state == PCI_D2 && !dev->d2_support))
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700492 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200494 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
John W. Linville064b53db2005-07-27 10:19:44 -0400495
John W. Linville32a36582005-09-14 09:52:42 -0400496 /* If we're (effectively) in D3, force entire word to 0.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497 * This doesn't affect PME_Status, disables PME_En, and
498 * sets PowerState to 0.
499 */
John W. Linville32a36582005-09-14 09:52:42 -0400500 switch (dev->current_state) {
John W. Linvilled3535fb2005-09-28 17:50:51 -0400501 case PCI_D0:
502 case PCI_D1:
503 case PCI_D2:
504 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
505 pmcsr |= state;
506 break;
Rafael J. Wysockif62795f2009-05-18 22:51:12 +0200507 case PCI_D3hot:
508 case PCI_D3cold:
John W. Linville32a36582005-09-14 09:52:42 -0400509 case PCI_UNKNOWN: /* Boot-up */
510 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100511 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200512 need_restore = true;
John W. Linville32a36582005-09-14 09:52:42 -0400513 /* Fall-through: force to D0 */
John W. Linville32a36582005-09-14 09:52:42 -0400514 default:
John W. Linvilled3535fb2005-09-28 17:50:51 -0400515 pmcsr = 0;
John W. Linville32a36582005-09-14 09:52:42 -0400516 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517 }
518
519 /* enter specified state */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200520 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700521
522 /* Mandatory power management transition delays */
523 /* see PCI PM 1.1 5.6.1 table 18 */
524 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -0700525 msleep(pci_pm_d3_delay);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526 else if (state == PCI_D2 || dev->current_state == PCI_D2)
Rafael J. Wysockiaa8c6c92009-01-16 21:54:43 +0100527 udelay(PCI_PM_D2_DELAY);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528
Rafael J. Wysockie13cdbd2009-10-05 00:48:40 +0200529 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
530 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
531 if (dev->current_state != state && printk_ratelimit())
532 dev_info(&dev->dev, "Refused to change power state, "
533 "currently in D%d\n", dev->current_state);
John W. Linville064b53db2005-07-27 10:19:44 -0400534
535 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
536 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
537 * from D3hot to D0 _may_ perform an internal reset, thereby
538 * going to "D0 Uninitialized" rather than "D0 Initialized".
539 * For example, at least some versions of the 3c905B and the
540 * 3c556B exhibit this behaviour.
541 *
542 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
543 * devices in a D3hot state at boot. Consequently, we need to
544 * restore at least the BARs so that the device will be
545 * accessible to its driver.
546 */
547 if (need_restore)
548 pci_restore_bars(dev);
549
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100550 if (dev->bus->self)
Shaohua Li7d715a62008-02-25 09:46:41 +0800551 pcie_aspm_pm_state_change(dev->bus->self);
552
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553 return 0;
554}
555
556/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200557 * pci_update_current_state - Read PCI power state of given device from its
558 * PCI PM registers and cache it
559 * @dev: PCI device to handle.
Rafael J. Wysockif06fc0b2008-12-27 16:30:52 +0100560 * @state: State to cache in case the device doesn't have the PM capability
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200561 */
Rafael J. Wysocki734104292009-01-07 13:07:15 +0100562void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200563{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200564 if (dev->pm_cap) {
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200565 u16 pmcsr;
566
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200567 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200568 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
Rafael J. Wysockif06fc0b2008-12-27 16:30:52 +0100569 } else {
570 dev->current_state = state;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200571 }
572}
573
574/**
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100575 * pci_platform_power_transition - Use platform to change device power state
576 * @dev: PCI device to handle.
577 * @state: State to put the device into.
578 */
579static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
580{
581 int error;
582
583 if (platform_pci_power_manageable(dev)) {
584 error = platform_pci_set_power_state(dev, state);
585 if (!error)
586 pci_update_current_state(dev, state);
587 } else {
588 error = -ENODEV;
589 /* Fall back to PCI_D0 if native PM is not supported */
Rafael J. Wysockib3bad722009-05-17 20:17:06 +0200590 if (!dev->pm_cap)
591 dev->current_state = PCI_D0;
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100592 }
593
594 return error;
595}
596
597/**
598 * __pci_start_power_transition - Start power transition of a PCI device
599 * @dev: PCI device to handle.
600 * @state: State to put the device into.
601 */
602static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
603{
604 if (state == PCI_D0)
605 pci_platform_power_transition(dev, PCI_D0);
606}
607
608/**
609 * __pci_complete_power_transition - Complete power transition of a PCI device
610 * @dev: PCI device to handle.
611 * @state: State to put the device into.
612 *
613 * This function should not be called directly by device drivers.
614 */
615int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
616{
617 return state > PCI_D0 ?
618 pci_platform_power_transition(dev, state) : -EINVAL;
619}
620EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
621
622/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200623 * pci_set_power_state - Set the power state of a PCI device
624 * @dev: PCI device to handle.
625 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
626 *
Nick Andrew877d0312009-01-26 11:06:57 +0100627 * Transition a device to a new power state, using the platform firmware and/or
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200628 * the device's PCI PM registers.
629 *
630 * RETURN VALUE:
631 * -EINVAL if the requested state is invalid.
632 * -EIO if device does not support PCI PM or its PM capabilities register has a
633 * wrong version, or device doesn't support the requested state.
634 * 0 if device already is in the requested state.
635 * 0 if device's power state has been successfully changed.
636 */
637int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
638{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200639 int error;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200640
641 /* bound the state we're entering */
642 if (state > PCI_D3hot)
643 state = PCI_D3hot;
644 else if (state < PCI_D0)
645 state = PCI_D0;
646 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
647 /*
648 * If the device or the parent bridge do not support PCI PM,
649 * ignore the request if we're doing anything other than putting
650 * it into D0 (which would only happen on boot).
651 */
652 return 0;
653
Rafael J. Wysocki4a865902009-03-16 22:40:36 +0100654 /* Check if we're already there */
655 if (dev->current_state == state)
656 return 0;
657
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100658 __pci_start_power_transition(dev, state);
659
Alan Cox979b1792008-07-24 17:18:38 +0100660 /* This device is quirked not to be put into D3, so
661 don't put it in D3 */
662 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
663 return 0;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200664
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100665 error = pci_raw_set_power_state(dev, state);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200666
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100667 if (!__pci_complete_power_transition(dev, state))
668 error = 0;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200669
670 return error;
671}
672
673/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700674 * pci_choose_state - Choose the power state of a PCI device
675 * @dev: PCI device to be suspended
676 * @state: target sleep state for the whole system. This is the value
677 * that is passed to suspend() function.
678 *
679 * Returns PCI power state suitable for given device and given system
680 * message.
681 */
682
683pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
684{
Shaohua Liab826ca2007-07-20 10:03:22 +0800685 pci_power_t ret;
David Shaohua Li0f644742005-03-19 00:15:48 -0500686
Linus Torvalds1da177e2005-04-16 15:20:36 -0700687 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
688 return PCI_D0;
689
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200690 ret = platform_pci_choose_state(dev);
691 if (ret != PCI_POWER_ERROR)
692 return ret;
Pavel Machekca078ba2005-09-03 15:56:57 -0700693
694 switch (state.event) {
695 case PM_EVENT_ON:
696 return PCI_D0;
697 case PM_EVENT_FREEZE:
David Brownellb887d2e2006-08-14 23:11:05 -0700698 case PM_EVENT_PRETHAW:
699 /* REVISIT both freeze and pre-thaw "should" use D0 */
Pavel Machekca078ba2005-09-03 15:56:57 -0700700 case PM_EVENT_SUSPEND:
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +0100701 case PM_EVENT_HIBERNATE:
Pavel Machekca078ba2005-09-03 15:56:57 -0700702 return PCI_D3hot;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703 default:
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600704 dev_info(&dev->dev, "unrecognized suspend event %d\n",
705 state.event);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700706 BUG();
707 }
708 return PCI_D0;
709}
710
711EXPORT_SYMBOL(pci_choose_state);
712
Yu Zhao89858512009-02-16 02:55:47 +0800713#define PCI_EXP_SAVE_REGS 7
714
Yu Zhao1b6b8ce2009-04-09 14:57:39 +0800715#define pcie_cap_has_devctl(type, flags) 1
716#define pcie_cap_has_lnkctl(type, flags) \
717 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
718 (type == PCI_EXP_TYPE_ROOT_PORT || \
719 type == PCI_EXP_TYPE_ENDPOINT || \
720 type == PCI_EXP_TYPE_LEG_END))
721#define pcie_cap_has_sltctl(type, flags) \
722 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
723 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
724 (type == PCI_EXP_TYPE_DOWNSTREAM && \
725 (flags & PCI_EXP_FLAGS_SLOT))))
726#define pcie_cap_has_rtctl(type, flags) \
727 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
728 (type == PCI_EXP_TYPE_ROOT_PORT || \
729 type == PCI_EXP_TYPE_RC_EC))
730#define pcie_cap_has_devctl2(type, flags) \
731 ((flags & PCI_EXP_FLAGS_VERS) > 1)
732#define pcie_cap_has_lnkctl2(type, flags) \
733 ((flags & PCI_EXP_FLAGS_VERS) > 1)
734#define pcie_cap_has_sltctl2(type, flags) \
735 ((flags & PCI_EXP_FLAGS_VERS) > 1)
736
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300737static int pci_save_pcie_state(struct pci_dev *dev)
738{
739 int pos, i = 0;
740 struct pci_cap_saved_state *save_state;
741 u16 *cap;
Yu Zhao1b6b8ce2009-04-09 14:57:39 +0800742 u16 flags;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300743
Kenji Kaneshige06a1cba2009-11-11 14:30:56 +0900744 pos = pci_pcie_cap(dev);
745 if (!pos)
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300746 return 0;
747
Eric W. Biederman9f355752007-03-08 13:06:13 -0700748 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300749 if (!save_state) {
Harvey Harrisone496b612009-01-07 16:22:37 -0800750 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300751 return -ENOMEM;
752 }
753 cap = (u16 *)&save_state->data[0];
754
Yu Zhao1b6b8ce2009-04-09 14:57:39 +0800755 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
756
757 if (pcie_cap_has_devctl(dev->pcie_type, flags))
758 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
759 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
760 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
761 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
762 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
763 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
764 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
765 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
766 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
767 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
768 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
769 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
770 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
Rafael J. Wysocki63f48982008-12-07 22:02:58 +0100771
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300772 return 0;
773}
774
775static void pci_restore_pcie_state(struct pci_dev *dev)
776{
777 int i = 0, pos;
778 struct pci_cap_saved_state *save_state;
779 u16 *cap;
Yu Zhao1b6b8ce2009-04-09 14:57:39 +0800780 u16 flags;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300781
782 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
783 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
784 if (!save_state || pos <= 0)
785 return;
786 cap = (u16 *)&save_state->data[0];
787
Yu Zhao1b6b8ce2009-04-09 14:57:39 +0800788 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
789
790 if (pcie_cap_has_devctl(dev->pcie_type, flags))
791 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
792 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
793 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
794 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
795 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
796 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
797 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
798 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
799 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
800 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
801 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
802 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
803 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300804}
805
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800806
807static int pci_save_pcix_state(struct pci_dev *dev)
808{
Rafael J. Wysocki63f48982008-12-07 22:02:58 +0100809 int pos;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800810 struct pci_cap_saved_state *save_state;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800811
812 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
813 if (pos <= 0)
814 return 0;
815
Shaohua Lif34303d2007-12-18 09:56:47 +0800816 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800817 if (!save_state) {
Harvey Harrisone496b612009-01-07 16:22:37 -0800818 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800819 return -ENOMEM;
820 }
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800821
Rafael J. Wysocki63f48982008-12-07 22:02:58 +0100822 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
823
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800824 return 0;
825}
826
827static void pci_restore_pcix_state(struct pci_dev *dev)
828{
829 int i = 0, pos;
830 struct pci_cap_saved_state *save_state;
831 u16 *cap;
832
833 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
834 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
835 if (!save_state || pos <= 0)
836 return;
837 cap = (u16 *)&save_state->data[0];
838
839 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800840}
841
842
Linus Torvalds1da177e2005-04-16 15:20:36 -0700843/**
844 * pci_save_state - save the PCI configuration space of a device before suspending
845 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700846 */
847int
848pci_save_state(struct pci_dev *dev)
849{
850 int i;
851 /* XXX: 100% dword access ok here? */
852 for (i = 0; i < 16; i++)
Kleber Sacilotto de Souza9e0b5b22009-11-25 00:55:51 -0200853 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
Rafael J. Wysockiaa8c6c92009-01-16 21:54:43 +0100854 dev->state_saved = true;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300855 if ((i = pci_save_pcie_state(dev)) != 0)
856 return i;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800857 if ((i = pci_save_pcix_state(dev)) != 0)
858 return i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859 return 0;
860}
861
862/**
863 * pci_restore_state - Restore the saved state of a PCI device
864 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865 */
866int
867pci_restore_state(struct pci_dev *dev)
868{
869 int i;
Al Virob4482a42007-10-14 19:35:40 +0100870 u32 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871
Alek Duc82f63e2009-08-08 08:46:19 +0800872 if (!dev->state_saved)
873 return 0;
Rafael J. Wysocki4b77b0a2009-09-09 23:49:59 +0200874
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300875 /* PCI Express register must be restored first */
876 pci_restore_pcie_state(dev);
877
Yu, Luming8b8c8d22006-04-25 00:00:34 -0700878 /*
879 * The Base Address register should be programmed before the command
880 * register(s)
881 */
882 for (i = 15; i >= 0; i--) {
Dave Jones04d9c1a2006-04-18 21:06:51 -0700883 pci_read_config_dword(dev, i * 4, &val);
884 if (val != dev->saved_config_space[i]) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600885 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
886 "space at offset %#x (was %#x, writing %#x)\n",
887 i, val, (int)dev->saved_config_space[i]);
Dave Jones04d9c1a2006-04-18 21:06:51 -0700888 pci_write_config_dword(dev,i * 4,
889 dev->saved_config_space[i]);
890 }
891 }
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800892 pci_restore_pcix_state(dev);
Shaohua Li41017f02006-02-08 17:11:38 +0800893 pci_restore_msi_state(dev);
Yu Zhao8c5cdb62009-03-20 11:25:12 +0800894 pci_restore_iov_state(dev);
Michael Ellerman8fed4b62007-01-25 19:34:08 +1100895
Rafael J. Wysocki4b77b0a2009-09-09 23:49:59 +0200896 dev->state_saved = false;
897
Linus Torvalds1da177e2005-04-16 15:20:36 -0700898 return 0;
899}
900
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900901static int do_pci_enable_device(struct pci_dev *dev, int bars)
902{
903 int err;
904
905 err = pci_set_power_state(dev, PCI_D0);
906 if (err < 0 && err != -EIO)
907 return err;
908 err = pcibios_enable_device(dev, bars);
909 if (err < 0)
910 return err;
911 pci_fixup_device(pci_fixup_enable, dev);
912
913 return 0;
914}
915
916/**
Tejun Heo0b62e132007-07-27 14:43:35 +0900917 * pci_reenable_device - Resume abandoned device
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900918 * @dev: PCI device to be resumed
919 *
920 * Note this function is a backend of pci_default_resume and is not supposed
921 * to be called by normal code, write proper resume handler and use it instead.
922 */
Tejun Heo0b62e132007-07-27 14:43:35 +0900923int pci_reenable_device(struct pci_dev *dev)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900924{
Yuji Shimada296ccb02009-04-03 16:41:46 +0900925 if (pci_is_enabled(dev))
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900926 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
927 return 0;
928}
929
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100930static int __pci_enable_device_flags(struct pci_dev *dev,
931 resource_size_t flags)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700932{
933 int err;
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100934 int i, bars = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700935
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900936 if (atomic_add_return(1, &dev->enable_cnt) > 1)
937 return 0; /* already enabled */
938
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100939 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
940 if (dev->resource[i].flags & flags)
941 bars |= (1 << i);
942
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900943 err = do_pci_enable_device(dev, bars);
Greg Kroah-Hartman95a62962005-07-28 11:37:33 -0700944 if (err < 0)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +0900945 atomic_dec(&dev->enable_cnt);
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +0900946 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700947}
948
949/**
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100950 * pci_enable_device_io - Initialize a device for use with IO space
951 * @dev: PCI device to be initialized
952 *
953 * Initialize device before it's used by a driver. Ask low-level code
954 * to enable I/O resources. Wake up the device if it was suspended.
955 * Beware, this function can fail.
956 */
957int pci_enable_device_io(struct pci_dev *dev)
958{
959 return __pci_enable_device_flags(dev, IORESOURCE_IO);
960}
961
962/**
963 * pci_enable_device_mem - Initialize a device for use with Memory space
964 * @dev: PCI device to be initialized
965 *
966 * Initialize device before it's used by a driver. Ask low-level code
967 * to enable Memory resources. Wake up the device if it was suspended.
968 * Beware, this function can fail.
969 */
970int pci_enable_device_mem(struct pci_dev *dev)
971{
972 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
973}
974
Linus Torvalds1da177e2005-04-16 15:20:36 -0700975/**
976 * pci_enable_device - Initialize device before it's used by a driver.
977 * @dev: PCI device to be initialized
978 *
979 * Initialize device before it's used by a driver. Ask low-level code
980 * to enable I/O and memory. Wake up the device if it was suspended.
981 * Beware, this function can fail.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800982 *
983 * Note we don't actually enable the device many times if we call
984 * this function repeatedly (we just increment the count).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700985 */
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -0800986int pci_enable_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700987{
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +1100988 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700989}
990
Tejun Heo9ac78492007-01-20 16:00:26 +0900991/*
992 * Managed PCI resources. This manages device on/off, intx/msi/msix
993 * on/off and BAR regions. pci_dev itself records msi/msix status, so
994 * there's no need to track it separately. pci_devres is initialized
995 * when a device is enabled using managed PCI device enable interface.
996 */
997struct pci_devres {
Tejun Heo7f375f32007-02-25 04:36:01 -0800998 unsigned int enabled:1;
999 unsigned int pinned:1;
Tejun Heo9ac78492007-01-20 16:00:26 +09001000 unsigned int orig_intx:1;
1001 unsigned int restore_intx:1;
1002 u32 region_mask;
1003};
1004
1005static void pcim_release(struct device *gendev, void *res)
1006{
1007 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1008 struct pci_devres *this = res;
1009 int i;
1010
1011 if (dev->msi_enabled)
1012 pci_disable_msi(dev);
1013 if (dev->msix_enabled)
1014 pci_disable_msix(dev);
1015
1016 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1017 if (this->region_mask & (1 << i))
1018 pci_release_region(dev, i);
1019
1020 if (this->restore_intx)
1021 pci_intx(dev, this->orig_intx);
1022
Tejun Heo7f375f32007-02-25 04:36:01 -08001023 if (this->enabled && !this->pinned)
Tejun Heo9ac78492007-01-20 16:00:26 +09001024 pci_disable_device(dev);
1025}
1026
1027static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1028{
1029 struct pci_devres *dr, *new_dr;
1030
1031 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1032 if (dr)
1033 return dr;
1034
1035 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1036 if (!new_dr)
1037 return NULL;
1038 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1039}
1040
1041static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1042{
1043 if (pci_is_managed(pdev))
1044 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1045 return NULL;
1046}
1047
1048/**
1049 * pcim_enable_device - Managed pci_enable_device()
1050 * @pdev: PCI device to be initialized
1051 *
1052 * Managed pci_enable_device().
1053 */
1054int pcim_enable_device(struct pci_dev *pdev)
1055{
1056 struct pci_devres *dr;
1057 int rc;
1058
1059 dr = get_pci_dr(pdev);
1060 if (unlikely(!dr))
1061 return -ENOMEM;
Tejun Heob95d58e2008-01-30 18:20:04 +09001062 if (dr->enabled)
1063 return 0;
Tejun Heo9ac78492007-01-20 16:00:26 +09001064
1065 rc = pci_enable_device(pdev);
1066 if (!rc) {
1067 pdev->is_managed = 1;
Tejun Heo7f375f32007-02-25 04:36:01 -08001068 dr->enabled = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +09001069 }
1070 return rc;
1071}
1072
1073/**
1074 * pcim_pin_device - Pin managed PCI device
1075 * @pdev: PCI device to pin
1076 *
1077 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1078 * driver detach. @pdev must have been enabled with
1079 * pcim_enable_device().
1080 */
1081void pcim_pin_device(struct pci_dev *pdev)
1082{
1083 struct pci_devres *dr;
1084
1085 dr = find_pci_dr(pdev);
Tejun Heo7f375f32007-02-25 04:36:01 -08001086 WARN_ON(!dr || !dr->enabled);
Tejun Heo9ac78492007-01-20 16:00:26 +09001087 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -08001088 dr->pinned = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +09001089}
1090
Linus Torvalds1da177e2005-04-16 15:20:36 -07001091/**
1092 * pcibios_disable_device - disable arch specific PCI resources for device dev
1093 * @dev: the PCI device to disable
1094 *
1095 * Disables architecture specific PCI resources for the device. This
1096 * is the default implementation. Architecture implementations can
1097 * override this.
1098 */
1099void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1100
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001101static void do_pci_disable_device(struct pci_dev *dev)
1102{
1103 u16 pci_command;
1104
1105 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1106 if (pci_command & PCI_COMMAND_MASTER) {
1107 pci_command &= ~PCI_COMMAND_MASTER;
1108 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1109 }
1110
1111 pcibios_disable_device(dev);
1112}
1113
1114/**
1115 * pci_disable_enabled_device - Disable device without updating enable_cnt
1116 * @dev: PCI device to disable
1117 *
1118 * NOTE: This function is a backend of PCI power management routines and is
1119 * not supposed to be called drivers.
1120 */
1121void pci_disable_enabled_device(struct pci_dev *dev)
1122{
Yuji Shimada296ccb02009-04-03 16:41:46 +09001123 if (pci_is_enabled(dev))
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001124 do_pci_disable_device(dev);
1125}
1126
Linus Torvalds1da177e2005-04-16 15:20:36 -07001127/**
1128 * pci_disable_device - Disable PCI device after use
1129 * @dev: PCI device to be disabled
1130 *
1131 * Signal to the system that the PCI device is not in use by the system
1132 * anymore. This only involves disabling PCI bus-mastering, if active.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -08001133 *
1134 * Note we don't actually disable the device until all callers of
1135 * pci_device_enable() have called pci_device_disable().
Linus Torvalds1da177e2005-04-16 15:20:36 -07001136 */
1137void
1138pci_disable_device(struct pci_dev *dev)
1139{
Tejun Heo9ac78492007-01-20 16:00:26 +09001140 struct pci_devres *dr;
Shaohua Li99dc8042006-05-26 10:58:27 +08001141
Tejun Heo9ac78492007-01-20 16:00:26 +09001142 dr = find_pci_dr(dev);
1143 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -08001144 dr->enabled = 0;
Tejun Heo9ac78492007-01-20 16:00:26 +09001145
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -08001146 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1147 return;
1148
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001149 do_pci_disable_device(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001150
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001151 dev->is_busmaster = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001152}
1153
1154/**
Brian Kingf7bdd122007-04-06 16:39:36 -05001155 * pcibios_set_pcie_reset_state - set reset state for device dev
Stefan Assmann45e829e2009-12-03 06:49:24 -05001156 * @dev: the PCIe device reset
Brian Kingf7bdd122007-04-06 16:39:36 -05001157 * @state: Reset state to enter into
1158 *
1159 *
Stefan Assmann45e829e2009-12-03 06:49:24 -05001160 * Sets the PCIe reset state for the device. This is the default
Brian Kingf7bdd122007-04-06 16:39:36 -05001161 * implementation. Architecture implementations can override this.
1162 */
1163int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1164 enum pcie_reset_state state)
1165{
1166 return -EINVAL;
1167}
1168
1169/**
1170 * pci_set_pcie_reset_state - set reset state for device dev
Stefan Assmann45e829e2009-12-03 06:49:24 -05001171 * @dev: the PCIe device reset
Brian Kingf7bdd122007-04-06 16:39:36 -05001172 * @state: Reset state to enter into
1173 *
1174 *
1175 * Sets the PCI reset state for the device.
1176 */
1177int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1178{
1179 return pcibios_set_pcie_reset_state(dev, state);
1180}
1181
1182/**
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001183 * pci_pme_capable - check the capability of PCI device to generate PME#
1184 * @dev: PCI device to handle.
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001185 * @state: PCI state from which device will issue PME#.
1186 */
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02001187bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001188{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001189 if (!dev->pm_cap)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001190 return false;
1191
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001192 return !!(dev->pme_support & (1 << state));
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001193}
1194
1195/**
1196 * pci_pme_active - enable or disable PCI device's PME# function
1197 * @dev: PCI device to handle.
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001198 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1199 *
1200 * The caller must verify that the device is capable of generating PME# before
1201 * calling this function with @enable equal to 'true'.
1202 */
Rafael J. Wysocki5a6c9b62008-08-08 00:14:24 +02001203void pci_pme_active(struct pci_dev *dev, bool enable)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001204{
1205 u16 pmcsr;
1206
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001207 if (!dev->pm_cap)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001208 return;
1209
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001210 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001211 /* Clear PME_Status by writing 1 to it and enable PME# */
1212 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1213 if (!enable)
1214 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1215
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001216 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001217
Bjorn Helgaas10c3d712009-11-04 10:32:42 -07001218 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001219 enable ? "enabled" : "disabled");
1220}
1221
1222/**
David Brownell075c1772007-04-26 00:12:06 -07001223 * pci_enable_wake - enable PCI device as wakeup event source
1224 * @dev: PCI device affected
1225 * @state: PCI state from which device will issue wakeup events
1226 * @enable: True to enable event generation; false to disable
Linus Torvalds1da177e2005-04-16 15:20:36 -07001227 *
David Brownell075c1772007-04-26 00:12:06 -07001228 * This enables the device as a wakeup event source, or disables it.
1229 * When such events involves platform-specific hooks, those hooks are
1230 * called automatically by this routine.
1231 *
1232 * Devices with legacy power management (no standard PCI PM capabilities)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001233 * always require such platform hooks.
David Brownell075c1772007-04-26 00:12:06 -07001234 *
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001235 * RETURN VALUE:
1236 * 0 is returned on success
1237 * -EINVAL is returned if device is not supposed to wake up the system
1238 * Error code depending on the platform is returned if both the platform and
1239 * the native mechanism fail to enable the generation of wake-up events
Linus Torvalds1da177e2005-04-16 15:20:36 -07001240 */
Frans Pop7d9a73f2009-06-17 00:16:15 +02001241int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001242{
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001243 int ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001244
Alan Sternbebd5902008-12-16 14:06:58 -05001245 if (enable && !device_may_wakeup(&dev->dev))
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001246 return -EINVAL;
1247
Rafael J. Wysockie80bb092009-09-08 23:14:49 +02001248 /* Don't do the same thing twice in a row for one device. */
1249 if (!!enable == !!dev->wakeup_prepared)
1250 return 0;
1251
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001252 /*
1253 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1254 * Anderson we should be doing PME# wake enable followed by ACPI wake
1255 * enable. To disable wake-up we call the platform first, for symmetry.
David Brownell075c1772007-04-26 00:12:06 -07001256 */
1257
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001258 if (enable) {
1259 int error;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001260
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001261 if (pci_pme_capable(dev, state))
1262 pci_pme_active(dev, true);
1263 else
1264 ret = 1;
1265 error = platform_pci_sleep_wake(dev, true);
1266 if (ret)
1267 ret = error;
Rafael J. Wysockie80bb092009-09-08 23:14:49 +02001268 if (!ret)
1269 dev->wakeup_prepared = true;
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001270 } else {
1271 platform_pci_sleep_wake(dev, false);
1272 pci_pme_active(dev, false);
Rafael J. Wysockie80bb092009-09-08 23:14:49 +02001273 dev->wakeup_prepared = false;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001274 }
1275
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001276 return ret;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001277}
1278
1279/**
Rafael J. Wysocki0235c4f2008-08-18 21:38:00 +02001280 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1281 * @dev: PCI device to prepare
1282 * @enable: True to enable wake-up event generation; false to disable
1283 *
1284 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1285 * and this function allows them to set that up cleanly - pci_enable_wake()
1286 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1287 * ordering constraints.
1288 *
1289 * This function only returns error code if the device is not capable of
1290 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1291 * enable wake-up power for it.
1292 */
1293int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1294{
1295 return pci_pme_capable(dev, PCI_D3cold) ?
1296 pci_enable_wake(dev, PCI_D3cold, enable) :
1297 pci_enable_wake(dev, PCI_D3hot, enable);
1298}
1299
1300/**
Jesse Barnes37139072008-07-28 11:49:26 -07001301 * pci_target_state - find an appropriate low power state for a given PCI dev
1302 * @dev: PCI device
1303 *
1304 * Use underlying platform code to find a supported low power state for @dev.
1305 * If the platform can't manage @dev, return the deepest state from which it
1306 * can generate wake events, based on any available PME info.
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001307 */
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02001308pci_power_t pci_target_state(struct pci_dev *dev)
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001309{
1310 pci_power_t target_state = PCI_D3hot;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001311
1312 if (platform_pci_power_manageable(dev)) {
1313 /*
1314 * Call the platform to choose the target state of the device
1315 * and enable wake-up from this state if supported.
1316 */
1317 pci_power_t state = platform_pci_choose_state(dev);
1318
1319 switch (state) {
1320 case PCI_POWER_ERROR:
1321 case PCI_UNKNOWN:
1322 break;
1323 case PCI_D1:
1324 case PCI_D2:
1325 if (pci_no_d1d2(dev))
1326 break;
1327 default:
1328 target_state = state;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001329 }
Rafael J. Wysockid2abdf62009-06-14 21:25:02 +02001330 } else if (!dev->pm_cap) {
1331 target_state = PCI_D0;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001332 } else if (device_may_wakeup(&dev->dev)) {
1333 /*
1334 * Find the deepest state from which the device can generate
1335 * wake-up events, make it the target state and enable device
1336 * to generate PME#.
1337 */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001338 if (dev->pme_support) {
1339 while (target_state
1340 && !(dev->pme_support & (1 << target_state)))
1341 target_state--;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001342 }
1343 }
1344
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02001345 return target_state;
1346}
1347
1348/**
1349 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1350 * @dev: Device to handle.
1351 *
1352 * Choose the power state appropriate for the device depending on whether
1353 * it can wake up the system and/or is power manageable by the platform
1354 * (PCI_D3hot is the default) and put the device into that state.
1355 */
1356int pci_prepare_to_sleep(struct pci_dev *dev)
1357{
1358 pci_power_t target_state = pci_target_state(dev);
1359 int error;
1360
1361 if (target_state == PCI_POWER_ERROR)
1362 return -EIO;
1363
Rafael J. Wysocki8efb8c72009-03-30 21:46:27 +02001364 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
Rafael J. Wysockic157dfa2008-07-13 22:45:06 +02001365
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001366 error = pci_set_power_state(dev, target_state);
1367
1368 if (error)
1369 pci_enable_wake(dev, target_state, false);
1370
1371 return error;
1372}
1373
1374/**
Randy Dunlap443bd1c2008-07-21 09:27:18 -07001375 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001376 * @dev: Device to handle.
1377 *
1378 * Disable device's sytem wake-up capability and put it into D0.
1379 */
1380int pci_back_from_sleep(struct pci_dev *dev)
1381{
1382 pci_enable_wake(dev, PCI_D0, false);
1383 return pci_set_power_state(dev, PCI_D0);
1384}
1385
1386/**
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001387 * pci_pm_init - Initialize PM functions of given PCI device
1388 * @dev: PCI device to handle.
1389 */
1390void pci_pm_init(struct pci_dev *dev)
1391{
1392 int pm;
1393 u16 pmc;
David Brownell075c1772007-04-26 00:12:06 -07001394
Rafael J. Wysockie80bb092009-09-08 23:14:49 +02001395 dev->wakeup_prepared = false;
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001396 dev->pm_cap = 0;
1397
Linus Torvalds1da177e2005-04-16 15:20:36 -07001398 /* find PCI PM capability in list */
1399 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
David Brownell075c1772007-04-26 00:12:06 -07001400 if (!pm)
Linus Torvalds50246dd2009-01-16 08:14:51 -08001401 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001402 /* Check device's ability to generate PME# */
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001403 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001404
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001405 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1406 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1407 pmc & PCI_PM_CAP_VER_MASK);
Linus Torvalds50246dd2009-01-16 08:14:51 -08001408 return;
David Brownell075c1772007-04-26 00:12:06 -07001409 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001410
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001411 dev->pm_cap = pm;
1412
1413 dev->d1_support = false;
1414 dev->d2_support = false;
1415 if (!pci_no_d1d2(dev)) {
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06001416 if (pmc & PCI_PM_CAP_D1)
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001417 dev->d1_support = true;
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06001418 if (pmc & PCI_PM_CAP_D2)
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001419 dev->d2_support = true;
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06001420
1421 if (dev->d1_support || dev->d2_support)
1422 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
Jesse Barnesec84f122008-09-23 11:43:34 -07001423 dev->d1_support ? " D1" : "",
1424 dev->d2_support ? " D2" : "");
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001425 }
1426
1427 pmc &= PCI_PM_CAP_PME_MASK;
1428 if (pmc) {
Bjorn Helgaas10c3d712009-11-04 10:32:42 -07001429 dev_printk(KERN_DEBUG, &dev->dev,
1430 "PME# supported from%s%s%s%s%s\n",
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06001431 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1432 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1433 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1434 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1435 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001436 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001437 /*
1438 * Make device's PM flags reflect the wake-up capability, but
1439 * let the user space enable it to wake up the system as needed.
1440 */
1441 device_set_wakeup_capable(&dev->dev, true);
1442 device_set_wakeup_enable(&dev->dev, false);
1443 /* Disable the PME# generation functionality */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001444 pci_pme_active(dev, false);
1445 } else {
1446 dev->pme_support = 0;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001447 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001448}
1449
Yu Zhao58c3a722008-10-14 14:02:53 +08001450/**
Jesse Barneseb9c39d2008-12-17 12:10:05 -08001451 * platform_pci_wakeup_init - init platform wakeup if present
1452 * @dev: PCI device
1453 *
1454 * Some devices don't have PCI PM caps but can still generate wakeup
1455 * events through platform methods (like ACPI events). If @dev supports
1456 * platform wakeup events, set the device flag to indicate as much. This
1457 * may be redundant if the device also supports PCI PM caps, but double
1458 * initialization should be safe in that case.
1459 */
1460void platform_pci_wakeup_init(struct pci_dev *dev)
1461{
1462 if (!platform_pci_can_wakeup(dev))
1463 return;
1464
1465 device_set_wakeup_capable(&dev->dev, true);
1466 device_set_wakeup_enable(&dev->dev, false);
1467 platform_pci_sleep_wake(dev, false);
1468}
1469
1470/**
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01001471 * pci_add_save_buffer - allocate buffer for saving given capability registers
1472 * @dev: the PCI device
1473 * @cap: the capability to allocate the buffer for
1474 * @size: requested size of the buffer
1475 */
1476static int pci_add_cap_save_buffer(
1477 struct pci_dev *dev, char cap, unsigned int size)
1478{
1479 int pos;
1480 struct pci_cap_saved_state *save_state;
1481
1482 pos = pci_find_capability(dev, cap);
1483 if (pos <= 0)
1484 return 0;
1485
1486 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1487 if (!save_state)
1488 return -ENOMEM;
1489
1490 save_state->cap_nr = cap;
1491 pci_add_saved_cap(dev, save_state);
1492
1493 return 0;
1494}
1495
1496/**
1497 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1498 * @dev: the PCI device
1499 */
1500void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1501{
1502 int error;
1503
Yu Zhao89858512009-02-16 02:55:47 +08001504 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1505 PCI_EXP_SAVE_REGS * sizeof(u16));
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01001506 if (error)
1507 dev_err(&dev->dev,
1508 "unable to preallocate PCI Express save buffer\n");
1509
1510 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1511 if (error)
1512 dev_err(&dev->dev,
1513 "unable to preallocate PCI-X save buffer\n");
1514}
1515
1516/**
Yu Zhao58c3a722008-10-14 14:02:53 +08001517 * pci_enable_ari - enable ARI forwarding if hardware support it
1518 * @dev: the PCI device
1519 */
1520void pci_enable_ari(struct pci_dev *dev)
1521{
1522 int pos;
1523 u32 cap;
1524 u16 ctrl;
Zhao, Yu81135872008-10-23 13:15:39 +08001525 struct pci_dev *bridge;
Yu Zhao58c3a722008-10-14 14:02:53 +08001526
Kenji Kaneshige5f4d91a2009-11-11 14:36:17 +09001527 if (!pci_is_pcie(dev) || dev->devfn)
Yu Zhao58c3a722008-10-14 14:02:53 +08001528 return;
1529
Zhao, Yu81135872008-10-23 13:15:39 +08001530 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
Yu Zhao58c3a722008-10-14 14:02:53 +08001531 if (!pos)
1532 return;
1533
Zhao, Yu81135872008-10-23 13:15:39 +08001534 bridge = dev->bus->self;
Kenji Kaneshige5f4d91a2009-11-11 14:36:17 +09001535 if (!bridge || !pci_is_pcie(bridge))
Zhao, Yu81135872008-10-23 13:15:39 +08001536 return;
1537
Kenji Kaneshige06a1cba2009-11-11 14:30:56 +09001538 pos = pci_pcie_cap(bridge);
Zhao, Yu81135872008-10-23 13:15:39 +08001539 if (!pos)
1540 return;
1541
1542 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
Yu Zhao58c3a722008-10-14 14:02:53 +08001543 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1544 return;
1545
Zhao, Yu81135872008-10-23 13:15:39 +08001546 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
Yu Zhao58c3a722008-10-14 14:02:53 +08001547 ctrl |= PCI_EXP_DEVCTL2_ARI;
Zhao, Yu81135872008-10-23 13:15:39 +08001548 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
Yu Zhao58c3a722008-10-14 14:02:53 +08001549
Zhao, Yu81135872008-10-23 13:15:39 +08001550 bridge->ari_enabled = 1;
Yu Zhao58c3a722008-10-14 14:02:53 +08001551}
1552
Chris Wright5d990b62009-12-04 12:15:21 -08001553static int pci_acs_enable;
1554
1555/**
1556 * pci_request_acs - ask for ACS to be enabled if supported
1557 */
1558void pci_request_acs(void)
1559{
1560 pci_acs_enable = 1;
1561}
1562
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07001563/**
Allen Kayae21ee62009-10-07 10:27:17 -07001564 * pci_enable_acs - enable ACS if hardware support it
1565 * @dev: the PCI device
1566 */
1567void pci_enable_acs(struct pci_dev *dev)
1568{
1569 int pos;
1570 u16 cap;
1571 u16 ctrl;
1572
Chris Wright5d990b62009-12-04 12:15:21 -08001573 if (!pci_acs_enable)
1574 return;
1575
Kenji Kaneshige5f4d91a2009-11-11 14:36:17 +09001576 if (!pci_is_pcie(dev))
Allen Kayae21ee62009-10-07 10:27:17 -07001577 return;
1578
1579 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
1580 if (!pos)
1581 return;
1582
1583 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
1584 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1585
1586 /* Source Validation */
1587 ctrl |= (cap & PCI_ACS_SV);
1588
1589 /* P2P Request Redirect */
1590 ctrl |= (cap & PCI_ACS_RR);
1591
1592 /* P2P Completion Redirect */
1593 ctrl |= (cap & PCI_ACS_CR);
1594
1595 /* Upstream Forwarding */
1596 ctrl |= (cap & PCI_ACS_UF);
1597
1598 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1599}
1600
1601/**
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07001602 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1603 * @dev: the PCI device
1604 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1605 *
1606 * Perform INTx swizzling for a device behind one level of bridge. This is
1607 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
Matthew Wilcox46b952a2009-07-01 14:24:30 -07001608 * behind bridges on add-in cards. For devices with ARI enabled, the slot
1609 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
1610 * the PCI Express Base Specification, Revision 2.1)
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07001611 */
1612u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
1613{
Matthew Wilcox46b952a2009-07-01 14:24:30 -07001614 int slot;
1615
1616 if (pci_ari_enabled(dev->bus))
1617 slot = 0;
1618 else
1619 slot = PCI_SLOT(dev->devfn);
1620
1621 return (((pin - 1) + slot) % 4) + 1;
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07001622}
1623
Linus Torvalds1da177e2005-04-16 15:20:36 -07001624int
1625pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1626{
1627 u8 pin;
1628
Kristen Accardi514d2072005-11-02 16:24:39 -08001629 pin = dev->pin;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001630 if (!pin)
1631 return -1;
Bjorn Helgaas878f2e52008-12-09 16:11:46 -07001632
Kenji Kaneshige8784fd42009-05-26 16:07:33 +09001633 while (!pci_is_root_bus(dev->bus)) {
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07001634 pin = pci_swizzle_interrupt_pin(dev, pin);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001635 dev = dev->bus->self;
1636 }
1637 *bridge = dev;
1638 return pin;
1639}
1640
1641/**
Bjorn Helgaas68feac82008-12-16 21:36:55 -07001642 * pci_common_swizzle - swizzle INTx all the way to root bridge
1643 * @dev: the PCI device
1644 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1645 *
1646 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1647 * bridges all the way up to a PCI root bus.
1648 */
1649u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
1650{
1651 u8 pin = *pinp;
1652
Kenji Kaneshige1eb39482009-05-26 16:08:36 +09001653 while (!pci_is_root_bus(dev->bus)) {
Bjorn Helgaas68feac82008-12-16 21:36:55 -07001654 pin = pci_swizzle_interrupt_pin(dev, pin);
1655 dev = dev->bus->self;
1656 }
1657 *pinp = pin;
1658 return PCI_SLOT(dev->devfn);
1659}
1660
1661/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07001662 * pci_release_region - Release a PCI bar
1663 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1664 * @bar: BAR to release
1665 *
1666 * Releases the PCI I/O and memory resources previously reserved by a
1667 * successful call to pci_request_region. Call this function only
1668 * after all use of the PCI regions has ceased.
1669 */
1670void pci_release_region(struct pci_dev *pdev, int bar)
1671{
Tejun Heo9ac78492007-01-20 16:00:26 +09001672 struct pci_devres *dr;
1673
Linus Torvalds1da177e2005-04-16 15:20:36 -07001674 if (pci_resource_len(pdev, bar) == 0)
1675 return;
1676 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1677 release_region(pci_resource_start(pdev, bar),
1678 pci_resource_len(pdev, bar));
1679 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1680 release_mem_region(pci_resource_start(pdev, bar),
1681 pci_resource_len(pdev, bar));
Tejun Heo9ac78492007-01-20 16:00:26 +09001682
1683 dr = find_pci_dr(pdev);
1684 if (dr)
1685 dr->region_mask &= ~(1 << bar);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001686}
1687
1688/**
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08001689 * __pci_request_region - Reserved PCI I/O and memory resource
Linus Torvalds1da177e2005-04-16 15:20:36 -07001690 * @pdev: PCI device whose resources are to be reserved
1691 * @bar: BAR to be reserved
1692 * @res_name: Name to be associated with resource.
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08001693 * @exclusive: whether the region access is exclusive or not
Linus Torvalds1da177e2005-04-16 15:20:36 -07001694 *
1695 * Mark the PCI region associated with PCI device @pdev BR @bar as
1696 * being reserved by owner @res_name. Do not access any
1697 * address inside the PCI regions unless this call returns
1698 * successfully.
1699 *
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08001700 * If @exclusive is set, then the region is marked so that userspace
1701 * is explicitly not allowed to map the resource via /dev/mem or
1702 * sysfs MMIO access.
1703 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07001704 * Returns 0 on success, or %EBUSY on error. A warning
1705 * message is also printed on failure.
1706 */
Arjan van de Vene8de1482008-10-22 19:55:31 -07001707static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
1708 int exclusive)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001709{
Tejun Heo9ac78492007-01-20 16:00:26 +09001710 struct pci_devres *dr;
1711
Linus Torvalds1da177e2005-04-16 15:20:36 -07001712 if (pci_resource_len(pdev, bar) == 0)
1713 return 0;
1714
1715 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1716 if (!request_region(pci_resource_start(pdev, bar),
1717 pci_resource_len(pdev, bar), res_name))
1718 goto err_out;
1719 }
1720 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
Arjan van de Vene8de1482008-10-22 19:55:31 -07001721 if (!__request_mem_region(pci_resource_start(pdev, bar),
1722 pci_resource_len(pdev, bar), res_name,
1723 exclusive))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001724 goto err_out;
1725 }
Tejun Heo9ac78492007-01-20 16:00:26 +09001726
1727 dr = find_pci_dr(pdev);
1728 if (dr)
1729 dr->region_mask |= 1 << bar;
1730
Linus Torvalds1da177e2005-04-16 15:20:36 -07001731 return 0;
1732
1733err_out:
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -06001734 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
Benjamin Herrenschmidt096e6f62008-10-20 15:07:37 +11001735 &pdev->resource[bar]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001736 return -EBUSY;
1737}
1738
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001739/**
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08001740 * pci_request_region - Reserve PCI I/O and memory resource
Arjan van de Vene8de1482008-10-22 19:55:31 -07001741 * @pdev: PCI device whose resources are to be reserved
1742 * @bar: BAR to be reserved
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08001743 * @res_name: Name to be associated with resource
Arjan van de Vene8de1482008-10-22 19:55:31 -07001744 *
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08001745 * Mark the PCI region associated with PCI device @pdev BAR @bar as
Arjan van de Vene8de1482008-10-22 19:55:31 -07001746 * being reserved by owner @res_name. Do not access any
1747 * address inside the PCI regions unless this call returns
1748 * successfully.
1749 *
1750 * Returns 0 on success, or %EBUSY on error. A warning
1751 * message is also printed on failure.
1752 */
1753int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1754{
1755 return __pci_request_region(pdev, bar, res_name, 0);
1756}
1757
1758/**
1759 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1760 * @pdev: PCI device whose resources are to be reserved
1761 * @bar: BAR to be reserved
1762 * @res_name: Name to be associated with resource.
1763 *
1764 * Mark the PCI region associated with PCI device @pdev BR @bar as
1765 * being reserved by owner @res_name. Do not access any
1766 * address inside the PCI regions unless this call returns
1767 * successfully.
1768 *
1769 * Returns 0 on success, or %EBUSY on error. A warning
1770 * message is also printed on failure.
1771 *
1772 * The key difference that _exclusive makes it that userspace is
1773 * explicitly not allowed to map the resource via /dev/mem or
1774 * sysfs.
1775 */
1776int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
1777{
1778 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
1779}
1780/**
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001781 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1782 * @pdev: PCI device whose resources were previously reserved
1783 * @bars: Bitmask of BARs to be released
1784 *
1785 * Release selected PCI I/O and memory resources previously reserved.
1786 * Call this function only after all use of the PCI regions has ceased.
1787 */
1788void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1789{
1790 int i;
1791
1792 for (i = 0; i < 6; i++)
1793 if (bars & (1 << i))
1794 pci_release_region(pdev, i);
1795}
1796
Arjan van de Vene8de1482008-10-22 19:55:31 -07001797int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
1798 const char *res_name, int excl)
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001799{
1800 int i;
1801
1802 for (i = 0; i < 6; i++)
1803 if (bars & (1 << i))
Arjan van de Vene8de1482008-10-22 19:55:31 -07001804 if (__pci_request_region(pdev, i, res_name, excl))
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001805 goto err_out;
1806 return 0;
1807
1808err_out:
1809 while(--i >= 0)
1810 if (bars & (1 << i))
1811 pci_release_region(pdev, i);
1812
1813 return -EBUSY;
1814}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001815
Arjan van de Vene8de1482008-10-22 19:55:31 -07001816
1817/**
1818 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1819 * @pdev: PCI device whose resources are to be reserved
1820 * @bars: Bitmask of BARs to be requested
1821 * @res_name: Name to be associated with resource
1822 */
1823int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1824 const char *res_name)
1825{
1826 return __pci_request_selected_regions(pdev, bars, res_name, 0);
1827}
1828
1829int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
1830 int bars, const char *res_name)
1831{
1832 return __pci_request_selected_regions(pdev, bars, res_name,
1833 IORESOURCE_EXCLUSIVE);
1834}
1835
Linus Torvalds1da177e2005-04-16 15:20:36 -07001836/**
1837 * pci_release_regions - Release reserved PCI I/O and memory resources
1838 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1839 *
1840 * Releases all PCI I/O and memory resources previously reserved by a
1841 * successful call to pci_request_regions. Call this function only
1842 * after all use of the PCI regions has ceased.
1843 */
1844
1845void pci_release_regions(struct pci_dev *pdev)
1846{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001847 pci_release_selected_regions(pdev, (1 << 6) - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001848}
1849
1850/**
1851 * pci_request_regions - Reserved PCI I/O and memory resources
1852 * @pdev: PCI device whose resources are to be reserved
1853 * @res_name: Name to be associated with resource.
1854 *
1855 * Mark all PCI regions associated with PCI device @pdev as
1856 * being reserved by owner @res_name. Do not access any
1857 * address inside the PCI regions unless this call returns
1858 * successfully.
1859 *
1860 * Returns 0 on success, or %EBUSY on error. A warning
1861 * message is also printed on failure.
1862 */
Jeff Garzik3c990e92006-03-04 21:52:42 -05001863int pci_request_regions(struct pci_dev *pdev, const char *res_name)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001864{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09001865 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001866}
1867
1868/**
Arjan van de Vene8de1482008-10-22 19:55:31 -07001869 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1870 * @pdev: PCI device whose resources are to be reserved
1871 * @res_name: Name to be associated with resource.
1872 *
1873 * Mark all PCI regions associated with PCI device @pdev as
1874 * being reserved by owner @res_name. Do not access any
1875 * address inside the PCI regions unless this call returns
1876 * successfully.
1877 *
1878 * pci_request_regions_exclusive() will mark the region so that
1879 * /dev/mem and the sysfs MMIO access will not be allowed.
1880 *
1881 * Returns 0 on success, or %EBUSY on error. A warning
1882 * message is also printed on failure.
1883 */
1884int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
1885{
1886 return pci_request_selected_regions_exclusive(pdev,
1887 ((1 << 6) - 1), res_name);
1888}
1889
Ben Hutchings6a479072008-12-23 03:08:29 +00001890static void __pci_set_master(struct pci_dev *dev, bool enable)
1891{
1892 u16 old_cmd, cmd;
1893
1894 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
1895 if (enable)
1896 cmd = old_cmd | PCI_COMMAND_MASTER;
1897 else
1898 cmd = old_cmd & ~PCI_COMMAND_MASTER;
1899 if (cmd != old_cmd) {
1900 dev_dbg(&dev->dev, "%s bus mastering\n",
1901 enable ? "enabling" : "disabling");
1902 pci_write_config_word(dev, PCI_COMMAND, cmd);
1903 }
1904 dev->is_busmaster = enable;
1905}
Arjan van de Vene8de1482008-10-22 19:55:31 -07001906
1907/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07001908 * pci_set_master - enables bus-mastering for device dev
1909 * @dev: the PCI device to enable
1910 *
1911 * Enables bus-mastering on the device and calls pcibios_set_master()
1912 * to do the needed arch specific settings.
1913 */
Ben Hutchings6a479072008-12-23 03:08:29 +00001914void pci_set_master(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001915{
Ben Hutchings6a479072008-12-23 03:08:29 +00001916 __pci_set_master(dev, true);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001917 pcibios_set_master(dev);
1918}
1919
Ben Hutchings6a479072008-12-23 03:08:29 +00001920/**
1921 * pci_clear_master - disables bus-mastering for device dev
1922 * @dev: the PCI device to disable
1923 */
1924void pci_clear_master(struct pci_dev *dev)
1925{
1926 __pci_set_master(dev, false);
1927}
1928
Linus Torvalds1da177e2005-04-16 15:20:36 -07001929/**
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001930 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1931 * @dev: the PCI device for which MWI is to be enabled
Linus Torvalds1da177e2005-04-16 15:20:36 -07001932 *
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001933 * Helper function for pci_set_mwi.
1934 * Originally copied from drivers/net/acenic.c.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001935 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1936 *
1937 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1938 */
Tejun Heo15ea76d2009-09-22 17:34:48 +09001939int pci_set_cacheline_size(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001940{
1941 u8 cacheline_size;
1942
1943 if (!pci_cache_line_size)
Tejun Heo15ea76d2009-09-22 17:34:48 +09001944 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001945
1946 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1947 equal to or multiple of the right value. */
1948 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1949 if (cacheline_size >= pci_cache_line_size &&
1950 (cacheline_size % pci_cache_line_size) == 0)
1951 return 0;
1952
1953 /* Write the correct value. */
1954 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1955 /* Read it back. */
1956 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1957 if (cacheline_size == pci_cache_line_size)
1958 return 0;
1959
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06001960 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
1961 "supported\n", pci_cache_line_size << 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001962
1963 return -EINVAL;
1964}
Tejun Heo15ea76d2009-09-22 17:34:48 +09001965EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
1966
1967#ifdef PCI_DISABLE_MWI
1968int pci_set_mwi(struct pci_dev *dev)
1969{
1970 return 0;
1971}
1972
1973int pci_try_set_mwi(struct pci_dev *dev)
1974{
1975 return 0;
1976}
1977
1978void pci_clear_mwi(struct pci_dev *dev)
1979{
1980}
1981
1982#else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001983
1984/**
1985 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1986 * @dev: the PCI device for which MWI is enabled
1987 *
Randy Dunlap694625c2007-07-09 11:55:54 -07001988 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001989 *
1990 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1991 */
1992int
1993pci_set_mwi(struct pci_dev *dev)
1994{
1995 int rc;
1996 u16 cmd;
1997
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06001998 rc = pci_set_cacheline_size(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001999 if (rc)
2000 return rc;
2001
2002 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2003 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06002004 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002005 cmd |= PCI_COMMAND_INVALIDATE;
2006 pci_write_config_word(dev, PCI_COMMAND, cmd);
2007 }
2008
2009 return 0;
2010}
2011
2012/**
Randy Dunlap694625c2007-07-09 11:55:54 -07002013 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2014 * @dev: the PCI device for which MWI is enabled
2015 *
2016 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2017 * Callers are not required to check the return value.
2018 *
2019 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2020 */
2021int pci_try_set_mwi(struct pci_dev *dev)
2022{
2023 int rc = pci_set_mwi(dev);
2024 return rc;
2025}
2026
2027/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07002028 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2029 * @dev: the PCI device to disable
2030 *
2031 * Disables PCI Memory-Write-Invalidate transaction on the device
2032 */
2033void
2034pci_clear_mwi(struct pci_dev *dev)
2035{
2036 u16 cmd;
2037
2038 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2039 if (cmd & PCI_COMMAND_INVALIDATE) {
2040 cmd &= ~PCI_COMMAND_INVALIDATE;
2041 pci_write_config_word(dev, PCI_COMMAND, cmd);
2042 }
2043}
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06002044#endif /* ! PCI_DISABLE_MWI */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002045
Brett M Russa04ce0f2005-08-15 15:23:41 -04002046/**
2047 * pci_intx - enables/disables PCI INTx for device dev
Randy Dunlap8f7020d2005-10-23 11:57:38 -07002048 * @pdev: the PCI device to operate on
2049 * @enable: boolean: whether to enable or disable PCI INTx
Brett M Russa04ce0f2005-08-15 15:23:41 -04002050 *
2051 * Enables/disables PCI INTx for device dev
2052 */
2053void
2054pci_intx(struct pci_dev *pdev, int enable)
2055{
2056 u16 pci_command, new;
2057
2058 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2059
2060 if (enable) {
2061 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2062 } else {
2063 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2064 }
2065
2066 if (new != pci_command) {
Tejun Heo9ac78492007-01-20 16:00:26 +09002067 struct pci_devres *dr;
2068
Brett M Russ2fd9d742005-09-09 10:02:22 -07002069 pci_write_config_word(pdev, PCI_COMMAND, new);
Tejun Heo9ac78492007-01-20 16:00:26 +09002070
2071 dr = find_pci_dr(pdev);
2072 if (dr && !dr->restore_intx) {
2073 dr->restore_intx = 1;
2074 dr->orig_intx = !enable;
2075 }
Brett M Russa04ce0f2005-08-15 15:23:41 -04002076 }
2077}
2078
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08002079/**
2080 * pci_msi_off - disables any msi or msix capabilities
Randy Dunlap8d7d86e2007-03-16 19:55:52 -07002081 * @dev: the PCI device to operate on
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08002082 *
2083 * If you want to use msi see pci_enable_msi and friends.
2084 * This is a lower level primitive that allows us to disable
2085 * msi operation at the device level.
2086 */
2087void pci_msi_off(struct pci_dev *dev)
2088{
2089 int pos;
2090 u16 control;
2091
2092 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2093 if (pos) {
2094 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2095 control &= ~PCI_MSI_FLAGS_ENABLE;
2096 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2097 }
2098 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2099 if (pos) {
2100 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2101 control &= ~PCI_MSIX_FLAGS_ENABLE;
2102 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2103 }
2104}
2105
Linus Torvalds1da177e2005-04-16 15:20:36 -07002106#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
2107/*
2108 * These can be overridden by arch-specific implementations
2109 */
2110int
2111pci_set_dma_mask(struct pci_dev *dev, u64 mask)
2112{
2113 if (!pci_dma_supported(dev, mask))
2114 return -EIO;
2115
2116 dev->dma_mask = mask;
Yinghai Luc6a41572009-11-25 16:28:50 -08002117 dev_dbg(&dev->dev, "using %dbit DMA mask\n", fls64(mask));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002118
2119 return 0;
2120}
2121
2122int
Linus Torvalds1da177e2005-04-16 15:20:36 -07002123pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
2124{
2125 if (!pci_dma_supported(dev, mask))
2126 return -EIO;
2127
2128 dev->dev.coherent_dma_mask = mask;
Yinghai Luc6a41572009-11-25 16:28:50 -08002129 dev_dbg(&dev->dev, "using %dbit consistent DMA mask\n", fls64(mask));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002130
2131 return 0;
2132}
2133#endif
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002134
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08002135#ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2136int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2137{
2138 return dma_set_max_seg_size(&dev->dev, size);
2139}
2140EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2141#endif
2142
FUJITA Tomonori59fc67d2008-02-04 22:28:14 -08002143#ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2144int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2145{
2146 return dma_set_seg_boundary(&dev->dev, mask);
2147}
2148EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2149#endif
2150
Yu Zhao8c1c6992009-06-13 15:52:13 +08002151static int pcie_flr(struct pci_dev *dev, int probe)
Sheng Yang8dd7f802008-10-21 17:38:25 +08002152{
Yu Zhao8c1c6992009-06-13 15:52:13 +08002153 int i;
2154 int pos;
Sheng Yang8dd7f802008-10-21 17:38:25 +08002155 u32 cap;
Shmulik Ravid04b55c42009-12-03 22:27:51 +02002156 u16 status, control;
Sheng Yang8dd7f802008-10-21 17:38:25 +08002157
Kenji Kaneshige06a1cba2009-11-11 14:30:56 +09002158 pos = pci_pcie_cap(dev);
Yu Zhao8c1c6992009-06-13 15:52:13 +08002159 if (!pos)
Sheng Yang8dd7f802008-10-21 17:38:25 +08002160 return -ENOTTY;
Yu Zhao8c1c6992009-06-13 15:52:13 +08002161
2162 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
Sheng Yang8dd7f802008-10-21 17:38:25 +08002163 if (!(cap & PCI_EXP_DEVCAP_FLR))
2164 return -ENOTTY;
2165
Sheng Yangd91cdc72008-11-11 17:17:47 +08002166 if (probe)
2167 return 0;
2168
Sheng Yang8dd7f802008-10-21 17:38:25 +08002169 /* Wait for Transaction Pending bit clean */
Yu Zhao8c1c6992009-06-13 15:52:13 +08002170 for (i = 0; i < 4; i++) {
2171 if (i)
2172 msleep((1 << (i - 1)) * 100);
Sheng Yang5fe5db02009-02-09 14:53:47 +08002173
Yu Zhao8c1c6992009-06-13 15:52:13 +08002174 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2175 if (!(status & PCI_EXP_DEVSTA_TRPND))
2176 goto clear;
2177 }
Sheng Yang8dd7f802008-10-21 17:38:25 +08002178
Yu Zhao8c1c6992009-06-13 15:52:13 +08002179 dev_err(&dev->dev, "transaction is not cleared; "
2180 "proceeding with reset anyway\n");
Sheng Yang5fe5db02009-02-09 14:53:47 +08002181
Yu Zhao8c1c6992009-06-13 15:52:13 +08002182clear:
Shmulik Ravid04b55c42009-12-03 22:27:51 +02002183 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2184 control |= PCI_EXP_DEVCTL_BCR_FLR;
2185 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2186
Yu Zhao8c1c6992009-06-13 15:52:13 +08002187 msleep(100);
Sheng Yang8dd7f802008-10-21 17:38:25 +08002188
Sheng Yang8dd7f802008-10-21 17:38:25 +08002189 return 0;
2190}
Sheng Yangd91cdc72008-11-11 17:17:47 +08002191
Yu Zhao8c1c6992009-06-13 15:52:13 +08002192static int pci_af_flr(struct pci_dev *dev, int probe)
Sheng Yang1ca88792008-11-11 17:17:48 +08002193{
Yu Zhao8c1c6992009-06-13 15:52:13 +08002194 int i;
2195 int pos;
Sheng Yang1ca88792008-11-11 17:17:48 +08002196 u8 cap;
Yu Zhao8c1c6992009-06-13 15:52:13 +08002197 u8 status;
Sheng Yang1ca88792008-11-11 17:17:48 +08002198
Yu Zhao8c1c6992009-06-13 15:52:13 +08002199 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2200 if (!pos)
Sheng Yang1ca88792008-11-11 17:17:48 +08002201 return -ENOTTY;
Yu Zhao8c1c6992009-06-13 15:52:13 +08002202
2203 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
Sheng Yang1ca88792008-11-11 17:17:48 +08002204 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2205 return -ENOTTY;
2206
2207 if (probe)
2208 return 0;
2209
Sheng Yang1ca88792008-11-11 17:17:48 +08002210 /* Wait for Transaction Pending bit clean */
Yu Zhao8c1c6992009-06-13 15:52:13 +08002211 for (i = 0; i < 4; i++) {
2212 if (i)
2213 msleep((1 << (i - 1)) * 100);
Sheng Yang5fe5db02009-02-09 14:53:47 +08002214
Yu Zhao8c1c6992009-06-13 15:52:13 +08002215 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2216 if (!(status & PCI_AF_STATUS_TP))
2217 goto clear;
2218 }
2219
2220 dev_err(&dev->dev, "transaction is not cleared; "
2221 "proceeding with reset anyway\n");
2222
2223clear:
2224 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
Sheng Yang1ca88792008-11-11 17:17:48 +08002225 msleep(100);
Sheng Yang5fe5db02009-02-09 14:53:47 +08002226
Sheng Yang1ca88792008-11-11 17:17:48 +08002227 return 0;
2228}
2229
Yu Zhaof85876b2009-06-13 15:52:14 +08002230static int pci_pm_reset(struct pci_dev *dev, int probe)
Sheng Yangd91cdc72008-11-11 17:17:47 +08002231{
Yu Zhaof85876b2009-06-13 15:52:14 +08002232 u16 csr;
Sheng Yangd91cdc72008-11-11 17:17:47 +08002233
Yu Zhaof85876b2009-06-13 15:52:14 +08002234 if (!dev->pm_cap)
2235 return -ENOTTY;
Sheng Yangd91cdc72008-11-11 17:17:47 +08002236
Yu Zhaof85876b2009-06-13 15:52:14 +08002237 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2238 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2239 return -ENOTTY;
Sheng Yang1ca88792008-11-11 17:17:48 +08002240
Yu Zhaof85876b2009-06-13 15:52:14 +08002241 if (probe)
2242 return 0;
2243
2244 if (dev->current_state != PCI_D0)
2245 return -EINVAL;
2246
2247 csr &= ~PCI_PM_CTRL_STATE_MASK;
2248 csr |= PCI_D3hot;
2249 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2250 msleep(pci_pm_d3_delay);
2251
2252 csr &= ~PCI_PM_CTRL_STATE_MASK;
2253 csr |= PCI_D0;
2254 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2255 msleep(pci_pm_d3_delay);
2256
2257 return 0;
2258}
2259
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08002260static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2261{
2262 u16 ctrl;
2263 struct pci_dev *pdev;
2264
Yu Zhao654b75e2009-06-26 14:04:46 +08002265 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08002266 return -ENOTTY;
2267
2268 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2269 if (pdev != dev)
2270 return -ENOTTY;
2271
2272 if (probe)
2273 return 0;
2274
2275 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2276 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2277 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2278 msleep(100);
2279
2280 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2281 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2282 msleep(100);
2283
2284 return 0;
2285}
2286
Dexuan Cuib9c3b262009-12-07 13:03:21 +08002287static int pci_dev_specific_reset(struct pci_dev *dev, int probe)
2288{
2289 struct pci_dev_reset_methods *i;
2290
2291 for (i = pci_dev_reset_methods; i->reset; i++) {
2292 if ((i->vendor == dev->vendor ||
2293 i->vendor == (u16)PCI_ANY_ID) &&
2294 (i->device == dev->device ||
2295 i->device == (u16)PCI_ANY_ID))
2296 return i->reset(dev, probe);
2297 }
2298
2299 return -ENOTTY;
2300}
2301
Yu Zhao8c1c6992009-06-13 15:52:13 +08002302static int pci_dev_reset(struct pci_dev *dev, int probe)
Sheng Yang8dd7f802008-10-21 17:38:25 +08002303{
Yu Zhao8c1c6992009-06-13 15:52:13 +08002304 int rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08002305
Yu Zhao8c1c6992009-06-13 15:52:13 +08002306 might_sleep();
Sheng Yang8dd7f802008-10-21 17:38:25 +08002307
Yu Zhao8c1c6992009-06-13 15:52:13 +08002308 if (!probe) {
2309 pci_block_user_cfg_access(dev);
2310 /* block PM suspend, driver probe, etc. */
2311 down(&dev->dev.sem);
2312 }
Sheng Yang8dd7f802008-10-21 17:38:25 +08002313
Dexuan Cuib9c3b262009-12-07 13:03:21 +08002314 rc = pci_dev_specific_reset(dev, probe);
2315 if (rc != -ENOTTY)
2316 goto done;
2317
Yu Zhao8c1c6992009-06-13 15:52:13 +08002318 rc = pcie_flr(dev, probe);
2319 if (rc != -ENOTTY)
2320 goto done;
2321
2322 rc = pci_af_flr(dev, probe);
Yu Zhaof85876b2009-06-13 15:52:14 +08002323 if (rc != -ENOTTY)
2324 goto done;
2325
2326 rc = pci_pm_reset(dev, probe);
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08002327 if (rc != -ENOTTY)
2328 goto done;
2329
2330 rc = pci_parent_bus_reset(dev, probe);
Yu Zhao8c1c6992009-06-13 15:52:13 +08002331done:
2332 if (!probe) {
2333 up(&dev->dev.sem);
2334 pci_unblock_user_cfg_access(dev);
2335 }
2336
2337 return rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08002338}
2339
2340/**
Yu Zhao8c1c6992009-06-13 15:52:13 +08002341 * __pci_reset_function - reset a PCI device function
2342 * @dev: PCI device to reset
Sheng Yang8dd7f802008-10-21 17:38:25 +08002343 *
2344 * Some devices allow an individual function to be reset without affecting
2345 * other functions in the same device. The PCI device must be responsive
2346 * to PCI config space in order to use this function.
2347 *
2348 * The device function is presumed to be unused when this function is called.
2349 * Resetting the device will make the contents of PCI configuration space
2350 * random, so any caller of this must be prepared to reinitialise the
2351 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2352 * etc.
2353 *
Yu Zhao8c1c6992009-06-13 15:52:13 +08002354 * Returns 0 if the device function was successfully reset or negative if the
Sheng Yang8dd7f802008-10-21 17:38:25 +08002355 * device doesn't support resetting a single function.
2356 */
Yu Zhao8c1c6992009-06-13 15:52:13 +08002357int __pci_reset_function(struct pci_dev *dev)
Sheng Yang8dd7f802008-10-21 17:38:25 +08002358{
Yu Zhao8c1c6992009-06-13 15:52:13 +08002359 return pci_dev_reset(dev, 0);
Sheng Yang8dd7f802008-10-21 17:38:25 +08002360}
Yu Zhao8c1c6992009-06-13 15:52:13 +08002361EXPORT_SYMBOL_GPL(__pci_reset_function);
Sheng Yang8dd7f802008-10-21 17:38:25 +08002362
2363/**
Michael S. Tsirkin711d5772009-07-27 23:37:48 +03002364 * pci_probe_reset_function - check whether the device can be safely reset
2365 * @dev: PCI device to reset
2366 *
2367 * Some devices allow an individual function to be reset without affecting
2368 * other functions in the same device. The PCI device must be responsive
2369 * to PCI config space in order to use this function.
2370 *
2371 * Returns 0 if the device function can be reset or negative if the
2372 * device doesn't support resetting a single function.
2373 */
2374int pci_probe_reset_function(struct pci_dev *dev)
2375{
2376 return pci_dev_reset(dev, 1);
2377}
2378
2379/**
Yu Zhao8c1c6992009-06-13 15:52:13 +08002380 * pci_reset_function - quiesce and reset a PCI device function
2381 * @dev: PCI device to reset
Sheng Yang8dd7f802008-10-21 17:38:25 +08002382 *
2383 * Some devices allow an individual function to be reset without affecting
2384 * other functions in the same device. The PCI device must be responsive
2385 * to PCI config space in order to use this function.
2386 *
2387 * This function does not just reset the PCI portion of a device, but
2388 * clears all the state associated with the device. This function differs
Yu Zhao8c1c6992009-06-13 15:52:13 +08002389 * from __pci_reset_function in that it saves and restores device state
Sheng Yang8dd7f802008-10-21 17:38:25 +08002390 * over the reset.
2391 *
Yu Zhao8c1c6992009-06-13 15:52:13 +08002392 * Returns 0 if the device function was successfully reset or negative if the
Sheng Yang8dd7f802008-10-21 17:38:25 +08002393 * device doesn't support resetting a single function.
2394 */
2395int pci_reset_function(struct pci_dev *dev)
2396{
Yu Zhao8c1c6992009-06-13 15:52:13 +08002397 int rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08002398
Yu Zhao8c1c6992009-06-13 15:52:13 +08002399 rc = pci_dev_reset(dev, 1);
2400 if (rc)
2401 return rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08002402
Sheng Yang8dd7f802008-10-21 17:38:25 +08002403 pci_save_state(dev);
2404
Yu Zhao8c1c6992009-06-13 15:52:13 +08002405 /*
2406 * both INTx and MSI are disabled after the Interrupt Disable bit
2407 * is set and the Bus Master bit is cleared.
2408 */
Sheng Yang8dd7f802008-10-21 17:38:25 +08002409 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2410
Yu Zhao8c1c6992009-06-13 15:52:13 +08002411 rc = pci_dev_reset(dev, 0);
Sheng Yang8dd7f802008-10-21 17:38:25 +08002412
2413 pci_restore_state(dev);
Sheng Yang8dd7f802008-10-21 17:38:25 +08002414
Yu Zhao8c1c6992009-06-13 15:52:13 +08002415 return rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08002416}
2417EXPORT_SYMBOL_GPL(pci_reset_function);
2418
2419/**
Peter Orubad556ad42007-05-15 13:59:13 +02002420 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2421 * @dev: PCI device to query
2422 *
2423 * Returns mmrbc: maximum designed memory read count in bytes
2424 * or appropriate error value.
2425 */
2426int pcix_get_max_mmrbc(struct pci_dev *dev)
2427{
Andrew Mortonb7b095c2007-07-09 11:55:50 -07002428 int err, cap;
Peter Orubad556ad42007-05-15 13:59:13 +02002429 u32 stat;
2430
2431 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2432 if (!cap)
2433 return -EINVAL;
2434
2435 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2436 if (err)
2437 return -EINVAL;
2438
Andrew Mortonb7b095c2007-07-09 11:55:50 -07002439 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
Peter Orubad556ad42007-05-15 13:59:13 +02002440}
2441EXPORT_SYMBOL(pcix_get_max_mmrbc);
2442
2443/**
2444 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2445 * @dev: PCI device to query
2446 *
2447 * Returns mmrbc: maximum memory read count in bytes
2448 * or appropriate error value.
2449 */
2450int pcix_get_mmrbc(struct pci_dev *dev)
2451{
2452 int ret, cap;
2453 u32 cmd;
2454
2455 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2456 if (!cap)
2457 return -EINVAL;
2458
2459 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2460 if (!ret)
2461 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
2462
2463 return ret;
2464}
2465EXPORT_SYMBOL(pcix_get_mmrbc);
2466
2467/**
2468 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2469 * @dev: PCI device to query
2470 * @mmrbc: maximum memory read count in bytes
2471 * valid values are 512, 1024, 2048, 4096
2472 *
2473 * If possible sets maximum memory read byte count, some bridges have erratas
2474 * that prevent this.
2475 */
2476int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
2477{
2478 int cap, err = -EINVAL;
2479 u32 stat, cmd, v, o;
2480
vignesh babu229f5af2007-08-13 18:23:14 +05302481 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
Peter Orubad556ad42007-05-15 13:59:13 +02002482 goto out;
2483
2484 v = ffs(mmrbc) - 10;
2485
2486 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2487 if (!cap)
2488 goto out;
2489
2490 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2491 if (err)
2492 goto out;
2493
2494 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
2495 return -E2BIG;
2496
2497 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2498 if (err)
2499 goto out;
2500
2501 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
2502 if (o != v) {
2503 if (v > o && dev->bus &&
2504 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
2505 return -EIO;
2506
2507 cmd &= ~PCI_X_CMD_MAX_READ;
2508 cmd |= v << 2;
2509 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
2510 }
2511out:
2512 return err;
2513}
2514EXPORT_SYMBOL(pcix_set_mmrbc);
2515
2516/**
2517 * pcie_get_readrq - get PCI Express read request size
2518 * @dev: PCI device to query
2519 *
2520 * Returns maximum memory read request in bytes
2521 * or appropriate error value.
2522 */
2523int pcie_get_readrq(struct pci_dev *dev)
2524{
2525 int ret, cap;
2526 u16 ctl;
2527
Kenji Kaneshige06a1cba2009-11-11 14:30:56 +09002528 cap = pci_pcie_cap(dev);
Peter Orubad556ad42007-05-15 13:59:13 +02002529 if (!cap)
2530 return -EINVAL;
2531
2532 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2533 if (!ret)
2534 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
2535
2536 return ret;
2537}
2538EXPORT_SYMBOL(pcie_get_readrq);
2539
2540/**
2541 * pcie_set_readrq - set PCI Express maximum memory read request
2542 * @dev: PCI device to query
Randy Dunlap42e61f42007-07-23 21:42:11 -07002543 * @rq: maximum memory read count in bytes
Peter Orubad556ad42007-05-15 13:59:13 +02002544 * valid values are 128, 256, 512, 1024, 2048, 4096
2545 *
2546 * If possible sets maximum read byte count
2547 */
2548int pcie_set_readrq(struct pci_dev *dev, int rq)
2549{
2550 int cap, err = -EINVAL;
2551 u16 ctl, v;
2552
vignesh babu229f5af2007-08-13 18:23:14 +05302553 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
Peter Orubad556ad42007-05-15 13:59:13 +02002554 goto out;
2555
2556 v = (ffs(rq) - 8) << 12;
2557
Kenji Kaneshige06a1cba2009-11-11 14:30:56 +09002558 cap = pci_pcie_cap(dev);
Peter Orubad556ad42007-05-15 13:59:13 +02002559 if (!cap)
2560 goto out;
2561
2562 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2563 if (err)
2564 goto out;
2565
2566 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
2567 ctl &= ~PCI_EXP_DEVCTL_READRQ;
2568 ctl |= v;
2569 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
2570 }
2571
2572out:
2573 return err;
2574}
2575EXPORT_SYMBOL(pcie_set_readrq);
2576
2577/**
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002578 * pci_select_bars - Make BAR mask from the type of resource
Randy Dunlapf95d8822007-02-10 14:41:56 -08002579 * @dev: the PCI device for which BAR mask is made
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002580 * @flags: resource type mask to be selected
2581 *
2582 * This helper routine makes bar mask from the type of resource.
2583 */
2584int pci_select_bars(struct pci_dev *dev, unsigned long flags)
2585{
2586 int i, bars = 0;
2587 for (i = 0; i < PCI_NUM_RESOURCES; i++)
2588 if (pci_resource_flags(dev, i) & flags)
2589 bars |= (1 << i);
2590 return bars;
2591}
2592
Yu Zhao613e7ed2008-11-22 02:41:27 +08002593/**
2594 * pci_resource_bar - get position of the BAR associated with a resource
2595 * @dev: the PCI device
2596 * @resno: the resource number
2597 * @type: the BAR type to be filled in
2598 *
2599 * Returns BAR position in config space, or 0 if the BAR is invalid.
2600 */
2601int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
2602{
Yu Zhaod1b054d2009-03-20 11:25:11 +08002603 int reg;
2604
Yu Zhao613e7ed2008-11-22 02:41:27 +08002605 if (resno < PCI_ROM_RESOURCE) {
2606 *type = pci_bar_unknown;
2607 return PCI_BASE_ADDRESS_0 + 4 * resno;
2608 } else if (resno == PCI_ROM_RESOURCE) {
2609 *type = pci_bar_mem32;
2610 return dev->rom_base_reg;
Yu Zhaod1b054d2009-03-20 11:25:11 +08002611 } else if (resno < PCI_BRIDGE_RESOURCES) {
2612 /* device specific resource */
2613 reg = pci_iov_resource_bar(dev, resno, type);
2614 if (reg)
2615 return reg;
Yu Zhao613e7ed2008-11-22 02:41:27 +08002616 }
2617
Bjorn Helgaas865df572009-11-04 10:32:57 -07002618 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
Yu Zhao613e7ed2008-11-22 02:41:27 +08002619 return 0;
2620}
2621
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10002622/**
2623 * pci_set_vga_state - set VGA decode state on device and parents if requested
Randy Dunlap19eea632009-09-17 15:28:22 -07002624 * @dev: the PCI device
2625 * @decode: true = enable decoding, false = disable decoding
2626 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2627 * @change_bridge: traverse ancestors and change bridges
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10002628 */
2629int pci_set_vga_state(struct pci_dev *dev, bool decode,
2630 unsigned int command_bits, bool change_bridge)
2631{
2632 struct pci_bus *bus;
2633 struct pci_dev *bridge;
2634 u16 cmd;
2635
2636 WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
2637
2638 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2639 if (decode == true)
2640 cmd |= command_bits;
2641 else
2642 cmd &= ~command_bits;
2643 pci_write_config_word(dev, PCI_COMMAND, cmd);
2644
2645 if (change_bridge == false)
2646 return 0;
2647
2648 bus = dev->bus;
2649 while (bus) {
2650 bridge = bus->self;
2651 if (bridge) {
2652 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
2653 &cmd);
2654 if (decode == true)
2655 cmd |= PCI_BRIDGE_CTL_VGA;
2656 else
2657 cmd &= ~PCI_BRIDGE_CTL_VGA;
2658 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
2659 cmd);
2660 }
2661 bus = bus->parent;
2662 }
2663 return 0;
2664}
2665
Yuji Shimada32a9a6822009-03-16 17:13:39 +09002666#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2667static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
Thomas Gleixnere9d1e492009-11-06 22:41:23 +00002668static DEFINE_SPINLOCK(resource_alignment_lock);
Yuji Shimada32a9a6822009-03-16 17:13:39 +09002669
2670/**
2671 * pci_specified_resource_alignment - get resource alignment specified by user.
2672 * @dev: the PCI device to get
2673 *
2674 * RETURNS: Resource alignment if it is specified.
2675 * Zero if it is not specified.
2676 */
2677resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
2678{
2679 int seg, bus, slot, func, align_order, count;
2680 resource_size_t align = 0;
2681 char *p;
2682
2683 spin_lock(&resource_alignment_lock);
2684 p = resource_alignment_param;
2685 while (*p) {
2686 count = 0;
2687 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
2688 p[count] == '@') {
2689 p += count + 1;
2690 } else {
2691 align_order = -1;
2692 }
2693 if (sscanf(p, "%x:%x:%x.%x%n",
2694 &seg, &bus, &slot, &func, &count) != 4) {
2695 seg = 0;
2696 if (sscanf(p, "%x:%x.%x%n",
2697 &bus, &slot, &func, &count) != 3) {
2698 /* Invalid format */
2699 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
2700 p);
2701 break;
2702 }
2703 }
2704 p += count;
2705 if (seg == pci_domain_nr(dev->bus) &&
2706 bus == dev->bus->number &&
2707 slot == PCI_SLOT(dev->devfn) &&
2708 func == PCI_FUNC(dev->devfn)) {
2709 if (align_order == -1) {
2710 align = PAGE_SIZE;
2711 } else {
2712 align = 1 << align_order;
2713 }
2714 /* Found */
2715 break;
2716 }
2717 if (*p != ';' && *p != ',') {
2718 /* End of param or invalid format */
2719 break;
2720 }
2721 p++;
2722 }
2723 spin_unlock(&resource_alignment_lock);
2724 return align;
2725}
2726
2727/**
2728 * pci_is_reassigndev - check if specified PCI is target device to reassign
2729 * @dev: the PCI device to check
2730 *
2731 * RETURNS: non-zero for PCI device is a target device to reassign,
2732 * or zero is not.
2733 */
2734int pci_is_reassigndev(struct pci_dev *dev)
2735{
2736 return (pci_specified_resource_alignment(dev) != 0);
2737}
2738
2739ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
2740{
2741 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
2742 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
2743 spin_lock(&resource_alignment_lock);
2744 strncpy(resource_alignment_param, buf, count);
2745 resource_alignment_param[count] = '\0';
2746 spin_unlock(&resource_alignment_lock);
2747 return count;
2748}
2749
2750ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
2751{
2752 size_t count;
2753 spin_lock(&resource_alignment_lock);
2754 count = snprintf(buf, size, "%s", resource_alignment_param);
2755 spin_unlock(&resource_alignment_lock);
2756 return count;
2757}
2758
2759static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
2760{
2761 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
2762}
2763
2764static ssize_t pci_resource_alignment_store(struct bus_type *bus,
2765 const char *buf, size_t count)
2766{
2767 return pci_set_resource_alignment_param(buf, count);
2768}
2769
2770BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
2771 pci_resource_alignment_store);
2772
2773static int __init pci_resource_alignment_sysfs_init(void)
2774{
2775 return bus_create_file(&pci_bus_type,
2776 &bus_attr_resource_alignment);
2777}
2778
2779late_initcall(pci_resource_alignment_sysfs_init);
2780
Jeff Garzik32a2eea2007-10-11 16:57:27 -04002781static void __devinit pci_no_domains(void)
2782{
2783#ifdef CONFIG_PCI_DOMAINS
2784 pci_domains_supported = 0;
2785#endif
2786}
2787
Andrew Patterson0ef5f8f2008-11-10 15:30:50 -07002788/**
2789 * pci_ext_cfg_enabled - can we access extended PCI config space?
2790 * @dev: The PCI device of the root bridge.
2791 *
2792 * Returns 1 if we can access PCI extended config space (offsets
2793 * greater than 0xff). This is the default implementation. Architecture
2794 * implementations can override this.
2795 */
2796int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
2797{
2798 return 1;
2799}
2800
Benjamin Herrenschmidt2d1c8612009-12-09 17:52:13 +11002801void __weak pci_fixup_cardbus(struct pci_bus *bus)
2802{
2803}
2804EXPORT_SYMBOL(pci_fixup_cardbus);
2805
Al Viroad04d312008-11-22 17:37:14 +00002806static int __init pci_setup(char *str)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002807{
2808 while (str) {
2809 char *k = strchr(str, ',');
2810 if (k)
2811 *k++ = 0;
2812 if (*str && (str = pcibios_setup(str)) && *str) {
Matthew Wilcox309e57d2006-03-05 22:33:34 -07002813 if (!strcmp(str, "nomsi")) {
2814 pci_no_msi();
Randy Dunlap7f785762007-10-05 13:17:58 -07002815 } else if (!strcmp(str, "noaer")) {
2816 pci_no_aer();
Jeff Garzik32a2eea2007-10-11 16:57:27 -04002817 } else if (!strcmp(str, "nodomains")) {
2818 pci_no_domains();
Atsushi Nemoto4516a612007-02-05 16:36:06 -08002819 } else if (!strncmp(str, "cbiosize=", 9)) {
2820 pci_cardbus_io_size = memparse(str + 9, &str);
2821 } else if (!strncmp(str, "cbmemsize=", 10)) {
2822 pci_cardbus_mem_size = memparse(str + 10, &str);
Yuji Shimada32a9a6822009-03-16 17:13:39 +09002823 } else if (!strncmp(str, "resource_alignment=", 19)) {
2824 pci_set_resource_alignment_param(str + 19,
2825 strlen(str + 19));
Andrew Patterson43c16402009-04-22 16:52:09 -06002826 } else if (!strncmp(str, "ecrc=", 5)) {
2827 pcie_ecrc_get_policy(str + 5);
Eric W. Biederman28760482009-09-09 14:09:24 -07002828 } else if (!strncmp(str, "hpiosize=", 9)) {
2829 pci_hotplug_io_size = memparse(str + 9, &str);
2830 } else if (!strncmp(str, "hpmemsize=", 10)) {
2831 pci_hotplug_mem_size = memparse(str + 10, &str);
Matthew Wilcox309e57d2006-03-05 22:33:34 -07002832 } else {
2833 printk(KERN_ERR "PCI: Unknown option `%s'\n",
2834 str);
2835 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002836 }
2837 str = k;
2838 }
Andi Kleen0637a702006-09-26 10:52:41 +02002839 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002840}
Andi Kleen0637a702006-09-26 10:52:41 +02002841early_param("pci", pci_setup);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002842
Tejun Heo0b62e132007-07-27 14:43:35 +09002843EXPORT_SYMBOL(pci_reenable_device);
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11002844EXPORT_SYMBOL(pci_enable_device_io);
2845EXPORT_SYMBOL(pci_enable_device_mem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002846EXPORT_SYMBOL(pci_enable_device);
Tejun Heo9ac78492007-01-20 16:00:26 +09002847EXPORT_SYMBOL(pcim_enable_device);
2848EXPORT_SYMBOL(pcim_pin_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002849EXPORT_SYMBOL(pci_disable_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002850EXPORT_SYMBOL(pci_find_capability);
2851EXPORT_SYMBOL(pci_bus_find_capability);
2852EXPORT_SYMBOL(pci_release_regions);
2853EXPORT_SYMBOL(pci_request_regions);
Arjan van de Vene8de1482008-10-22 19:55:31 -07002854EXPORT_SYMBOL(pci_request_regions_exclusive);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002855EXPORT_SYMBOL(pci_release_region);
2856EXPORT_SYMBOL(pci_request_region);
Arjan van de Vene8de1482008-10-22 19:55:31 -07002857EXPORT_SYMBOL(pci_request_region_exclusive);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002858EXPORT_SYMBOL(pci_release_selected_regions);
2859EXPORT_SYMBOL(pci_request_selected_regions);
Arjan van de Vene8de1482008-10-22 19:55:31 -07002860EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002861EXPORT_SYMBOL(pci_set_master);
Ben Hutchings6a479072008-12-23 03:08:29 +00002862EXPORT_SYMBOL(pci_clear_master);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002863EXPORT_SYMBOL(pci_set_mwi);
Randy Dunlap694625c2007-07-09 11:55:54 -07002864EXPORT_SYMBOL(pci_try_set_mwi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002865EXPORT_SYMBOL(pci_clear_mwi);
Brett M Russa04ce0f2005-08-15 15:23:41 -04002866EXPORT_SYMBOL_GPL(pci_intx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002867EXPORT_SYMBOL(pci_set_dma_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002868EXPORT_SYMBOL(pci_set_consistent_dma_mask);
2869EXPORT_SYMBOL(pci_assign_resource);
2870EXPORT_SYMBOL(pci_find_parent_resource);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002871EXPORT_SYMBOL(pci_select_bars);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002872
2873EXPORT_SYMBOL(pci_set_power_state);
2874EXPORT_SYMBOL(pci_save_state);
2875EXPORT_SYMBOL(pci_restore_state);
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02002876EXPORT_SYMBOL(pci_pme_capable);
Rafael J. Wysocki5a6c9b62008-08-08 00:14:24 +02002877EXPORT_SYMBOL(pci_pme_active);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002878EXPORT_SYMBOL(pci_enable_wake);
Rafael J. Wysocki0235c4f2008-08-18 21:38:00 +02002879EXPORT_SYMBOL(pci_wake_from_d3);
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02002880EXPORT_SYMBOL(pci_target_state);
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02002881EXPORT_SYMBOL(pci_prepare_to_sleep);
2882EXPORT_SYMBOL(pci_back_from_sleep);
Brian Kingf7bdd122007-04-06 16:39:36 -05002883EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002884