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Marc Zyngierde3ce082015-03-11 15:42:59 +00001/*
2 * Driver code for Tegra's Legacy Interrupt Controller
3 *
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Heavily based on the original arch/arm/mach-tegra/irq.c code:
7 * Copyright (C) 2011 Google, Inc.
8 *
9 * Author:
10 * Colin Cross <ccross@android.com>
11 *
12 * Copyright (C) 2010,2013, NVIDIA Corporation
13 *
14 * This software is licensed under the terms of the GNU General Public
15 * License version 2, as published by the Free Software Foundation, and
16 * may be copied, distributed, and modified under those terms.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 */
24
25#include <linux/io.h>
26#include <linux/irq.h>
Joel Porquet41a83e02015-07-07 17:11:46 -040027#include <linux/irqchip.h>
Marc Zyngierde3ce082015-03-11 15:42:59 +000028#include <linux/irqdomain.h>
29#include <linux/of_address.h>
30#include <linux/slab.h>
31#include <linux/syscore_ops.h>
32
33#include <dt-bindings/interrupt-controller/arm-gic.h>
34
Marc Zyngierde3ce082015-03-11 15:42:59 +000035#define ICTLR_CPU_IEP_VFIQ 0x08
36#define ICTLR_CPU_IEP_FIR 0x14
37#define ICTLR_CPU_IEP_FIR_SET 0x18
38#define ICTLR_CPU_IEP_FIR_CLR 0x1c
39
40#define ICTLR_CPU_IER 0x20
41#define ICTLR_CPU_IER_SET 0x24
42#define ICTLR_CPU_IER_CLR 0x28
43#define ICTLR_CPU_IEP_CLASS 0x2C
44
45#define ICTLR_COP_IER 0x30
46#define ICTLR_COP_IER_SET 0x34
47#define ICTLR_COP_IER_CLR 0x38
48#define ICTLR_COP_IEP_CLASS 0x3c
49
Thierry Reding1eec5822015-03-23 11:26:19 +010050#define TEGRA_MAX_NUM_ICTLRS 6
Marc Zyngierde3ce082015-03-11 15:42:59 +000051
52static unsigned int num_ictlrs;
53
54struct tegra_ictlr_soc {
55 unsigned int num_ictlrs;
56};
57
58static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
59 .num_ictlrs = 4,
60};
61
62static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
63 .num_ictlrs = 5,
64};
65
Thierry Reding1eec5822015-03-23 11:26:19 +010066static const struct tegra_ictlr_soc tegra210_ictlr_soc = {
67 .num_ictlrs = 6,
68};
69
Marc Zyngierde3ce082015-03-11 15:42:59 +000070static const struct of_device_id ictlr_matches[] = {
Thierry Reding1eec5822015-03-23 11:26:19 +010071 { .compatible = "nvidia,tegra210-ictlr", .data = &tegra210_ictlr_soc },
Marc Zyngierde3ce082015-03-11 15:42:59 +000072 { .compatible = "nvidia,tegra30-ictlr", .data = &tegra30_ictlr_soc },
73 { .compatible = "nvidia,tegra20-ictlr", .data = &tegra20_ictlr_soc },
74 { }
75};
76
77struct tegra_ictlr_info {
78 void __iomem *base[TEGRA_MAX_NUM_ICTLRS];
79#ifdef CONFIG_PM_SLEEP
80 u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
81 u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
82 u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
83 u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
84
85 u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
86#endif
87};
88
89static struct tegra_ictlr_info *lic;
90
91static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long reg)
92{
93 void __iomem *base = d->chip_data;
94 u32 mask;
95
96 mask = BIT(d->hwirq % 32);
97 writel_relaxed(mask, base + reg);
98}
99
100static void tegra_mask(struct irq_data *d)
101{
102 tegra_ictlr_write_mask(d, ICTLR_CPU_IER_CLR);
103 irq_chip_mask_parent(d);
104}
105
106static void tegra_unmask(struct irq_data *d)
107{
108 tegra_ictlr_write_mask(d, ICTLR_CPU_IER_SET);
109 irq_chip_unmask_parent(d);
110}
111
112static void tegra_eoi(struct irq_data *d)
113{
114 tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_CLR);
115 irq_chip_eoi_parent(d);
116}
117
118static int tegra_retrigger(struct irq_data *d)
119{
120 tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_SET);
121 return irq_chip_retrigger_hierarchy(d);
122}
123
124#ifdef CONFIG_PM_SLEEP
125static int tegra_set_wake(struct irq_data *d, unsigned int enable)
126{
127 u32 irq = d->hwirq;
128 u32 index, mask;
129
130 index = (irq / 32);
131 mask = BIT(irq % 32);
132 if (enable)
133 lic->ictlr_wake_mask[index] |= mask;
134 else
135 lic->ictlr_wake_mask[index] &= ~mask;
136
137 /*
138 * Do *not* call into the parent, as the GIC doesn't have any
139 * wake-up facility...
140 */
141 return 0;
142}
143
144static int tegra_ictlr_suspend(void)
145{
146 unsigned long flags;
147 unsigned int i;
148
149 local_irq_save(flags);
150 for (i = 0; i < num_ictlrs; i++) {
151 void __iomem *ictlr = lic->base[i];
152
153 /* Save interrupt state */
154 lic->cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
155 lic->cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);
156 lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
157 lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
158
159 /* Disable COP interrupts */
160 writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
161
162 /* Disable CPU interrupts */
163 writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
164
165 /* Enable the wakeup sources of ictlr */
166 writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
167 }
168 local_irq_restore(flags);
169
170 return 0;
171}
172
173static void tegra_ictlr_resume(void)
174{
175 unsigned long flags;
176 unsigned int i;
177
178 local_irq_save(flags);
179 for (i = 0; i < num_ictlrs; i++) {
180 void __iomem *ictlr = lic->base[i];
181
182 writel_relaxed(lic->cpu_iep[i],
183 ictlr + ICTLR_CPU_IEP_CLASS);
184 writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
185 writel_relaxed(lic->cpu_ier[i],
186 ictlr + ICTLR_CPU_IER_SET);
187 writel_relaxed(lic->cop_iep[i],
188 ictlr + ICTLR_COP_IEP_CLASS);
189 writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
190 writel_relaxed(lic->cop_ier[i],
191 ictlr + ICTLR_COP_IER_SET);
192 }
193 local_irq_restore(flags);
194}
195
196static struct syscore_ops tegra_ictlr_syscore_ops = {
197 .suspend = tegra_ictlr_suspend,
198 .resume = tegra_ictlr_resume,
199};
200
201static void tegra_ictlr_syscore_init(void)
202{
203 register_syscore_ops(&tegra_ictlr_syscore_ops);
204}
205#else
206#define tegra_set_wake NULL
207static inline void tegra_ictlr_syscore_init(void) {}
208#endif
209
210static struct irq_chip tegra_ictlr_chip = {
211 .name = "LIC",
212 .irq_eoi = tegra_eoi,
213 .irq_mask = tegra_mask,
214 .irq_unmask = tegra_unmask,
215 .irq_retrigger = tegra_retrigger,
216 .irq_set_wake = tegra_set_wake,
Lucas Stach209da392015-10-25 16:39:12 +0100217 .irq_set_type = irq_chip_set_type_parent,
Marc Zyngierde3ce082015-03-11 15:42:59 +0000218 .flags = IRQCHIP_MASK_ON_SUSPEND,
219#ifdef CONFIG_SMP
220 .irq_set_affinity = irq_chip_set_affinity_parent,
221#endif
222};
223
Marc Zyngierf833f572015-10-13 12:51:33 +0100224static int tegra_ictlr_domain_translate(struct irq_domain *d,
225 struct irq_fwspec *fwspec,
226 unsigned long *hwirq,
227 unsigned int *type)
Marc Zyngierde3ce082015-03-11 15:42:59 +0000228{
Marc Zyngierf833f572015-10-13 12:51:33 +0100229 if (is_of_node(fwspec->fwnode)) {
230 if (fwspec->param_count != 3)
231 return -EINVAL;
Marc Zyngierde3ce082015-03-11 15:42:59 +0000232
Marc Zyngierf833f572015-10-13 12:51:33 +0100233 /* No PPI should point to this domain */
234 if (fwspec->param[0] != 0)
235 return -EINVAL;
236
237 *hwirq = fwspec->param[1];
238 *type = fwspec->param[2];
239 return 0;
240 }
241
242 return -EINVAL;
Marc Zyngierde3ce082015-03-11 15:42:59 +0000243}
244
245static int tegra_ictlr_domain_alloc(struct irq_domain *domain,
246 unsigned int virq,
247 unsigned int nr_irqs, void *data)
248{
Marc Zyngierf833f572015-10-13 12:51:33 +0100249 struct irq_fwspec *fwspec = data;
250 struct irq_fwspec parent_fwspec;
Marc Zyngierde3ce082015-03-11 15:42:59 +0000251 struct tegra_ictlr_info *info = domain->host_data;
252 irq_hw_number_t hwirq;
253 unsigned int i;
254
Marc Zyngierf833f572015-10-13 12:51:33 +0100255 if (fwspec->param_count != 3)
Marc Zyngierde3ce082015-03-11 15:42:59 +0000256 return -EINVAL; /* Not GIC compliant */
Marc Zyngierf833f572015-10-13 12:51:33 +0100257 if (fwspec->param[0] != GIC_SPI)
Marc Zyngierde3ce082015-03-11 15:42:59 +0000258 return -EINVAL; /* No PPI should point to this domain */
259
Marc Zyngierf833f572015-10-13 12:51:33 +0100260 hwirq = fwspec->param[1];
Marc Zyngierde3ce082015-03-11 15:42:59 +0000261 if (hwirq >= (num_ictlrs * 32))
262 return -EINVAL;
263
264 for (i = 0; i < nr_irqs; i++) {
265 int ictlr = (hwirq + i) / 32;
266
267 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
268 &tegra_ictlr_chip,
Lucas Stach9cf82e72015-05-09 22:06:54 +0200269 info->base[ictlr]);
Marc Zyngierde3ce082015-03-11 15:42:59 +0000270 }
271
Marc Zyngierf833f572015-10-13 12:51:33 +0100272 parent_fwspec = *fwspec;
273 parent_fwspec.fwnode = domain->parent->fwnode;
274 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
275 &parent_fwspec);
Marc Zyngierde3ce082015-03-11 15:42:59 +0000276}
277
278static void tegra_ictlr_domain_free(struct irq_domain *domain,
279 unsigned int virq,
280 unsigned int nr_irqs)
281{
282 unsigned int i;
283
284 for (i = 0; i < nr_irqs; i++) {
285 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
286 irq_domain_reset_irq_data(d);
287 }
288}
289
290static const struct irq_domain_ops tegra_ictlr_domain_ops = {
Marc Zyngierf833f572015-10-13 12:51:33 +0100291 .translate = tegra_ictlr_domain_translate,
292 .alloc = tegra_ictlr_domain_alloc,
293 .free = tegra_ictlr_domain_free,
Marc Zyngierde3ce082015-03-11 15:42:59 +0000294};
295
296static int __init tegra_ictlr_init(struct device_node *node,
297 struct device_node *parent)
298{
299 struct irq_domain *parent_domain, *domain;
300 const struct of_device_id *match;
301 const struct tegra_ictlr_soc *soc;
302 unsigned int i;
303 int err;
304
305 if (!parent) {
306 pr_err("%s: no parent, giving up\n", node->full_name);
307 return -ENODEV;
308 }
309
310 parent_domain = irq_find_host(parent);
311 if (!parent_domain) {
312 pr_err("%s: unable to obtain parent domain\n", node->full_name);
313 return -ENXIO;
314 }
315
316 match = of_match_node(ictlr_matches, node);
317 if (!match) /* Should never happen... */
318 return -ENODEV;
319
320 soc = match->data;
321
322 lic = kzalloc(sizeof(*lic), GFP_KERNEL);
323 if (!lic)
324 return -ENOMEM;
325
326 for (i = 0; i < TEGRA_MAX_NUM_ICTLRS; i++) {
327 void __iomem *base;
328
329 base = of_iomap(node, i);
330 if (!base)
331 break;
332
333 lic->base[i] = base;
334
335 /* Disable all interrupts */
336 writel_relaxed(~0UL, base + ICTLR_CPU_IER_CLR);
337 /* All interrupts target IRQ */
338 writel_relaxed(0, base + ICTLR_CPU_IEP_CLASS);
339
340 num_ictlrs++;
341 }
342
343 if (!num_ictlrs) {
344 pr_err("%s: no valid regions, giving up\n", node->full_name);
345 err = -ENOMEM;
346 goto out_free;
347 }
348
349 WARN(num_ictlrs != soc->num_ictlrs,
350 "%s: Found %u interrupt controllers in DT; expected %u.\n",
351 node->full_name, num_ictlrs, soc->num_ictlrs);
352
353
354 domain = irq_domain_add_hierarchy(parent_domain, 0, num_ictlrs * 32,
355 node, &tegra_ictlr_domain_ops,
356 lic);
357 if (!domain) {
358 pr_err("%s: failed to allocated domain\n", node->full_name);
359 err = -ENOMEM;
360 goto out_unmap;
361 }
362
363 tegra_ictlr_syscore_init();
364
365 pr_info("%s: %d interrupts forwarded to %s\n",
366 node->full_name, num_ictlrs * 32, parent->full_name);
367
368 return 0;
369
370out_unmap:
371 for (i = 0; i < num_ictlrs; i++)
372 iounmap(lic->base[i]);
373out_free:
374 kfree(lic);
375 return err;
376}
377
378IRQCHIP_DECLARE(tegra20_ictlr, "nvidia,tegra20-ictlr", tegra_ictlr_init);
379IRQCHIP_DECLARE(tegra30_ictlr, "nvidia,tegra30-ictlr", tegra_ictlr_init);
Thierry Reding1eec5822015-03-23 11:26:19 +0100380IRQCHIP_DECLARE(tegra210_ictlr, "nvidia,tegra210-ictlr", tegra_ictlr_init);