R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * Based on "omap4.dtsi" |
| 8 | */ |
| 9 | |
| 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 11 | #include <dt-bindings/pinctrl/dra.h> |
| 12 | |
| 13 | #include "skeleton.dtsi" |
| 14 | |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 15 | #define MAX_SOURCES 400 |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 16 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 17 | / { |
| 18 | #address-cells = <1>; |
| 19 | #size-cells = <1>; |
| 20 | |
| 21 | compatible = "ti,dra7xx"; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 22 | interrupt-parent = <&crossbar_mpu>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 23 | |
| 24 | aliases { |
Nishanth Menon | 20b8094 | 2013-10-16 15:21:03 -0500 | [diff] [blame] | 25 | i2c0 = &i2c1; |
| 26 | i2c1 = &i2c2; |
| 27 | i2c2 = &i2c3; |
| 28 | i2c3 = &i2c4; |
| 29 | i2c4 = &i2c5; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 30 | serial0 = &uart1; |
| 31 | serial1 = &uart2; |
| 32 | serial2 = &uart3; |
| 33 | serial3 = &uart4; |
| 34 | serial4 = &uart5; |
| 35 | serial5 = &uart6; |
Nishanth Menon | 065bd7f | 2014-10-21 11:18:15 -0500 | [diff] [blame] | 36 | serial6 = &uart7; |
| 37 | serial7 = &uart8; |
| 38 | serial8 = &uart9; |
| 39 | serial9 = &uart10; |
Mugunthan V N | ef9c5b6 | 2014-10-21 15:31:00 +0530 | [diff] [blame] | 40 | ethernet0 = &cpsw_emac0; |
| 41 | ethernet1 = &cpsw_emac1; |
Roger Quadros | 9ec49b9 | 2014-08-15 16:08:36 +0300 | [diff] [blame] | 42 | d_can0 = &dcan1; |
| 43 | d_can1 = &dcan2; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 44 | }; |
| 45 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 46 | timer { |
| 47 | compatible = "arm,armv7-timer"; |
| 48 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 49 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 50 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 51 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 52 | interrupt-parent = <&gic>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 53 | }; |
| 54 | |
| 55 | gic: interrupt-controller@48211000 { |
| 56 | compatible = "arm,cortex-a15-gic"; |
| 57 | interrupt-controller; |
| 58 | #interrupt-cells = <3>; |
| 59 | reg = <0x48211000 0x1000>, |
| 60 | <0x48212000 0x1000>, |
| 61 | <0x48214000 0x2000>, |
| 62 | <0x48216000 0x2000>; |
| 63 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 64 | interrupt-parent = <&gic>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 65 | }; |
| 66 | |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 67 | wakeupgen: interrupt-controller@48281000 { |
| 68 | compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; |
| 69 | interrupt-controller; |
| 70 | #interrupt-cells = <3>; |
| 71 | reg = <0x48281000 0x1000>; |
| 72 | interrupt-parent = <&gic>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 73 | }; |
| 74 | |
| 75 | /* |
Geert Uytterhoeven | 5c5be9d | 2014-03-28 11:11:37 +0100 | [diff] [blame] | 76 | * The soc node represents the soc top level view. It is used for IPs |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 77 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 78 | */ |
| 79 | soc { |
| 80 | compatible = "ti,omap-infra"; |
| 81 | mpu { |
| 82 | compatible = "ti,omap5-mpu"; |
| 83 | ti,hwmods = "mpu"; |
| 84 | }; |
| 85 | }; |
| 86 | |
| 87 | /* |
| 88 | * XXX: Use a flat representation of the SOC interconnect. |
| 89 | * The real OMAP interconnect network is quite complex. |
Geert Uytterhoeven | b7ab524 | 2014-03-28 11:11:39 +0100 | [diff] [blame] | 90 | * Since it will not bring real advantage to represent that in DT for |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 91 | * the moment, just use a fake OCP bus entry to represent the whole bus |
| 92 | * hierarchy. |
| 93 | */ |
| 94 | ocp { |
Rajendra Nayak | fba387a | 2014-04-10 11:34:32 -0500 | [diff] [blame] | 95 | compatible = "ti,dra7-l3-noc", "simple-bus"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 96 | #address-cells = <1>; |
| 97 | #size-cells = <1>; |
| 98 | ranges; |
| 99 | ti,hwmods = "l3_main_1", "l3_main_2"; |
Rajendra Nayak | fba387a | 2014-04-10 11:34:32 -0500 | [diff] [blame] | 100 | reg = <0x44000000 0x1000000>, |
| 101 | <0x45000000 0x1000>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 102 | interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 103 | <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 104 | |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 105 | l4_cfg: l4@4a000000 { |
| 106 | compatible = "ti,dra7-l4-cfg", "simple-bus"; |
| 107 | #address-cells = <1>; |
| 108 | #size-cells = <1>; |
| 109 | ranges = <0 0x4a000000 0x22c000>; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 110 | |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 111 | scm: scm@2000 { |
| 112 | compatible = "ti,dra7-scm-core", "simple-bus"; |
| 113 | reg = <0x2000 0x2000>; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 114 | #address-cells = <1>; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 115 | #size-cells = <1>; |
| 116 | ranges = <0 0x2000 0x2000>; |
| 117 | |
| 118 | scm_conf: scm_conf@0 { |
| 119 | compatible = "syscon"; |
| 120 | reg = <0x0 0x1400>; |
| 121 | #address-cells = <1>; |
| 122 | #size-cells = <1>; |
| 123 | |
| 124 | pbias_regulator: pbias_regulator { |
| 125 | compatible = "ti,pbias-omap"; |
| 126 | reg = <0xe00 0x4>; |
| 127 | syscon = <&scm_conf>; |
| 128 | pbias_mmc_reg: pbias_mmc_omap5 { |
| 129 | regulator-name = "pbias_mmc_omap5"; |
| 130 | regulator-min-microvolt = <1800000>; |
| 131 | regulator-max-microvolt = <3000000>; |
| 132 | }; |
| 133 | }; |
| 134 | }; |
| 135 | |
| 136 | dra7_pmx_core: pinmux@1400 { |
| 137 | compatible = "ti,dra7-padconf", |
| 138 | "pinctrl-single"; |
| 139 | reg = <0x1400 0x0464>; |
| 140 | #address-cells = <1>; |
| 141 | #size-cells = <0>; |
| 142 | #interrupt-cells = <1>; |
| 143 | interrupt-controller; |
| 144 | pinctrl-single,register-width = <32>; |
| 145 | pinctrl-single,function-mask = <0x3fffffff>; |
| 146 | }; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 147 | }; |
| 148 | |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 149 | cm_core_aon: cm_core_aon@5000 { |
| 150 | compatible = "ti,dra7-cm-core-aon"; |
| 151 | reg = <0x5000 0x2000>; |
| 152 | |
| 153 | cm_core_aon_clocks: clocks { |
| 154 | #address-cells = <1>; |
| 155 | #size-cells = <0>; |
| 156 | }; |
| 157 | |
| 158 | cm_core_aon_clockdomains: clockdomains { |
| 159 | }; |
| 160 | }; |
| 161 | |
| 162 | cm_core: cm_core@8000 { |
| 163 | compatible = "ti,dra7-cm-core"; |
| 164 | reg = <0x8000 0x3000>; |
| 165 | |
| 166 | cm_core_clocks: clocks { |
| 167 | #address-cells = <1>; |
| 168 | #size-cells = <0>; |
| 169 | }; |
| 170 | |
| 171 | cm_core_clockdomains: clockdomains { |
| 172 | }; |
| 173 | }; |
| 174 | }; |
| 175 | |
| 176 | l4_wkup: l4@4ae00000 { |
| 177 | compatible = "ti,dra7-l4-wkup", "simple-bus"; |
| 178 | #address-cells = <1>; |
| 179 | #size-cells = <1>; |
| 180 | ranges = <0 0x4ae00000 0x3f000>; |
| 181 | |
| 182 | counter32k: counter@4000 { |
| 183 | compatible = "ti,omap-counter32k"; |
| 184 | reg = <0x4000 0x40>; |
| 185 | ti,hwmods = "counter_32k"; |
| 186 | }; |
| 187 | |
| 188 | prm: prm@6000 { |
| 189 | compatible = "ti,dra7-prm"; |
| 190 | reg = <0x6000 0x3000>; |
| 191 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| 192 | |
| 193 | prm_clocks: clocks { |
| 194 | #address-cells = <1>; |
| 195 | #size-cells = <0>; |
| 196 | }; |
| 197 | |
| 198 | prm_clockdomains: clockdomains { |
| 199 | }; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 200 | }; |
| 201 | }; |
| 202 | |
Kishon Vijay Abraham I | 18dcd79 | 2014-07-14 16:12:23 +0530 | [diff] [blame] | 203 | axi@0 { |
| 204 | compatible = "simple-bus"; |
| 205 | #size-cells = <1>; |
| 206 | #address-cells = <1>; |
| 207 | ranges = <0x51000000 0x51000000 0x3000 |
| 208 | 0x0 0x20000000 0x10000000>; |
| 209 | pcie@51000000 { |
| 210 | compatible = "ti,dra7-pcie"; |
| 211 | reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; |
| 212 | reg-names = "rc_dbics", "ti_conf", "config"; |
| 213 | interrupts = <0 232 0x4>, <0 233 0x4>; |
| 214 | #address-cells = <3>; |
| 215 | #size-cells = <2>; |
| 216 | device_type = "pci"; |
| 217 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 |
| 218 | 0x82000000 0 0x20013000 0x13000 0 0xffed000>; |
| 219 | #interrupt-cells = <1>; |
| 220 | num-lanes = <1>; |
| 221 | ti,hwmods = "pcie1"; |
| 222 | phys = <&pcie1_phy>; |
| 223 | phy-names = "pcie-phy0"; |
| 224 | interrupt-map-mask = <0 0 0 7>; |
| 225 | interrupt-map = <0 0 0 1 &pcie1_intc 1>, |
| 226 | <0 0 0 2 &pcie1_intc 2>, |
| 227 | <0 0 0 3 &pcie1_intc 3>, |
| 228 | <0 0 0 4 &pcie1_intc 4>; |
| 229 | pcie1_intc: interrupt-controller { |
| 230 | interrupt-controller; |
| 231 | #address-cells = <0>; |
| 232 | #interrupt-cells = <1>; |
| 233 | }; |
| 234 | }; |
| 235 | }; |
| 236 | |
| 237 | axi@1 { |
| 238 | compatible = "simple-bus"; |
| 239 | #size-cells = <1>; |
| 240 | #address-cells = <1>; |
| 241 | ranges = <0x51800000 0x51800000 0x3000 |
| 242 | 0x0 0x30000000 0x10000000>; |
| 243 | status = "disabled"; |
| 244 | pcie@51000000 { |
| 245 | compatible = "ti,dra7-pcie"; |
| 246 | reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; |
| 247 | reg-names = "rc_dbics", "ti_conf", "config"; |
| 248 | interrupts = <0 355 0x4>, <0 356 0x4>; |
| 249 | #address-cells = <3>; |
| 250 | #size-cells = <2>; |
| 251 | device_type = "pci"; |
| 252 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 |
| 253 | 0x82000000 0 0x30013000 0x13000 0 0xffed000>; |
| 254 | #interrupt-cells = <1>; |
| 255 | num-lanes = <1>; |
| 256 | ti,hwmods = "pcie2"; |
| 257 | phys = <&pcie2_phy>; |
| 258 | phy-names = "pcie-phy0"; |
| 259 | interrupt-map-mask = <0 0 0 7>; |
| 260 | interrupt-map = <0 0 0 1 &pcie2_intc 1>, |
| 261 | <0 0 0 2 &pcie2_intc 2>, |
| 262 | <0 0 0 3 &pcie2_intc 3>, |
| 263 | <0 0 0 4 &pcie2_intc 4>; |
| 264 | pcie2_intc: interrupt-controller { |
| 265 | interrupt-controller; |
| 266 | #address-cells = <0>; |
| 267 | #interrupt-cells = <1>; |
| 268 | }; |
| 269 | }; |
| 270 | }; |
| 271 | |
Keerthy | f7397ed | 2015-03-23 14:39:38 -0500 | [diff] [blame] | 272 | bandgap: bandgap@4a0021e0 { |
| 273 | reg = <0x4a0021e0 0xc |
| 274 | 0x4a00232c 0xc |
| 275 | 0x4a002380 0x2c |
| 276 | 0x4a0023C0 0x3c |
| 277 | 0x4a002564 0x8 |
| 278 | 0x4a002574 0x50>; |
| 279 | compatible = "ti,dra752-bandgap"; |
| 280 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
| 281 | #thermal-sensor-cells = <1>; |
| 282 | }; |
| 283 | |
Roger Quadros | ae3c0f7 | 2014-09-03 17:21:45 +0300 | [diff] [blame] | 284 | dra7_ctrl_core: ctrl_core@4a002000 { |
| 285 | compatible = "syscon"; |
| 286 | reg = <0x4a002000 0x6d0>; |
| 287 | }; |
| 288 | |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 289 | dra7_ctrl_general: tisyscon@4a002e00 { |
| 290 | compatible = "syscon"; |
| 291 | reg = <0x4a002e00 0x7c>; |
| 292 | }; |
| 293 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 294 | sdma: dma-controller@4a056000 { |
| 295 | compatible = "ti,omap4430-sdma"; |
| 296 | reg = <0x4a056000 0x1000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 297 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
| 298 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| 299 | <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 300 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 301 | #dma-cells = <1>; |
Peter Ujfalusi | 08d9b32 | 2015-02-20 15:42:06 +0200 | [diff] [blame] | 302 | dma-channels = <32>; |
| 303 | dma-requests = <127>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 304 | }; |
| 305 | |
| 306 | gpio1: gpio@4ae10000 { |
| 307 | compatible = "ti,omap4-gpio"; |
| 308 | reg = <0x4ae10000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 309 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 310 | ti,hwmods = "gpio1"; |
| 311 | gpio-controller; |
| 312 | #gpio-cells = <2>; |
| 313 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 314 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 315 | }; |
| 316 | |
| 317 | gpio2: gpio@48055000 { |
| 318 | compatible = "ti,omap4-gpio"; |
| 319 | reg = <0x48055000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 320 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 321 | ti,hwmods = "gpio2"; |
| 322 | gpio-controller; |
| 323 | #gpio-cells = <2>; |
| 324 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 325 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 326 | }; |
| 327 | |
| 328 | gpio3: gpio@48057000 { |
| 329 | compatible = "ti,omap4-gpio"; |
| 330 | reg = <0x48057000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 331 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 332 | ti,hwmods = "gpio3"; |
| 333 | gpio-controller; |
| 334 | #gpio-cells = <2>; |
| 335 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 336 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 337 | }; |
| 338 | |
| 339 | gpio4: gpio@48059000 { |
| 340 | compatible = "ti,omap4-gpio"; |
| 341 | reg = <0x48059000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 342 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 343 | ti,hwmods = "gpio4"; |
| 344 | gpio-controller; |
| 345 | #gpio-cells = <2>; |
| 346 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 347 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 348 | }; |
| 349 | |
| 350 | gpio5: gpio@4805b000 { |
| 351 | compatible = "ti,omap4-gpio"; |
| 352 | reg = <0x4805b000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 353 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 354 | ti,hwmods = "gpio5"; |
| 355 | gpio-controller; |
| 356 | #gpio-cells = <2>; |
| 357 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 358 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 359 | }; |
| 360 | |
| 361 | gpio6: gpio@4805d000 { |
| 362 | compatible = "ti,omap4-gpio"; |
| 363 | reg = <0x4805d000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 364 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 365 | ti,hwmods = "gpio6"; |
| 366 | gpio-controller; |
| 367 | #gpio-cells = <2>; |
| 368 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 369 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 370 | }; |
| 371 | |
| 372 | gpio7: gpio@48051000 { |
| 373 | compatible = "ti,omap4-gpio"; |
| 374 | reg = <0x48051000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 375 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 376 | ti,hwmods = "gpio7"; |
| 377 | gpio-controller; |
| 378 | #gpio-cells = <2>; |
| 379 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 380 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 381 | }; |
| 382 | |
| 383 | gpio8: gpio@48053000 { |
| 384 | compatible = "ti,omap4-gpio"; |
| 385 | reg = <0x48053000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 386 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 387 | ti,hwmods = "gpio8"; |
| 388 | gpio-controller; |
| 389 | #gpio-cells = <2>; |
| 390 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 391 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 392 | }; |
| 393 | |
| 394 | uart1: serial@4806a000 { |
| 395 | compatible = "ti,omap4-uart"; |
| 396 | reg = <0x4806a000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 397 | interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 398 | ti,hwmods = "uart1"; |
| 399 | clock-frequency = <48000000>; |
| 400 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 401 | dmas = <&sdma 49>, <&sdma 50>; |
| 402 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 403 | }; |
| 404 | |
| 405 | uart2: serial@4806c000 { |
| 406 | compatible = "ti,omap4-uart"; |
| 407 | reg = <0x4806c000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 408 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 409 | ti,hwmods = "uart2"; |
| 410 | clock-frequency = <48000000>; |
| 411 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 412 | dmas = <&sdma 51>, <&sdma 52>; |
| 413 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 414 | }; |
| 415 | |
| 416 | uart3: serial@48020000 { |
| 417 | compatible = "ti,omap4-uart"; |
| 418 | reg = <0x48020000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 419 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 420 | ti,hwmods = "uart3"; |
| 421 | clock-frequency = <48000000>; |
| 422 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 423 | dmas = <&sdma 53>, <&sdma 54>; |
| 424 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 425 | }; |
| 426 | |
| 427 | uart4: serial@4806e000 { |
| 428 | compatible = "ti,omap4-uart"; |
| 429 | reg = <0x4806e000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 430 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 431 | ti,hwmods = "uart4"; |
| 432 | clock-frequency = <48000000>; |
| 433 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 434 | dmas = <&sdma 55>, <&sdma 56>; |
| 435 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 436 | }; |
| 437 | |
| 438 | uart5: serial@48066000 { |
| 439 | compatible = "ti,omap4-uart"; |
| 440 | reg = <0x48066000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 441 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 442 | ti,hwmods = "uart5"; |
| 443 | clock-frequency = <48000000>; |
| 444 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 445 | dmas = <&sdma 63>, <&sdma 64>; |
| 446 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 447 | }; |
| 448 | |
| 449 | uart6: serial@48068000 { |
| 450 | compatible = "ti,omap4-uart"; |
| 451 | reg = <0x48068000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 452 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 453 | ti,hwmods = "uart6"; |
| 454 | clock-frequency = <48000000>; |
| 455 | status = "disabled"; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 456 | dmas = <&sdma 79>, <&sdma 80>; |
| 457 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 458 | }; |
| 459 | |
| 460 | uart7: serial@48420000 { |
| 461 | compatible = "ti,omap4-uart"; |
| 462 | reg = <0x48420000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 463 | interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 464 | ti,hwmods = "uart7"; |
| 465 | clock-frequency = <48000000>; |
| 466 | status = "disabled"; |
| 467 | }; |
| 468 | |
| 469 | uart8: serial@48422000 { |
| 470 | compatible = "ti,omap4-uart"; |
| 471 | reg = <0x48422000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 472 | interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 473 | ti,hwmods = "uart8"; |
| 474 | clock-frequency = <48000000>; |
| 475 | status = "disabled"; |
| 476 | }; |
| 477 | |
| 478 | uart9: serial@48424000 { |
| 479 | compatible = "ti,omap4-uart"; |
| 480 | reg = <0x48424000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 481 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 482 | ti,hwmods = "uart9"; |
| 483 | clock-frequency = <48000000>; |
| 484 | status = "disabled"; |
| 485 | }; |
| 486 | |
| 487 | uart10: serial@4ae2b000 { |
| 488 | compatible = "ti,omap4-uart"; |
| 489 | reg = <0x4ae2b000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 490 | interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 491 | ti,hwmods = "uart10"; |
| 492 | clock-frequency = <48000000>; |
| 493 | status = "disabled"; |
| 494 | }; |
| 495 | |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 496 | mailbox1: mailbox@4a0f4000 { |
| 497 | compatible = "ti,omap4-mailbox"; |
| 498 | reg = <0x4a0f4000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 499 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, |
| 500 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 501 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 502 | ti,hwmods = "mailbox1"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 503 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 504 | ti,mbox-num-users = <3>; |
| 505 | ti,mbox-num-fifos = <8>; |
| 506 | status = "disabled"; |
| 507 | }; |
| 508 | |
| 509 | mailbox2: mailbox@4883a000 { |
| 510 | compatible = "ti,omap4-mailbox"; |
| 511 | reg = <0x4883a000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 512 | interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, |
| 513 | <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, |
| 514 | <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, |
| 515 | <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 516 | ti,hwmods = "mailbox2"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 517 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 518 | ti,mbox-num-users = <4>; |
| 519 | ti,mbox-num-fifos = <12>; |
| 520 | status = "disabled"; |
| 521 | }; |
| 522 | |
| 523 | mailbox3: mailbox@4883c000 { |
| 524 | compatible = "ti,omap4-mailbox"; |
| 525 | reg = <0x4883c000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 526 | interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, |
| 527 | <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, |
| 528 | <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, |
| 529 | <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 530 | ti,hwmods = "mailbox3"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 531 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 532 | ti,mbox-num-users = <4>; |
| 533 | ti,mbox-num-fifos = <12>; |
| 534 | status = "disabled"; |
| 535 | }; |
| 536 | |
| 537 | mailbox4: mailbox@4883e000 { |
| 538 | compatible = "ti,omap4-mailbox"; |
| 539 | reg = <0x4883e000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 540 | interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, |
| 541 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, |
| 542 | <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, |
| 543 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 544 | ti,hwmods = "mailbox4"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 545 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 546 | ti,mbox-num-users = <4>; |
| 547 | ti,mbox-num-fifos = <12>; |
| 548 | status = "disabled"; |
| 549 | }; |
| 550 | |
| 551 | mailbox5: mailbox@48840000 { |
| 552 | compatible = "ti,omap4-mailbox"; |
| 553 | reg = <0x48840000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 554 | interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, |
| 555 | <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, |
| 556 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, |
| 557 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 558 | ti,hwmods = "mailbox5"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 559 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 560 | ti,mbox-num-users = <4>; |
| 561 | ti,mbox-num-fifos = <12>; |
| 562 | status = "disabled"; |
| 563 | }; |
| 564 | |
| 565 | mailbox6: mailbox@48842000 { |
| 566 | compatible = "ti,omap4-mailbox"; |
| 567 | reg = <0x48842000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 568 | interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
| 569 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, |
| 570 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, |
| 571 | <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 572 | ti,hwmods = "mailbox6"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 573 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 574 | ti,mbox-num-users = <4>; |
| 575 | ti,mbox-num-fifos = <12>; |
| 576 | status = "disabled"; |
| 577 | }; |
| 578 | |
| 579 | mailbox7: mailbox@48844000 { |
| 580 | compatible = "ti,omap4-mailbox"; |
| 581 | reg = <0x48844000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 582 | interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, |
| 583 | <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, |
| 584 | <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, |
| 585 | <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 586 | ti,hwmods = "mailbox7"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 587 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 588 | ti,mbox-num-users = <4>; |
| 589 | ti,mbox-num-fifos = <12>; |
| 590 | status = "disabled"; |
| 591 | }; |
| 592 | |
| 593 | mailbox8: mailbox@48846000 { |
| 594 | compatible = "ti,omap4-mailbox"; |
| 595 | reg = <0x48846000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 596 | interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, |
| 597 | <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, |
| 598 | <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, |
| 599 | <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 600 | ti,hwmods = "mailbox8"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 601 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 602 | ti,mbox-num-users = <4>; |
| 603 | ti,mbox-num-fifos = <12>; |
| 604 | status = "disabled"; |
| 605 | }; |
| 606 | |
| 607 | mailbox9: mailbox@4885e000 { |
| 608 | compatible = "ti,omap4-mailbox"; |
| 609 | reg = <0x4885e000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 610 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, |
| 611 | <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, |
| 612 | <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, |
| 613 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 614 | ti,hwmods = "mailbox9"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 615 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 616 | ti,mbox-num-users = <4>; |
| 617 | ti,mbox-num-fifos = <12>; |
| 618 | status = "disabled"; |
| 619 | }; |
| 620 | |
| 621 | mailbox10: mailbox@48860000 { |
| 622 | compatible = "ti,omap4-mailbox"; |
| 623 | reg = <0x48860000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 624 | interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, |
| 625 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, |
| 626 | <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, |
| 627 | <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 628 | ti,hwmods = "mailbox10"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 629 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 630 | ti,mbox-num-users = <4>; |
| 631 | ti,mbox-num-fifos = <12>; |
| 632 | status = "disabled"; |
| 633 | }; |
| 634 | |
| 635 | mailbox11: mailbox@48862000 { |
| 636 | compatible = "ti,omap4-mailbox"; |
| 637 | reg = <0x48862000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 638 | interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, |
| 639 | <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, |
| 640 | <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, |
| 641 | <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 642 | ti,hwmods = "mailbox11"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 643 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 644 | ti,mbox-num-users = <4>; |
| 645 | ti,mbox-num-fifos = <12>; |
| 646 | status = "disabled"; |
| 647 | }; |
| 648 | |
| 649 | mailbox12: mailbox@48864000 { |
| 650 | compatible = "ti,omap4-mailbox"; |
| 651 | reg = <0x48864000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 652 | interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, |
| 653 | <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, |
| 654 | <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, |
| 655 | <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 656 | ti,hwmods = "mailbox12"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 657 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 658 | ti,mbox-num-users = <4>; |
| 659 | ti,mbox-num-fifos = <12>; |
| 660 | status = "disabled"; |
| 661 | }; |
| 662 | |
| 663 | mailbox13: mailbox@48802000 { |
| 664 | compatible = "ti,omap4-mailbox"; |
| 665 | reg = <0x48802000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 666 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, |
| 667 | <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, |
| 668 | <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, |
| 669 | <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 670 | ti,hwmods = "mailbox13"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 671 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 672 | ti,mbox-num-users = <4>; |
| 673 | ti,mbox-num-fifos = <12>; |
| 674 | status = "disabled"; |
| 675 | }; |
| 676 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 677 | timer1: timer@4ae18000 { |
| 678 | compatible = "ti,omap5430-timer"; |
| 679 | reg = <0x4ae18000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 680 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 681 | ti,hwmods = "timer1"; |
| 682 | ti,timer-alwon; |
| 683 | }; |
| 684 | |
| 685 | timer2: timer@48032000 { |
| 686 | compatible = "ti,omap5430-timer"; |
| 687 | reg = <0x48032000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 688 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 689 | ti,hwmods = "timer2"; |
| 690 | }; |
| 691 | |
| 692 | timer3: timer@48034000 { |
| 693 | compatible = "ti,omap5430-timer"; |
| 694 | reg = <0x48034000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 695 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 696 | ti,hwmods = "timer3"; |
| 697 | }; |
| 698 | |
| 699 | timer4: timer@48036000 { |
| 700 | compatible = "ti,omap5430-timer"; |
| 701 | reg = <0x48036000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 702 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 703 | ti,hwmods = "timer4"; |
| 704 | }; |
| 705 | |
| 706 | timer5: timer@48820000 { |
| 707 | compatible = "ti,omap5430-timer"; |
| 708 | reg = <0x48820000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 709 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 710 | ti,hwmods = "timer5"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 711 | }; |
| 712 | |
| 713 | timer6: timer@48822000 { |
| 714 | compatible = "ti,omap5430-timer"; |
| 715 | reg = <0x48822000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 716 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 717 | ti,hwmods = "timer6"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 718 | }; |
| 719 | |
| 720 | timer7: timer@48824000 { |
| 721 | compatible = "ti,omap5430-timer"; |
| 722 | reg = <0x48824000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 723 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 724 | ti,hwmods = "timer7"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 725 | }; |
| 726 | |
| 727 | timer8: timer@48826000 { |
| 728 | compatible = "ti,omap5430-timer"; |
| 729 | reg = <0x48826000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 730 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 731 | ti,hwmods = "timer8"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 732 | }; |
| 733 | |
| 734 | timer9: timer@4803e000 { |
| 735 | compatible = "ti,omap5430-timer"; |
| 736 | reg = <0x4803e000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 737 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 738 | ti,hwmods = "timer9"; |
| 739 | }; |
| 740 | |
| 741 | timer10: timer@48086000 { |
| 742 | compatible = "ti,omap5430-timer"; |
| 743 | reg = <0x48086000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 744 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 745 | ti,hwmods = "timer10"; |
| 746 | }; |
| 747 | |
| 748 | timer11: timer@48088000 { |
| 749 | compatible = "ti,omap5430-timer"; |
| 750 | reg = <0x48088000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 751 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 752 | ti,hwmods = "timer11"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 753 | }; |
| 754 | |
| 755 | timer13: timer@48828000 { |
| 756 | compatible = "ti,omap5430-timer"; |
| 757 | reg = <0x48828000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 758 | interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 759 | ti,hwmods = "timer13"; |
| 760 | status = "disabled"; |
| 761 | }; |
| 762 | |
| 763 | timer14: timer@4882a000 { |
| 764 | compatible = "ti,omap5430-timer"; |
| 765 | reg = <0x4882a000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 766 | interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 767 | ti,hwmods = "timer14"; |
| 768 | status = "disabled"; |
| 769 | }; |
| 770 | |
| 771 | timer15: timer@4882c000 { |
| 772 | compatible = "ti,omap5430-timer"; |
| 773 | reg = <0x4882c000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 774 | interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 775 | ti,hwmods = "timer15"; |
| 776 | status = "disabled"; |
| 777 | }; |
| 778 | |
| 779 | timer16: timer@4882e000 { |
| 780 | compatible = "ti,omap5430-timer"; |
| 781 | reg = <0x4882e000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 782 | interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 783 | ti,hwmods = "timer16"; |
| 784 | status = "disabled"; |
| 785 | }; |
| 786 | |
| 787 | wdt2: wdt@4ae14000 { |
Lokesh Vutla | be66883 | 2014-11-12 10:54:15 +0530 | [diff] [blame] | 788 | compatible = "ti,omap3-wdt"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 789 | reg = <0x4ae14000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 790 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 791 | ti,hwmods = "wd_timer2"; |
| 792 | }; |
| 793 | |
Suman Anna | dbd7c19 | 2014-01-13 18:26:46 -0600 | [diff] [blame] | 794 | hwspinlock: spinlock@4a0f6000 { |
| 795 | compatible = "ti,omap4-hwspinlock"; |
| 796 | reg = <0x4a0f6000 0x1000>; |
| 797 | ti,hwmods = "spinlock"; |
| 798 | #hwlock-cells = <1>; |
| 799 | }; |
| 800 | |
Archit Taneja | 1a5fe3c | 2013-12-17 15:32:21 +0530 | [diff] [blame] | 801 | dmm@4e000000 { |
| 802 | compatible = "ti,omap5-dmm"; |
| 803 | reg = <0x4e000000 0x800>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 804 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
Archit Taneja | 1a5fe3c | 2013-12-17 15:32:21 +0530 | [diff] [blame] | 805 | ti,hwmods = "dmm"; |
| 806 | }; |
| 807 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 808 | i2c1: i2c@48070000 { |
| 809 | compatible = "ti,omap4-i2c"; |
| 810 | reg = <0x48070000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 811 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 812 | #address-cells = <1>; |
| 813 | #size-cells = <0>; |
| 814 | ti,hwmods = "i2c1"; |
| 815 | status = "disabled"; |
| 816 | }; |
| 817 | |
| 818 | i2c2: i2c@48072000 { |
| 819 | compatible = "ti,omap4-i2c"; |
| 820 | reg = <0x48072000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 821 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 822 | #address-cells = <1>; |
| 823 | #size-cells = <0>; |
| 824 | ti,hwmods = "i2c2"; |
| 825 | status = "disabled"; |
| 826 | }; |
| 827 | |
| 828 | i2c3: i2c@48060000 { |
| 829 | compatible = "ti,omap4-i2c"; |
| 830 | reg = <0x48060000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 831 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 832 | #address-cells = <1>; |
| 833 | #size-cells = <0>; |
| 834 | ti,hwmods = "i2c3"; |
| 835 | status = "disabled"; |
| 836 | }; |
| 837 | |
| 838 | i2c4: i2c@4807a000 { |
| 839 | compatible = "ti,omap4-i2c"; |
| 840 | reg = <0x4807a000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 841 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 842 | #address-cells = <1>; |
| 843 | #size-cells = <0>; |
| 844 | ti,hwmods = "i2c4"; |
| 845 | status = "disabled"; |
| 846 | }; |
| 847 | |
| 848 | i2c5: i2c@4807c000 { |
| 849 | compatible = "ti,omap4-i2c"; |
| 850 | reg = <0x4807c000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 851 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 852 | #address-cells = <1>; |
| 853 | #size-cells = <0>; |
| 854 | ti,hwmods = "i2c5"; |
| 855 | status = "disabled"; |
| 856 | }; |
| 857 | |
| 858 | mmc1: mmc@4809c000 { |
| 859 | compatible = "ti,omap4-hsmmc"; |
| 860 | reg = <0x4809c000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 861 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 862 | ti,hwmods = "mmc1"; |
| 863 | ti,dual-volt; |
| 864 | ti,needs-special-reset; |
| 865 | dmas = <&sdma 61>, <&sdma 62>; |
| 866 | dma-names = "tx", "rx"; |
| 867 | status = "disabled"; |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 868 | pbias-supply = <&pbias_mmc_reg>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 869 | }; |
| 870 | |
| 871 | mmc2: mmc@480b4000 { |
| 872 | compatible = "ti,omap4-hsmmc"; |
| 873 | reg = <0x480b4000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 874 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 875 | ti,hwmods = "mmc2"; |
| 876 | ti,needs-special-reset; |
| 877 | dmas = <&sdma 47>, <&sdma 48>; |
| 878 | dma-names = "tx", "rx"; |
| 879 | status = "disabled"; |
| 880 | }; |
| 881 | |
| 882 | mmc3: mmc@480ad000 { |
| 883 | compatible = "ti,omap4-hsmmc"; |
| 884 | reg = <0x480ad000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 885 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 886 | ti,hwmods = "mmc3"; |
| 887 | ti,needs-special-reset; |
| 888 | dmas = <&sdma 77>, <&sdma 78>; |
| 889 | dma-names = "tx", "rx"; |
| 890 | status = "disabled"; |
| 891 | }; |
| 892 | |
| 893 | mmc4: mmc@480d1000 { |
| 894 | compatible = "ti,omap4-hsmmc"; |
| 895 | reg = <0x480d1000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 896 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 897 | ti,hwmods = "mmc4"; |
| 898 | ti,needs-special-reset; |
| 899 | dmas = <&sdma 57>, <&sdma 58>; |
| 900 | dma-names = "tx", "rx"; |
| 901 | status = "disabled"; |
| 902 | }; |
| 903 | |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 904 | abb_mpu: regulator-abb-mpu { |
| 905 | compatible = "ti,abb-v3"; |
| 906 | regulator-name = "abb_mpu"; |
| 907 | #address-cells = <0>; |
| 908 | #size-cells = <0>; |
| 909 | clocks = <&sys_clkin1>; |
| 910 | ti,settling-time = <50>; |
| 911 | ti,clock-cycles = <16>; |
| 912 | |
| 913 | reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, |
Nishanth Menon | 1822734 | 2015-04-16 16:56:33 -0500 | [diff] [blame] | 914 | <0x4ae06014 0x4>, <0x4a003b20 0xc>, |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 915 | <0x4ae0c158 0x4>; |
| 916 | reg-names = "setup-address", "control-address", |
| 917 | "int-address", "efuse-address", |
| 918 | "ldo-address"; |
| 919 | ti,tranxdone-status-mask = <0x80>; |
| 920 | /* LDOVBBMPU_FBB_MUX_CTRL */ |
| 921 | ti,ldovbb-override-mask = <0x400>; |
| 922 | /* LDOVBBMPU_FBB_VSET_OUT */ |
| 923 | ti,ldovbb-vset-mask = <0x1F>; |
| 924 | |
| 925 | /* |
| 926 | * NOTE: only FBB mode used but actual vset will |
| 927 | * determine final biasing |
| 928 | */ |
| 929 | ti,abb_info = < |
| 930 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 931 | 1060000 0 0x0 0 0x02000000 0x01F00000 |
| 932 | 1160000 0 0x4 0 0x02000000 0x01F00000 |
| 933 | 1210000 0 0x8 0 0x02000000 0x01F00000 |
| 934 | >; |
| 935 | }; |
| 936 | |
| 937 | abb_ivahd: regulator-abb-ivahd { |
| 938 | compatible = "ti,abb-v3"; |
| 939 | regulator-name = "abb_ivahd"; |
| 940 | #address-cells = <0>; |
| 941 | #size-cells = <0>; |
| 942 | clocks = <&sys_clkin1>; |
| 943 | ti,settling-time = <50>; |
| 944 | ti,clock-cycles = <16>; |
| 945 | |
| 946 | reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, |
Nishanth Menon | 1822734 | 2015-04-16 16:56:33 -0500 | [diff] [blame] | 947 | <0x4ae06010 0x4>, <0x4a0025cc 0xc>, |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 948 | <0x4a002470 0x4>; |
| 949 | reg-names = "setup-address", "control-address", |
| 950 | "int-address", "efuse-address", |
| 951 | "ldo-address"; |
| 952 | ti,tranxdone-status-mask = <0x40000000>; |
| 953 | /* LDOVBBIVA_FBB_MUX_CTRL */ |
| 954 | ti,ldovbb-override-mask = <0x400>; |
| 955 | /* LDOVBBIVA_FBB_VSET_OUT */ |
| 956 | ti,ldovbb-vset-mask = <0x1F>; |
| 957 | |
| 958 | /* |
| 959 | * NOTE: only FBB mode used but actual vset will |
| 960 | * determine final biasing |
| 961 | */ |
| 962 | ti,abb_info = < |
| 963 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 964 | 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 965 | 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 966 | 1250000 0 0x8 0 0x02000000 0x01F00000 |
| 967 | >; |
| 968 | }; |
| 969 | |
| 970 | abb_dspeve: regulator-abb-dspeve { |
| 971 | compatible = "ti,abb-v3"; |
| 972 | regulator-name = "abb_dspeve"; |
| 973 | #address-cells = <0>; |
| 974 | #size-cells = <0>; |
| 975 | clocks = <&sys_clkin1>; |
| 976 | ti,settling-time = <50>; |
| 977 | ti,clock-cycles = <16>; |
| 978 | |
| 979 | reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, |
Nishanth Menon | 1822734 | 2015-04-16 16:56:33 -0500 | [diff] [blame] | 980 | <0x4ae06010 0x4>, <0x4a0025e0 0xc>, |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 981 | <0x4a00246c 0x4>; |
| 982 | reg-names = "setup-address", "control-address", |
| 983 | "int-address", "efuse-address", |
| 984 | "ldo-address"; |
| 985 | ti,tranxdone-status-mask = <0x20000000>; |
| 986 | /* LDOVBBDSPEVE_FBB_MUX_CTRL */ |
| 987 | ti,ldovbb-override-mask = <0x400>; |
| 988 | /* LDOVBBDSPEVE_FBB_VSET_OUT */ |
| 989 | ti,ldovbb-vset-mask = <0x1F>; |
| 990 | |
| 991 | /* |
| 992 | * NOTE: only FBB mode used but actual vset will |
| 993 | * determine final biasing |
| 994 | */ |
| 995 | ti,abb_info = < |
| 996 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 997 | 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 998 | 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 999 | 1250000 0 0x8 0 0x02000000 0x01F00000 |
| 1000 | >; |
| 1001 | }; |
| 1002 | |
| 1003 | abb_gpu: regulator-abb-gpu { |
| 1004 | compatible = "ti,abb-v3"; |
| 1005 | regulator-name = "abb_gpu"; |
| 1006 | #address-cells = <0>; |
| 1007 | #size-cells = <0>; |
| 1008 | clocks = <&sys_clkin1>; |
| 1009 | ti,settling-time = <50>; |
| 1010 | ti,clock-cycles = <16>; |
| 1011 | |
| 1012 | reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, |
Nishanth Menon | 1822734 | 2015-04-16 16:56:33 -0500 | [diff] [blame] | 1013 | <0x4ae06010 0x4>, <0x4a003b08 0xc>, |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 1014 | <0x4ae0c154 0x4>; |
| 1015 | reg-names = "setup-address", "control-address", |
| 1016 | "int-address", "efuse-address", |
| 1017 | "ldo-address"; |
| 1018 | ti,tranxdone-status-mask = <0x10000000>; |
| 1019 | /* LDOVBBGPU_FBB_MUX_CTRL */ |
| 1020 | ti,ldovbb-override-mask = <0x400>; |
| 1021 | /* LDOVBBGPU_FBB_VSET_OUT */ |
| 1022 | ti,ldovbb-vset-mask = <0x1F>; |
| 1023 | |
| 1024 | /* |
| 1025 | * NOTE: only FBB mode used but actual vset will |
| 1026 | * determine final biasing |
| 1027 | */ |
| 1028 | ti,abb_info = < |
| 1029 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1030 | 1090000 0 0x0 0 0x02000000 0x01F00000 |
| 1031 | 1210000 0 0x4 0 0x02000000 0x01F00000 |
| 1032 | 1280000 0 0x8 0 0x02000000 0x01F00000 |
| 1033 | >; |
| 1034 | }; |
| 1035 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1036 | mcspi1: spi@48098000 { |
| 1037 | compatible = "ti,omap4-mcspi"; |
| 1038 | reg = <0x48098000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1039 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1040 | #address-cells = <1>; |
| 1041 | #size-cells = <0>; |
| 1042 | ti,hwmods = "mcspi1"; |
| 1043 | ti,spi-num-cs = <4>; |
| 1044 | dmas = <&sdma 35>, |
| 1045 | <&sdma 36>, |
| 1046 | <&sdma 37>, |
| 1047 | <&sdma 38>, |
| 1048 | <&sdma 39>, |
| 1049 | <&sdma 40>, |
| 1050 | <&sdma 41>, |
| 1051 | <&sdma 42>; |
| 1052 | dma-names = "tx0", "rx0", "tx1", "rx1", |
| 1053 | "tx2", "rx2", "tx3", "rx3"; |
| 1054 | status = "disabled"; |
| 1055 | }; |
| 1056 | |
| 1057 | mcspi2: spi@4809a000 { |
| 1058 | compatible = "ti,omap4-mcspi"; |
| 1059 | reg = <0x4809a000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1060 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1061 | #address-cells = <1>; |
| 1062 | #size-cells = <0>; |
| 1063 | ti,hwmods = "mcspi2"; |
| 1064 | ti,spi-num-cs = <2>; |
| 1065 | dmas = <&sdma 43>, |
| 1066 | <&sdma 44>, |
| 1067 | <&sdma 45>, |
| 1068 | <&sdma 46>; |
| 1069 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
| 1070 | status = "disabled"; |
| 1071 | }; |
| 1072 | |
| 1073 | mcspi3: spi@480b8000 { |
| 1074 | compatible = "ti,omap4-mcspi"; |
| 1075 | reg = <0x480b8000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1076 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1077 | #address-cells = <1>; |
| 1078 | #size-cells = <0>; |
| 1079 | ti,hwmods = "mcspi3"; |
| 1080 | ti,spi-num-cs = <2>; |
| 1081 | dmas = <&sdma 15>, <&sdma 16>; |
| 1082 | dma-names = "tx0", "rx0"; |
| 1083 | status = "disabled"; |
| 1084 | }; |
| 1085 | |
| 1086 | mcspi4: spi@480ba000 { |
| 1087 | compatible = "ti,omap4-mcspi"; |
| 1088 | reg = <0x480ba000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1089 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1090 | #address-cells = <1>; |
| 1091 | #size-cells = <0>; |
| 1092 | ti,hwmods = "mcspi4"; |
| 1093 | ti,spi-num-cs = <1>; |
| 1094 | dmas = <&sdma 70>, <&sdma 71>; |
| 1095 | dma-names = "tx0", "rx0"; |
| 1096 | status = "disabled"; |
| 1097 | }; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 1098 | |
| 1099 | qspi: qspi@4b300000 { |
| 1100 | compatible = "ti,dra7xxx-qspi"; |
| 1101 | reg = <0x4b300000 0x100>; |
| 1102 | reg-names = "qspi_base"; |
| 1103 | #address-cells = <1>; |
| 1104 | #size-cells = <0>; |
| 1105 | ti,hwmods = "qspi"; |
| 1106 | clocks = <&qspi_gfclk_div>; |
| 1107 | clock-names = "fck"; |
| 1108 | num-cs = <4>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1109 | interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 1110 | status = "disabled"; |
| 1111 | }; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1112 | |
| 1113 | omap_control_sata: control-phy@4a002374 { |
| 1114 | compatible = "ti,control-phy-pipe3"; |
| 1115 | reg = <0x4a002374 0x4>; |
| 1116 | reg-names = "power"; |
| 1117 | clocks = <&sys_clkin1>; |
| 1118 | clock-names = "sysclk"; |
| 1119 | }; |
| 1120 | |
| 1121 | /* OCP2SCP3 */ |
| 1122 | ocp2scp@4a090000 { |
| 1123 | compatible = "ti,omap-ocp2scp"; |
| 1124 | #address-cells = <1>; |
| 1125 | #size-cells = <1>; |
| 1126 | ranges; |
| 1127 | reg = <0x4a090000 0x20>; |
| 1128 | ti,hwmods = "ocp2scp3"; |
| 1129 | sata_phy: phy@4A096000 { |
| 1130 | compatible = "ti,phy-pipe3-sata"; |
| 1131 | reg = <0x4A096000 0x80>, /* phy_rx */ |
| 1132 | <0x4A096400 0x64>, /* phy_tx */ |
| 1133 | <0x4A096800 0x40>; /* pll_ctrl */ |
| 1134 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| 1135 | ctrl-module = <&omap_control_sata>; |
Roger Quadros | 773c5a0 | 2015-01-13 14:23:21 +0200 | [diff] [blame] | 1136 | clocks = <&sys_clkin1>, <&sata_ref_clk>; |
| 1137 | clock-names = "sysclk", "refclk"; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1138 | #phy-cells = <0>; |
| 1139 | }; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1140 | |
| 1141 | pcie1_phy: pciephy@4a094000 { |
| 1142 | compatible = "ti,phy-pipe3-pcie"; |
| 1143 | reg = <0x4a094000 0x80>, /* phy_rx */ |
| 1144 | <0x4a094400 0x64>; /* phy_tx */ |
| 1145 | reg-names = "phy_rx", "phy_tx"; |
| 1146 | ctrl-module = <&omap_control_pcie1phy>; |
| 1147 | clocks = <&dpll_pcie_ref_ck>, |
| 1148 | <&dpll_pcie_ref_m2ldo_ck>, |
| 1149 | <&optfclk_pciephy1_32khz>, |
| 1150 | <&optfclk_pciephy1_clk>, |
| 1151 | <&optfclk_pciephy1_div_clk>, |
| 1152 | <&optfclk_pciephy_div>; |
| 1153 | clock-names = "dpll_ref", "dpll_ref_m2", |
| 1154 | "wkupclk", "refclk", |
| 1155 | "div-clk", "phy-div"; |
| 1156 | #phy-cells = <0>; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1157 | }; |
| 1158 | |
| 1159 | pcie2_phy: pciephy@4a095000 { |
| 1160 | compatible = "ti,phy-pipe3-pcie"; |
| 1161 | reg = <0x4a095000 0x80>, /* phy_rx */ |
| 1162 | <0x4a095400 0x64>; /* phy_tx */ |
| 1163 | reg-names = "phy_rx", "phy_tx"; |
| 1164 | ctrl-module = <&omap_control_pcie2phy>; |
| 1165 | clocks = <&dpll_pcie_ref_ck>, |
| 1166 | <&dpll_pcie_ref_m2ldo_ck>, |
| 1167 | <&optfclk_pciephy2_32khz>, |
| 1168 | <&optfclk_pciephy2_clk>, |
| 1169 | <&optfclk_pciephy2_div_clk>, |
| 1170 | <&optfclk_pciephy_div>; |
| 1171 | clock-names = "dpll_ref", "dpll_ref_m2", |
| 1172 | "wkupclk", "refclk", |
| 1173 | "div-clk", "phy-div"; |
| 1174 | #phy-cells = <0>; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1175 | status = "disabled"; |
| 1176 | }; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1177 | }; |
| 1178 | |
| 1179 | sata: sata@4a141100 { |
| 1180 | compatible = "snps,dwc-ahci"; |
| 1181 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1182 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1183 | phys = <&sata_phy>; |
| 1184 | phy-names = "sata-phy"; |
| 1185 | clocks = <&sata_ref_clk>; |
| 1186 | ti,hwmods = "sata"; |
| 1187 | }; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1188 | |
Kishon Vijay Abraham I | d1ff66b | 2014-07-14 16:12:21 +0530 | [diff] [blame] | 1189 | omap_control_pcie1phy: control-phy@0x4a003c40 { |
| 1190 | compatible = "ti,control-phy-pcie"; |
| 1191 | reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; |
| 1192 | reg-names = "power", "control_sma", "pcie_pcs"; |
| 1193 | clocks = <&sys_clkin1>; |
| 1194 | clock-names = "sysclk"; |
| 1195 | }; |
| 1196 | |
| 1197 | omap_control_pcie2phy: control-pcie@0x4a003c44 { |
| 1198 | compatible = "ti,control-phy-pcie"; |
| 1199 | reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; |
| 1200 | reg-names = "power", "control_sma", "pcie_pcs"; |
| 1201 | clocks = <&sys_clkin1>; |
| 1202 | clock-names = "sysclk"; |
| 1203 | status = "disabled"; |
| 1204 | }; |
| 1205 | |
Nishanth Menon | 00edd31 | 2015-04-08 18:56:27 -0500 | [diff] [blame] | 1206 | rtc: rtc@48838000 { |
Lokesh Vutla | bc07831 | 2014-11-19 17:53:08 +0530 | [diff] [blame] | 1207 | compatible = "ti,am3352-rtc"; |
| 1208 | reg = <0x48838000 0x100>; |
| 1209 | interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, |
| 1210 | <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; |
| 1211 | ti,hwmods = "rtcss"; |
| 1212 | clocks = <&sys_32k_ck>; |
| 1213 | }; |
| 1214 | |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1215 | omap_control_usb2phy1: control-phy@4a002300 { |
| 1216 | compatible = "ti,control-phy-usb2"; |
| 1217 | reg = <0x4a002300 0x4>; |
| 1218 | reg-names = "power"; |
| 1219 | }; |
| 1220 | |
| 1221 | omap_control_usb3phy1: control-phy@4a002370 { |
| 1222 | compatible = "ti,control-phy-pipe3"; |
| 1223 | reg = <0x4a002370 0x4>; |
| 1224 | reg-names = "power"; |
| 1225 | }; |
| 1226 | |
| 1227 | omap_control_usb2phy2: control-phy@0x4a002e74 { |
| 1228 | compatible = "ti,control-phy-usb2-dra7"; |
| 1229 | reg = <0x4a002e74 0x4>; |
| 1230 | reg-names = "power"; |
| 1231 | }; |
| 1232 | |
| 1233 | /* OCP2SCP1 */ |
| 1234 | ocp2scp@4a080000 { |
| 1235 | compatible = "ti,omap-ocp2scp"; |
| 1236 | #address-cells = <1>; |
| 1237 | #size-cells = <1>; |
| 1238 | ranges; |
| 1239 | reg = <0x4a080000 0x20>; |
| 1240 | ti,hwmods = "ocp2scp1"; |
| 1241 | |
| 1242 | usb2_phy1: phy@4a084000 { |
| 1243 | compatible = "ti,omap-usb2"; |
| 1244 | reg = <0x4a084000 0x400>; |
| 1245 | ctrl-module = <&omap_control_usb2phy1>; |
| 1246 | clocks = <&usb_phy1_always_on_clk32k>, |
| 1247 | <&usb_otg_ss1_refclk960m>; |
| 1248 | clock-names = "wkupclk", |
| 1249 | "refclk"; |
| 1250 | #phy-cells = <0>; |
| 1251 | }; |
| 1252 | |
| 1253 | usb2_phy2: phy@4a085000 { |
| 1254 | compatible = "ti,omap-usb2"; |
| 1255 | reg = <0x4a085000 0x400>; |
| 1256 | ctrl-module = <&omap_control_usb2phy2>; |
| 1257 | clocks = <&usb_phy2_always_on_clk32k>, |
| 1258 | <&usb_otg_ss2_refclk960m>; |
| 1259 | clock-names = "wkupclk", |
| 1260 | "refclk"; |
| 1261 | #phy-cells = <0>; |
| 1262 | }; |
| 1263 | |
| 1264 | usb3_phy1: phy@4a084400 { |
| 1265 | compatible = "ti,omap-usb3"; |
| 1266 | reg = <0x4a084400 0x80>, |
| 1267 | <0x4a084800 0x64>, |
| 1268 | <0x4a084c00 0x40>; |
| 1269 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
| 1270 | ctrl-module = <&omap_control_usb3phy1>; |
| 1271 | clocks = <&usb_phy3_always_on_clk32k>, |
| 1272 | <&sys_clkin1>, |
| 1273 | <&usb_otg_ss1_refclk960m>; |
| 1274 | clock-names = "wkupclk", |
| 1275 | "sysclk", |
| 1276 | "refclk"; |
| 1277 | #phy-cells = <0>; |
| 1278 | }; |
| 1279 | }; |
| 1280 | |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1281 | omap_dwc3_1: omap_dwc3_1@48880000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1282 | compatible = "ti,dwc3"; |
| 1283 | ti,hwmods = "usb_otg_ss1"; |
| 1284 | reg = <0x48880000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1285 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1286 | #address-cells = <1>; |
| 1287 | #size-cells = <1>; |
| 1288 | utmi-mode = <2>; |
| 1289 | ranges; |
| 1290 | usb1: usb@48890000 { |
| 1291 | compatible = "snps,dwc3"; |
| 1292 | reg = <0x48890000 0x17000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1293 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1294 | phys = <&usb2_phy1>, <&usb3_phy1>; |
| 1295 | phy-names = "usb2-phy", "usb3-phy"; |
| 1296 | tx-fifo-resize; |
| 1297 | maximum-speed = "super-speed"; |
| 1298 | dr_mode = "otg"; |
Felipe Balbi | 8c60673 | 2015-01-15 09:38:03 -0600 | [diff] [blame] | 1299 | snps,dis_u3_susphy_quirk; |
| 1300 | snps,dis_u2_susphy_quirk; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1301 | }; |
| 1302 | }; |
| 1303 | |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1304 | omap_dwc3_2: omap_dwc3_2@488c0000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1305 | compatible = "ti,dwc3"; |
| 1306 | ti,hwmods = "usb_otg_ss2"; |
| 1307 | reg = <0x488c0000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1308 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1309 | #address-cells = <1>; |
| 1310 | #size-cells = <1>; |
| 1311 | utmi-mode = <2>; |
| 1312 | ranges; |
| 1313 | usb2: usb@488d0000 { |
| 1314 | compatible = "snps,dwc3"; |
| 1315 | reg = <0x488d0000 0x17000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1316 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1317 | phys = <&usb2_phy2>; |
| 1318 | phy-names = "usb2-phy"; |
| 1319 | tx-fifo-resize; |
| 1320 | maximum-speed = "high-speed"; |
| 1321 | dr_mode = "otg"; |
Felipe Balbi | 8c60673 | 2015-01-15 09:38:03 -0600 | [diff] [blame] | 1322 | snps,dis_u3_susphy_quirk; |
| 1323 | snps,dis_u2_susphy_quirk; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1324 | }; |
| 1325 | }; |
| 1326 | |
| 1327 | /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1328 | omap_dwc3_3: omap_dwc3_3@48900000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1329 | compatible = "ti,dwc3"; |
| 1330 | ti,hwmods = "usb_otg_ss3"; |
| 1331 | reg = <0x48900000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1332 | interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1333 | #address-cells = <1>; |
| 1334 | #size-cells = <1>; |
| 1335 | utmi-mode = <2>; |
| 1336 | ranges; |
| 1337 | status = "disabled"; |
| 1338 | usb3: usb@48910000 { |
| 1339 | compatible = "snps,dwc3"; |
| 1340 | reg = <0x48910000 0x17000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1341 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1342 | tx-fifo-resize; |
| 1343 | maximum-speed = "high-speed"; |
| 1344 | dr_mode = "otg"; |
Felipe Balbi | 8c60673 | 2015-01-15 09:38:03 -0600 | [diff] [blame] | 1345 | snps,dis_u3_susphy_quirk; |
| 1346 | snps,dis_u2_susphy_quirk; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1347 | }; |
| 1348 | }; |
| 1349 | |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1350 | elm: elm@48078000 { |
| 1351 | compatible = "ti,am3352-elm"; |
| 1352 | reg = <0x48078000 0xfc0>; /* device IO registers */ |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1353 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1354 | ti,hwmods = "elm"; |
| 1355 | status = "disabled"; |
| 1356 | }; |
| 1357 | |
| 1358 | gpmc: gpmc@50000000 { |
| 1359 | compatible = "ti,am3352-gpmc"; |
| 1360 | ti,hwmods = "gpmc"; |
| 1361 | reg = <0x50000000 0x37c>; /* device IO registers */ |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1362 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1363 | gpmc,num-cs = <8>; |
| 1364 | gpmc,num-waitpins = <2>; |
| 1365 | #address-cells = <2>; |
| 1366 | #size-cells = <1>; |
| 1367 | status = "disabled"; |
| 1368 | }; |
Peter Ujfalusi | 2ca0945 | 2014-05-07 13:20:48 +0300 | [diff] [blame] | 1369 | |
| 1370 | atl: atl@4843c000 { |
| 1371 | compatible = "ti,dra7-atl"; |
| 1372 | reg = <0x4843c000 0x3ff>; |
| 1373 | ti,hwmods = "atl"; |
| 1374 | ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, |
| 1375 | <&atl_clkin2_ck>, <&atl_clkin3_ck>; |
| 1376 | clocks = <&atl_gfclk_mux>; |
| 1377 | clock-names = "fck"; |
| 1378 | status = "disabled"; |
| 1379 | }; |
Olof Johansson | 412a9bb | 2014-07-18 22:16:15 -0700 | [diff] [blame] | 1380 | |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 1381 | crossbar_mpu: crossbar@4a002a48 { |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1382 | compatible = "ti,irq-crossbar"; |
| 1383 | reg = <0x4a002a48 0x130>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 1384 | interrupt-controller; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 1385 | interrupt-parent = <&wakeupgen>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 1386 | #interrupt-cells = <3>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1387 | ti,max-irqs = <160>; |
| 1388 | ti,max-crossbar-sources = <MAX_SOURCES>; |
| 1389 | ti,reg-size = <2>; |
| 1390 | ti,irqs-reserved = <0 1 2 3 5 6 131 132>; |
| 1391 | ti,irqs-skip = <10 133 139 140>; |
| 1392 | ti,irqs-safe-map = <0>; |
| 1393 | }; |
Mugunthan V N | ef9c5b6 | 2014-10-21 15:31:00 +0530 | [diff] [blame] | 1394 | |
| 1395 | mac: ethernet@4a100000 { |
| 1396 | compatible = "ti,cpsw"; |
| 1397 | ti,hwmods = "gmac"; |
| 1398 | clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; |
| 1399 | clock-names = "fck", "cpts"; |
| 1400 | cpdma_channels = <8>; |
| 1401 | ale_entries = <1024>; |
| 1402 | bd_ram_size = <0x2000>; |
| 1403 | no_bd_ram = <0>; |
| 1404 | rx_descs = <64>; |
| 1405 | mac_control = <0x20>; |
| 1406 | slaves = <2>; |
| 1407 | active_slave = <0>; |
| 1408 | cpts_clock_mult = <0x80000000>; |
| 1409 | cpts_clock_shift = <29>; |
| 1410 | reg = <0x48484000 0x1000 |
| 1411 | 0x48485200 0x2E00>; |
| 1412 | #address-cells = <1>; |
| 1413 | #size-cells = <1>; |
| 1414 | /* |
| 1415 | * rx_thresh_pend |
| 1416 | * rx_pend |
| 1417 | * tx_pend |
| 1418 | * misc_pend |
| 1419 | */ |
| 1420 | interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, |
| 1421 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, |
| 1422 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, |
| 1423 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; |
| 1424 | ranges; |
| 1425 | status = "disabled"; |
| 1426 | |
| 1427 | davinci_mdio: mdio@48485000 { |
| 1428 | compatible = "ti,davinci_mdio"; |
| 1429 | #address-cells = <1>; |
| 1430 | #size-cells = <0>; |
| 1431 | ti,hwmods = "davinci_mdio"; |
| 1432 | bus_freq = <1000000>; |
| 1433 | reg = <0x48485000 0x100>; |
| 1434 | }; |
| 1435 | |
| 1436 | cpsw_emac0: slave@48480200 { |
| 1437 | /* Filled in by U-Boot */ |
| 1438 | mac-address = [ 00 00 00 00 00 00 ]; |
| 1439 | }; |
| 1440 | |
| 1441 | cpsw_emac1: slave@48480300 { |
| 1442 | /* Filled in by U-Boot */ |
| 1443 | mac-address = [ 00 00 00 00 00 00 ]; |
| 1444 | }; |
| 1445 | |
| 1446 | phy_sel: cpsw-phy-sel@4a002554 { |
| 1447 | compatible = "ti,dra7xx-cpsw-phy-sel"; |
| 1448 | reg= <0x4a002554 0x4>; |
| 1449 | reg-names = "gmii-sel"; |
| 1450 | }; |
| 1451 | }; |
| 1452 | |
Roger Quadros | 9ec49b9 | 2014-08-15 16:08:36 +0300 | [diff] [blame] | 1453 | dcan1: can@481cc000 { |
| 1454 | compatible = "ti,dra7-d_can"; |
| 1455 | ti,hwmods = "dcan1"; |
| 1456 | reg = <0x4ae3c000 0x2000>; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 1457 | syscon-raminit = <&scm_conf 0x558 0>; |
Roger Quadros | 9ec49b9 | 2014-08-15 16:08:36 +0300 | [diff] [blame] | 1458 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; |
| 1459 | clocks = <&dcan1_sys_clk_mux>; |
| 1460 | status = "disabled"; |
| 1461 | }; |
| 1462 | |
| 1463 | dcan2: can@481d0000 { |
| 1464 | compatible = "ti,dra7-d_can"; |
| 1465 | ti,hwmods = "dcan2"; |
| 1466 | reg = <0x48480000 0x2000>; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 1467 | syscon-raminit = <&scm_conf 0x558 1>; |
Roger Quadros | 9ec49b9 | 2014-08-15 16:08:36 +0300 | [diff] [blame] | 1468 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
| 1469 | clocks = <&sys_clkin1>; |
| 1470 | status = "disabled"; |
| 1471 | }; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1472 | }; |
Keerthy | f7397ed | 2015-03-23 14:39:38 -0500 | [diff] [blame] | 1473 | |
| 1474 | thermal_zones: thermal-zones { |
| 1475 | #include "omap4-cpu-thermal.dtsi" |
| 1476 | #include "omap5-gpu-thermal.dtsi" |
| 1477 | #include "omap5-core-thermal.dtsi" |
| 1478 | }; |
| 1479 | |
| 1480 | }; |
| 1481 | |
| 1482 | &cpu_thermal { |
| 1483 | polling-delay = <500>; /* milliseconds */ |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1484 | }; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 1485 | |
| 1486 | /include/ "dra7xx-clocks.dtsi" |