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Matthew Wilcoxb60503b2011-01-20 12:50:14 -05001/*
2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef _LINUX_NVME_H
20#define _LINUX_NVME_H
21
22#include <linux/types.h>
23
24struct nvme_bar {
25 __u64 cap; /* Controller Capabilities */
26 __u32 vs; /* Version */
Matthew Wilcox897cfe12011-02-14 12:20:15 -050027 __u32 intms; /* Interrupt Mask Set */
28 __u32 intmc; /* Interrupt Mask Clear */
Matthew Wilcoxb60503b2011-01-20 12:50:14 -050029 __u32 cc; /* Controller Configuration */
Matthew Wilcox897cfe12011-02-14 12:20:15 -050030 __u32 rsvd1; /* Reserved */
Matthew Wilcoxb60503b2011-01-20 12:50:14 -050031 __u32 csts; /* Controller Status */
Matthew Wilcox897cfe12011-02-14 12:20:15 -050032 __u32 rsvd2; /* Reserved */
Matthew Wilcoxb60503b2011-01-20 12:50:14 -050033 __u32 aqa; /* Admin Queue Attributes */
34 __u64 asq; /* Admin SQ Base Address */
35 __u64 acq; /* Admin CQ Base Address */
36};
37
38enum {
39 NVME_CC_ENABLE = 1 << 0,
40 NVME_CC_CSS_NVM = 0 << 4,
41 NVME_CC_MPS_SHIFT = 7,
42 NVME_CC_ARB_RR = 0 << 11,
43 NVME_CC_ARB_WRRU = 1 << 11,
44 NVME_CC_ARB_VS = 3 << 11,
45 NVME_CC_SHN_NONE = 0 << 13,
46 NVME_CC_SHN_NORMAL = 1 << 13,
47 NVME_CC_SHN_ABRUPT = 2 << 13,
48 NVME_CSTS_RDY = 1 << 0,
49 NVME_CSTS_CFS = 1 << 1,
50 NVME_CSTS_SHST_NORMAL = 0 << 2,
51 NVME_CSTS_SHST_OCCUR = 1 << 2,
52 NVME_CSTS_SHST_CMPLT = 2 << 2,
53};
54
55#define NVME_VS(major, minor) (major << 16 | minor)
56
57struct nvme_id_ctrl {
58 __le16 vid;
59 __le16 ssvid;
60 char sn[20];
61 char mn[40];
62 char fr[8];
63 __le32 nn;
64 __u8 rab;
65 __u8 rsvd77[178];
66 __le16 oacs;
67 __u8 acl;
68 __u8 aerl;
69 __u8 frmw;
70 __u8 lpa;
71 __u8 elpe;
72 __u8 npss;
73 __u8 rsvd264[248];
74 __le64 psd[32];
75 __le16 oncs;
76 __le16 fuses;
77 __u8 fna;
78 __u8 vwc;
79 __le16 awun;
80 __le16 awupf;
81 __u8 rsvd778[246];
82 __u8 cmdset[2048];
83 __u8 vs[1024];
84};
85
86struct nvme_lbaf {
87 __le16 ms;
88 __u8 ds;
89 __u8 rp;
90};
91
92struct nvme_id_ns {
93 __le64 nsze;
94 __le64 ncap;
95 __le64 nuse;
96 __u8 nsfeat;
97 __u8 nlbaf;
98 __u8 flbas;
99 __u8 mc;
100 __u8 dpc;
101 __u8 dps;
102 __u8 rsvd30[98];
103 struct nvme_lbaf lbaf[16];
104 __u8 rsvd192[192];
105 __u8 vs[3712];
106};
107
108enum {
109 NVME_NS_FEAT_THIN = 1 << 0,
110 NVME_LBAF_RP_BEST = 0,
111 NVME_LBAF_RP_BETTER = 1,
112 NVME_LBAF_RP_GOOD = 2,
113 NVME_LBAF_RP_DEGRADED = 3,
114};
115
116struct nvme_lba_range_type {
117 __u8 type;
118 __u8 attributes;
119 __u8 rsvd2[14];
120 __u64 slba;
121 __u64 nlb;
122 __u8 guid[16];
123 __u8 rsvd48[16];
124};
125
126enum {
127 NVME_LBART_TYPE_FS = 0x01,
128 NVME_LBART_TYPE_RAID = 0x02,
129 NVME_LBART_TYPE_CACHE = 0x03,
130 NVME_LBART_TYPE_SWAP = 0x04,
131
132 NVME_LBART_ATTRIB_TEMP = 1 << 0,
133 NVME_LBART_ATTRIB_HIDE = 1 << 1,
134};
135
136/* I/O commands */
137
138enum nvme_opcode {
139 nvme_cmd_flush = 0x00,
140 nvme_cmd_write = 0x01,
141 nvme_cmd_read = 0x02,
142 nvme_cmd_write_uncor = 0x04,
143 nvme_cmd_compare = 0x05,
144 nvme_cmd_dsm = 0x09,
145};
146
Matthew Wilcox7b4fe9b2011-01-26 10:01:21 -0500147struct nvme_common_command {
148 __u8 opcode;
149 __u8 flags;
150 __u16 command_id;
151 __le32 nsid;
152 __u64 rsvd2;
153 __le64 metadata;
154 __le64 prp1;
155 __le64 prp2;
156 __u32 rsvd10[6];
157};
158
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500159struct nvme_rw_command {
160 __u8 opcode;
161 __u8 flags;
162 __u16 command_id;
163 __le32 nsid;
164 __u64 rsvd2;
165 __le64 metadata;
166 __le64 prp1;
167 __le64 prp2;
168 __le64 slba;
169 __le16 length;
170 __le16 control;
171 __le32 dsmgmt;
172 __le32 reftag;
173 __le16 apptag;
174 __le16 appmask;
175};
176
177enum {
178 NVME_RW_LR = 1 << 15,
179 NVME_RW_FUA = 1 << 14,
180 NVME_RW_DSM_FREQ_UNSPEC = 0,
181 NVME_RW_DSM_FREQ_TYPICAL = 1,
182 NVME_RW_DSM_FREQ_RARE = 2,
183 NVME_RW_DSM_FREQ_READS = 3,
184 NVME_RW_DSM_FREQ_WRITES = 4,
185 NVME_RW_DSM_FREQ_RW = 5,
186 NVME_RW_DSM_FREQ_ONCE = 6,
187 NVME_RW_DSM_FREQ_PREFETCH = 7,
188 NVME_RW_DSM_FREQ_TEMP = 8,
189 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
190 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
191 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
192 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
193 NVME_RW_DSM_SEQ_REQ = 1 << 6,
194 NVME_RW_DSM_COMPRESSED = 1 << 7,
195};
196
197/* Admin commands */
198
199enum nvme_admin_opcode {
200 nvme_admin_delete_sq = 0x00,
201 nvme_admin_create_sq = 0x01,
Krzysztof Wierzbicki2ddc4f72011-02-28 08:27:13 +0100202 nvme_admin_get_log_page = 0x02,
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500203 nvme_admin_delete_cq = 0x04,
204 nvme_admin_create_cq = 0x05,
205 nvme_admin_identify = 0x06,
206 nvme_admin_abort_cmd = 0x08,
207 nvme_admin_set_features = 0x09,
Krzysztof Wierzbicki2ddc4f72011-02-28 08:27:13 +0100208 nvme_admin_get_features = 0x0a,
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500209 nvme_admin_async_event = 0x0c,
Krzysztof Wierzbicki2ddc4f72011-02-28 08:27:13 +0100210 nvme_admin_activate_fw = 0x10,
211 nvme_admin_download_fw = 0x11,
212 nvme_admin_format_nvm = 0x80,
213 nvme_admin_security_send = 0x81,
214 nvme_admin_security_recv = 0x82,
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500215};
216
217enum {
218 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
219 NVME_CQ_IRQ_ENABLED = (1 << 1),
220 NVME_SQ_PRIO_URGENT = (0 << 1),
221 NVME_SQ_PRIO_HIGH = (1 << 1),
222 NVME_SQ_PRIO_MEDIUM = (2 << 1),
223 NVME_SQ_PRIO_LOW = (3 << 1),
224 NVME_FEAT_ARBITRATION = 0x01,
225 NVME_FEAT_POWER_MGMT = 0x02,
226 NVME_FEAT_LBA_RANGE = 0x03,
227 NVME_FEAT_TEMP_THRESH = 0x04,
228 NVME_FEAT_ERR_RECOVERY = 0x05,
229 NVME_FEAT_VOLATILE_WC = 0x06,
230 NVME_FEAT_NUM_QUEUES = 0x07,
231 NVME_FEAT_IRQ_COALESCE = 0x08,
232 NVME_FEAT_IRQ_CONFIG = 0x09,
233 NVME_FEAT_WRITE_ATOMIC = 0x0a,
234 NVME_FEAT_ASYNC_EVENT = 0x0b,
235 NVME_FEAT_SW_PROGRESS = 0x0c,
236};
237
238struct nvme_identify {
239 __u8 opcode;
240 __u8 flags;
241 __u16 command_id;
242 __le32 nsid;
243 __u64 rsvd2[2];
244 __le64 prp1;
245 __le64 prp2;
246 __le32 cns;
247 __u32 rsvd11[5];
248};
249
250struct nvme_features {
251 __u8 opcode;
252 __u8 flags;
253 __u16 command_id;
254 __le32 nsid;
255 __u64 rsvd2[2];
256 __le64 prp1;
257 __le64 prp2;
258 __le32 fid;
259 __le32 dword11;
260 __u32 rsvd12[4];
261};
262
263struct nvme_create_cq {
264 __u8 opcode;
265 __u8 flags;
266 __u16 command_id;
Matthew Wilcox6ee44cd2011-02-03 10:58:26 -0500267 __u32 rsvd1[5];
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500268 __le64 prp1;
269 __u64 rsvd8;
270 __le16 cqid;
271 __le16 qsize;
272 __le16 cq_flags;
273 __le16 irq_vector;
274 __u32 rsvd12[4];
275};
276
277struct nvme_create_sq {
278 __u8 opcode;
279 __u8 flags;
280 __u16 command_id;
Matthew Wilcox6ee44cd2011-02-03 10:58:26 -0500281 __u32 rsvd1[5];
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500282 __le64 prp1;
283 __u64 rsvd8;
284 __le16 sqid;
285 __le16 qsize;
286 __le16 sq_flags;
287 __le16 cqid;
Matthew Wilcox6ee44cd2011-02-03 10:58:26 -0500288 __u32 rsvd12[4];
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500289};
290
291struct nvme_delete_queue {
292 __u8 opcode;
293 __u8 flags;
294 __u16 command_id;
295 __u32 rsvd1[9];
296 __le16 qid;
Matthew Wilcox6ee44cd2011-02-03 10:58:26 -0500297 __u16 rsvd10;
298 __u32 rsvd11[5];
299};
300
301struct nvme_download_firmware {
302 __u8 opcode;
303 __u8 flags;
304 __u16 command_id;
305 __u32 rsvd1[5];
306 __le64 prp1;
307 __le64 prp2;
308 __le32 numd;
309 __le32 offset;
310 __u32 rsvd12[4];
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500311};
312
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500313struct nvme_command {
314 union {
315 struct nvme_common_command common;
316 struct nvme_rw_command rw;
317 struct nvme_identify identify;
318 struct nvme_features features;
319 struct nvme_create_cq create_cq;
320 struct nvme_create_sq create_sq;
321 struct nvme_delete_queue delete_queue;
Matthew Wilcox6ee44cd2011-02-03 10:58:26 -0500322 struct nvme_download_firmware dlfw;
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500323 };
324};
325
326/* XXX: Sync with spec */
327enum {
328 NVME_SC_SUCCESS = 0x0,
329 NVME_SC_INVALID_OPCODE = 0x1,
330 NVME_SC_INVALID_FIELD = 0x2,
331 NVME_SC_CMDID_CONFLICT = 0x3,
332 NVME_SC_DATA_XFER_ERROR = 0x4,
333 NVME_SC_POWER_LOSS = 0x5,
334 NVME_SC_INTERNAL = 0x6,
335 NVME_SC_ABORT_REQ = 0x7,
336 NVME_SC_ABORT_QUEUE = 0x8,
337 NVME_SC_FUSED_FAIL = 0x9,
338 NVME_SC_FUSED_MISSING = 0xa,
Matthew Wilcox7a63e072011-02-03 09:20:57 -0500339 NVME_SC_INVALID_NS = 0xb,
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500340 NVME_SC_LBA_RANGE = 0x80,
341 NVME_SC_CAP_EXCEEDED = 0x81,
342 NVME_SC_NS_NOT_READY = 0x82,
343 NVME_SC_CQ_INVALID = 0x100,
344 NVME_SC_QID_INVALID = 0x101,
345 NVME_SC_QUEUE_SIZE = 0x102,
Matthew Wilcox7a63e072011-02-03 09:20:57 -0500346 NVME_SC_ABORT_LIMIT = 0x103,
347 NVME_SC_ABORT_MISSING = 0x104,
348 NVME_SC_ASYNC_LIMIT = 0x105,
349 NVME_SC_FIRMWARE_SLOT = 0x106,
350 NVME_SC_FIRMWARE_IMAGE = 0x107,
351 NVME_SC_INVALID_VECTOR = 0x108,
352 NVME_SC_INVALID_LOG_PAGE = 0x109,
353 NVME_SC_INVALID_FORMAT = 0x10a,
354 NVME_SC_BAD_ATTRIBUTES = 0x180,
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500355 NVME_SC_WRITE_FAULT = 0x280,
356 NVME_SC_READ_ERROR = 0x281,
Matthew Wilcox7a63e072011-02-03 09:20:57 -0500357 NVME_SC_GUARD_CHECK = 0x282,
358 NVME_SC_APPTAG_CHECK = 0x283,
359 NVME_SC_REFTAG_CHECK = 0x284,
360 NVME_SC_COMPARE_FAILED = 0x285,
361 NVME_SC_ACCESS_DENIED = 0x286,
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500362};
363
364struct nvme_completion {
365 __le32 result; /* Used by admin commands to return data */
Matthew Wilcox6ee44cd2011-02-03 10:58:26 -0500366 __u32 rsvd;
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500367 __le16 sq_head; /* how much of this queue may be reclaimed */
368 __le16 sq_id; /* submission queue that generated this entry */
369 __u16 command_id; /* of the command which completed */
370 __le16 status; /* did the command fail, and if so, why? */
371};
372
Matthew Wilcoxa53295b2011-02-01 16:13:29 -0500373struct nvme_user_io {
374 __u8 opcode;
375 __u8 flags;
376 __u16 control;
377 __u32 nsid;
378 __u64 metadata;
379 __u64 addr;
380 __u64 slba;
381 __u16 nblocks;
382 __u16 block_shift;
383 __u32 dsmgmt;
384 __u32 reftag;
385 __u16 apptag;
386 __u16 appmask;
387 __u32 result;
388};
389
Matthew Wilcox6ee44cd2011-02-03 10:58:26 -0500390struct nvme_dlfw {
391 __u64 addr;
392 __u32 length; /* In dwords */
393 __u32 offset; /* In dwords */
394};
395
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500396#define NVME_IOCTL_IDENTIFY_NS _IOW('N', 0x40, struct nvme_id_ns)
397#define NVME_IOCTL_IDENTIFY_CTRL _IOW('N', 0x41, struct nvme_id_ctrl)
398#define NVME_IOCTL_GET_RANGE_TYPE _IOW('N', 0x42, struct nvme_lba_range_type)
Matthew Wilcoxa53295b2011-02-01 16:13:29 -0500399#define NVME_IOCTL_SUBMIT_IO _IOWR('N', 0x43, struct nvme_rw_command)
Matthew Wilcox6ee44cd2011-02-03 10:58:26 -0500400#define NVME_IOCTL_DOWNLOAD_FW _IOR('N', 0x44, struct nvme_dlfw)
401#define NVME_IOCTL_ACTIVATE_FW _IO('N', 0x45)
Matthew Wilcoxb60503b2011-01-20 12:50:14 -0500402
403#endif /* _LINUX_NVME_H */