blob: 2949cfc2dd31ab9c234c55cf706c09f8e6848573 [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
Jeff Garzikfb9f8902007-03-02 18:17:22 -05002 * pata_cmd64x.c - CMD64x PATA for new ATA layer
Jeff Garzik669a5db2006-08-29 18:12:40 -04003 * (C) 2005 Red Hat Inc
Alan Coxab771632008-10-27 15:09:10 +00004 * Alan Cox <alan@lxorguk.ukuu.org.uk>
Bartlomiej Zolnierkiewicza2bd6222010-01-18 18:14:55 +01005 * (C) 2009-2010 Bartlomiej Zolnierkiewicz
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +03006 * (C) 2012 MontaVista Software, LLC <source@mvista.com>
Jeff Garzik669a5db2006-08-29 18:12:40 -04007 *
8 * Based upon
9 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
10 *
11 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
12 * Note, this driver is not used at all on other systems because
13 * there the "BIOS" has done all of the following already.
14 * Due to massive hardware bugs, UltraDMA is only supported
15 * on the 646U2 and not on the 646U.
16 *
17 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
18 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
19 *
20 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
21 *
22 * TODO
23 * Testing work
24 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040025
Jeff Garzik669a5db2006-08-29 18:12:40 -040026#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/blkdev.h>
31#include <linux/delay.h>
32#include <scsi/scsi_host.h>
33#include <linux/libata.h>
34
35#define DRV_NAME "pata_cmd64x"
Sergei Shtylyovb8cec3c2012-03-11 22:28:18 +030036#define DRV_VERSION "0.2.18"
Jeff Garzik669a5db2006-08-29 18:12:40 -040037
38/*
39 * CMD64x specific registers definition.
40 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040041
Jeff Garzik669a5db2006-08-29 18:12:40 -040042enum {
43 CFR = 0x50,
Bartlomiej Zolnierkiewicz03a849e2010-01-18 18:15:11 +010044 CFR_INTR_CH0 = 0x04,
James Bottomley9281b162011-04-24 14:30:14 -050045 CNTRL = 0x51,
46 CNTRL_CH0 = 0x04,
47 CNTRL_CH1 = 0x08,
Jeff Garzik669a5db2006-08-29 18:12:40 -040048 CMDTIM = 0x52,
49 ARTTIM0 = 0x53,
50 DRWTIM0 = 0x54,
51 ARTTIM1 = 0x55,
52 DRWTIM1 = 0x56,
53 ARTTIM23 = 0x57,
54 ARTTIM23_DIS_RA2 = 0x04,
55 ARTTIM23_DIS_RA3 = 0x08,
56 ARTTIM23_INTR_CH1 = 0x10,
Jeff Garzik669a5db2006-08-29 18:12:40 -040057 DRWTIM2 = 0x58,
58 BRST = 0x59,
59 DRWTIM3 = 0x5b,
60 BMIDECR0 = 0x70,
61 MRDMODE = 0x71,
62 MRDMODE_INTR_CH0 = 0x04,
63 MRDMODE_INTR_CH1 = 0x08,
Jeff Garzik669a5db2006-08-29 18:12:40 -040064 BMIDESR0 = 0x72,
65 UDIDETCR0 = 0x73,
66 DTPR0 = 0x74,
67 BMIDECR1 = 0x78,
68 BMIDECSR = 0x79,
Jeff Garzik669a5db2006-08-29 18:12:40 -040069 UDIDETCR1 = 0x7B,
70 DTPR1 = 0x7C
71};
72
Jeff Garzika73984a2007-03-09 08:37:46 -050073static int cmd648_cable_detect(struct ata_port *ap)
Jeff Garzik669a5db2006-08-29 18:12:40 -040074{
75 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
76 u8 r;
77
78 /* Check cable detect bits */
79 pci_read_config_byte(pdev, BMIDECSR, &r);
80 if (r & (1 << ap->port_no))
Jeff Garzika73984a2007-03-09 08:37:46 -050081 return ATA_CBL_PATA80;
82 return ATA_CBL_PATA40;
Jeff Garzik669a5db2006-08-29 18:12:40 -040083}
84
85/**
Bartlomiej Zolnierkiewicz57242762011-10-11 19:57:40 +020086 * cmd64x_set_timing - set PIO and MWDMA timing
Jeff Garzik669a5db2006-08-29 18:12:40 -040087 * @ap: ATA interface
88 * @adev: ATA device
Alan Cox05d1eff2007-08-10 13:59:49 -070089 * @mode: mode
Jeff Garzik669a5db2006-08-29 18:12:40 -040090 *
Alan Cox05d1eff2007-08-10 13:59:49 -070091 * Called to do the PIO and MWDMA mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -040092 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040093
Alan Cox05d1eff2007-08-10 13:59:49 -070094static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode)
Jeff Garzik669a5db2006-08-29 18:12:40 -040095{
96 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
97 struct ata_timing t;
98 const unsigned long T = 1000000 / 33;
99 const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
Jeff Garzik85cd7252006-08-31 00:03:49 -0400100
Jeff Garzik669a5db2006-08-29 18:12:40 -0400101 u8 reg;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400102
Jeff Garzik669a5db2006-08-29 18:12:40 -0400103 /* Port layout is not logical so use a table */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400104 const u8 arttim_port[2][2] = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400105 { ARTTIM0, ARTTIM1 },
106 { ARTTIM23, ARTTIM23 }
107 };
108 const u8 drwtim_port[2][2] = {
109 { DRWTIM0, DRWTIM1 },
110 { DRWTIM2, DRWTIM3 }
111 };
Jeff Garzik85cd7252006-08-31 00:03:49 -0400112
Jeff Garzik669a5db2006-08-29 18:12:40 -0400113 int arttim = arttim_port[ap->port_no][adev->devno];
114 int drwtim = drwtim_port[ap->port_no][adev->devno];
Jeff Garzik85cd7252006-08-31 00:03:49 -0400115
Alan Cox05d1eff2007-08-10 13:59:49 -0700116 /* ata_timing_compute is smart and will produce timings for MWDMA
117 that don't violate the drives PIO capabilities. */
118 if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400119 printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
120 return;
121 }
122 if (ap->port_no) {
123 /* Slave has shared address setup */
124 struct ata_device *pair = ata_dev_pair(adev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400125
Jeff Garzik669a5db2006-08-29 18:12:40 -0400126 if (pair) {
127 struct ata_timing tp;
128 ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
129 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
130 }
131 }
Jeff Garzik85cd7252006-08-31 00:03:49 -0400132
Jeff Garzik669a5db2006-08-29 18:12:40 -0400133 printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
134 t.active, t.recover, t.setup);
135 if (t.recover > 16) {
136 t.active += t.recover - 16;
137 t.recover = 16;
138 }
139 if (t.active > 16)
140 t.active = 16;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400141
Jeff Garzik669a5db2006-08-29 18:12:40 -0400142 /* Now convert the clocks into values we can actually stuff into
143 the chip */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400144
Bartlomiej Zolnierkiewicza2bd6222010-01-18 18:14:55 +0100145 if (t.recover == 16)
146 t.recover = 0;
147 else if (t.recover > 1)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400148 t.recover--;
149 else
150 t.recover = 15;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400151
Jeff Garzik669a5db2006-08-29 18:12:40 -0400152 if (t.setup > 4)
153 t.setup = 0xC0;
154 else
155 t.setup = setup_data[t.setup];
Jeff Garzik85cd7252006-08-31 00:03:49 -0400156
Jeff Garzik669a5db2006-08-29 18:12:40 -0400157 t.active &= 0x0F; /* 0 = 16 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400158
Jeff Garzik669a5db2006-08-29 18:12:40 -0400159 /* Load setup timing */
160 pci_read_config_byte(pdev, arttim, &reg);
161 reg &= 0x3F;
162 reg |= t.setup;
163 pci_write_config_byte(pdev, arttim, reg);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400164
Jeff Garzik669a5db2006-08-29 18:12:40 -0400165 /* Load active/recovery */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400166 pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400167}
168
169/**
Alan Cox05d1eff2007-08-10 13:59:49 -0700170 * cmd64x_set_piomode - set initial PIO mode data
171 * @ap: ATA interface
172 * @adev: ATA device
173 *
174 * Used when configuring the devices ot set the PIO timings. All the
175 * actual work is done by the PIO/MWDMA setting helper
176 */
177
178static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
179{
180 cmd64x_set_timing(ap, adev, adev->pio_mode);
181}
182
183/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400184 * cmd64x_set_dmamode - set initial DMA mode data
185 * @ap: ATA interface
186 * @adev: ATA device
187 *
188 * Called to do the DMA mode setup.
189 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400190
Jeff Garzik669a5db2006-08-29 18:12:40 -0400191static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
192{
193 static const u8 udma_data[] = {
Alan6a40da02007-01-24 11:49:03 +0000194 0x30, 0x20, 0x10, 0x20, 0x10, 0x00
Jeff Garzik669a5db2006-08-29 18:12:40 -0400195 };
Jeff Garzik85cd7252006-08-31 00:03:49 -0400196
Jeff Garzik669a5db2006-08-29 18:12:40 -0400197 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
198 u8 regU, regD;
199
200 int pciU = UDIDETCR0 + 8 * ap->port_no;
201 int pciD = BMIDESR0 + 8 * ap->port_no;
202 int shift = 2 * adev->devno;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400203
Jeff Garzik669a5db2006-08-29 18:12:40 -0400204 pci_read_config_byte(pdev, pciD, &regD);
205 pci_read_config_byte(pdev, pciU, &regU);
206
Alan6a40da02007-01-24 11:49:03 +0000207 /* DMA bits off */
208 regD &= ~(0x20 << adev->devno);
209 /* DMA control bits */
210 regU &= ~(0x30 << shift);
211 /* DMA timing bits */
212 regU &= ~(0x05 << adev->devno);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400213
Alan6a40da02007-01-24 11:49:03 +0000214 if (adev->dma_mode >= XFER_UDMA_0) {
Adrian Bunk24b7ce92007-10-20 01:02:48 +0200215 /* Merge the timing value */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400216 regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
Alan6a40da02007-01-24 11:49:03 +0000217 /* Merge the control bits */
218 regU |= 1 << adev->devno; /* UDMA on */
Bartlomiej Zolnierkiewicz509426b2009-12-20 19:22:33 +0100219 if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
Alan6a40da02007-01-24 11:49:03 +0000220 regU |= 4 << adev->devno;
Alan Cox05d1eff2007-08-10 13:59:49 -0700221 } else {
222 regU &= ~ (1 << adev->devno); /* UDMA off */
223 cmd64x_set_timing(ap, adev, adev->dma_mode);
224 }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400225
226 regD |= 0x20 << adev->devno;
227
228 pci_write_config_byte(pdev, pciU, regU);
229 pci_write_config_byte(pdev, pciD, regD);
230}
231
232/**
Sergei Shtylyovb8cec3c2012-03-11 22:28:18 +0300233 * cmd64x_sff_irq_check - check IDE interrupt
234 * @ap: ATA interface
235 *
236 * Check IDE interrupt in CFR/ARTTIM23 registers.
237 */
238
239static bool cmd64x_sff_irq_check(struct ata_port *ap)
240{
241 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
242 int irq_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
243 int irq_reg = ap->port_no ? ARTTIM23 : CFR;
244 u8 irq_stat;
245
246 /* NOTE: reading the register should clear the interrupt */
247 pci_read_config_byte(pdev, irq_reg, &irq_stat);
248
249 return irq_stat & irq_mask;
250}
251
252/**
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300253 * cmd64x_sff_irq_clear - clear IDE interrupt
254 * @ap: ATA interface
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300255 *
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300256 * Clear IDE interrupt in CFR/ARTTIM23 and DMA status registers.
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300257 */
258
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300259static void cmd64x_sff_irq_clear(struct ata_port *ap)
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300260{
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300261 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
262 int irq_reg = ap->port_no ? ARTTIM23 : CFR;
263 u8 irq_stat;
264
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300265 ata_bmdma_irq_clear(ap);
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300266
267 /* Reading the register should be enough to clear the interrupt */
268 pci_read_config_byte(pdev, irq_reg, &irq_stat);
269}
270
271/**
Sergei Shtylyovb8cec3c2012-03-11 22:28:18 +0300272 * cmd648_sff_irq_check - check IDE interrupt
273 * @ap: ATA interface
274 *
275 * Check IDE interrupt in MRDMODE register.
276 */
277
278static bool cmd648_sff_irq_check(struct ata_port *ap)
279{
280 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
281 unsigned long base = pci_resource_start(pdev, 4);
282 int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0;
283 u8 mrdmode = inb(base + 1);
284
285 return mrdmode & irq_mask;
286}
287
288/**
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300289 * cmd648_sff_irq_clear - clear IDE interrupt
290 * @ap: ATA interface
Jeff Garzik669a5db2006-08-29 18:12:40 -0400291 *
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300292 * Clear IDE interrupt in MRDMODE and DMA status registers.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400293 */
294
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300295static void cmd648_sff_irq_clear(struct ata_port *ap)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400296{
Jeff Garzik669a5db2006-08-29 18:12:40 -0400297 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300298 unsigned long base = pci_resource_start(pdev, 4);
299 int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0;
300 u8 mrdmode;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400301
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300302 ata_bmdma_irq_clear(ap);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400303
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300304 /* Clear this port's interrupt bit (leaving the other port alone) */
305 mrdmode = inb(base + 1);
306 mrdmode &= ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1);
307 outb(mrdmode | irq_mask, base + 1);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400308}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400309
Jeff Garzik669a5db2006-08-29 18:12:40 -0400310/**
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300311 * cmd646r1_bmdma_stop - DMA stop callback
Jeff Garzik669a5db2006-08-29 18:12:40 -0400312 * @qc: Command in progress
313 *
Jeff Garzik06393af2009-12-20 15:39:55 -0500314 * Stub for now while investigating the r1 quirk in the old driver.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400315 */
316
Jeff Garzik06393af2009-12-20 15:39:55 -0500317static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400318{
319 ata_bmdma_stop(qc);
320}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400321
Jeff Garzik669a5db2006-08-29 18:12:40 -0400322static struct scsi_host_template cmd64x_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900323 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400324};
325
Tejun Heo029cfd62008-03-25 12:22:49 +0900326static const struct ata_port_operations cmd64x_base_ops = {
327 .inherits = &ata_bmdma_port_ops,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400328 .set_piomode = cmd64x_set_piomode,
329 .set_dmamode = cmd64x_set_dmamode,
Tejun Heo029cfd62008-03-25 12:22:49 +0900330};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400331
Tejun Heo029cfd62008-03-25 12:22:49 +0900332static struct ata_port_operations cmd64x_port_ops = {
333 .inherits = &cmd64x_base_ops,
Sergei Shtylyovb8cec3c2012-03-11 22:28:18 +0300334 .sff_irq_check = cmd64x_sff_irq_check,
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300335 .sff_irq_clear = cmd64x_sff_irq_clear,
Jeff Garzika73984a2007-03-09 08:37:46 -0500336 .cable_detect = ata_cable_40wire,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400337};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400338
339static struct ata_port_operations cmd646r1_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900340 .inherits = &cmd64x_base_ops,
Sergei Shtylyovb8cec3c2012-03-11 22:28:18 +0300341 .sff_irq_check = cmd64x_sff_irq_check,
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300342 .sff_irq_clear = cmd64x_sff_irq_clear,
Jeff Garzik06393af2009-12-20 15:39:55 -0500343 .bmdma_stop = cmd646r1_bmdma_stop,
Tejun Heo029cfd62008-03-25 12:22:49 +0900344 .cable_detect = ata_cable_40wire,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400345};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400346
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300347static struct ata_port_operations cmd646r3_port_ops = {
348 .inherits = &cmd64x_base_ops,
Sergei Shtylyovb8cec3c2012-03-11 22:28:18 +0300349 .sff_irq_check = cmd648_sff_irq_check,
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300350 .sff_irq_clear = cmd648_sff_irq_clear,
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300351 .cable_detect = ata_cable_40wire,
352};
353
Jeff Garzik669a5db2006-08-29 18:12:40 -0400354static struct ata_port_operations cmd648_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900355 .inherits = &cmd64x_base_ops,
Sergei Shtylyovb8cec3c2012-03-11 22:28:18 +0300356 .sff_irq_check = cmd648_sff_irq_check,
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300357 .sff_irq_clear = cmd648_sff_irq_clear,
Tejun Heo029cfd62008-03-25 12:22:49 +0900358 .cable_detect = cmd648_cable_detect,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400359};
360
Bartlomiej Zolnierkiewiczf4c6ae52011-10-11 19:56:03 +0200361static void cmd64x_fixup(struct pci_dev *pdev)
362{
363 u8 mrdmode;
364
365 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
366 pci_read_config_byte(pdev, MRDMODE, &mrdmode);
367 mrdmode &= ~0x30; /* IRQ set up */
368 mrdmode |= 0x02; /* Memory read line enable */
369 pci_write_config_byte(pdev, MRDMODE, mrdmode);
370
371 /* PPC specific fixup copied from old driver */
372#ifdef CONFIG_PPC
373 pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
374#endif
375}
376
Jeff Garzik669a5db2006-08-29 18:12:40 -0400377static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
378{
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300379 static const struct ata_port_info cmd_info[7] = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400380 { /* CMD 643 - no UDMA */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400381 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100382 .pio_mask = ATA_PIO4,
383 .mwdma_mask = ATA_MWDMA2,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400384 .port_ops = &cmd64x_port_ops
385 },
386 { /* CMD 646 with broken UDMA */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400387 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100388 .pio_mask = ATA_PIO4,
389 .mwdma_mask = ATA_MWDMA2,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400390 .port_ops = &cmd64x_port_ops
391 },
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300392 { /* CMD 646U with broken UDMA */
393 .flags = ATA_FLAG_SLAVE_POSS,
394 .pio_mask = ATA_PIO4,
395 .mwdma_mask = ATA_MWDMA2,
396 .port_ops = &cmd646r3_port_ops
397 },
398 { /* CMD 646U2 with working UDMA */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400399 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100400 .pio_mask = ATA_PIO4,
401 .mwdma_mask = ATA_MWDMA2,
Alan Coxdbf0c892007-07-26 18:43:01 +0100402 .udma_mask = ATA_UDMA2,
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300403 .port_ops = &cmd646r3_port_ops
Jeff Garzik669a5db2006-08-29 18:12:40 -0400404 },
405 { /* CMD 646 rev 1 */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400406 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100407 .pio_mask = ATA_PIO4,
408 .mwdma_mask = ATA_MWDMA2,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400409 .port_ops = &cmd646r1_port_ops
410 },
411 { /* CMD 648 */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400412 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100413 .pio_mask = ATA_PIO4,
414 .mwdma_mask = ATA_MWDMA2,
Alan Coxdbf0c892007-07-26 18:43:01 +0100415 .udma_mask = ATA_UDMA4,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400416 .port_ops = &cmd648_port_ops
417 },
418 { /* CMD 649 */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400419 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100420 .pio_mask = ATA_PIO4,
421 .mwdma_mask = ATA_MWDMA2,
Alan Coxdbf0c892007-07-26 18:43:01 +0100422 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400423 .port_ops = &cmd648_port_ops
424 }
425 };
Jeff Garzik641589b2012-07-25 16:07:40 -0400426 const struct ata_port_info *ppi[] = {
James Bottomley9281b162011-04-24 14:30:14 -0500427 &cmd_info[id->driver_data],
428 &cmd_info[id->driver_data],
429 NULL
430 };
Bartlomiej Zolnierkiewiczf4c6ae52011-10-11 19:56:03 +0200431 u8 reg;
Tejun Heof08048e2008-03-25 12:22:47 +0900432 int rc;
James Bottomley9281b162011-04-24 14:30:14 -0500433 struct pci_dev *bridge = pdev->bus->self;
434 /* mobility split bridges don't report enabled ports correctly */
435 int port_ok = !(bridge && bridge->vendor ==
436 PCI_VENDOR_ID_MOBILITY_ELECTRONICS);
437 /* all (with exceptions below) apart from 643 have CNTRL_CH0 bit */
438 int cntrl_ch0_ok = (id->driver_data != 0);
Tejun Heof08048e2008-03-25 12:22:47 +0900439
440 rc = pcim_enable_device(pdev);
441 if (rc)
442 return rc;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400443
Jeff Garzik669a5db2006-08-29 18:12:40 -0400444 if (id->driver_data == 0) /* 643 */
Tejun Heo9363c382008-04-07 22:47:16 +0900445 ata_pci_bmdma_clear_simplex(pdev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400446
Sergei Shtylyov8fcfa7b2012-03-11 22:29:02 +0300447 if (pdev->device == PCI_DEVICE_ID_CMD_646)
448 switch (pdev->revision) {
449 /* UDMA works since rev 5 */
450 default:
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300451 ppi[0] = &cmd_info[3];
452 ppi[1] = &cmd_info[3];
453 break;
454 /* Interrupts in MRDMODE since rev 3 */
455 case 3:
456 case 4:
Tejun Heo1626aeb2007-05-04 12:43:58 +0200457 ppi[0] = &cmd_info[2];
James Bottomley9281b162011-04-24 14:30:14 -0500458 ppi[1] = &cmd_info[2];
Sergei Shtylyov8fcfa7b2012-03-11 22:29:02 +0300459 break;
Sergei Shtylyov8fcfa7b2012-03-11 22:29:02 +0300460 /* Rev 1 with other problems? */
461 case 1:
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300462 ppi[0] = &cmd_info[4];
463 ppi[1] = &cmd_info[4];
Sergei Shtylyov8fcfa7b2012-03-11 22:29:02 +0300464 /* FALL THRU */
465 /* Early revs have no CNTRL_CH0 */
466 case 2:
467 case 0:
James Bottomley9281b162011-04-24 14:30:14 -0500468 cntrl_ch0_ok = 0;
Sergei Shtylyov8fcfa7b2012-03-11 22:29:02 +0300469 break;
470 }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400471
Bartlomiej Zolnierkiewiczf4c6ae52011-10-11 19:56:03 +0200472 cmd64x_fixup(pdev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400473
James Bottomley9281b162011-04-24 14:30:14 -0500474 /* check for enabled ports */
475 pci_read_config_byte(pdev, CNTRL, &reg);
476 if (!port_ok)
Joe Perchesa52f5142012-10-28 01:05:40 -0700477 dev_notice(&pdev->dev, "Mobility Bridge detected, ignoring CNTRL port enable/disable\n");
James Bottomley9281b162011-04-24 14:30:14 -0500478 if (port_ok && cntrl_ch0_ok && !(reg & CNTRL_CH0)) {
Joe Perchesa52f5142012-10-28 01:05:40 -0700479 dev_notice(&pdev->dev, "Primary port is disabled\n");
James Bottomley9281b162011-04-24 14:30:14 -0500480 ppi[0] = &ata_dummy_port_info;
Jeff Garzik641589b2012-07-25 16:07:40 -0400481
James Bottomley9281b162011-04-24 14:30:14 -0500482 }
483 if (port_ok && !(reg & CNTRL_CH1)) {
Joe Perchesa52f5142012-10-28 01:05:40 -0700484 dev_notice(&pdev->dev, "Secondary port is disabled\n");
James Bottomley9281b162011-04-24 14:30:14 -0500485 ppi[1] = &ata_dummy_port_info;
486 }
487
Tejun Heo1c5afdf2010-05-19 22:10:22 +0200488 return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400489}
490
Tejun Heo438ac6d2007-03-02 17:31:26 +0900491#ifdef CONFIG_PM
Alan7f72a372006-11-22 16:59:07 +0000492static int cmd64x_reinit_one(struct pci_dev *pdev)
493{
Tejun Heof08048e2008-03-25 12:22:47 +0900494 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heof08048e2008-03-25 12:22:47 +0900495 int rc;
496
497 rc = ata_pci_device_do_resume(pdev);
498 if (rc)
499 return rc;
500
Bartlomiej Zolnierkiewiczf4c6ae52011-10-11 19:56:03 +0200501 cmd64x_fixup(pdev);
502
Tejun Heof08048e2008-03-25 12:22:47 +0900503 ata_host_resume(host);
504 return 0;
Alan7f72a372006-11-22 16:59:07 +0000505}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900506#endif
Alan7f72a372006-11-22 16:59:07 +0000507
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400508static const struct pci_device_id cmd64x[] = {
509 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
510 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300511 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 5 },
512 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 6 },
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400513
514 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400515};
516
517static struct pci_driver cmd64x_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400518 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400519 .id_table = cmd64x,
520 .probe = cmd64x_init_one,
Alan7f72a372006-11-22 16:59:07 +0000521 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900522#ifdef CONFIG_PM
Alan7f72a372006-11-22 16:59:07 +0000523 .suspend = ata_pci_device_suspend,
524 .resume = cmd64x_reinit_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900525#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400526};
527
Axel Lin2fc75da2012-04-19 13:43:05 +0800528module_pci_driver(cmd64x_pci_driver);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400529
Jeff Garzik669a5db2006-08-29 18:12:40 -0400530MODULE_AUTHOR("Alan Cox");
531MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
532MODULE_LICENSE("GPL");
533MODULE_DEVICE_TABLE(pci, cmd64x);
534MODULE_VERSION(DRV_VERSION);