| David Howells | b920de1 | 2008-02-08 04:19:31 -0800 | [diff] [blame] | 1 | /* MN10300 On-board I/O port module registers |
| 2 | * |
| 3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. |
| 4 | * Written by David Howells (dhowells@redhat.com) |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public Licence |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the Licence, or (at your option) any later version. |
| 10 | */ |
| 11 | #ifndef _ASM_PIO_REGS_H |
| 12 | #define _ASM_PIO_REGS_H |
| 13 | |
| 14 | #include <asm/cpu-regs.h> |
| 15 | #include <asm/intctl-regs.h> |
| 16 | |
| 17 | #ifdef __KERNEL__ |
| 18 | |
| 19 | /* I/O port 0 */ |
| 20 | #define P0MD __SYSREG(0xdb000000, u16) /* mode reg */ |
| 21 | #define P0MD_0 0x0003 /* mask */ |
| 22 | #define P0MD_0_IN 0x0000 /* input mode */ |
| 23 | #define P0MD_0_OUT 0x0001 /* output mode */ |
| 24 | #define P0MD_0_TM0IO 0x0002 /* timer 0 I/O mode */ |
| 25 | #define P0MD_0_EYECLK 0x0003 /* test signal output (clock) */ |
| 26 | #define P0MD_1 0x000c |
| 27 | #define P0MD_1_IN 0x0000 |
| 28 | #define P0MD_1_OUT 0x0004 |
| 29 | #define P0MD_1_TM1IO 0x0008 /* timer 1 I/O mode */ |
| 30 | #define P0MD_1_EYED 0x000c /* test signal output (data) */ |
| 31 | #define P0MD_2 0x0030 |
| 32 | #define P0MD_2_IN 0x0000 |
| 33 | #define P0MD_2_OUT 0x0010 |
| 34 | #define P0MD_2_TM2IO 0x0020 /* timer 2 I/O mode */ |
| 35 | #define P0MD_3 0x00c0 |
| 36 | #define P0MD_3_IN 0x0000 |
| 37 | #define P0MD_3_OUT 0x0040 |
| 38 | #define P0MD_3_TM3IO 0x0080 /* timer 3 I/O mode */ |
| 39 | #define P0MD_4 0x0300 |
| 40 | #define P0MD_4_IN 0x0000 |
| 41 | #define P0MD_4_OUT 0x0100 |
| 42 | #define P0MD_4_TM4IO 0x0200 /* timer 4 I/O mode */ |
| 43 | #define P0MD_4_XCTS 0x0300 /* XCTS input for serial port 2 */ |
| 44 | #define P0MD_5 0x0c00 |
| 45 | #define P0MD_5_IN 0x0000 |
| 46 | #define P0MD_5_OUT 0x0400 |
| 47 | #define P0MD_5_TM5IO 0x0800 /* timer 5 I/O mode */ |
| 48 | #define P0MD_6 0x3000 |
| 49 | #define P0MD_6_IN 0x0000 |
| 50 | #define P0MD_6_OUT 0x1000 |
| 51 | #define P0MD_6_TM6IOA 0x2000 /* timer 6 I/O mode A */ |
| 52 | #define P0MD_7 0xc000 |
| 53 | #define P0MD_7_IN 0x0000 |
| 54 | #define P0MD_7_OUT 0x4000 |
| 55 | #define P0MD_7_TM6IOB 0x8000 /* timer 6 I/O mode B */ |
| 56 | |
| 57 | #define P0IN __SYSREG(0xdb000004, u8) /* in reg */ |
| 58 | #define P0OUT __SYSREG(0xdb000008, u8) /* out reg */ |
| 59 | |
| 60 | #define P0TMIO __SYSREG(0xdb00000c, u8) /* TM pin I/O control reg */ |
| 61 | #define P0TMIO_TM0_IN 0x00 |
| 62 | #define P0TMIO_TM0_OUT 0x01 |
| 63 | #define P0TMIO_TM1_IN 0x00 |
| 64 | #define P0TMIO_TM1_OUT 0x02 |
| 65 | #define P0TMIO_TM2_IN 0x00 |
| 66 | #define P0TMIO_TM2_OUT 0x04 |
| 67 | #define P0TMIO_TM3_IN 0x00 |
| 68 | #define P0TMIO_TM3_OUT 0x08 |
| 69 | #define P0TMIO_TM4_IN 0x00 |
| 70 | #define P0TMIO_TM4_OUT 0x10 |
| 71 | #define P0TMIO_TM5_IN 0x00 |
| 72 | #define P0TMIO_TM5_OUT 0x20 |
| 73 | #define P0TMIO_TM6A_IN 0x00 |
| 74 | #define P0TMIO_TM6A_OUT 0x40 |
| 75 | #define P0TMIO_TM6B_IN 0x00 |
| 76 | #define P0TMIO_TM6B_OUT 0x80 |
| 77 | |
| 78 | /* I/O port 1 */ |
| 79 | #define P1MD __SYSREG(0xdb000100, u16) /* mode reg */ |
| 80 | #define P1MD_0 0x0003 /* mask */ |
| 81 | #define P1MD_0_IN 0x0000 /* input mode */ |
| 82 | #define P1MD_0_OUT 0x0001 /* output mode */ |
| 83 | #define P1MD_0_TM7IO 0x0002 /* timer 7 I/O mode */ |
| 84 | #define P1MD_0_ADTRG 0x0003 /* A/D converter trigger mode */ |
| 85 | #define P1MD_1 0x000c |
| 86 | #define P1MD_1_IN 0x0000 |
| 87 | #define P1MD_1_OUT 0x0004 |
| 88 | #define P1MD_1_TM8IO 0x0008 /* timer 8 I/O mode */ |
| 89 | #define P1MD_1_XDMR0 0x000c /* DMA request input 0 mode */ |
| 90 | #define P1MD_2 0x0030 |
| 91 | #define P1MD_2_IN 0x0000 |
| 92 | #define P1MD_2_OUT 0x0010 |
| 93 | #define P1MD_2_TM9IO 0x0020 /* timer 9 I/O mode */ |
| 94 | #define P1MD_2_XDMR1 0x0030 /* DMA request input 1 mode */ |
| 95 | #define P1MD_3 0x00c0 |
| 96 | #define P1MD_3_IN 0x0000 |
| 97 | #define P1MD_3_OUT 0x0040 |
| 98 | #define P1MD_3_TM10IO 0x0080 /* timer 10 I/O mode */ |
| 99 | #define P1MD_3_FRQS0 0x00c0 /* CPU clock multiplier setting input 0 mode */ |
| 100 | #define P1MD_4 0x0300 |
| 101 | #define P1MD_4_IN 0x0000 |
| 102 | #define P1MD_4_OUT 0x0100 |
| 103 | #define P1MD_4_TM11IO 0x0200 /* timer 11 I/O mode */ |
| 104 | #define P1MD_4_FRQS1 0x0300 /* CPU clock multiplier setting input 1 mode */ |
| 105 | |
| 106 | #define P1IN __SYSREG(0xdb000104, u8) /* in reg */ |
| 107 | #define P1OUT __SYSREG(0xdb000108, u8) /* out reg */ |
| 108 | #define P1TMIO __SYSREG(0xdb00010c, u8) /* TM pin I/O control reg */ |
| 109 | #define P1TMIO_TM11_IN 0x00 |
| 110 | #define P1TMIO_TM11_OUT 0x01 |
| 111 | #define P1TMIO_TM10_IN 0x00 |
| 112 | #define P1TMIO_TM10_OUT 0x02 |
| 113 | #define P1TMIO_TM9_IN 0x00 |
| 114 | #define P1TMIO_TM9_OUT 0x04 |
| 115 | #define P1TMIO_TM8_IN 0x00 |
| 116 | #define P1TMIO_TM8_OUT 0x08 |
| 117 | #define P1TMIO_TM7_IN 0x00 |
| 118 | #define P1TMIO_TM7_OUT 0x10 |
| 119 | |
| 120 | /* I/O port 2 */ |
| 121 | #define P2MD __SYSREG(0xdb000200, u16) /* mode reg */ |
| 122 | #define P2MD_0 0x0003 /* mask */ |
| 123 | #define P2MD_0_IN 0x0000 /* input mode */ |
| 124 | #define P2MD_0_OUT 0x0001 /* output mode */ |
| 125 | #define P2MD_0_BOOTBW 0x0003 /* boot bus width selector mode */ |
| 126 | #define P2MD_1 0x000c |
| 127 | #define P2MD_1_IN 0x0000 |
| 128 | #define P2MD_1_OUT 0x0004 |
| 129 | #define P2MD_1_BOOTSEL 0x000c /* boot device selector mode */ |
| 130 | #define P2MD_2 0x0030 |
| 131 | #define P2MD_2_IN 0x0000 |
| 132 | #define P2MD_2_OUT 0x0010 |
| 133 | #define P2MD_3 0x00c0 |
| 134 | #define P2MD_3_IN 0x0000 |
| 135 | #define P2MD_3_OUT 0x0040 |
| 136 | #define P2MD_3_CKIO 0x00c0 /* mode */ |
| 137 | #define P2MD_4 0x0300 |
| 138 | #define P2MD_4_IN 0x0000 |
| 139 | #define P2MD_4_OUT 0x0100 |
| 140 | #define P2MD_4_CMOD 0x0300 /* mode */ |
| 141 | |
| 142 | #define P2IN __SYSREG(0xdb000204, u8) /* in reg */ |
| 143 | #define P2OUT __SYSREG(0xdb000208, u8) /* out reg */ |
| 144 | #define P2TMIO __SYSREG(0xdb00020c, u8) /* TM pin I/O control reg */ |
| 145 | |
| 146 | /* I/O port 3 */ |
| 147 | #define P3MD __SYSREG(0xdb000300, u16) /* mode reg */ |
| 148 | #define P3MD_0 0x0003 /* mask */ |
| 149 | #define P3MD_0_IN 0x0000 /* input mode */ |
| 150 | #define P3MD_0_OUT 0x0001 /* output mode */ |
| 151 | #define P3MD_0_AFRXD 0x0002 /* AFR interface mode */ |
| 152 | #define P3MD_1 0x000c |
| 153 | #define P3MD_1_IN 0x0000 |
| 154 | #define P3MD_1_OUT 0x0004 |
| 155 | #define P3MD_1_AFTXD 0x0008 /* AFR interface mode */ |
| 156 | #define P3MD_2 0x0030 |
| 157 | #define P3MD_2_IN 0x0000 |
| 158 | #define P3MD_2_OUT 0x0010 |
| 159 | #define P3MD_2_AFSCLK 0x0020 /* AFR interface mode */ |
| 160 | #define P3MD_3 0x00c0 |
| 161 | #define P3MD_3_IN 0x0000 |
| 162 | #define P3MD_3_OUT 0x0040 |
| 163 | #define P3MD_3_AFFS 0x0080 /* AFR interface mode */ |
| 164 | #define P3MD_4 0x0300 |
| 165 | #define P3MD_4_IN 0x0000 |
| 166 | #define P3MD_4_OUT 0x0100 |
| 167 | #define P3MD_4_AFEHC 0x0200 /* AFR interface mode */ |
| 168 | |
| 169 | #define P3IN __SYSREG(0xdb000304, u8) /* in reg */ |
| 170 | #define P3OUT __SYSREG(0xdb000308, u8) /* out reg */ |
| 171 | |
| 172 | /* I/O port 4 */ |
| 173 | #define P4MD __SYSREG(0xdb000400, u16) /* mode reg */ |
| 174 | #define P4MD_0 0x0003 /* mask */ |
| 175 | #define P4MD_0_IN 0x0000 /* input mode */ |
| 176 | #define P4MD_0_OUT 0x0001 /* output mode */ |
| 177 | #define P4MD_0_SCL0 0x0002 /* I2C/serial mode */ |
| 178 | #define P4MD_1 0x000c |
| 179 | #define P4MD_1_IN 0x0000 |
| 180 | #define P4MD_1_OUT 0x0004 |
| 181 | #define P4MD_1_SDA0 0x0008 |
| 182 | #define P4MD_2 0x0030 |
| 183 | #define P4MD_2_IN 0x0000 |
| 184 | #define P4MD_2_OUT 0x0010 |
| 185 | #define P4MD_2_SCL1 0x0020 |
| 186 | #define P4MD_3 0x00c0 |
| 187 | #define P4MD_3_IN 0x0000 |
| 188 | #define P4MD_3_OUT 0x0040 |
| 189 | #define P4MD_3_SDA1 0x0080 |
| 190 | #define P4MD_4 0x0300 |
| 191 | #define P4MD_4_IN 0x0000 |
| 192 | #define P4MD_4_OUT 0x0100 |
| 193 | #define P4MD_4_SBO0 0x0200 |
| 194 | #define P4MD_5 0x0c00 |
| 195 | #define P4MD_5_IN 0x0000 |
| 196 | #define P4MD_5_OUT 0x0400 |
| 197 | #define P4MD_5_SBO1 0x0800 |
| 198 | #define P4MD_6 0x3000 |
| 199 | #define P4MD_6_IN 0x0000 |
| 200 | #define P4MD_6_OUT 0x1000 |
| 201 | #define P4MD_6_SBT0 0x2000 |
| 202 | #define P4MD_7 0xc000 |
| 203 | #define P4MD_7_IN 0x0000 |
| 204 | #define P4MD_7_OUT 0x4000 |
| 205 | #define P4MD_7_SBT1 0x8000 |
| 206 | |
| 207 | #define P4IN __SYSREG(0xdb000404, u8) /* in reg */ |
| 208 | #define P4OUT __SYSREG(0xdb000408, u8) /* out reg */ |
| 209 | |
| 210 | /* I/O port 5 */ |
| 211 | #define P5MD __SYSREG(0xdb000500, u16) /* mode reg */ |
| 212 | #define P5MD_0 0x0003 /* mask */ |
| 213 | #define P5MD_0_IN 0x0000 /* input mode */ |
| 214 | #define P5MD_0_OUT 0x0001 /* output mode */ |
| 215 | #define P5MD_0_IRTXD 0x0002 /* IrDA mode */ |
| 216 | #define P5MD_0_SOUT 0x0004 /* serial mode */ |
| 217 | #define P5MD_1 0x000c |
| 218 | #define P5MD_1_IN 0x0000 |
| 219 | #define P5MD_1_OUT 0x0004 |
| 220 | #define P5MD_1_IRRXDS 0x0008 /* IrDA mode */ |
| 221 | #define P5MD_1_SIN 0x000c /* serial mode */ |
| 222 | #define P5MD_2 0x0030 |
| 223 | #define P5MD_2_IN 0x0000 |
| 224 | #define P5MD_2_OUT 0x0010 |
| 225 | #define P5MD_2_IRRXDF 0x0020 /* IrDA mode */ |
| 226 | |
| 227 | #define P5IN __SYSREG(0xdb000504, u8) /* in reg */ |
| 228 | #define P5OUT __SYSREG(0xdb000508, u8) /* out reg */ |
| 229 | |
| 230 | |
| 231 | #endif /* __KERNEL__ */ |
| 232 | |
| 233 | #endif /* _ASM_PIO_REGS_H */ |