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Kukjin Kim83014572011-11-06 13:54:56 +09001/* linux/arch/arm/mach-exynos/include/mach/map.h
Kukjin Kim7d30e8b2011-02-14 16:33:10 +09002 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * EXYNOS4 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17
18/*
19 * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
20 * So need to define it, and here is to avoid redefinition warning.
21 */
22#define S3C_UART_OFFSET (0x10000)
23
24#include <plat/map-s5p.h>
25
Kukjin Kim56b20922011-08-20 13:41:21 +090026#define EXYNOS4_PA_SYSRAM0 0x02025000
27#define EXYNOS4_PA_SYSRAM1 0x02020000
Kukjin Kim94c7ca72012-02-11 22:15:45 +090028#define EXYNOS5_PA_SYSRAM 0x02020000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090029
Sylwester Nawrocki604eefe2011-03-12 08:58:01 +090030#define EXYNOS4_PA_FIMC0 0x11800000
31#define EXYNOS4_PA_FIMC1 0x11810000
32#define EXYNOS4_PA_FIMC2 0x11820000
33#define EXYNOS4_PA_FIMC3 0x11830000
34
Andrzej Pietrasiewicz3dbe6d42012-03-10 02:45:42 -080035#define EXYNOS4_PA_JPEG 0x11840000
36
Sylwester Nawrocki06050e52012-05-12 15:31:53 +090037/* x = 0...1 */
38#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000))
39
Kamil Debski561ab532011-12-27 17:16:44 +090040#define EXYNOS4_PA_G2D 0x12800000
41
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090042#define EXYNOS4_PA_I2S0 0x03830000
43#define EXYNOS4_PA_I2S1 0xE3100000
44#define EXYNOS4_PA_I2S2 0xE2A00000
45
46#define EXYNOS4_PA_PCM0 0x03840000
47#define EXYNOS4_PA_PCM1 0x13980000
48#define EXYNOS4_PA_PCM2 0x13990000
49
50#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
51
52#define EXYNOS4_PA_ONENAND 0x0C000000
53#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
54
Kukjin Kim94c7ca72012-02-11 22:15:45 +090055#define EXYNOS_PA_CHIPID 0x10000000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090056
57#define EXYNOS4_PA_SYSCON 0x10010000
Kukjin Kim94c7ca72012-02-11 22:15:45 +090058#define EXYNOS5_PA_SYSCON 0x10050100
59
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090060#define EXYNOS4_PA_PMU 0x10020000
Kukjin Kim94c7ca72012-02-11 22:15:45 +090061#define EXYNOS5_PA_PMU 0x10040000
62
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090063#define EXYNOS4_PA_CMU 0x10030000
Kukjin Kim94c7ca72012-02-11 22:15:45 +090064#define EXYNOS5_PA_CMU 0x10010000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090065
Changhwan Youn2b740152011-03-11 10:39:35 +090066#define EXYNOS4_PA_SYSTIMER 0x10050000
Kukjin Kim94c7ca72012-02-11 22:15:45 +090067#define EXYNOS5_PA_SYSTIMER 0x101C0000
68
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090069#define EXYNOS4_PA_WATCHDOG 0x10060000
Kukjin Kim94c7ca72012-02-11 22:15:45 +090070#define EXYNOS5_PA_WATCHDOG 0x101D0000
71
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090072#define EXYNOS4_PA_RTC 0x10070000
73
Naveen Krishna Ch344021c2011-03-05 09:48:31 +090074#define EXYNOS4_PA_KEYPAD 0x100A0000
75
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090076#define EXYNOS4_PA_DMC0 0x10400000
MyungJoo Ham2bde0b02011-12-01 15:12:30 +090077#define EXYNOS4_PA_DMC1 0x10410000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090078
Changhwan Youneb13f2b2011-07-16 10:48:47 +090079#define EXYNOS4_PA_COMBINER 0x10440000
Kukjin Kim94c7ca72012-02-11 22:15:45 +090080#define EXYNOS5_PA_COMBINER 0x10440000
Changhwan Youneb13f2b2011-07-16 10:48:47 +090081
82#define EXYNOS4_PA_GIC_CPU 0x10480000
83#define EXYNOS4_PA_GIC_DIST 0x10490000
Changhwan Younc9ce7db2012-04-24 14:31:11 -070084#define EXYNOS5_PA_GIC_CPU 0x10482000
85#define EXYNOS5_PA_GIC_DIST 0x10481000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090086
87#define EXYNOS4_PA_COREPERI 0x10500000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090088#define EXYNOS4_PA_TWD 0x10500600
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090089#define EXYNOS4_PA_L2CC 0x10502000
90
Boojin Kim9ed76e02012-02-15 13:15:12 +090091#define EXYNOS4_PA_MDMA0 0x10810000
Kukjin Kim82145132012-09-17 19:08:09 +090092#define EXYNOS4_PA_MDMA1 0x12850000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090093#define EXYNOS4_PA_PDMA0 0x12680000
94#define EXYNOS4_PA_PDMA1 0x12690000
Thomas Abraham60806222012-04-10 08:37:59 -070095#define EXYNOS5_PA_MDMA0 0x10800000
96#define EXYNOS5_PA_MDMA1 0x11C10000
97#define EXYNOS5_PA_PDMA0 0x121A0000
98#define EXYNOS5_PA_PDMA1 0x121B0000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090099
100#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
KyongHo Chobca10b92012-04-04 09:23:02 -0700101#define EXYNOS4_PA_SYSMMU_2D_ACP 0x10A40000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900102#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
103#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
104#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
105#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
106#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
107#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
108#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
109#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
KyongHo Chobca10b92012-04-04 09:23:02 -0700110#define EXYNOS4_PA_SYSMMU_FIMC_ISP 0x12260000
111#define EXYNOS4_PA_SYSMMU_FIMC_DRC 0x12270000
112#define EXYNOS4_PA_SYSMMU_FIMC_FD 0x122A0000
113#define EXYNOS4_PA_SYSMMU_ISPCPU 0x122B0000
114#define EXYNOS4_PA_SYSMMU_FIMC_LITE0 0x123B0000
115#define EXYNOS4_PA_SYSMMU_FIMC_LITE1 0x123C0000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900116#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
117#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
118#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
119#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
120#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
121#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
122#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
KyongHo Chobca10b92012-04-04 09:23:02 -0700123
Shaik Ameer Basha11286582012-09-07 14:13:08 +0900124#define EXYNOS5_PA_GSC0 0x13E00000
125#define EXYNOS5_PA_GSC1 0x13E10000
126#define EXYNOS5_PA_GSC2 0x13E20000
127#define EXYNOS5_PA_GSC3 0x13E30000
128
KyongHo Chobca10b92012-04-04 09:23:02 -0700129#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000
130#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000
131#define EXYNOS5_PA_SYSMMU_2D 0x10A60000
132#define EXYNOS5_PA_SYSMMU_MFC_L 0x11200000
133#define EXYNOS5_PA_SYSMMU_MFC_R 0x11210000
134#define EXYNOS5_PA_SYSMMU_ROTATOR 0x11D40000
135#define EXYNOS5_PA_SYSMMU_MDMA2 0x11D50000
136#define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000
137#define EXYNOS5_PA_SYSMMU_IOP 0x12360000
138#define EXYNOS5_PA_SYSMMU_RTIC 0x12370000
KyongHo Chobca10b92012-04-04 09:23:02 -0700139#define EXYNOS5_PA_SYSMMU_ISP 0x13260000
140#define EXYNOS5_PA_SYSMMU_DRC 0x12370000
141#define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000
142#define EXYNOS5_PA_SYSMMU_SCALERP 0x13290000
143#define EXYNOS5_PA_SYSMMU_FD 0x132A0000
144#define EXYNOS5_PA_SYSMMU_ISPCPU 0x132B0000
145#define EXYNOS5_PA_SYSMMU_ODC 0x132C0000
146#define EXYNOS5_PA_SYSMMU_DIS0 0x132D0000
147#define EXYNOS5_PA_SYSMMU_DIS1 0x132E0000
148#define EXYNOS5_PA_SYSMMU_3DNR 0x132F0000
149#define EXYNOS5_PA_SYSMMU_LITE0 0x13C40000
150#define EXYNOS5_PA_SYSMMU_LITE1 0x13C50000
151#define EXYNOS5_PA_SYSMMU_GSC0 0x13E80000
152#define EXYNOS5_PA_SYSMMU_GSC1 0x13E90000
153#define EXYNOS5_PA_SYSMMU_GSC2 0x13EA0000
154#define EXYNOS5_PA_SYSMMU_GSC3 0x13EB0000
155#define EXYNOS5_PA_SYSMMU_FIMD1 0x14640000
156#define EXYNOS5_PA_SYSMMU_TV 0x14650000
157
Padmavathi Venna74ac23a2011-12-26 16:42:15 +0900158#define EXYNOS4_PA_SPI0 0x13920000
159#define EXYNOS4_PA_SPI1 0x13930000
160#define EXYNOS4_PA_SPI2 0x13940000
Thomas Abrahamb0b27812012-07-14 10:54:31 +0900161#define EXYNOS5_PA_SPI0 0x12D20000
162#define EXYNOS5_PA_SPI1 0x12D30000
163#define EXYNOS5_PA_SPI2 0x12D40000
Padmavathi Venna74ac23a2011-12-26 16:42:15 +0900164
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900165#define EXYNOS4_PA_GPIO1 0x11400000
166#define EXYNOS4_PA_GPIO2 0x11000000
167#define EXYNOS4_PA_GPIO3 0x03860000
Sangsu Parkbcdc87b2012-03-12 16:23:33 -0700168#define EXYNOS5_PA_GPIO1 0x11400000
169#define EXYNOS5_PA_GPIO2 0x13400000
170#define EXYNOS5_PA_GPIO3 0x10D10000
171#define EXYNOS5_PA_GPIO4 0x03860000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900172
173#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
174#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
175
Jonghun Han1aee2ad2011-07-21 15:46:19 +0900176#define EXYNOS4_PA_FIMD0 0x11C00000
177
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900178#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
Seungwon Jeond7919582011-07-21 00:34:58 +0900179#define EXYNOS4_PA_DWMCI 0x12550000
Thomas Abrahama5c17772012-09-26 08:54:42 +0900180#define EXYNOS5_PA_DWMCI0 0x12200000
181#define EXYNOS5_PA_DWMCI1 0x12210000
182#define EXYNOS5_PA_DWMCI2 0x12220000
183#define EXYNOS5_PA_DWMCI3 0x12230000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900184
Lukasz Majewski8ea2d9e2012-05-13 08:28:28 +0900185#define EXYNOS4_PA_HSOTG 0x12480000
186#define EXYNOS4_PA_USB_HSPHY 0x125B0000
187
Abhilash Kesavan40360212011-03-15 18:35:24 +0900188#define EXYNOS4_PA_SATA 0x12560000
189#define EXYNOS4_PA_SATAPHY 0x125D0000
190#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
191
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900192#define EXYNOS4_PA_SROMC 0x12570000
Kukjin Kim94c7ca72012-02-11 22:15:45 +0900193#define EXYNOS5_PA_SROMC 0x12250000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900194
Joonyoung Shim3e112662011-04-08 13:22:09 +0900195#define EXYNOS4_PA_EHCI 0x12580000
Jingoo Han6e7eb1702011-12-23 11:19:36 +0900196#define EXYNOS4_PA_OHCI 0x12590000
Joonyoung Shim8f1d1692011-04-08 13:22:10 +0900197#define EXYNOS4_PA_HSPHY 0x125B0000
Kamil Debski0f75a962011-07-21 16:42:30 +0900198#define EXYNOS4_PA_MFC 0x13400000
Joonyoung Shim3e112662011-04-08 13:22:09 +0900199
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900200#define EXYNOS4_PA_UART 0x13800000
Kukjin Kim94c7ca72012-02-11 22:15:45 +0900201#define EXYNOS5_PA_UART 0x12C00000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900202
Tomasz Stanislawskifbf05562011-09-19 16:44:42 +0900203#define EXYNOS4_PA_VP 0x12C00000
204#define EXYNOS4_PA_MIXER 0x12C10000
205#define EXYNOS4_PA_SDO 0x12C20000
206#define EXYNOS4_PA_HDMI 0x12D00000
Tomasz Stanislawskic40e7e02011-09-16 18:44:36 +0900207#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
208
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900209#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
Kukjin Kim94c7ca72012-02-11 22:15:45 +0900210#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000))
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900211
MyungJoo Ham0e9e5262011-07-20 21:08:18 +0900212#define EXYNOS4_PA_ADC 0x13910000
213#define EXYNOS4_PA_ADC1 0x13911000
214
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900215#define EXYNOS4_PA_AC97 0x139A0000
216
Seungwhan Youn4dd508b2011-03-08 10:56:55 +0900217#define EXYNOS4_PA_SPDIF 0x139B0000
218
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900219#define EXYNOS4_PA_TIMER 0x139D0000
Kukjin Kim94c7ca72012-02-11 22:15:45 +0900220#define EXYNOS5_PA_TIMER 0x12DD0000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900221
222#define EXYNOS4_PA_SDRAM 0x40000000
Kukjin Kim94c7ca72012-02-11 22:15:45 +0900223#define EXYNOS5_PA_SDRAM 0x40000000
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900224
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900225/* Compatibiltiy Defines */
226
227#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
228#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
229#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
230#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
231#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
232#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
233#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
234#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
235#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
236#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
237#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
238#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
239#define S3C_PA_RTC EXYNOS4_PA_RTC
240#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
Padmavathi Venna74ac23a2011-12-26 16:42:15 +0900241#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
242#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
243#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
Lukasz Majewski8ea2d9e2012-05-13 08:28:28 +0900244#define S3C_PA_USB_HSOTG EXYNOS4_PA_HSOTG
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900245
Kukjin Kim83014572011-11-06 13:54:56 +0900246#define S5P_PA_EHCI EXYNOS4_PA_EHCI
Sylwester Nawrocki604eefe2011-03-12 08:58:01 +0900247#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
248#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
249#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
250#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
Andrzej Pietrasiewicz3dbe6d42012-03-10 02:45:42 -0800251#define S5P_PA_JPEG EXYNOS4_PA_JPEG
Kamil Debski561ab532011-12-27 17:16:44 +0900252#define S5P_PA_G2D EXYNOS4_PA_G2D
Jonghun Han1aee2ad2011-07-21 15:46:19 +0900253#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
Tomasz Stanislawskifbf05562011-09-19 16:44:42 +0900254#define S5P_PA_HDMI EXYNOS4_PA_HDMI
Tomasz Stanislawskic40e7e02011-09-16 18:44:36 +0900255#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
Kukjin Kim83014572011-11-06 13:54:56 +0900256#define S5P_PA_MFC EXYNOS4_PA_MFC
257#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
258#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
259#define S5P_PA_MIXER EXYNOS4_PA_MIXER
260#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
261#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
262#define S5P_PA_SDO EXYNOS4_PA_SDO
263#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
Kukjin Kim83014572011-11-06 13:54:56 +0900264#define S5P_PA_VP EXYNOS4_PA_VP
Tomasz Stanislawskic40e7e02011-09-16 18:44:36 +0900265
Kukjin Kim83014572011-11-06 13:54:56 +0900266#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
267#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
Naveen Krishna Ch344021c2011-03-05 09:48:31 +0900268#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
269
Kukjin Kim83014572011-11-06 13:54:56 +0900270/* Compatibility UART */
271
Kukjin Kim171c0672012-02-10 11:57:53 +0900272#define EXYNOS4_PA_UART0 0x13800000
273#define EXYNOS4_PA_UART1 0x13810000
274#define EXYNOS4_PA_UART2 0x13820000
275#define EXYNOS4_PA_UART3 0x13830000
276#define EXYNOS4_SZ_UART SZ_256
277
278#define EXYNOS5_PA_UART0 0x12C00000
279#define EXYNOS5_PA_UART1 0x12C10000
280#define EXYNOS5_PA_UART2 0x12C20000
281#define EXYNOS5_PA_UART3 0x12C30000
282#define EXYNOS5_SZ_UART SZ_256
283
Kukjin Kim83014572011-11-06 13:54:56 +0900284#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900285
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900286#endif /* __ASM_ARCH_MAP_H */