Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 1 | /* |
Grant Likely | c103de2 | 2011-06-04 18:38:28 -0600 | [diff] [blame] | 2 | * U300 GPIO module. |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 3 | * |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 4 | * Copyright (C) 2007-2012 ST-Ericsson AB |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 5 | * License terms: GNU General Public License (GPL) version 2 |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 6 | * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0) |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 7 | * Author: Linus Walleij <linus.walleij@linaro.org> |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 8 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 9 | */ |
| 10 | #include <linux/module.h> |
| 11 | #include <linux/interrupt.h> |
| 12 | #include <linux/delay.h> |
| 13 | #include <linux/errno.h> |
| 14 | #include <linux/io.h> |
| 15 | #include <linux/clk.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/gpio.h> |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 19 | #include <linux/slab.h> |
Linus Walleij | 28a8d14 | 2012-02-09 01:52:22 +0100 | [diff] [blame] | 20 | #include <linux/pinctrl/consumer.h> |
Linus Walleij | dc0b1aa | 2011-11-16 21:58:10 +0100 | [diff] [blame] | 21 | #include <linux/pinctrl/pinconf-generic.h> |
Linus Walleij | dc0b1aa | 2011-11-16 21:58:10 +0100 | [diff] [blame] | 22 | #include "pinctrl-coh901.h" |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 23 | |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 24 | #define U300_GPIO_PORT_STRIDE (0x30) |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 25 | /* |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 26 | * Control Register 32bit (R/W) |
| 27 | * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores |
| 28 | * gives the number of GPIO pins. |
| 29 | * bit 8-2 (mask 0x000001FC) contains the core version ID. |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 30 | */ |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 31 | #define U300_GPIO_CR (0x00) |
| 32 | #define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL) |
| 33 | #define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL) |
| 34 | #define U300_GPIO_PXPDIR (0x04) |
| 35 | #define U300_GPIO_PXPDOR (0x08) |
| 36 | #define U300_GPIO_PXPCR (0x0C) |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 37 | #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL) |
| 38 | #define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL) |
| 39 | #define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL) |
| 40 | #define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL) |
| 41 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL) |
| 42 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL) |
| 43 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL) |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 44 | #define U300_GPIO_PXPER (0x10) |
| 45 | #define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL) |
| 46 | #define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL) |
| 47 | #define U300_GPIO_PXIEV (0x14) |
| 48 | #define U300_GPIO_PXIEN (0x18) |
| 49 | #define U300_GPIO_PXIFR (0x1C) |
| 50 | #define U300_GPIO_PXICR (0x20) |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 51 | #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL) |
| 52 | #define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL) |
| 53 | #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL) |
| 54 | #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 55 | |
| 56 | /* 8 bits per port, no version has more than 7 ports */ |
Linus Walleij | b263e9b | 2013-05-23 20:09:43 +0200 | [diff] [blame] | 57 | #define U300_GPIO_NUM_PORTS 7 |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 58 | #define U300_GPIO_PINS_PER_PORT 8 |
Linus Walleij | b263e9b | 2013-05-23 20:09:43 +0200 | [diff] [blame] | 59 | #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS) |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 60 | |
Linus Walleij | 523dcce | 2014-03-25 13:37:17 +0100 | [diff] [blame] | 61 | struct u300_gpio_port { |
| 62 | struct u300_gpio *gpio; |
| 63 | char name[8]; |
| 64 | int irq; |
| 65 | int number; |
| 66 | u8 toggle_edge_mode; |
| 67 | }; |
| 68 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 69 | struct u300_gpio { |
| 70 | struct gpio_chip chip; |
Linus Walleij | 523dcce | 2014-03-25 13:37:17 +0100 | [diff] [blame] | 71 | struct u300_gpio_port ports[U300_GPIO_NUM_PORTS]; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 72 | struct clk *clk; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 73 | void __iomem *base; |
| 74 | struct device *dev; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 75 | u32 stride; |
| 76 | /* Register offsets */ |
| 77 | u32 pcr; |
| 78 | u32 dor; |
| 79 | u32 dir; |
| 80 | u32 per; |
| 81 | u32 icr; |
| 82 | u32 ien; |
| 83 | u32 iev; |
| 84 | }; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 85 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 86 | /* |
| 87 | * Macro to expand to read a specific register found in the "gpio" |
| 88 | * struct. It requires the struct u300_gpio *gpio variable to exist in |
| 89 | * its context. It calculates the port offset from the given pin |
| 90 | * offset, muliplies by the port stride and adds the register offset |
| 91 | * so it provides a pointer to the desired register. |
| 92 | */ |
| 93 | #define U300_PIN_REG(pin, reg) \ |
| 94 | (gpio->base + (pin >> 3) * gpio->stride + gpio->reg) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 95 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 96 | /* |
| 97 | * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO |
| 98 | * register. |
| 99 | */ |
| 100 | #define U300_PIN_BIT(pin) \ |
| 101 | (1 << (pin & 0x07)) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 102 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 103 | struct u300_gpio_confdata { |
| 104 | u16 bias_mode; |
| 105 | bool output; |
| 106 | int outval; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 107 | }; |
| 108 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 109 | #define U300_FLOATING_INPUT { \ |
Linus Walleij | a050b3e | 2011-11-16 20:10:09 +0100 | [diff] [blame] | 110 | .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \ |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 111 | .output = false, \ |
| 112 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 113 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 114 | #define U300_PULL_UP_INPUT { \ |
Linus Walleij | a050b3e | 2011-11-16 20:10:09 +0100 | [diff] [blame] | 115 | .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \ |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 116 | .output = false, \ |
| 117 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 118 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 119 | #define U300_OUTPUT_LOW { \ |
| 120 | .output = true, \ |
| 121 | .outval = 0, \ |
| 122 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 123 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 124 | #define U300_OUTPUT_HIGH { \ |
| 125 | .output = true, \ |
| 126 | .outval = 1, \ |
| 127 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 128 | |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 129 | /* Initial configuration */ |
Uwe Kleine-König | 122dbe7 | 2012-03-30 22:04:51 +0200 | [diff] [blame] | 130 | static const struct __initconst u300_gpio_confdata |
Linus Walleij | b263e9b | 2013-05-23 20:09:43 +0200 | [diff] [blame] | 131 | bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 132 | /* Port 0, pins 0-7 */ |
| 133 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 134 | U300_FLOATING_INPUT, |
| 135 | U300_OUTPUT_HIGH, |
| 136 | U300_FLOATING_INPUT, |
| 137 | U300_OUTPUT_LOW, |
| 138 | U300_OUTPUT_LOW, |
| 139 | U300_OUTPUT_LOW, |
| 140 | U300_OUTPUT_LOW, |
| 141 | U300_OUTPUT_LOW, |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 142 | }, |
| 143 | /* Port 1, pins 0-7 */ |
| 144 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 145 | U300_OUTPUT_LOW, |
| 146 | U300_OUTPUT_LOW, |
| 147 | U300_OUTPUT_LOW, |
| 148 | U300_PULL_UP_INPUT, |
| 149 | U300_FLOATING_INPUT, |
| 150 | U300_OUTPUT_HIGH, |
| 151 | U300_OUTPUT_LOW, |
| 152 | U300_OUTPUT_LOW, |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 153 | }, |
| 154 | /* Port 2, pins 0-7 */ |
| 155 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 156 | U300_FLOATING_INPUT, |
| 157 | U300_FLOATING_INPUT, |
| 158 | U300_FLOATING_INPUT, |
| 159 | U300_FLOATING_INPUT, |
| 160 | U300_OUTPUT_LOW, |
| 161 | U300_PULL_UP_INPUT, |
| 162 | U300_OUTPUT_LOW, |
| 163 | U300_PULL_UP_INPUT, |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 164 | }, |
| 165 | /* Port 3, pins 0-7 */ |
| 166 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 167 | U300_PULL_UP_INPUT, |
| 168 | U300_OUTPUT_LOW, |
| 169 | U300_FLOATING_INPUT, |
| 170 | U300_FLOATING_INPUT, |
| 171 | U300_FLOATING_INPUT, |
| 172 | U300_FLOATING_INPUT, |
| 173 | U300_FLOATING_INPUT, |
| 174 | U300_FLOATING_INPUT, |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 175 | }, |
| 176 | /* Port 4, pins 0-7 */ |
| 177 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 178 | U300_FLOATING_INPUT, |
| 179 | U300_FLOATING_INPUT, |
| 180 | U300_FLOATING_INPUT, |
| 181 | U300_FLOATING_INPUT, |
| 182 | U300_FLOATING_INPUT, |
| 183 | U300_FLOATING_INPUT, |
| 184 | U300_FLOATING_INPUT, |
| 185 | U300_FLOATING_INPUT, |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 186 | }, |
| 187 | /* Port 5, pins 0-7 */ |
| 188 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 189 | U300_FLOATING_INPUT, |
| 190 | U300_FLOATING_INPUT, |
| 191 | U300_FLOATING_INPUT, |
| 192 | U300_FLOATING_INPUT, |
| 193 | U300_FLOATING_INPUT, |
| 194 | U300_FLOATING_INPUT, |
| 195 | U300_FLOATING_INPUT, |
| 196 | U300_FLOATING_INPUT, |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 197 | }, |
| 198 | /* Port 6, pind 0-7 */ |
| 199 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 200 | U300_FLOATING_INPUT, |
| 201 | U300_FLOATING_INPUT, |
| 202 | U300_FLOATING_INPUT, |
| 203 | U300_FLOATING_INPUT, |
| 204 | U300_FLOATING_INPUT, |
| 205 | U300_FLOATING_INPUT, |
| 206 | U300_FLOATING_INPUT, |
| 207 | U300_FLOATING_INPUT, |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 208 | } |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 209 | }; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 210 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 211 | static int u300_gpio_get(struct gpio_chip *chip, unsigned offset) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 212 | { |
Linus Walleij | 014c1b3 | 2015-12-08 09:33:30 +0100 | [diff] [blame] | 213 | struct u300_gpio *gpio = gpiochip_get_data(chip); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 214 | |
Linus Walleij | 01a6283 | 2015-12-21 16:25:11 +0100 | [diff] [blame] | 215 | return !!(readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset)); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 216 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 217 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 218 | static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
Linus Walleij | ee17962 | 2009-09-28 12:36:18 +0100 | [diff] [blame] | 219 | { |
Linus Walleij | 014c1b3 | 2015-12-08 09:33:30 +0100 | [diff] [blame] | 220 | struct u300_gpio *gpio = gpiochip_get_data(chip); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 221 | unsigned long flags; |
| 222 | u32 val; |
Linus Walleij | ee17962 | 2009-09-28 12:36:18 +0100 | [diff] [blame] | 223 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 224 | local_irq_save(flags); |
| 225 | |
| 226 | val = readl(U300_PIN_REG(offset, dor)); |
| 227 | if (value) |
| 228 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 229 | else |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 230 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 231 | |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 232 | local_irq_restore(flags); |
| 233 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 234 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 235 | static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 236 | { |
Linus Walleij | 014c1b3 | 2015-12-08 09:33:30 +0100 | [diff] [blame] | 237 | struct u300_gpio *gpio = gpiochip_get_data(chip); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 238 | unsigned long flags; |
| 239 | u32 val; |
| 240 | |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 241 | local_irq_save(flags); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 242 | val = readl(U300_PIN_REG(offset, pcr)); |
| 243 | /* Mask out this pin, note 2 bits per setting */ |
| 244 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); |
| 245 | writel(val, U300_PIN_REG(offset, pcr)); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 246 | local_irq_restore(flags); |
| 247 | return 0; |
| 248 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 249 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 250 | static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
| 251 | int value) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 252 | { |
Linus Walleij | 014c1b3 | 2015-12-08 09:33:30 +0100 | [diff] [blame] | 253 | struct u300_gpio *gpio = gpiochip_get_data(chip); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 254 | unsigned long flags; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 255 | u32 oldmode; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 256 | u32 val; |
| 257 | |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 258 | local_irq_save(flags); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 259 | val = readl(U300_PIN_REG(offset, pcr)); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 260 | /* |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 261 | * Drive mode must be set by the special mode set function, set |
| 262 | * push/pull mode by default if no mode has been selected. |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 263 | */ |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 264 | oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK << |
| 265 | ((offset & 0x07) << 1)); |
| 266 | /* mode = 0 means input, else some mode is already set */ |
| 267 | if (oldmode == 0) { |
| 268 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << |
| 269 | ((offset & 0x07) << 1)); |
| 270 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL |
| 271 | << ((offset & 0x07) << 1)); |
| 272 | writel(val, U300_PIN_REG(offset, pcr)); |
| 273 | } |
| 274 | u300_gpio_set(chip, offset, value); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 275 | local_irq_restore(flags); |
| 276 | return 0; |
| 277 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 278 | |
Linus Walleij | dc0b1aa | 2011-11-16 21:58:10 +0100 | [diff] [blame] | 279 | /* Returning -EINVAL means "supported but not available" */ |
| 280 | int u300_gpio_config_get(struct gpio_chip *chip, |
| 281 | unsigned offset, |
| 282 | unsigned long *config) |
| 283 | { |
Linus Walleij | 014c1b3 | 2015-12-08 09:33:30 +0100 | [diff] [blame] | 284 | struct u300_gpio *gpio = gpiochip_get_data(chip); |
Linus Walleij | dc0b1aa | 2011-11-16 21:58:10 +0100 | [diff] [blame] | 285 | enum pin_config_param param = (enum pin_config_param) *config; |
| 286 | bool biasmode; |
| 287 | u32 drmode; |
| 288 | |
| 289 | /* One bit per pin, clamp to bool range */ |
| 290 | biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset)); |
| 291 | |
| 292 | /* Mask out the two bits for this pin and shift to bits 0,1 */ |
| 293 | drmode = readl(U300_PIN_REG(offset, pcr)); |
| 294 | drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); |
| 295 | drmode >>= ((offset & 0x07) << 1); |
| 296 | |
Sachin Kamat | 8b0ef25 | 2013-03-15 10:39:52 +0530 | [diff] [blame] | 297 | switch (param) { |
Linus Walleij | dc0b1aa | 2011-11-16 21:58:10 +0100 | [diff] [blame] | 298 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: |
| 299 | *config = 0; |
| 300 | if (biasmode) |
| 301 | return 0; |
| 302 | else |
| 303 | return -EINVAL; |
| 304 | break; |
| 305 | case PIN_CONFIG_BIAS_PULL_UP: |
| 306 | *config = 0; |
| 307 | if (!biasmode) |
| 308 | return 0; |
| 309 | else |
| 310 | return -EINVAL; |
| 311 | break; |
| 312 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
| 313 | *config = 0; |
| 314 | if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL) |
| 315 | return 0; |
| 316 | else |
| 317 | return -EINVAL; |
| 318 | break; |
| 319 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
| 320 | *config = 0; |
| 321 | if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN) |
| 322 | return 0; |
| 323 | else |
| 324 | return -EINVAL; |
| 325 | break; |
| 326 | case PIN_CONFIG_DRIVE_OPEN_SOURCE: |
| 327 | *config = 0; |
| 328 | if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE) |
| 329 | return 0; |
| 330 | else |
| 331 | return -EINVAL; |
| 332 | break; |
| 333 | default: |
| 334 | break; |
| 335 | } |
| 336 | return -ENOTSUPP; |
| 337 | } |
| 338 | |
| 339 | int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset, |
| 340 | enum pin_config_param param) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 341 | { |
Linus Walleij | 014c1b3 | 2015-12-08 09:33:30 +0100 | [diff] [blame] | 342 | struct u300_gpio *gpio = gpiochip_get_data(chip); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 343 | unsigned long flags; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 344 | u32 val; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 345 | |
| 346 | local_irq_save(flags); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 347 | switch (param) { |
Linus Walleij | a050b3e | 2011-11-16 20:10:09 +0100 | [diff] [blame] | 348 | case PIN_CONFIG_BIAS_DISABLE: |
| 349 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 350 | val = readl(U300_PIN_REG(offset, per)); |
| 351 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); |
| 352 | break; |
Linus Walleij | a050b3e | 2011-11-16 20:10:09 +0100 | [diff] [blame] | 353 | case PIN_CONFIG_BIAS_PULL_UP: |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 354 | val = readl(U300_PIN_REG(offset, per)); |
| 355 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); |
| 356 | break; |
Linus Walleij | a050b3e | 2011-11-16 20:10:09 +0100 | [diff] [blame] | 357 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 358 | val = readl(U300_PIN_REG(offset, pcr)); |
| 359 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK |
| 360 | << ((offset & 0x07) << 1)); |
| 361 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL |
| 362 | << ((offset & 0x07) << 1)); |
| 363 | writel(val, U300_PIN_REG(offset, pcr)); |
| 364 | break; |
Linus Walleij | a050b3e | 2011-11-16 20:10:09 +0100 | [diff] [blame] | 365 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 366 | val = readl(U300_PIN_REG(offset, pcr)); |
| 367 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK |
| 368 | << ((offset & 0x07) << 1)); |
| 369 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN |
| 370 | << ((offset & 0x07) << 1)); |
| 371 | writel(val, U300_PIN_REG(offset, pcr)); |
| 372 | break; |
Linus Walleij | a050b3e | 2011-11-16 20:10:09 +0100 | [diff] [blame] | 373 | case PIN_CONFIG_DRIVE_OPEN_SOURCE: |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 374 | val = readl(U300_PIN_REG(offset, pcr)); |
| 375 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK |
| 376 | << ((offset & 0x07) << 1)); |
| 377 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE |
| 378 | << ((offset & 0x07) << 1)); |
| 379 | writel(val, U300_PIN_REG(offset, pcr)); |
| 380 | break; |
| 381 | default: |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 382 | local_irq_restore(flags); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 383 | dev_err(gpio->dev, "illegal configuration requested\n"); |
| 384 | return -EINVAL; |
| 385 | } |
| 386 | local_irq_restore(flags); |
| 387 | return 0; |
| 388 | } |
| 389 | |
| 390 | static struct gpio_chip u300_gpio_chip = { |
| 391 | .label = "u300-gpio-chip", |
| 392 | .owner = THIS_MODULE, |
Jonas Gorski | 98c85d5 | 2015-10-11 17:34:19 +0200 | [diff] [blame] | 393 | .request = gpiochip_generic_request, |
| 394 | .free = gpiochip_generic_free, |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 395 | .get = u300_gpio_get, |
| 396 | .set = u300_gpio_set, |
| 397 | .direction_input = u300_gpio_direction_input, |
| 398 | .direction_output = u300_gpio_direction_output, |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 399 | }; |
| 400 | |
| 401 | static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset) |
| 402 | { |
| 403 | u32 val; |
| 404 | |
| 405 | val = readl(U300_PIN_REG(offset, icr)); |
| 406 | /* Set mode depending on state */ |
| 407 | if (u300_gpio_get(&gpio->chip, offset)) { |
| 408 | /* High now, let's trigger on falling edge next then */ |
| 409 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); |
| 410 | dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n", |
| 411 | offset); |
| 412 | } else { |
| 413 | /* Low now, let's trigger on rising edge next then */ |
| 414 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); |
| 415 | dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n", |
| 416 | offset); |
| 417 | } |
| 418 | } |
| 419 | |
| 420 | static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger) |
| 421 | { |
Linus Walleij | 523dcce | 2014-03-25 13:37:17 +0100 | [diff] [blame] | 422 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
Linus Walleij | 014c1b3 | 2015-12-08 09:33:30 +0100 | [diff] [blame] | 423 | struct u300_gpio *gpio = gpiochip_get_data(chip); |
Linus Walleij | 523dcce | 2014-03-25 13:37:17 +0100 | [diff] [blame] | 424 | struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3]; |
| 425 | int offset = d->hwirq; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 426 | u32 val; |
| 427 | |
| 428 | if ((trigger & IRQF_TRIGGER_RISING) && |
| 429 | (trigger & IRQF_TRIGGER_FALLING)) { |
| 430 | /* |
| 431 | * The GPIO block can only trigger on falling OR rising edges, |
| 432 | * not both. So we need to toggle the mode whenever the pin |
| 433 | * goes from one state to the other with a special state flag |
| 434 | */ |
| 435 | dev_dbg(gpio->dev, |
| 436 | "trigger on both rising and falling edge on pin %d\n", |
| 437 | offset); |
| 438 | port->toggle_edge_mode |= U300_PIN_BIT(offset); |
| 439 | u300_toggle_trigger(gpio, offset); |
| 440 | } else if (trigger & IRQF_TRIGGER_RISING) { |
| 441 | dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n", |
| 442 | offset); |
| 443 | val = readl(U300_PIN_REG(offset, icr)); |
| 444 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); |
| 445 | port->toggle_edge_mode &= ~U300_PIN_BIT(offset); |
| 446 | } else if (trigger & IRQF_TRIGGER_FALLING) { |
| 447 | dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n", |
| 448 | offset); |
| 449 | val = readl(U300_PIN_REG(offset, icr)); |
| 450 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); |
| 451 | port->toggle_edge_mode &= ~U300_PIN_BIT(offset); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 452 | } |
| 453 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 454 | return 0; |
| 455 | } |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 456 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 457 | static void u300_gpio_irq_enable(struct irq_data *d) |
| 458 | { |
Linus Walleij | 523dcce | 2014-03-25 13:37:17 +0100 | [diff] [blame] | 459 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
Linus Walleij | 014c1b3 | 2015-12-08 09:33:30 +0100 | [diff] [blame] | 460 | struct u300_gpio *gpio = gpiochip_get_data(chip); |
Linus Walleij | 523dcce | 2014-03-25 13:37:17 +0100 | [diff] [blame] | 461 | struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3]; |
| 462 | int offset = d->hwirq; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 463 | u32 val; |
| 464 | unsigned long flags; |
| 465 | |
Linus Walleij | a6c45b9 | 2012-10-17 18:31:20 +0200 | [diff] [blame] | 466 | dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n", |
| 467 | d->hwirq, port->name, offset); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 468 | local_irq_save(flags); |
| 469 | val = readl(U300_PIN_REG(offset, ien)); |
| 470 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); |
| 471 | local_irq_restore(flags); |
| 472 | } |
| 473 | |
| 474 | static void u300_gpio_irq_disable(struct irq_data *d) |
| 475 | { |
Linus Walleij | 523dcce | 2014-03-25 13:37:17 +0100 | [diff] [blame] | 476 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
Linus Walleij | 014c1b3 | 2015-12-08 09:33:30 +0100 | [diff] [blame] | 477 | struct u300_gpio *gpio = gpiochip_get_data(chip); |
Linus Walleij | 523dcce | 2014-03-25 13:37:17 +0100 | [diff] [blame] | 478 | int offset = d->hwirq; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 479 | u32 val; |
| 480 | unsigned long flags; |
| 481 | |
| 482 | local_irq_save(flags); |
| 483 | val = readl(U300_PIN_REG(offset, ien)); |
| 484 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); |
| 485 | local_irq_restore(flags); |
Linus Walleij | 8c1d50a | 2014-03-14 18:24:30 +0100 | [diff] [blame] | 486 | } |
| 487 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 488 | static struct irq_chip u300_gpio_irqchip = { |
| 489 | .name = "u300-gpio-irqchip", |
| 490 | .irq_enable = u300_gpio_irq_enable, |
| 491 | .irq_disable = u300_gpio_irq_disable, |
| 492 | .irq_set_type = u300_gpio_irq_type, |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 493 | }; |
| 494 | |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 495 | static void u300_gpio_irq_handler(struct irq_desc *desc) |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 496 | { |
Thomas Gleixner | fc02a46 | 2015-07-13 01:50:02 +0200 | [diff] [blame] | 497 | unsigned int irq = irq_desc_get_irq(desc); |
Jiang Liu | 5663bb2 | 2015-06-04 12:13:16 +0800 | [diff] [blame] | 498 | struct irq_chip *parent_chip = irq_desc_get_chip(desc); |
| 499 | struct gpio_chip *chip = irq_desc_get_handler_data(desc); |
Linus Walleij | 014c1b3 | 2015-12-08 09:33:30 +0100 | [diff] [blame] | 500 | struct u300_gpio *gpio = gpiochip_get_data(chip); |
Linus Walleij | 523dcce | 2014-03-25 13:37:17 +0100 | [diff] [blame] | 501 | struct u300_gpio_port *port = &gpio->ports[irq - chip->base]; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 502 | int pinoffset = port->number << 3; /* get the right stride */ |
| 503 | unsigned long val; |
| 504 | |
Linus Walleij | 523dcce | 2014-03-25 13:37:17 +0100 | [diff] [blame] | 505 | chained_irq_enter(parent_chip, desc); |
| 506 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 507 | /* Read event register */ |
| 508 | val = readl(U300_PIN_REG(pinoffset, iev)); |
| 509 | /* Mask relevant bits */ |
| 510 | val &= 0xFFU; /* 8 bits per port */ |
| 511 | /* ACK IRQ (clear event) */ |
| 512 | writel(val, U300_PIN_REG(pinoffset, iev)); |
| 513 | |
| 514 | /* Call IRQ handler */ |
| 515 | if (val != 0) { |
| 516 | int irqoffset; |
| 517 | |
| 518 | for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 519 | int offset = pinoffset + irqoffset; |
Linus Walleij | 523dcce | 2014-03-25 13:37:17 +0100 | [diff] [blame] | 520 | int pin_irq = irq_find_mapping(chip->irqdomain, offset); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 521 | |
| 522 | dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n", |
| 523 | pin_irq, offset); |
| 524 | generic_handle_irq(pin_irq); |
| 525 | /* |
| 526 | * Triggering IRQ on both rising and falling edge |
| 527 | * needs mockery |
| 528 | */ |
| 529 | if (port->toggle_edge_mode & U300_PIN_BIT(offset)) |
| 530 | u300_toggle_trigger(gpio, offset); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 531 | } |
| 532 | } |
| 533 | |
Linus Walleij | 523dcce | 2014-03-25 13:37:17 +0100 | [diff] [blame] | 534 | chained_irq_exit(parent_chip, desc); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 535 | } |
| 536 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 537 | static void __init u300_gpio_init_pin(struct u300_gpio *gpio, |
| 538 | int offset, |
| 539 | const struct u300_gpio_confdata *conf) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 540 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 541 | /* Set mode: input or output */ |
| 542 | if (conf->output) { |
| 543 | u300_gpio_direction_output(&gpio->chip, offset, conf->outval); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 544 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 545 | /* Deactivate bias mode for output */ |
Linus Walleij | dc0b1aa | 2011-11-16 21:58:10 +0100 | [diff] [blame] | 546 | u300_gpio_config_set(&gpio->chip, offset, |
| 547 | PIN_CONFIG_BIAS_HIGH_IMPEDANCE); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 548 | |
| 549 | /* Set drive mode for output */ |
Linus Walleij | dc0b1aa | 2011-11-16 21:58:10 +0100 | [diff] [blame] | 550 | u300_gpio_config_set(&gpio->chip, offset, |
| 551 | PIN_CONFIG_DRIVE_PUSH_PULL); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 552 | |
| 553 | dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n", |
| 554 | offset, conf->outval); |
| 555 | } else { |
| 556 | u300_gpio_direction_input(&gpio->chip, offset); |
| 557 | |
| 558 | /* Always set output low on input pins */ |
| 559 | u300_gpio_set(&gpio->chip, offset, 0); |
| 560 | |
| 561 | /* Set bias mode for input */ |
Linus Walleij | dc0b1aa | 2011-11-16 21:58:10 +0100 | [diff] [blame] | 562 | u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 563 | |
| 564 | dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n", |
| 565 | offset, conf->bias_mode); |
| 566 | } |
| 567 | } |
| 568 | |
Linus Walleij | b263e9b | 2013-05-23 20:09:43 +0200 | [diff] [blame] | 569 | static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio) |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 570 | { |
| 571 | int i, j; |
| 572 | |
| 573 | /* Write default config and values to all pins */ |
Linus Walleij | b263e9b | 2013-05-23 20:09:43 +0200 | [diff] [blame] | 574 | for (i = 0; i < U300_GPIO_NUM_PORTS; i++) { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 575 | for (j = 0; j < 8; j++) { |
| 576 | const struct u300_gpio_confdata *conf; |
| 577 | int offset = (i*8) + j; |
| 578 | |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 579 | conf = &bs335_gpio_config[i][j]; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 580 | u300_gpio_init_pin(gpio, offset, conf); |
| 581 | } |
| 582 | } |
| 583 | } |
| 584 | |
Linus Walleij | 387923c | 2012-11-20 14:28:07 +0100 | [diff] [blame] | 585 | /* |
| 586 | * Here we map a GPIO in the local gpio_chip pin space to a pin in |
| 587 | * the local pinctrl pin space. The pin controller used is |
| 588 | * pinctrl-u300. |
| 589 | */ |
| 590 | struct coh901_pinpair { |
| 591 | unsigned int offset; |
| 592 | unsigned int pin_base; |
| 593 | }; |
| 594 | |
| 595 | #define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b } |
| 596 | |
| 597 | static struct coh901_pinpair coh901_pintable[] = { |
| 598 | COH901_PINRANGE(10, 426), |
| 599 | COH901_PINRANGE(11, 180), |
| 600 | COH901_PINRANGE(12, 165), /* MS/MMC card insertion */ |
| 601 | COH901_PINRANGE(13, 179), |
| 602 | COH901_PINRANGE(14, 178), |
| 603 | COH901_PINRANGE(16, 194), |
| 604 | COH901_PINRANGE(17, 193), |
| 605 | COH901_PINRANGE(18, 192), |
| 606 | COH901_PINRANGE(19, 191), |
| 607 | COH901_PINRANGE(20, 186), |
| 608 | COH901_PINRANGE(21, 185), |
| 609 | COH901_PINRANGE(22, 184), |
| 610 | COH901_PINRANGE(23, 183), |
| 611 | COH901_PINRANGE(24, 182), |
| 612 | COH901_PINRANGE(25, 181), |
| 613 | }; |
| 614 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 615 | static int __init u300_gpio_probe(struct platform_device *pdev) |
| 616 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 617 | struct u300_gpio *gpio; |
Linus Walleij | 585583f | 2012-10-17 18:49:05 +0200 | [diff] [blame] | 618 | struct resource *memres; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 619 | int err = 0; |
| 620 | int portno; |
| 621 | u32 val; |
| 622 | u32 ifr; |
| 623 | int i; |
| 624 | |
Linus Walleij | 585583f | 2012-10-17 18:49:05 +0200 | [diff] [blame] | 625 | gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL); |
| 626 | if (gpio == NULL) |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 627 | return -ENOMEM; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 628 | |
| 629 | gpio->chip = u300_gpio_chip; |
Linus Walleij | b263e9b | 2013-05-23 20:09:43 +0200 | [diff] [blame] | 630 | gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT; |
Linus Walleij | 58383c7 | 2015-11-04 09:56:26 +0100 | [diff] [blame] | 631 | gpio->chip.parent = &pdev->dev; |
Linus Walleij | b263e9b | 2013-05-23 20:09:43 +0200 | [diff] [blame] | 632 | gpio->chip.base = 0; |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 633 | gpio->dev = &pdev->dev; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 634 | |
Linus Walleij | 585583f | 2012-10-17 18:49:05 +0200 | [diff] [blame] | 635 | memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Thierry Reding | 9e0c1fb | 2013-01-21 11:09:14 +0100 | [diff] [blame] | 636 | gpio->base = devm_ioremap_resource(&pdev->dev, memres); |
| 637 | if (IS_ERR(gpio->base)) |
| 638 | return PTR_ERR(gpio->base); |
Linus Walleij | 585583f | 2012-10-17 18:49:05 +0200 | [diff] [blame] | 639 | |
| 640 | gpio->clk = devm_clk_get(gpio->dev, NULL); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 641 | if (IS_ERR(gpio->clk)) { |
| 642 | err = PTR_ERR(gpio->clk); |
| 643 | dev_err(gpio->dev, "could not get GPIO clock\n"); |
Linus Walleij | 585583f | 2012-10-17 18:49:05 +0200 | [diff] [blame] | 644 | return err; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 645 | } |
Linus Walleij | 585583f | 2012-10-17 18:49:05 +0200 | [diff] [blame] | 646 | |
Linus Walleij | 27e8461 | 2012-06-19 23:36:15 +0200 | [diff] [blame] | 647 | err = clk_prepare_enable(gpio->clk); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 648 | if (err) { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 649 | dev_err(gpio->dev, "could not enable GPIO clock\n"); |
Linus Walleij | 585583f | 2012-10-17 18:49:05 +0200 | [diff] [blame] | 650 | return err; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 651 | } |
| 652 | |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 653 | dev_info(gpio->dev, |
| 654 | "initializing GPIO Controller COH 901 571/3\n"); |
| 655 | gpio->stride = U300_GPIO_PORT_STRIDE; |
| 656 | gpio->pcr = U300_GPIO_PXPCR; |
| 657 | gpio->dor = U300_GPIO_PXPDOR; |
| 658 | gpio->dir = U300_GPIO_PXPDIR; |
| 659 | gpio->per = U300_GPIO_PXPER; |
| 660 | gpio->icr = U300_GPIO_PXICR; |
| 661 | gpio->ien = U300_GPIO_PXIEN; |
| 662 | gpio->iev = U300_GPIO_PXIEV; |
| 663 | ifr = U300_GPIO_PXIFR; |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 664 | |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 665 | val = readl(gpio->base + U300_GPIO_CR); |
| 666 | dev_info(gpio->dev, "COH901571/3 block version: %d, " \ |
| 667 | "number of cores: %d totalling %d pins\n", |
| 668 | ((val & 0x000001FC) >> 2), |
| 669 | ((val & 0x0000FE00) >> 9), |
| 670 | ((val & 0x0000FE00) >> 9) * 8); |
| 671 | writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, |
| 672 | gpio->base + U300_GPIO_CR); |
Linus Walleij | b263e9b | 2013-05-23 20:09:43 +0200 | [diff] [blame] | 673 | u300_gpio_init_coh901571(gpio); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 674 | |
Linus Walleij | 351c216 | 2013-04-10 10:49:31 +0200 | [diff] [blame] | 675 | #ifdef CONFIG_OF_GPIO |
| 676 | gpio->chip.of_node = pdev->dev.of_node; |
| 677 | #endif |
Linus Walleij | 014c1b3 | 2015-12-08 09:33:30 +0100 | [diff] [blame] | 678 | err = gpiochip_add_data(&gpio->chip, gpio); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 679 | if (err) { |
| 680 | dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); |
| 681 | goto err_no_chip; |
| 682 | } |
| 683 | |
Linus Walleij | 523dcce | 2014-03-25 13:37:17 +0100 | [diff] [blame] | 684 | err = gpiochip_irqchip_add(&gpio->chip, |
| 685 | &u300_gpio_irqchip, |
| 686 | 0, |
| 687 | handle_simple_irq, |
| 688 | IRQ_TYPE_EDGE_FALLING); |
| 689 | if (err) { |
| 690 | dev_err(gpio->dev, "no GPIO irqchip\n"); |
| 691 | goto err_no_irqchip; |
| 692 | } |
| 693 | |
| 694 | /* Add each port with its IRQ separately */ |
| 695 | for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) { |
| 696 | struct u300_gpio_port *port = &gpio->ports[portno]; |
| 697 | |
| 698 | snprintf(port->name, 8, "gpio%d", portno); |
| 699 | port->number = portno; |
| 700 | port->gpio = gpio; |
| 701 | |
| 702 | port->irq = platform_get_irq(pdev, portno); |
| 703 | |
| 704 | gpiochip_set_chained_irqchip(&gpio->chip, |
| 705 | &u300_gpio_irqchip, |
| 706 | port->irq, |
| 707 | u300_gpio_irq_handler); |
| 708 | |
| 709 | /* Turns off irq force (test register) for this port */ |
| 710 | writel(0x0, gpio->base + portno * gpio->stride + ifr); |
| 711 | } |
| 712 | dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno); |
| 713 | |
Linus Walleij | 387923c | 2012-11-20 14:28:07 +0100 | [diff] [blame] | 714 | /* |
| 715 | * Add pinctrl pin ranges, the pin controller must be registered |
| 716 | * at this point |
| 717 | */ |
| 718 | for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) { |
| 719 | struct coh901_pinpair *p = &coh901_pintable[i]; |
| 720 | |
| 721 | err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300", |
| 722 | p->offset, p->pin_base, 1); |
| 723 | if (err) |
| 724 | goto err_no_range; |
| 725 | } |
| 726 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 727 | platform_set_drvdata(pdev, gpio); |
| 728 | |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 729 | return 0; |
| 730 | |
Linus Walleij | 387923c | 2012-11-20 14:28:07 +0100 | [diff] [blame] | 731 | err_no_range: |
Linus Walleij | 523dcce | 2014-03-25 13:37:17 +0100 | [diff] [blame] | 732 | err_no_irqchip: |
abdoulaye berthe | b4e7c55 | 2014-07-12 22:30:13 +0200 | [diff] [blame] | 733 | gpiochip_remove(&gpio->chip); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 734 | err_no_chip: |
Linus Walleij | 27e8461 | 2012-06-19 23:36:15 +0200 | [diff] [blame] | 735 | clk_disable_unprepare(gpio->clk); |
Axel Lin | 8035720 | 2012-11-14 00:16:14 +0800 | [diff] [blame] | 736 | dev_err(&pdev->dev, "module ERROR:%d\n", err); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 737 | return err; |
| 738 | } |
| 739 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 740 | static int __exit u300_gpio_remove(struct platform_device *pdev) |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 741 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 742 | struct u300_gpio *gpio = platform_get_drvdata(pdev); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 743 | |
| 744 | /* Turn off the GPIO block */ |
Linus Walleij | 04b13de | 2012-08-13 10:36:55 +0200 | [diff] [blame] | 745 | writel(0x00000000U, gpio->base + U300_GPIO_CR); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 746 | |
abdoulaye berthe | b4e7c55 | 2014-07-12 22:30:13 +0200 | [diff] [blame] | 747 | gpiochip_remove(&gpio->chip); |
Linus Walleij | 27e8461 | 2012-06-19 23:36:15 +0200 | [diff] [blame] | 748 | clk_disable_unprepare(gpio->clk); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 749 | return 0; |
| 750 | } |
| 751 | |
Linus Walleij | 351c216 | 2013-04-10 10:49:31 +0200 | [diff] [blame] | 752 | static const struct of_device_id u300_gpio_match[] = { |
| 753 | { .compatible = "stericsson,gpio-coh901" }, |
| 754 | {}, |
| 755 | }; |
| 756 | |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 757 | static struct platform_driver u300_gpio_driver = { |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 758 | .driver = { |
| 759 | .name = "u300-gpio", |
Linus Walleij | 351c216 | 2013-04-10 10:49:31 +0200 | [diff] [blame] | 760 | .of_match_table = u300_gpio_match, |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 761 | }, |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 762 | .remove = __exit_p(u300_gpio_remove), |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 763 | }; |
| 764 | |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 765 | static int __init u300_gpio_init(void) |
| 766 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 767 | return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 768 | } |
| 769 | |
| 770 | static void __exit u300_gpio_exit(void) |
| 771 | { |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 772 | platform_driver_unregister(&u300_gpio_driver); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 773 | } |
| 774 | |
| 775 | arch_initcall(u300_gpio_init); |
| 776 | module_exit(u300_gpio_exit); |
| 777 | |
| 778 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); |
Linus Walleij | cc890cd | 2011-09-08 09:04:51 +0100 | [diff] [blame] | 779 | MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver"); |
Linus Walleij | bd41b99 | 2009-04-23 21:15:04 +0100 | [diff] [blame] | 780 | MODULE_LICENSE("GPL"); |