Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2012-2016 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #ifndef _INTEL_DPLL_MGR_H_ |
| 26 | #define _INTEL_DPLL_MGR_H_ |
| 27 | |
| 28 | struct drm_i915_private; |
Ander Conselvan de Oliveira | c2a9fcd | 2016-03-08 17:46:20 +0200 | [diff] [blame^] | 29 | struct intel_crtc; |
| 30 | struct intel_crtc_state; |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 31 | |
| 32 | enum intel_dpll_id { |
| 33 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ |
| 34 | /* real shared dpll ids must be >= 0 */ |
| 35 | DPLL_ID_PCH_PLL_A = 0, |
| 36 | DPLL_ID_PCH_PLL_B = 1, |
| 37 | /* hsw/bdw */ |
| 38 | DPLL_ID_WRPLL1 = 0, |
| 39 | DPLL_ID_WRPLL2 = 1, |
| 40 | DPLL_ID_SPLL = 2, |
| 41 | |
| 42 | /* skl */ |
| 43 | DPLL_ID_SKL_DPLL1 = 0, |
| 44 | DPLL_ID_SKL_DPLL2 = 1, |
| 45 | DPLL_ID_SKL_DPLL3 = 2, |
| 46 | }; |
| 47 | #define I915_NUM_PLLS 3 |
| 48 | |
| 49 | struct intel_dpll_hw_state { |
| 50 | /* i9xx, pch plls */ |
| 51 | uint32_t dpll; |
| 52 | uint32_t dpll_md; |
| 53 | uint32_t fp0; |
| 54 | uint32_t fp1; |
| 55 | |
| 56 | /* hsw, bdw */ |
| 57 | uint32_t wrpll; |
| 58 | uint32_t spll; |
| 59 | |
| 60 | /* skl */ |
| 61 | /* |
| 62 | * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in |
| 63 | * lower part of ctrl1 and they get shifted into position when writing |
| 64 | * the register. This allows us to easily compare the state to share |
| 65 | * the DPLL. |
| 66 | */ |
| 67 | uint32_t ctrl1; |
| 68 | /* HDMI only, 0 when used for DP */ |
| 69 | uint32_t cfgcr1, cfgcr2; |
| 70 | |
| 71 | /* bxt */ |
| 72 | uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, |
| 73 | pcsdw12; |
| 74 | }; |
| 75 | |
| 76 | struct intel_shared_dpll_config { |
| 77 | unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ |
| 78 | struct intel_dpll_hw_state hw_state; |
| 79 | }; |
| 80 | |
| 81 | struct intel_shared_dpll { |
| 82 | struct intel_shared_dpll_config config; |
| 83 | |
| 84 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
| 85 | bool on; /* is the PLL actually active? Disabled during modeset */ |
| 86 | const char *name; |
| 87 | /* should match the index in the dev_priv->shared_dplls array */ |
| 88 | enum intel_dpll_id id; |
| 89 | /* The mode_set hook is optional and should be used together with the |
| 90 | * intel_prepare_shared_dpll function. */ |
| 91 | void (*mode_set)(struct drm_i915_private *dev_priv, |
| 92 | struct intel_shared_dpll *pll); |
| 93 | void (*enable)(struct drm_i915_private *dev_priv, |
| 94 | struct intel_shared_dpll *pll); |
| 95 | void (*disable)(struct drm_i915_private *dev_priv, |
| 96 | struct intel_shared_dpll *pll); |
| 97 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
| 98 | struct intel_shared_dpll *pll, |
| 99 | struct intel_dpll_hw_state *hw_state); |
| 100 | }; |
| 101 | |
| 102 | #define SKL_DPLL0 0 |
| 103 | #define SKL_DPLL1 1 |
| 104 | #define SKL_DPLL2 2 |
| 105 | #define SKL_DPLL3 3 |
| 106 | |
Ander Conselvan de Oliveira | c2a9fcd | 2016-03-08 17:46:20 +0200 | [diff] [blame^] | 107 | /* shared dpll functions */ |
| 108 | struct intel_shared_dpll * |
| 109 | intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, |
| 110 | enum intel_dpll_id id); |
| 111 | enum intel_dpll_id |
| 112 | intel_get_shared_dpll_id(struct drm_i915_private *dev_priv, |
| 113 | struct intel_shared_dpll *pll); |
| 114 | void |
| 115 | intel_shared_dpll_config_get(struct intel_shared_dpll_config *config, |
| 116 | struct intel_shared_dpll *pll, |
| 117 | struct intel_crtc *crtc); |
| 118 | void |
| 119 | intel_shared_dpll_config_put(struct intel_shared_dpll_config *config, |
| 120 | struct intel_shared_dpll *pll, |
| 121 | struct intel_crtc *crtc); |
| 122 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
| 123 | struct intel_shared_dpll *pll, |
| 124 | bool state); |
| 125 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) |
| 126 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) |
| 127 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
| 128 | struct intel_crtc_state *state); |
| 129 | void intel_prepare_shared_dpll(struct intel_crtc *crtc); |
| 130 | void intel_enable_shared_dpll(struct intel_crtc *crtc); |
| 131 | void intel_disable_shared_dpll(struct intel_crtc *crtc); |
| 132 | void intel_shared_dpll_commit(struct drm_atomic_state *state); |
| 133 | void intel_shared_dpll_init(struct drm_device *dev); |
| 134 | |
Ander Conselvan de Oliveira | ac7f11c | 2016-03-08 17:46:19 +0200 | [diff] [blame] | 135 | |
| 136 | #endif /* _INTEL_DPLL_MGR_H_ */ |