Girish Mahadevan | 2ef85af | 2017-02-14 14:42:22 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | #include <linux/clk.h> |
| 15 | #include <linux/interrupt.h> |
| 16 | #include <linux/io.h> |
| 17 | #include <linux/module.h> |
| 18 | #include <linux/of.h> |
| 19 | #include <linux/qcom-geni-se.h> |
| 20 | #include <linux/spi/spi.h> |
| 21 | |
| 22 | #define SPI_NUM_CHIPSELECT (4) |
| 23 | #define SPI_XFER_TIMEOUT_MS (250) |
| 24 | #define SPI_OVERSAMPLING (2) |
| 25 | /* SPI SE specific registers */ |
| 26 | #define SE_SPI_CPHA (0x224) |
| 27 | #define SE_SPI_LOOPBACK (0x22C) |
| 28 | #define SE_SPI_CPOL (0x230) |
| 29 | #define SE_SPI_DEMUX_OUTPUT_INV (0x24C) |
| 30 | #define SE_SPI_DEMUX_SEL (0x250) |
| 31 | #define SE_SPI_TRANS_CFG (0x25C) |
| 32 | #define SE_SPI_WORD_LEN (0x268) |
| 33 | #define SE_SPI_TX_TRANS_LEN (0x26C) |
| 34 | #define SE_SPI_RX_TRANS_LEN (0x270) |
| 35 | #define SE_SPI_PRE_POST_CMD_DLY (0x274) |
| 36 | #define SE_SPI_DELAY_COUNTERS (0x278) |
| 37 | |
| 38 | /* SE_SPI_CPHA register fields */ |
| 39 | #define CPHA (BIT(0)) |
| 40 | |
| 41 | /* SE_SPI_LOOPBACK register fields */ |
| 42 | #define LOOPBACK_ENABLE (0x1) |
| 43 | #define NORMAL_MODE (0x0) |
| 44 | #define LOOPBACK_MSK (GENMASK(1, 0)) |
| 45 | |
| 46 | /* SE_SPI_CPOL register fields */ |
| 47 | #define CPOL (BIT(2)) |
| 48 | |
| 49 | /* SE_SPI_DEMUX_OUTPUT_INV register fields */ |
| 50 | #define CS_DEMUX_OUTPUT_INV_MSK (GENMASK(3, 0)) |
| 51 | |
| 52 | /* SE_SPI_DEMUX_SEL register fields */ |
| 53 | #define CS_DEMUX_OUTPUT_SEL (GENMASK(3, 0)) |
| 54 | |
| 55 | /* SE_SPI_TX_TRANS_CFG register fields */ |
| 56 | #define CS_TOGGLE (BIT(0)) |
| 57 | |
| 58 | /* SE_SPI_WORD_LEN register fields */ |
| 59 | #define WORD_LEN_MSK (GENMASK(9, 0)) |
| 60 | #define MIN_WORD_LEN (4) |
| 61 | |
| 62 | /* SPI_TX/SPI_RX_TRANS_LEN fields */ |
| 63 | #define TRANS_LEN_MSK (GENMASK(23, 0)) |
| 64 | |
| 65 | /* M_CMD OP codes for SPI */ |
| 66 | #define SPI_TX_ONLY (1) |
| 67 | #define SPI_RX_ONLY (2) |
| 68 | #define SPI_FULL_DUPLEX (3) |
| 69 | #define SPI_TX_RX (7) |
| 70 | #define SPI_CS_ASSERT (8) |
| 71 | #define SPI_CS_DEASSERT (9) |
| 72 | #define SPI_SCK_ONLY (10) |
| 73 | /* M_CMD params for SPI */ |
| 74 | #define SPI_PRE_CMD_DELAY (0) |
| 75 | #define TIMESTAMP_BEFORE (1) |
| 76 | #define FRAGMENTATION (2) |
| 77 | #define TIMESTAMP_AFTER (3) |
| 78 | #define POST_CMD_DELAY (4) |
| 79 | |
| 80 | struct spi_geni_master { |
| 81 | struct se_geni_rsc spi_rsc; |
| 82 | resource_size_t phys_addr; |
| 83 | resource_size_t size; |
| 84 | void __iomem *base; |
| 85 | int irq; |
| 86 | struct device *dev; |
| 87 | int rx_fifo_depth; |
| 88 | int tx_fifo_depth; |
| 89 | int tx_fifo_width; |
| 90 | int tx_wm; |
| 91 | bool setup; |
| 92 | u32 cur_speed_hz; |
| 93 | int cur_word_len; |
| 94 | unsigned int tx_rem_bytes; |
| 95 | unsigned int rx_rem_bytes; |
| 96 | struct spi_transfer *cur_xfer; |
| 97 | struct completion xfer_done; |
| 98 | }; |
| 99 | |
| 100 | static struct spi_master *get_spi_master(struct device *dev) |
| 101 | { |
| 102 | struct platform_device *pdev = to_platform_device(dev); |
| 103 | struct spi_master *spi = platform_get_drvdata(pdev); |
| 104 | |
| 105 | return spi; |
| 106 | } |
| 107 | |
| 108 | static int get_sclk(u32 speed_hz, unsigned long *sclk_freq) |
| 109 | { |
| 110 | u32 root_freq[] = { 19200000 }; |
| 111 | |
| 112 | *sclk_freq = root_freq[0]; |
| 113 | return 0; |
| 114 | } |
| 115 | |
| 116 | static int do_spi_clk_cfg(u32 speed_hz, struct spi_geni_master *mas) |
| 117 | { |
| 118 | unsigned long sclk_freq; |
| 119 | int div = 0; |
| 120 | int idx; |
| 121 | struct se_geni_rsc *rsc = &mas->spi_rsc; |
| 122 | int ret = 0; |
| 123 | u32 clk_sel = geni_read_reg(mas->base, SE_GENI_CLK_SEL); |
| 124 | u32 m_clk_cfg = geni_read_reg(mas->base, GENI_SER_M_CLK_CFG); |
| 125 | |
| 126 | clk_sel &= ~CLK_SEL_MSK; |
| 127 | m_clk_cfg &= ~CLK_DIV_MSK; |
| 128 | |
| 129 | idx = get_sclk(speed_hz, &sclk_freq); |
| 130 | if (idx < 0) { |
| 131 | ret = -EINVAL; |
| 132 | goto spi_clk_cfg_exit; |
| 133 | } |
| 134 | div = (sclk_freq / (SPI_OVERSAMPLING / speed_hz)); |
| 135 | |
| 136 | clk_sel |= (idx & CLK_SEL_MSK); |
| 137 | m_clk_cfg |= ((div << CLK_DIV_SHFT) | SER_CLK_EN); |
| 138 | ret = clk_set_rate(rsc->se_clk, sclk_freq); |
| 139 | if (ret) |
| 140 | goto spi_clk_cfg_exit; |
| 141 | |
| 142 | geni_write_reg(clk_sel, mas->base, SE_GENI_CLK_SEL); |
| 143 | geni_write_reg(m_clk_cfg, mas->base, GENI_SER_M_CLK_CFG); |
| 144 | spi_clk_cfg_exit: |
| 145 | return ret; |
| 146 | } |
| 147 | |
| 148 | static void spi_setup_word_len(struct spi_geni_master *mas, u32 mode, |
| 149 | int bits_per_word) |
| 150 | { |
| 151 | int pack_words = mas->tx_fifo_width / bits_per_word; |
| 152 | bool msb_first = (mode & SPI_LSB_FIRST) ? false : true; |
| 153 | u32 word_len = geni_read_reg(mas->base, SE_SPI_WORD_LEN); |
| 154 | |
| 155 | word_len &= ~WORD_LEN_MSK; |
| 156 | word_len |= ((bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK); |
| 157 | se_config_packing(mas->base, bits_per_word, pack_words, msb_first); |
| 158 | geni_write_reg(word_len, mas->base, SE_SPI_WORD_LEN); |
| 159 | } |
| 160 | |
| 161 | static int spi_geni_prepare_message(struct spi_master *spi_mas, |
| 162 | struct spi_message *spi_msg) |
| 163 | { |
| 164 | struct spi_device *spi_slv = spi_msg->spi; |
| 165 | struct spi_geni_master *mas = spi_master_get_devdata(spi_mas); |
| 166 | u16 mode = spi_slv->mode; |
| 167 | u32 loopback_cfg = geni_read_reg(mas->base, SE_SPI_LOOPBACK); |
| 168 | u32 cpol = geni_read_reg(mas->base, SE_SPI_CPOL); |
| 169 | u32 cpha = geni_read_reg(mas->base, SE_SPI_CPHA); |
| 170 | u32 demux_sel = geni_read_reg(mas->base, SE_SPI_DEMUX_SEL); |
| 171 | u32 demux_output_inv = |
| 172 | geni_read_reg(mas->base, SE_SPI_DEMUX_OUTPUT_INV); |
| 173 | int ret = 0; |
| 174 | |
| 175 | loopback_cfg &= ~LOOPBACK_MSK; |
| 176 | cpol &= ~CPOL; |
| 177 | cpha &= ~CPHA; |
| 178 | demux_output_inv &= ~BIT(spi_slv->chip_select); |
| 179 | |
| 180 | if (mode & SPI_LOOP) |
| 181 | loopback_cfg |= LOOPBACK_ENABLE; |
| 182 | |
| 183 | if (mode & SPI_CPOL) |
| 184 | cpol |= CPOL; |
| 185 | |
| 186 | if (mode & SPI_CPHA) |
| 187 | cpha |= CPHA; |
| 188 | |
| 189 | if (spi_slv->mode & SPI_CS_HIGH) |
| 190 | demux_output_inv |= BIT(spi_slv->chip_select); |
| 191 | |
| 192 | demux_sel |= BIT(spi_slv->chip_select); |
| 193 | mas->cur_speed_hz = spi_slv->max_speed_hz; |
| 194 | mas->cur_word_len = spi_slv->bits_per_word; |
| 195 | |
| 196 | ret = do_spi_clk_cfg(mas->cur_speed_hz, mas); |
| 197 | if (ret) { |
| 198 | dev_err(&spi_mas->dev, "Err setting clks ret %d\n", ret); |
| 199 | goto prepare_message_exit; |
| 200 | } |
| 201 | spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); |
| 202 | geni_write_reg(loopback_cfg, mas->base, SE_SPI_LOOPBACK); |
| 203 | geni_write_reg(demux_sel, mas->base, SE_SPI_DEMUX_SEL); |
| 204 | geni_write_reg(cpha, mas->base, SE_SPI_CPHA); |
| 205 | geni_write_reg(cpol, mas->base, SE_SPI_CPOL); |
| 206 | geni_write_reg(demux_output_inv, mas->base, SE_SPI_DEMUX_OUTPUT_INV); |
| 207 | /* Ensure message level attributes are written before returning */ |
| 208 | mb(); |
| 209 | prepare_message_exit: |
| 210 | return ret; |
| 211 | } |
| 212 | |
| 213 | static int spi_geni_unprepare_message(struct spi_master *spi_mas, |
| 214 | struct spi_message *spi_msg) |
| 215 | { |
| 216 | struct spi_geni_master *mas = spi_master_get_devdata(spi_mas); |
| 217 | |
| 218 | mas->cur_speed_hz = 0; |
| 219 | mas->cur_word_len = 0; |
| 220 | return 0; |
| 221 | } |
| 222 | |
| 223 | static int spi_geni_prepare_transfer_hardware(struct spi_master *spi) |
| 224 | { |
| 225 | struct spi_geni_master *mas = spi_master_get_devdata(spi); |
| 226 | int ret = 0; |
| 227 | |
| 228 | ret = pm_runtime_get_sync(mas->dev); |
| 229 | if (ret < 0) { |
| 230 | dev_err(mas->dev, "Error enabling SE resources\n"); |
| 231 | pm_runtime_put_noidle(mas->dev); |
| 232 | goto exit_prepare_transfer_hardware; |
| 233 | } else { |
| 234 | ret = 0; |
| 235 | } |
| 236 | |
| 237 | if (unlikely(!mas->setup)) { |
| 238 | int proto = get_se_proto(mas->base); |
| 239 | |
| 240 | if (unlikely(proto != SPI)) { |
| 241 | dev_err(mas->dev, "Invalid proto %d\n", proto); |
| 242 | return -ENXIO; |
| 243 | } |
| 244 | geni_se_init(mas->base, FIFO_MODE, 0x0, |
| 245 | (mas->tx_fifo_depth - 2)); |
| 246 | mas->tx_fifo_depth = get_tx_fifo_depth(mas->base); |
| 247 | mas->rx_fifo_depth = get_rx_fifo_depth(mas->base); |
| 248 | mas->tx_fifo_width = get_tx_fifo_width(mas->base); |
| 249 | /* Transmit an entire FIFO worth of data per IRQ */ |
| 250 | mas->tx_wm = 1; |
| 251 | dev_dbg(mas->dev, "tx_fifo %d rx_fifo %d tx_width %d\n", |
| 252 | mas->tx_fifo_depth, mas->rx_fifo_depth, |
| 253 | mas->tx_fifo_width); |
| 254 | mas->setup = true; |
| 255 | } |
| 256 | exit_prepare_transfer_hardware: |
| 257 | return ret; |
| 258 | } |
| 259 | |
| 260 | static int spi_geni_unprepare_transfer_hardware(struct spi_master *spi) |
| 261 | { |
| 262 | struct spi_geni_master *mas = spi_master_get_devdata(spi); |
| 263 | |
| 264 | pm_runtime_put_sync(mas->dev); |
| 265 | return 0; |
| 266 | } |
| 267 | |
| 268 | static void setup_fifo_xfer(struct spi_transfer *xfer, |
| 269 | struct spi_geni_master *mas, u16 mode, |
| 270 | struct spi_master *spi) |
| 271 | { |
| 272 | u32 m_cmd = 0; |
| 273 | u32 m_param = 0; |
| 274 | u32 spi_tx_cfg = geni_read_reg(mas->base, SE_SPI_TRANS_CFG); |
| 275 | u32 trans_len = 0; |
| 276 | |
| 277 | if (xfer->bits_per_word != mas->cur_word_len) { |
| 278 | spi_setup_word_len(mas, mode, xfer->bits_per_word); |
| 279 | mas->cur_word_len = xfer->bits_per_word; |
| 280 | } |
| 281 | |
| 282 | if (xfer->tx_buf && xfer->rx_buf) |
| 283 | m_cmd = SPI_FULL_DUPLEX; |
| 284 | else if (xfer->tx_buf) |
| 285 | m_cmd = SPI_TX_ONLY; |
| 286 | else if (xfer->rx_buf) |
| 287 | m_cmd = SPI_RX_ONLY; |
| 288 | |
| 289 | spi_tx_cfg &= ~CS_TOGGLE; |
| 290 | if (xfer->cs_change) |
| 291 | spi_tx_cfg |= CS_TOGGLE; |
| 292 | trans_len = ((xfer->len / (mas->cur_word_len >> 3)) & TRANS_LEN_MSK); |
| 293 | if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) |
| 294 | m_param |= FRAGMENTATION; |
| 295 | |
| 296 | mas->cur_xfer = xfer; |
| 297 | if (m_cmd & SPI_TX_ONLY) { |
| 298 | mas->tx_rem_bytes = xfer->len; |
| 299 | geni_write_reg(trans_len, mas->base, SE_SPI_TX_TRANS_LEN); |
| 300 | } |
| 301 | |
| 302 | if (m_cmd & SPI_RX_ONLY) { |
| 303 | geni_write_reg(trans_len, mas->base, SE_SPI_RX_TRANS_LEN); |
| 304 | mas->rx_rem_bytes = xfer->len; |
| 305 | } |
| 306 | geni_write_reg(spi_tx_cfg, mas->base, SE_SPI_TRANS_CFG); |
| 307 | geni_setup_m_cmd(mas->base, m_cmd, m_param); |
| 308 | geni_write_reg(mas->tx_wm, mas->base, SE_GENI_TX_WATERMARK_REG); |
| 309 | /* Ensure all writes are done before the WM interrupt */ |
| 310 | mb(); |
| 311 | } |
| 312 | |
| 313 | static void handle_fifo_timeout(struct spi_geni_master *mas) |
| 314 | { |
| 315 | unsigned long timeout; |
| 316 | u32 tx_trans_len = geni_read_reg(mas->base, SE_SPI_TX_TRANS_LEN); |
| 317 | u32 rx_trans_len = geni_read_reg(mas->base, SE_SPI_RX_TRANS_LEN); |
| 318 | u32 spi_tx_cfg = geni_read_reg(mas->base, SE_SPI_TRANS_CFG); |
| 319 | u32 m_cmd = geni_read_reg(mas->base, SE_GENI_M_CMD0); |
| 320 | |
| 321 | /* Timed-out on a FIFO xfer, print relevant reg info. */ |
| 322 | dev_err(mas->dev, "tx_rem_bytes %d rx_rem_bytes %d\n", |
| 323 | mas->tx_rem_bytes, mas->rx_rem_bytes); |
| 324 | dev_err(mas->dev, "tx_trans_len %d rx_trans_len %d\n", tx_trans_len, |
| 325 | rx_trans_len); |
| 326 | dev_err(mas->dev, "spi_tx_cfg 0x%x m_cmd 0x%x\n", spi_tx_cfg, m_cmd); |
| 327 | reinit_completion(&mas->xfer_done); |
| 328 | geni_cancel_m_cmd(mas->base); |
| 329 | /* Ensure cmd cancel is written */ |
| 330 | mb(); |
| 331 | timeout = wait_for_completion_timeout(&mas->xfer_done, HZ); |
| 332 | if (!timeout) { |
| 333 | reinit_completion(&mas->xfer_done); |
| 334 | geni_abort_m_cmd(mas->base); |
| 335 | /* Ensure cmd abort is written */ |
| 336 | mb(); |
| 337 | timeout = wait_for_completion_timeout(&mas->xfer_done, |
| 338 | HZ); |
| 339 | if (!timeout) |
| 340 | dev_err(mas->dev, |
| 341 | "Failed to cancel/abort m_cmd\n"); |
| 342 | } |
| 343 | } |
| 344 | |
| 345 | static int spi_geni_transfer_one(struct spi_master *spi, |
| 346 | struct spi_device *slv, |
| 347 | struct spi_transfer *xfer) |
| 348 | { |
| 349 | int ret = 0; |
| 350 | struct spi_geni_master *mas = spi_master_get_devdata(spi); |
| 351 | unsigned long timeout; |
| 352 | |
| 353 | if ((xfer->tx_buf == NULL) && (xfer->rx_buf == NULL)) { |
| 354 | dev_err(mas->dev, "Invalid xfer both tx rx are NULL\n"); |
| 355 | return -EINVAL; |
| 356 | } |
| 357 | |
| 358 | reinit_completion(&mas->xfer_done); |
| 359 | /* Speed and bits per word can be overridden per transfer */ |
| 360 | if (xfer->speed_hz != mas->cur_speed_hz) { |
| 361 | ret = do_spi_clk_cfg(mas->cur_speed_hz, mas); |
| 362 | if (ret) { |
| 363 | dev_err(mas->dev, "%s:Err setting clks:%d\n", |
| 364 | __func__, ret); |
| 365 | goto geni_transfer_one_exit; |
| 366 | } |
| 367 | mas->cur_speed_hz = xfer->speed_hz; |
| 368 | } |
| 369 | |
| 370 | setup_fifo_xfer(xfer, mas, slv->mode, spi); |
| 371 | timeout = wait_for_completion_timeout(&mas->xfer_done, |
| 372 | msecs_to_jiffies(SPI_XFER_TIMEOUT_MS)); |
| 373 | if (!timeout) { |
| 374 | dev_err(mas->dev, "Xfer[len %d tx %p rx %p n %d] timed out.\n", |
| 375 | xfer->len, xfer->tx_buf, |
| 376 | xfer->rx_buf, |
| 377 | xfer->bits_per_word); |
| 378 | ret = -ETIMEDOUT; |
| 379 | handle_fifo_timeout(mas); |
| 380 | } |
| 381 | geni_transfer_one_exit: |
| 382 | return ret; |
| 383 | } |
| 384 | |
| 385 | static void geni_spi_handle_tx(struct spi_geni_master *mas) |
| 386 | { |
| 387 | int i = 0; |
| 388 | int tx_fifo_width = (mas->tx_fifo_width >> 3); |
| 389 | int max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * tx_fifo_width; |
| 390 | const u8 *tx_buf = mas->cur_xfer->tx_buf; |
| 391 | |
| 392 | tx_buf += (mas->cur_xfer->len - mas->tx_rem_bytes); |
| 393 | max_bytes = min_t(int, mas->tx_rem_bytes, max_bytes); |
| 394 | while (i < max_bytes) { |
| 395 | int j; |
| 396 | u32 fifo_word = 0; |
| 397 | u8 *fifo_byte; |
| 398 | int bytes_to_write = min_t(int, (max_bytes - i), tx_fifo_width); |
| 399 | |
| 400 | fifo_byte = (u8 *)&fifo_word; |
| 401 | for (j = 0; j < bytes_to_write; j++) |
| 402 | fifo_byte[j] = tx_buf[i++]; |
| 403 | geni_write_reg(fifo_word, mas->base, SE_GENI_TX_FIFOn); |
| 404 | /* Ensure FIFO writes are written in order */ |
| 405 | mb(); |
| 406 | } |
| 407 | mas->tx_rem_bytes -= max_bytes; |
| 408 | if (!mas->tx_rem_bytes) { |
| 409 | geni_write_reg(0, mas->base, SE_GENI_TX_WATERMARK_REG); |
| 410 | /* Barrier here before return to prevent further ISRs */ |
| 411 | mb(); |
| 412 | } |
| 413 | } |
| 414 | |
| 415 | static void geni_spi_handle_rx(struct spi_geni_master *mas) |
| 416 | { |
| 417 | int i = 0; |
| 418 | int fifo_width = (mas->tx_fifo_width >> 3); |
| 419 | u32 rx_fifo_status = geni_read_reg(mas->base, SE_GENI_RX_FIFO_STATUS); |
| 420 | int rx_bytes = 0; |
| 421 | int rx_wc = 0; |
| 422 | u8 *rx_buf = mas->cur_xfer->rx_buf; |
| 423 | |
| 424 | rx_wc = (rx_fifo_status & RX_FIFO_WC_MSK); |
| 425 | if (rx_fifo_status & RX_LAST) { |
| 426 | int rx_last_byte_valid = |
| 427 | (rx_fifo_status & RX_LAST_BYTE_VALID_MSK) |
| 428 | >> RX_LAST_BYTE_VALID_SHFT; |
| 429 | if (rx_last_byte_valid && (rx_last_byte_valid < 4)) { |
| 430 | rx_wc -= 1; |
| 431 | rx_bytes += rx_last_byte_valid; |
| 432 | } |
| 433 | } |
| 434 | rx_bytes += rx_wc * fifo_width; |
| 435 | rx_bytes = min_t(int, mas->rx_rem_bytes, rx_bytes); |
| 436 | rx_buf += (mas->cur_xfer->len - mas->rx_rem_bytes); |
| 437 | while (i < rx_bytes) { |
| 438 | u32 fifo_word = 0; |
| 439 | u8 *fifo_byte; |
| 440 | int read_bytes = min_t(int, (rx_bytes - i), fifo_width); |
| 441 | int j; |
| 442 | |
| 443 | fifo_word = geni_read_reg(mas->base, SE_GENI_RX_FIFOn); |
| 444 | fifo_byte = (u8 *)&fifo_word; |
| 445 | for (j = 0; j < read_bytes; j++) |
| 446 | rx_buf[i++] = fifo_byte[j]; |
| 447 | } |
| 448 | mas->rx_rem_bytes -= rx_bytes; |
| 449 | } |
| 450 | |
| 451 | static irqreturn_t geni_spi_irq(int irq, void *dev) |
| 452 | { |
| 453 | struct spi_geni_master *mas = dev; |
| 454 | u32 m_irq = geni_read_reg(mas->base, SE_GENI_M_IRQ_STATUS); |
| 455 | |
| 456 | if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN)) |
| 457 | geni_spi_handle_rx(mas); |
| 458 | |
| 459 | if ((m_irq & M_TX_FIFO_WATERMARK_EN)) |
| 460 | geni_spi_handle_tx(mas); |
| 461 | |
| 462 | if ((m_irq & M_CMD_DONE_EN) || (m_irq & M_CMD_CANCEL_EN) || |
| 463 | (m_irq & M_CMD_ABORT_EN)) { |
| 464 | complete(&mas->xfer_done); |
| 465 | } |
| 466 | geni_write_reg(m_irq, mas->base, SE_GENI_M_IRQ_CLEAR); |
| 467 | return IRQ_HANDLED; |
| 468 | } |
| 469 | |
| 470 | static int spi_geni_probe(struct platform_device *pdev) |
| 471 | { |
| 472 | int ret; |
| 473 | struct spi_master *spi; |
| 474 | struct spi_geni_master *geni_mas; |
| 475 | struct se_geni_rsc *rsc; |
| 476 | struct resource *res; |
| 477 | |
| 478 | spi = spi_alloc_master(&pdev->dev, sizeof(struct spi_geni_master)); |
| 479 | if (!spi) { |
| 480 | ret = -ENOMEM; |
| 481 | dev_err(&pdev->dev, "Failed to alloc spi struct\n"); |
| 482 | goto spi_geni_probe_err; |
| 483 | } |
| 484 | |
| 485 | platform_set_drvdata(pdev, spi); |
| 486 | geni_mas = spi_master_get_devdata(spi); |
| 487 | rsc = &geni_mas->spi_rsc; |
| 488 | geni_mas->dev = &pdev->dev; |
| 489 | spi->dev.of_node = pdev->dev.of_node; |
| 490 | rsc->geni_pinctrl = devm_pinctrl_get(&pdev->dev); |
| 491 | if (IS_ERR_OR_NULL(rsc->geni_pinctrl)) { |
| 492 | dev_err(&pdev->dev, "No pinctrl config specified!\n"); |
| 493 | ret = PTR_ERR(rsc->geni_pinctrl); |
| 494 | goto spi_geni_probe_err; |
| 495 | } |
| 496 | |
| 497 | rsc->geni_gpio_active = pinctrl_lookup_state(rsc->geni_pinctrl, |
| 498 | PINCTRL_DEFAULT); |
| 499 | if (IS_ERR_OR_NULL(rsc->geni_gpio_active)) { |
| 500 | dev_err(&pdev->dev, "No default config specified!\n"); |
| 501 | ret = PTR_ERR(rsc->geni_gpio_active); |
| 502 | goto spi_geni_probe_err; |
| 503 | } |
| 504 | |
| 505 | rsc->geni_gpio_sleep = pinctrl_lookup_state(rsc->geni_pinctrl, |
| 506 | PINCTRL_SLEEP); |
| 507 | if (IS_ERR_OR_NULL(rsc->geni_gpio_sleep)) { |
| 508 | dev_err(&pdev->dev, "No sleep config specified!\n"); |
| 509 | ret = PTR_ERR(rsc->geni_gpio_sleep); |
| 510 | goto spi_geni_probe_err; |
| 511 | } |
| 512 | |
| 513 | rsc->se_clk = devm_clk_get(&pdev->dev, "se-clk"); |
| 514 | if (IS_ERR(rsc->se_clk)) { |
| 515 | ret = PTR_ERR(rsc->se_clk); |
| 516 | dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); |
| 517 | goto spi_geni_probe_err; |
| 518 | } |
| 519 | |
| 520 | rsc->m_ahb_clk = devm_clk_get(&pdev->dev, "m-ahb"); |
| 521 | if (IS_ERR(rsc->m_ahb_clk)) { |
| 522 | ret = PTR_ERR(rsc->m_ahb_clk); |
| 523 | dev_err(&pdev->dev, "Err getting M AHB clk %d\n", ret); |
| 524 | goto spi_geni_probe_err; |
| 525 | } |
| 526 | |
| 527 | rsc->s_ahb_clk = devm_clk_get(&pdev->dev, "s-ahb"); |
| 528 | if (IS_ERR(rsc->s_ahb_clk)) { |
| 529 | ret = PTR_ERR(rsc->s_ahb_clk); |
| 530 | dev_err(&pdev->dev, "Err getting S AHB clk %d\n", ret); |
| 531 | goto spi_geni_probe_err; |
| 532 | } |
| 533 | |
| 534 | if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency", |
| 535 | &spi->max_speed_hz)) { |
| 536 | dev_err(&pdev->dev, "Max frequency not specified.\n"); |
| 537 | ret = -ENXIO; |
| 538 | goto spi_geni_probe_err; |
| 539 | } |
| 540 | |
| 541 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "se_phys"); |
| 542 | if (!res) { |
| 543 | ret = -ENXIO; |
| 544 | dev_err(&pdev->dev, "Err getting IO region\n"); |
| 545 | goto spi_geni_probe_err; |
| 546 | } |
| 547 | |
| 548 | geni_mas->phys_addr = res->start; |
| 549 | geni_mas->size = resource_size(res); |
| 550 | geni_mas->base = devm_ioremap(&pdev->dev, res->start, |
| 551 | resource_size(res)); |
| 552 | if (!geni_mas->base) { |
| 553 | ret = -ENOMEM; |
| 554 | dev_err(&pdev->dev, "Err IO mapping iomem\n"); |
| 555 | goto spi_geni_probe_err; |
| 556 | } |
| 557 | |
| 558 | geni_mas->irq = platform_get_irq(pdev, 0); |
| 559 | if (geni_mas->irq < 0) { |
| 560 | dev_err(&pdev->dev, "Err getting IRQ\n"); |
| 561 | ret = geni_mas->irq; |
| 562 | goto spi_geni_probe_unmap; |
| 563 | } |
| 564 | ret = devm_request_irq(&pdev->dev, geni_mas->irq, geni_spi_irq, |
| 565 | IRQF_TRIGGER_HIGH, "spi_geni", geni_mas); |
| 566 | if (ret) { |
| 567 | dev_err(&pdev->dev, "Request_irq failed:%d: err:%d\n", |
| 568 | geni_mas->irq, ret); |
| 569 | goto spi_geni_probe_unmap; |
| 570 | } |
| 571 | |
| 572 | spi->mode_bits = (SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH); |
| 573 | spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
| 574 | spi->num_chipselect = SPI_NUM_CHIPSELECT; |
| 575 | spi->prepare_transfer_hardware = spi_geni_prepare_transfer_hardware; |
| 576 | spi->prepare_message = spi_geni_prepare_message; |
| 577 | spi->unprepare_message = spi_geni_unprepare_message; |
| 578 | spi->transfer_one = spi_geni_transfer_one; |
| 579 | spi->unprepare_transfer_hardware |
| 580 | = spi_geni_unprepare_transfer_hardware; |
| 581 | spi->auto_runtime_pm = false; |
| 582 | |
| 583 | init_completion(&geni_mas->xfer_done); |
| 584 | pm_runtime_enable(&pdev->dev); |
| 585 | ret = spi_register_master(spi); |
| 586 | if (ret) { |
| 587 | dev_err(&pdev->dev, "Failed to register SPI master\n"); |
| 588 | goto spi_geni_probe_unmap; |
| 589 | } |
| 590 | return ret; |
| 591 | spi_geni_probe_unmap: |
| 592 | devm_iounmap(&pdev->dev, geni_mas->base); |
| 593 | spi_geni_probe_err: |
| 594 | spi_master_put(spi); |
| 595 | return ret; |
| 596 | } |
| 597 | |
| 598 | static int spi_geni_remove(struct platform_device *pdev) |
| 599 | { |
| 600 | struct spi_master *master = platform_get_drvdata(pdev); |
| 601 | struct spi_geni_master *geni_mas = spi_master_get_devdata(master); |
| 602 | |
| 603 | spi_unregister_master(master); |
| 604 | se_geni_resources_off(&geni_mas->spi_rsc); |
| 605 | pm_runtime_put_noidle(&pdev->dev); |
| 606 | pm_runtime_disable(&pdev->dev); |
| 607 | return 0; |
| 608 | } |
| 609 | |
| 610 | #ifdef CONFIG_PM |
| 611 | static int spi_geni_runtime_suspend(struct device *dev) |
| 612 | { |
| 613 | int ret = 0; |
| 614 | struct spi_master *spi = get_spi_master(dev); |
| 615 | struct spi_geni_master *geni_mas = spi_master_get_devdata(spi); |
| 616 | |
| 617 | ret = se_geni_resources_off(&geni_mas->spi_rsc); |
| 618 | return ret; |
| 619 | } |
| 620 | |
| 621 | static int spi_geni_runtime_resume(struct device *dev) |
| 622 | { |
| 623 | int ret = 0; |
| 624 | struct spi_master *spi = get_spi_master(dev); |
| 625 | struct spi_geni_master *geni_mas = spi_master_get_devdata(spi); |
| 626 | |
| 627 | ret = se_geni_resources_on(&geni_mas->spi_rsc); |
| 628 | return ret; |
| 629 | } |
| 630 | |
| 631 | static int spi_geni_resume(struct device *dev) |
| 632 | { |
| 633 | return 0; |
| 634 | } |
| 635 | |
| 636 | static int spi_geni_suspend(struct device *dev) |
| 637 | { |
| 638 | if (!pm_runtime_status_suspended(dev)) |
| 639 | return -EBUSY; |
| 640 | return 0; |
| 641 | } |
| 642 | #else |
| 643 | static int spi_geni_runtime_suspend(struct device *dev) |
| 644 | { |
| 645 | return 0; |
| 646 | } |
| 647 | |
| 648 | static int spi_geni_runtime_resume(struct device *dev) |
| 649 | { |
| 650 | return 0; |
| 651 | } |
| 652 | |
| 653 | static int spi_geni_resume(struct device *dev) |
| 654 | { |
| 655 | return 0; |
| 656 | } |
| 657 | |
| 658 | static int spi_geni_suspend(struct device *dev) |
| 659 | { |
| 660 | return 0; |
| 661 | } |
| 662 | #endif |
| 663 | |
| 664 | static const struct dev_pm_ops spi_geni_pm_ops = { |
| 665 | SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend, |
| 666 | spi_geni_runtime_resume, NULL) |
| 667 | SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume) |
| 668 | }; |
| 669 | |
| 670 | static const struct of_device_id spi_geni_dt_match[] = { |
| 671 | { .compatible = "qcom,spi-geni" }, |
| 672 | {} |
| 673 | }; |
| 674 | |
| 675 | static struct platform_driver spi_geni_driver = { |
| 676 | .probe = spi_geni_probe, |
| 677 | .remove = spi_geni_remove, |
| 678 | .driver = { |
| 679 | .name = "spi_geni", |
| 680 | .pm = &spi_geni_pm_ops, |
| 681 | .of_match_table = spi_geni_dt_match, |
| 682 | }, |
| 683 | }; |
| 684 | module_platform_driver(spi_geni_driver); |
| 685 | |
| 686 | MODULE_LICENSE("GPL v2"); |
| 687 | MODULE_ALIAS("platform:spi_geni"); |