arch/arm/boot/dts/ls1021a.dtsi

/*
 * Copyright 2013-2014 Freescale Semiconductor, Inc.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of
 *     the License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 *     You should have received a copy of the GNU General Public
 *     License along with this file; if not, write to the Free
 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
 *     MA 02110-1301 USA
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton64.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "fsl,ls1021a";
	interrupt-parent = <&gic>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		serial0 = &lpuart0;
		serial1 = &lpuart1;
		serial2 = &lpuart2;
		serial3 = &lpuart3;
		serial4 = &lpuart4;
		serial5 = &lpuart5;
		sysclk = &sysclk;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@f00 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0xf00>;
			clocks = <&cluster1_clk>;
		};

		cpu@f01 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0xf01>;
			clocks = <&cluster1_clk>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		device_type = "soc";
		interrupt-parent = <&gic>;
		ranges;

		gic: interrupt-controller@1400000 {
			compatible = "arm,cortex-a7-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x0 0x1401000 0x0 0x1000>,
			      <0x0 0x1402000 0x0 0x1000>,
			      <0x0 0x1404000 0x0 0x2000>,
			      <0x0 0x1406000 0x0 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;

		};

		ifc: ifc@1530000 {
			compatible = "fsl,ifc", "simple-bus";
			reg = <0x0 0x1530000 0x0 0x10000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
		};

		dcfg: dcfg@1ee0000 {
			compatible = "fsl,ls1021a-dcfg", "syscon";
			reg = <0x0 0x1ee0000 0x0 0x10000>;
			big-endian;
		};

		esdhc: esdhc@1560000 {
			compatible = "fsl,esdhc";
			reg = <0x0 0x1560000 0x0 0x10000>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <0>;
			voltage-ranges = <1800 1800 3300 3300>;
			sdhci,auto-cmd12;
			big-endian;
			bus-width = <4>;
			status = "disabled";
		};

		scfg: scfg@1570000 {
			compatible = "fsl,ls1021a-scfg", "syscon";
			reg = <0x0 0x1570000 0x0 0x10000>;
			big-endian;
		};

		clockgen: clocking@1ee1000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x1ee1000 0x10000>;

			sysclk: sysclk {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-output-names = "sysclk";
			};

			cga_pll1: pll@800 {
				compatible = "fsl,qoriq-core-pll-2.0";
				#clock-cells = <1>;
				reg = <0x800 0x10>;
				clocks = <&sysclk>;
				clock-output-names = "cga-pll1", "cga-pll1-div2",
						     "cga-pll1-div4";
			};

			platform_clk: pll@c00 {
				compatible = "fsl,qoriq-core-pll-2.0";
				#clock-cells = <1>;
				reg = <0xc00 0x10>;
				clocks = <&sysclk>;
				clock-output-names = "platform-clk", "platform-clk-div2";
			};

			cluster1_clk: clk0c0@0 {
				compatible = "fsl,qoriq-core-mux-2.0";
				#clock-cells = <0>;
				reg = <0x0 0x10>;
				clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
				clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
				clock-output-names = "cluster1-clk";
			};
		};

		dspi0: dspi@2100000 {
			compatible = "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2100000 0x0 0x10000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "dspi";
			clocks = <&platform_clk 1>;
			spi-num-chipselects = <5>;
			big-endian;
			status = "disabled";
		};

		dspi1: dspi@2110000 {
			compatible = "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2110000 0x0 0x10000>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "dspi";
			clocks = <&platform_clk 1>;
			spi-num-chipselects = <5>;
			big-endian;
			status = "disabled";
		};

		i2c0: i2c@2180000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2180000 0x0 0x10000>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "i2c";
			clocks = <&platform_clk 1>;
			status = "disabled";
		};

		i2c1: i2c@2190000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2190000 0x0 0x10000>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "i2c";
			clocks = <&platform_clk 1>;
			status = "disabled";
		};

		i2c2: i2c@21a0000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21a0000 0x0 0x10000>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "i2c";
			clocks = <&platform_clk 1>;
			status = "disabled";
		};

		uart0: serial@21c0500 {
			compatible = "fsl,16550-FIFO64", "ns16550a";
			reg = <0x0 0x21c0500 0x0 0x100>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <0>;
			fifo-size = <15>;
			status = "disabled";
		};

		uart1: serial@21c0600 {
			compatible = "fsl,16550-FIFO64", "ns16550a";
			reg = <0x0 0x21c0600 0x0 0x100>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <0>;
			fifo-size = <15>;
			status = "disabled";
		};

		uart2: serial@21d0500 {
			compatible = "fsl,16550-FIFO64", "ns16550a";
			reg = <0x0 0x21d0500 0x0 0x100>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <0>;
			fifo-size = <15>;
			status = "disabled";
		};

		uart3: serial@21d0600 {
			compatible = "fsl,16550-FIFO64", "ns16550a";
			reg = <0x0 0x21d0600 0x0 0x100>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <0>;
			fifo-size = <15>;
			status = "disabled";
		};

		lpuart0: serial@2950000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2950000 0x0 0x1000>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysclk>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart1: serial@2960000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2960000 0x0 0x1000>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&platform_clk 1>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart2: serial@2970000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2970000 0x0 0x1000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&platform_clk 1>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart3: serial@2980000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2980000 0x0 0x1000>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&platform_clk 1>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart4: serial@2990000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2990000 0x0 0x1000>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&platform_clk 1>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart5: serial@29a0000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x29a0000 0x0 0x1000>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&platform_clk 1>;
			clock-names = "ipg";
			status = "disabled";
		};

		wdog0: watchdog@2ad0000 {
			compatible = "fsl,imx21-wdt";
			reg = <0x0 0x2ad0000 0x0 0x10000>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&platform_clk 1>;
			clock-names = "wdog-en";
			big-endian;
		};

		sai1: sai@2b50000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0x2b50000 0x0 0x10000>;
			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&platform_clk 1>, <&platform_clk 1>,
				 <&platform_clk 1>, <&platform_clk 1>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 47>,
			       <&edma0 1 46>;
			status = "disabled";
		};

		sai2: sai@2b60000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0x2b60000 0x0 0x10000>;
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&platform_clk 1>, <&platform_clk 1>,
				 <&platform_clk 1>, <&platform_clk 1>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 45>,
			       <&edma0 1 44>;
			status = "disabled";
		};

		edma0: edma@2c00000 {
			#dma-cells = <2>;
			compatible = "fsl,vf610-edma";
			reg = <0x0 0x2c00000 0x0 0x10000>,
			      <0x0 0x2c10000 0x0 0x10000>,
			      <0x0 0x2c20000 0x0 0x10000>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "edma-tx", "edma-err";
			dma-channels = <32>;
			big-endian;
			clock-names = "dmamux0", "dmamux1";
			clocks = <&platform_clk 1>,
				 <&platform_clk 1>;
		};

		mdio0: mdio@2d24000 {
			compatible = "gianfar";
			device_type = "mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2d24000 0x0 0x4000>;
		};

		enet0: ethernet@2d10000 {
			compatible = "fsl,etsec2";
			device_type = "network";
			#address-cells = <2>;
			#size-cells = <2>;
			interrupt-parent = <&gic>;
			model = "eTSEC";
			fsl,magic-packet;
			ranges;

			queue-group@2d10000 {
				#address-cells = <2>;
				#size-cells = <2>;
				reg = <0x0 0x2d10000 0x0 0x1000>;
				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
			};

			queue-group@2d14000  {
				#address-cells = <2>;
				#size-cells = <2>;
				reg = <0x0 0x2d14000 0x0 0x1000>;
				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		enet1: ethernet@2d50000 {
			compatible = "fsl,etsec2";
			device_type = "network";
			#address-cells = <2>;
			#size-cells = <2>;
			interrupt-parent = <&gic>;
			model = "eTSEC";
			ranges;

			queue-group@2d50000  {
				#address-cells = <2>;
				#size-cells = <2>;
				reg = <0x0 0x2d50000 0x0 0x1000>;
				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
			};

			queue-group@2d54000  {
				#address-cells = <2>;
				#size-cells = <2>;
				reg = <0x0 0x2d54000 0x0 0x1000>;
				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		enet2: ethernet@2d90000 {
			compatible = "fsl,etsec2";
			device_type = "network";
			#address-cells = <2>;
			#size-cells = <2>;
			interrupt-parent = <&gic>;
			model = "eTSEC";
			ranges;

			queue-group@2d90000  {
				#address-cells = <2>;
				#size-cells = <2>;
				reg = <0x0 0x2d90000 0x0 0x1000>;
				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
			};

			queue-group@2d94000  {
				#address-cells = <2>;
				#size-cells = <2>;
				reg = <0x0 0x2d94000 0x0 0x1000>;
				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		usb@8600000 {
			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
			reg = <0x0 0x8600000 0x0 0x1000>;
			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "host";
			phy_type = "ulpi";
		};

		usb3@3100000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x3100000 0x0 0x10000>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "host";
		};
	};
};