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John Linnb85a3ef2011-06-20 11:47:27 -06001/*
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -07002 * Copyright (C) 2011 - 2014 Xilinx
John Linnb85a3ef2011-06-20 11:47:27 -06003 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
Josh Cartwrighte06f1a92012-10-31 12:24:48 -060013/include/ "skeleton.dtsi"
John Linnb85a3ef2011-06-20 11:47:27 -060014
John Linnb85a3ef2011-06-20 11:47:27 -060015/ {
Josh Cartwrighte06f1a92012-10-31 12:24:48 -060016 compatible = "xlnx,zynq-7000";
John Linnb85a3ef2011-06-20 11:47:27 -060017
Soren Brinkmann41e4cdb2013-11-26 17:04:49 -080018 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu@0 {
23 compatible = "arm,cortex-a9";
24 device_type = "cpu";
25 reg = <0>;
26 clocks = <&clkc 3>;
Soren Brinkmannb2bf5d42014-04-04 16:14:12 -070027 clock-latency = <1000>;
Soren Brinkmanne1e22df2014-05-02 14:07:32 -070028 cpu0-supply = <&regulator_vccpint>;
Soren Brinkmanncd325292014-02-19 15:14:44 -080029 operating-points = <
30 /* kHz uV */
31 666667 1000000
32 333334 1000000
Soren Brinkmanncd325292014-02-19 15:14:44 -080033 >;
Soren Brinkmann41e4cdb2013-11-26 17:04:49 -080034 };
35
36 cpu@1 {
37 compatible = "arm,cortex-a9";
38 device_type = "cpu";
39 reg = <1>;
40 clocks = <&clkc 3>;
41 };
42 };
43
Michal Simek268a8202013-03-20 13:37:01 +010044 pmu {
45 compatible = "arm,cortex-a9-pmu";
46 interrupts = <0 5 4>, <0 6 4>;
47 interrupt-parent = <&intc>;
48 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
49 };
50
Soren Brinkmanne1e22df2014-05-02 14:07:32 -070051 regulator_vccpint: fixedregulator@0 {
52 compatible = "regulator-fixed";
53 regulator-name = "VCCPINT";
54 regulator-min-microvolt = <1000000>;
55 regulator-max-microvolt = <1000000>;
56 regulator-boot-on;
57 regulator-always-on;
58 };
59
John Linnb85a3ef2011-06-20 11:47:27 -060060 amba {
61 compatible = "simple-bus";
62 #address-cells = <1>;
63 #size-cells = <1>;
Josh Cartwrighte06f1a92012-10-31 12:24:48 -060064 interrupt-parent = <&intc>;
John Linnb85a3ef2011-06-20 11:47:27 -060065 ranges;
66
Michal Simek70472c42014-09-24 15:28:59 +020067 adc: adc@f8007100 {
Soren Brinkmann21555602014-06-05 09:05:23 -070068 compatible = "xlnx,zynq-xadc-1.00.a";
69 reg = <0xf8007100 0x20>;
70 interrupts = <0 7 4>;
71 interrupt-parent = <&intc>;
72 clocks = <&clkc 12>;
Michal Simekfdf26182014-07-23 15:03:03 +020073 };
74
75 can0: can@e0008000 {
76 compatible = "xlnx,zynq-can-1.0";
77 status = "disabled";
78 clocks = <&clkc 19>, <&clkc 36>;
79 clock-names = "can_clk", "pclk";
80 reg = <0xe0008000 0x1000>;
81 interrupts = <0 28 4>;
82 interrupt-parent = <&intc>;
83 tx-fifo-depth = <0x40>;
84 rx-fifo-depth = <0x40>;
85 };
86
87 can1: can@e0009000 {
88 compatible = "xlnx,zynq-can-1.0";
89 status = "disabled";
90 clocks = <&clkc 20>, <&clkc 37>;
91 clock-names = "can_clk", "pclk";
92 reg = <0xe0009000 0x1000>;
93 interrupts = <0 51 4>;
94 interrupt-parent = <&intc>;
95 tx-fifo-depth = <0x40>;
96 rx-fifo-depth = <0x40>;
97 };
Soren Brinkmanne0a5c552014-07-10 11:53:38 -070098
99 gpio0: gpio@e000a000 {
100 compatible = "xlnx,zynq-gpio-1.0";
101 #gpio-cells = <2>;
102 clocks = <&clkc 42>;
103 gpio-controller;
104 interrupt-parent = <&intc>;
105 interrupts = <0 20 4>;
106 reg = <0xe000a000 0x1000>;
Soren Brinkmann21555602014-06-05 09:05:23 -0700107 };
108
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700109 i2c0: i2c@e0004000 {
Soren Brinkmann0f6faa32014-04-04 14:27:56 -0700110 compatible = "cdns,i2c-r1p10";
111 status = "disabled";
112 clocks = <&clkc 38>;
113 interrupt-parent = <&intc>;
114 interrupts = <0 25 4>;
115 reg = <0xe0004000 0x1000>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 };
119
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700120 i2c1: i2c@e0005000 {
Soren Brinkmann0f6faa32014-04-04 14:27:56 -0700121 compatible = "cdns,i2c-r1p10";
122 status = "disabled";
123 clocks = <&clkc 39>;
124 interrupt-parent = <&intc>;
125 interrupts = <0 48 4>;
126 reg = <0xe0005000 0x1000>;
127 #address-cells = <1>;
128 #size-cells = <0>;
129 };
130
John Linnb85a3ef2011-06-20 11:47:27 -0600131 intc: interrupt-controller@f8f01000 {
Josh Cartwrightf447ed22012-10-17 19:46:49 -0500132 compatible = "arm,cortex-a9-gic";
133 #interrupt-cells = <3>;
John Linnb85a3ef2011-06-20 11:47:27 -0600134 interrupt-controller;
Josh Cartwrightf447ed22012-10-17 19:46:49 -0500135 reg = <0xF8F01000 0x1000>,
136 <0xF8F00100 0x100>;
John Linnb85a3ef2011-06-20 11:47:27 -0600137 };
138
Michal Simek8abef062014-09-24 15:16:01 +0200139 L2: cache-controller@f8f02000 {
Josh Cartwright0fcfdbc2012-10-23 17:34:22 -0500140 compatible = "arm,pl310-cache";
141 reg = <0xF8F02000 0x1000>;
Soren Brinkmann39c41df92013-07-31 16:24:59 -0700142 arm,data-latency = <3 2 2>;
143 arm,tag-latency = <2 2 2>;
Josh Cartwright0fcfdbc2012-10-23 17:34:22 -0500144 cache-unified;
145 cache-level = <2>;
146 };
147
Michal Simek6c7ba412014-09-24 15:53:39 +0200148 mc: memory-controller@f8006000 {
Soren Brinkmann36ad5ae2014-09-02 14:19:08 -0700149 compatible = "xlnx,zynq-ddrc-a05";
150 reg = <0xf8006000 0x1000>;
Michal Simek2329efb2014-10-20 15:15:47 +0200151 };
Soren Brinkmann36ad5ae2014-09-02 14:19:08 -0700152
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700153 uart0: serial@e0000000 {
Soren Brinkmann8fe93462014-04-04 17:23:45 -0700154 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
Soren Brinkmannec11ebc2013-06-13 09:37:16 -0700155 status = "disabled";
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700156 clocks = <&clkc 23>, <&clkc 40>;
Soren Brinkmann8fe93462014-04-04 17:23:45 -0700157 clock-names = "uart_clk", "pclk";
John Linnb85a3ef2011-06-20 11:47:27 -0600158 reg = <0xE0000000 0x1000>;
Josh Cartwrightf447ed22012-10-17 19:46:49 -0500159 interrupts = <0 27 4>;
John Linnb85a3ef2011-06-20 11:47:27 -0600160 };
Josh Cartwright78d67852012-10-31 13:45:17 -0600161
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700162 uart1: serial@e0001000 {
Soren Brinkmann8fe93462014-04-04 17:23:45 -0700163 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
Soren Brinkmannec11ebc2013-06-13 09:37:16 -0700164 status = "disabled";
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700165 clocks = <&clkc 24>, <&clkc 41>;
Soren Brinkmann8fe93462014-04-04 17:23:45 -0700166 clock-names = "uart_clk", "pclk";
Josh Cartwright78d67852012-10-31 13:45:17 -0600167 reg = <0xE0001000 0x1000>;
168 interrupts = <0 50 4>;
Josh Cartwright78d67852012-10-31 13:45:17 -0600169 };
Josh Cartwright0f586fb2012-11-08 12:04:26 -0600170
Andreas Färberf07ab7a2014-07-25 13:12:31 +0200171 spi0: spi@e0006000 {
172 compatible = "xlnx,zynq-spi-r1p6";
173 reg = <0xe0006000 0x1000>;
174 status = "disabled";
175 interrupt-parent = <&intc>;
176 interrupts = <0 26 4>;
177 clocks = <&clkc 25>, <&clkc 34>;
178 clock-names = "ref_clk", "pclk";
179 #address-cells = <1>;
180 #size-cells = <0>;
181 };
182
183 spi1: spi@e0007000 {
184 compatible = "xlnx,zynq-spi-r1p6";
185 reg = <0xe0007000 0x1000>;
186 status = "disabled";
187 interrupt-parent = <&intc>;
188 interrupts = <0 49 4>;
189 clocks = <&clkc 26>, <&clkc 35>;
190 clock-names = "ref_clk", "pclk";
191 #address-cells = <1>;
192 #size-cells = <0>;
193 };
194
Steffen Trumtrar982264c2013-12-11 09:29:49 -0800195 gem0: ethernet@e000b000 {
196 compatible = "cdns,gem";
Soren Brinkmannb5241fb2014-09-16 08:08:38 -0700197 reg = <0xe000b000 0x1000>;
Steffen Trumtrar982264c2013-12-11 09:29:49 -0800198 status = "disabled";
199 interrupts = <0 22 4>;
200 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
201 clock-names = "pclk", "hclk", "tx_clk";
Soren Brinkmannedbd35e2014-08-20 08:56:58 -0700202 #address-cells = <1>;
203 #size-cells = <0>;
Steffen Trumtrar982264c2013-12-11 09:29:49 -0800204 };
205
206 gem1: ethernet@e000c000 {
207 compatible = "cdns,gem";
Soren Brinkmannb5241fb2014-09-16 08:08:38 -0700208 reg = <0xe000c000 0x1000>;
Steffen Trumtrar982264c2013-12-11 09:29:49 -0800209 status = "disabled";
210 interrupts = <0 45 4>;
211 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
212 clock-names = "pclk", "hclk", "tx_clk";
Soren Brinkmannedbd35e2014-08-20 08:56:58 -0700213 #address-cells = <1>;
214 #size-cells = <0>;
Steffen Trumtrar982264c2013-12-11 09:29:49 -0800215 };
216
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700217 sdhci0: sdhci@e0100000 {
Soren Brinkmann3f7c7302013-12-02 10:02:37 -0800218 compatible = "arasan,sdhci-8.9a";
219 status = "disabled";
220 clock-names = "clk_xin", "clk_ahb";
221 clocks = <&clkc 21>, <&clkc 32>;
222 interrupt-parent = <&intc>;
223 interrupts = <0 24 4>;
224 reg = <0xe0100000 0x1000>;
Michal Simeke65b1582014-08-21 12:45:05 +0200225 };
Soren Brinkmann3f7c7302013-12-02 10:02:37 -0800226
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700227 sdhci1: sdhci@e0101000 {
Soren Brinkmann3f7c7302013-12-02 10:02:37 -0800228 compatible = "arasan,sdhci-8.9a";
229 status = "disabled";
230 clock-names = "clk_xin", "clk_ahb";
231 clocks = <&clkc 22>, <&clkc 33>;
232 interrupt-parent = <&intc>;
233 interrupts = <0 47 4>;
234 reg = <0xe0101000 0x1000>;
Michal Simeke65b1582014-08-21 12:45:05 +0200235 };
Soren Brinkmann3f7c7302013-12-02 10:02:37 -0800236
Josh Cartwright0f586fb2012-11-08 12:04:26 -0600237 slcr: slcr@f8000000 {
Michal Simekb0504e32013-11-18 16:48:19 +0100238 #address-cells = <1>;
239 #size-cells = <1>;
Soren Brinkmannf52948e2015-01-09 07:43:50 -0800240 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
Josh Cartwright0f586fb2012-11-08 12:04:26 -0600241 reg = <0xF8000000 0x1000>;
Michal Simekb0504e32013-11-18 16:48:19 +0100242 ranges;
243 clkc: clkc@100 {
244 #clock-cells = <1>;
245 compatible = "xlnx,ps7-clkc";
Michal Simekb0504e32013-11-18 16:48:19 +0100246 fclk-enable = <0>;
247 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
248 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
249 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
250 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
251 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
252 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
253 "gem1_aper", "sdio0_aper", "sdio1_aper",
254 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
255 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
256 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
257 "dbg_trc", "dbg_apb";
258 reg = <0x100 0x100>;
Josh Cartwright0f586fb2012-11-08 12:04:26 -0600259 };
Soren Brinkmannf52948e2015-01-09 07:43:50 -0800260
261 pinctrl0: pinctrl@700 {
262 compatible = "xlnx,pinctrl-zynq";
263 reg = <0x700 0x200>;
264 syscon = <&slcr>;
265 };
Josh Cartwright0f586fb2012-11-08 12:04:26 -0600266 };
Josh Cartwright91dc9852012-10-31 13:56:14 -0600267
Andreas Färberfbb4add2014-07-25 01:00:15 +0200268 dmac_s: dmac@f8003000 {
269 compatible = "arm,pl330", "arm,primecell";
270 reg = <0xf8003000 0x1000>;
271 interrupt-parent = <&intc>;
Michal Simek41683582014-08-21 11:27:05 +0200272 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
273 "dma4", "dma5", "dma6", "dma7";
Andreas Färberfbb4add2014-07-25 01:00:15 +0200274 interrupts = <0 13 4>,
275 <0 14 4>, <0 15 4>,
276 <0 16 4>, <0 17 4>,
277 <0 40 4>, <0 41 4>,
278 <0 42 4>, <0 43 4>;
279 #dma-cells = <1>;
280 #dma-channels = <8>;
281 #dma-requests = <4>;
282 clocks = <&clkc 27>;
283 clock-names = "apb_pclk";
284 };
285
Michal Simek00f7dc62013-07-31 09:19:59 +0200286 devcfg: devcfg@f8007000 {
287 compatible = "xlnx,zynq-devcfg-1.0";
288 reg = <0xf8007000 0x100>;
Michal Simeke65b1582014-08-21 12:45:05 +0200289 };
Michal Simek00f7dc62013-07-31 09:19:59 +0200290
Soren Brinkmannfa94bd52013-09-18 11:48:38 -0700291 global_timer: timer@f8f00200 {
292 compatible = "arm,cortex-a9-global-timer";
293 reg = <0xf8f00200 0x20>;
294 interrupts = <1 11 0x301>;
295 interrupt-parent = <&intc>;
296 clocks = <&clkc 4>;
297 };
298
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700299 ttc0: timer@f8001000 {
Michal Simeke9329002013-03-20 10:15:28 +0100300 interrupt-parent = <&intc>;
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700301 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
Michal Simeke9329002013-03-20 10:15:28 +0100302 compatible = "cdns,ttc";
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700303 clocks = <&clkc 6>;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600304 reg = <0xF8001000 0x1000>;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600305 };
306
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700307 ttc1: timer@f8002000 {
Michal Simeke9329002013-03-20 10:15:28 +0100308 interrupt-parent = <&intc>;
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700309 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
Michal Simeke9329002013-03-20 10:15:28 +0100310 compatible = "cdns,ttc";
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700311 clocks = <&clkc 6>;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600312 reg = <0xF8002000 0x1000>;
Josh Cartwright91dc9852012-10-31 13:56:14 -0600313 };
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700314
315 scutimer: timer@f8f00600 {
Michal Simek2f34e0a2013-03-27 13:36:39 +0100316 interrupt-parent = <&intc>;
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700317 interrupts = <1 13 0x301>;
Michal Simek2f34e0a2013-03-27 13:36:39 +0100318 compatible = "arm,cortex-a9-twd-timer";
Soren Brinkmannf7b1e9b2014-05-05 10:16:08 -0700319 reg = <0xf8f00600 0x20>;
Soren Brinkmann30e1e282013-05-13 10:46:38 -0700320 clocks = <&clkc 4>;
Michal Simeke65b1582014-08-21 12:45:05 +0200321 };
Michal Simek67142972014-10-02 15:09:15 +0200322
Soren Brinkmann1643b312014-12-02 08:07:11 -0800323 usb0: usb@e0002000 {
324 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
325 status = "disabled";
326 clocks = <&clkc 28>;
327 interrupt-parent = <&intc>;
328 interrupts = <0 21 4>;
329 reg = <0xe0002000 0x1000>;
330 phy_type = "ulpi";
331 };
332
333 usb1: usb@e0003000 {
334 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
335 status = "disabled";
336 clocks = <&clkc 29>;
337 interrupt-parent = <&intc>;
338 interrupts = <0 44 4>;
339 reg = <0xe0003000 0x1000>;
340 phy_type = "ulpi";
341 };
342
Michal Simek67142972014-10-02 15:09:15 +0200343 watchdog0: watchdog@f8005000 {
344 clocks = <&clkc 45>;
Michal Simek8f63a0b2015-01-15 13:45:08 +0100345 compatible = "cdns,wdt-r1p2";
Michal Simek67142972014-10-02 15:09:15 +0200346 interrupt-parent = <&intc>;
347 interrupts = <0 9 1>;
348 reg = <0xf8005000 0x1000>;
Michal Simek67142972014-10-02 15:09:15 +0200349 timeout-sec = <10>;
350 };
John Linnb85a3ef2011-06-20 11:47:27 -0600351 };
352};