Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2007 David Airlie |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * David Airlie |
| 25 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 26 | #include <linux/module.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 27 | #include <linux/slab.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 28 | #include <linux/fb.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 29 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/drmP.h> |
| 31 | #include <drm/drm_crtc.h> |
| 32 | #include <drm/drm_crtc_helper.h> |
| 33 | #include <drm/radeon_drm.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 34 | #include "radeon.h" |
| 35 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 36 | #include <drm/drm_fb_helper.h> |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 37 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 38 | #include <linux/vga_switcheroo.h> |
| 39 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 40 | /* object hierarchy - |
| 41 | this contains a helper + a radeon fb |
| 42 | the helper contains a pointer to radeon framebuffer baseclass. |
| 43 | */ |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 44 | struct radeon_fbdev { |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 45 | struct drm_fb_helper helper; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 46 | struct radeon_framebuffer rfb; |
| 47 | struct list_head fbdev_list; |
| 48 | struct radeon_device *rdev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 49 | }; |
| 50 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 51 | static struct fb_ops radeonfb_ops = { |
| 52 | .owner = THIS_MODULE, |
Michel Dänzer | c88f9f0 | 2009-09-15 17:09:30 +0200 | [diff] [blame] | 53 | .fb_check_var = drm_fb_helper_check_var, |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 54 | .fb_set_par = drm_fb_helper_set_par, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 55 | .fb_fillrect = cfb_fillrect, |
| 56 | .fb_copyarea = cfb_copyarea, |
| 57 | .fb_imageblit = cfb_imageblit, |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 58 | .fb_pan_display = drm_fb_helper_pan_display, |
| 59 | .fb_blank = drm_fb_helper_blank, |
Dave Airlie | 068143d | 2009-10-05 09:58:02 +1000 | [diff] [blame] | 60 | .fb_setcmap = drm_fb_helper_setcmap, |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 61 | .fb_debug_enter = drm_fb_helper_debug_enter, |
| 62 | .fb_debug_leave = drm_fb_helper_debug_leave, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 63 | }; |
| 64 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 65 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 66 | int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 67 | { |
| 68 | int aligned = width; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 69 | int align_large = (ASIC_IS_AVIVO(rdev)) || tiled; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 70 | int pitch_mask = 0; |
| 71 | |
| 72 | switch (bpp / 8) { |
| 73 | case 1: |
| 74 | pitch_mask = align_large ? 255 : 127; |
| 75 | break; |
| 76 | case 2: |
| 77 | pitch_mask = align_large ? 127 : 31; |
| 78 | break; |
| 79 | case 3: |
| 80 | case 4: |
| 81 | pitch_mask = align_large ? 63 : 15; |
| 82 | break; |
| 83 | } |
| 84 | |
| 85 | aligned += pitch_mask; |
| 86 | aligned &= ~pitch_mask; |
| 87 | return aligned; |
| 88 | } |
| 89 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 90 | static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 91 | { |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 92 | struct radeon_bo *rbo = gem_to_radeon_bo(gobj); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 93 | int ret; |
| 94 | |
| 95 | ret = radeon_bo_reserve(rbo, false); |
| 96 | if (likely(ret == 0)) { |
| 97 | radeon_bo_kunmap(rbo); |
Dave Airlie | 29d08b3 | 2010-09-27 16:17:17 +1000 | [diff] [blame] | 98 | radeon_bo_unpin(rbo); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 99 | radeon_bo_unreserve(rbo); |
| 100 | } |
| 101 | drm_gem_object_unreference_unlocked(gobj); |
| 102 | } |
| 103 | |
| 104 | static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev, |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 105 | struct drm_mode_fb_cmd2 *mode_cmd, |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 106 | struct drm_gem_object **gobj_p) |
| 107 | { |
| 108 | struct radeon_device *rdev = rfbdev->rdev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 109 | struct drm_gem_object *gobj = NULL; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 110 | struct radeon_bo *rbo = NULL; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 111 | bool fb_tiled = false; /* useful for testing */ |
Michel Dänzer | c88f9f0 | 2009-09-15 17:09:30 +0200 | [diff] [blame] | 112 | u32 tiling_flags = 0; |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 113 | int ret; |
| 114 | int aligned_size, size; |
Dave Airlie | e40b6fc | 2011-02-18 15:51:57 +1000 | [diff] [blame] | 115 | int height = mode_cmd->height; |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 116 | u32 bpp, depth; |
| 117 | |
Dave Airlie | 248dbc2 | 2011-11-29 20:02:54 +0000 | [diff] [blame] | 118 | drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 119 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 120 | /* need to align pitch with crtc limits */ |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 121 | mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, bpp, |
| 122 | fb_tiled) * ((bpp + 1) / 8); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 123 | |
Dave Airlie | e40b6fc | 2011-02-18 15:51:57 +1000 | [diff] [blame] | 124 | if (rdev->family >= CHIP_R600) |
| 125 | height = ALIGN(mode_cmd->height, 8); |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 126 | size = mode_cmd->pitches[0] * height; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 127 | aligned_size = ALIGN(size, PAGE_SIZE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 128 | ret = radeon_gem_object_create(rdev, aligned_size, 0, |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 129 | RADEON_GEM_DOMAIN_VRAM, |
Dave Airlie | 4dfe947 | 2010-08-23 08:27:47 +1000 | [diff] [blame] | 130 | false, true, |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 131 | &gobj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 132 | if (ret) { |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 133 | printk(KERN_ERR "failed to allocate framebuffer (%d)\n", |
| 134 | aligned_size); |
| 135 | return -ENOMEM; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 136 | } |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 137 | rbo = gem_to_radeon_bo(gobj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 138 | |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 139 | if (fb_tiled) |
Michel Dänzer | c88f9f0 | 2009-09-15 17:09:30 +0200 | [diff] [blame] | 140 | tiling_flags = RADEON_TILING_MACRO; |
| 141 | |
| 142 | #ifdef __BIG_ENDIAN |
Dave Airlie | 435ddd9 | 2011-11-29 11:42:50 +0000 | [diff] [blame] | 143 | switch (bpp) { |
Michel Dänzer | c88f9f0 | 2009-09-15 17:09:30 +0200 | [diff] [blame] | 144 | case 32: |
| 145 | tiling_flags |= RADEON_TILING_SWAP_32BIT; |
| 146 | break; |
| 147 | case 16: |
| 148 | tiling_flags |= RADEON_TILING_SWAP_16BIT; |
| 149 | default: |
| 150 | break; |
| 151 | } |
| 152 | #endif |
| 153 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 154 | if (tiling_flags) { |
| 155 | ret = radeon_bo_set_tiling_flags(rbo, |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 156 | tiling_flags | RADEON_TILING_SURFACE, |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 157 | mode_cmd->pitches[0]); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 158 | if (ret) |
| 159 | dev_err(rdev->dev, "FB failed to set tiling flags\n"); |
| 160 | } |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 161 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 162 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 163 | ret = radeon_bo_reserve(rbo, false); |
| 164 | if (unlikely(ret != 0)) |
| 165 | goto out_unref; |
Michel Dänzer | 0349af7 | 2012-03-14 17:12:42 +0100 | [diff] [blame] | 166 | /* Only 27 bit offset for legacy CRTC */ |
| 167 | ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, |
| 168 | ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, |
| 169 | NULL); |
Jerome Glisse | f92e93e | 2009-06-22 18:15:58 +0200 | [diff] [blame] | 170 | if (ret) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 171 | radeon_bo_unreserve(rbo); |
| 172 | goto out_unref; |
| 173 | } |
| 174 | if (fb_tiled) |
| 175 | radeon_bo_check_tiling(rbo, 0, 0); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 176 | ret = radeon_bo_kmap(rbo, NULL); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 177 | radeon_bo_unreserve(rbo); |
| 178 | if (ret) { |
Jerome Glisse | f92e93e | 2009-06-22 18:15:58 +0200 | [diff] [blame] | 179 | goto out_unref; |
| 180 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 181 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 182 | *gobj_p = gobj; |
| 183 | return 0; |
| 184 | out_unref: |
| 185 | radeonfb_destroy_pinned_object(gobj); |
| 186 | *gobj_p = NULL; |
| 187 | return ret; |
| 188 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 189 | |
Daniel Vetter | cd5428a | 2013-01-21 23:42:49 +0100 | [diff] [blame] | 190 | static int radeonfb_create(struct drm_fb_helper *helper, |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 191 | struct drm_fb_helper_surface_size *sizes) |
| 192 | { |
Daniel Vetter | cd5428a | 2013-01-21 23:42:49 +0100 | [diff] [blame] | 193 | struct radeon_fbdev *rfbdev = (struct radeon_fbdev *)helper; |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 194 | struct radeon_device *rdev = rfbdev->rdev; |
| 195 | struct fb_info *info; |
| 196 | struct drm_framebuffer *fb = NULL; |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 197 | struct drm_mode_fb_cmd2 mode_cmd; |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 198 | struct drm_gem_object *gobj = NULL; |
| 199 | struct radeon_bo *rbo = NULL; |
| 200 | struct device *device = &rdev->pdev->dev; |
| 201 | int ret; |
| 202 | unsigned long tmp; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 203 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 204 | mode_cmd.width = sizes->surface_width; |
| 205 | mode_cmd.height = sizes->surface_height; |
| 206 | |
| 207 | /* avivo can't scanout real 24bpp */ |
| 208 | if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev)) |
| 209 | sizes->surface_bpp = 32; |
| 210 | |
Jesse Barnes | 308e5bc | 2011-11-14 14:51:28 -0800 | [diff] [blame] | 211 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, |
| 212 | sizes->surface_depth); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 213 | |
| 214 | ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj); |
Dave Airlie | aaefcd4 | 2012-03-06 10:44:40 +0000 | [diff] [blame] | 215 | if (ret) { |
| 216 | DRM_ERROR("failed to create fbcon object %d\n", ret); |
| 217 | return ret; |
| 218 | } |
| 219 | |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 220 | rbo = gem_to_radeon_bo(gobj); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 221 | |
| 222 | /* okay we have an object now allocate the framebuffer */ |
| 223 | info = framebuffer_alloc(0, device); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 224 | if (info == NULL) { |
| 225 | ret = -ENOMEM; |
| 226 | goto out_unref; |
| 227 | } |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 228 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 229 | info->par = rfbdev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 230 | |
Dave Airlie | aaefcd4 | 2012-03-06 10:44:40 +0000 | [diff] [blame] | 231 | ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj); |
| 232 | if (ret) { |
Masanari Iida | 8b513d0 | 2013-05-21 23:13:12 +0900 | [diff] [blame] | 233 | DRM_ERROR("failed to initialize framebuffer %d\n", ret); |
Dave Airlie | aaefcd4 | 2012-03-06 10:44:40 +0000 | [diff] [blame] | 234 | goto out_unref; |
| 235 | } |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 236 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 237 | fb = &rfbdev->rfb.base; |
| 238 | |
| 239 | /* setup helper */ |
| 240 | rfbdev->helper.fb = fb; |
| 241 | rfbdev->helper.fbdev = info; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 242 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 243 | memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo)); |
Dave Airlie | bf8e828 | 2009-08-17 10:20:47 +1000 | [diff] [blame] | 244 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 245 | strcpy(info->fix.id, "radeondrmfb"); |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 246 | |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 247 | drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth); |
Dave Airlie | 3632ef8 | 2011-01-15 09:27:00 +1000 | [diff] [blame] | 248 | |
Jesse Barnes | 8fd4bd2 | 2010-06-23 12:56:12 -0700 | [diff] [blame] | 249 | info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 250 | info->fbops = &radeonfb_ops; |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 251 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 252 | tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start; |
Jerome Glisse | f92e93e | 2009-06-22 18:15:58 +0200 | [diff] [blame] | 253 | info->fix.smem_start = rdev->mc.aper_base + tmp; |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 254 | info->fix.smem_len = radeon_bo_size(rbo); |
| 255 | info->screen_base = rbo->kptr; |
| 256 | info->screen_size = radeon_bo_size(rbo); |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 257 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 258 | drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height); |
Dave Airlie | ed8f0d9 | 2009-07-29 17:07:38 +1000 | [diff] [blame] | 259 | |
| 260 | /* setup aperture base/size for vesafb takeover */ |
Marcin Slusarz | 1471ca9 | 2010-05-16 17:27:03 +0200 | [diff] [blame] | 261 | info->apertures = alloc_apertures(1); |
| 262 | if (!info->apertures) { |
| 263 | ret = -ENOMEM; |
| 264 | goto out_unref; |
| 265 | } |
| 266 | info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base; |
Dave Airlie | 68d3059 | 2010-12-20 10:54:48 +1000 | [diff] [blame] | 267 | info->apertures->ranges[0].size = rdev->mc.aper_size; |
Dave Airlie | ed8f0d9 | 2009-07-29 17:07:38 +1000 | [diff] [blame] | 268 | |
Sascha Hauer | fb2a99e | 2012-02-06 10:58:19 +0100 | [diff] [blame] | 269 | /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 270 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 271 | if (info->screen_base == NULL) { |
| 272 | ret = -ENOSPC; |
| 273 | goto out_unref; |
| 274 | } |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 275 | |
| 276 | ret = fb_alloc_cmap(&info->cmap, 256, 0); |
| 277 | if (ret) { |
| 278 | ret = -ENOMEM; |
| 279 | goto out_unref; |
| 280 | } |
| 281 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 282 | DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); |
| 283 | DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 284 | DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 285 | DRM_INFO("fb depth is %d\n", fb->depth); |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 286 | DRM_INFO(" pitch is %d\n", fb->pitches[0]); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 287 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 288 | vga_switcheroo_client_fb_set(rdev->ddev->pdev, info); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 289 | return 0; |
| 290 | |
| 291 | out_unref: |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 292 | if (rbo) { |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 293 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 294 | } |
Jerome Glisse | f92e93e | 2009-06-22 18:15:58 +0200 | [diff] [blame] | 295 | if (fb && ret) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 296 | drm_gem_object_unreference(gobj); |
Daniel Vetter | 3620636 | 2012-12-10 20:42:17 +0100 | [diff] [blame] | 297 | drm_framebuffer_unregister_private(fb); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 298 | drm_framebuffer_cleanup(fb); |
| 299 | kfree(fb); |
| 300 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 301 | return ret; |
| 302 | } |
| 303 | |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 304 | void radeon_fb_output_poll_changed(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 305 | { |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 306 | drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper); |
Dave Airlie | 5c4426a | 2010-03-30 05:34:17 +0000 | [diff] [blame] | 307 | } |
| 308 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 309 | static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 310 | { |
| 311 | struct fb_info *info; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 312 | struct radeon_framebuffer *rfb = &rfbdev->rfb; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 313 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 314 | if (rfbdev->helper.fbdev) { |
| 315 | info = rfbdev->helper.fbdev; |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 316 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 317 | unregister_framebuffer(info); |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 318 | if (info->cmap.len) |
| 319 | fb_dealloc_cmap(&info->cmap); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 320 | framebuffer_release(info); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 321 | } |
| 322 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 323 | if (rfb->obj) { |
Dave Airlie | 29d08b3 | 2010-09-27 16:17:17 +1000 | [diff] [blame] | 324 | radeonfb_destroy_pinned_object(rfb->obj); |
| 325 | rfb->obj = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 326 | } |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 327 | drm_fb_helper_fini(&rfbdev->helper); |
Daniel Vetter | 3620636 | 2012-12-10 20:42:17 +0100 | [diff] [blame] | 328 | drm_framebuffer_unregister_private(&rfb->base); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 329 | drm_framebuffer_cleanup(&rfb->base); |
Dave Airlie | 785b93e | 2009-08-28 15:46:53 +1000 | [diff] [blame] | 330 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 331 | return 0; |
| 332 | } |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 333 | |
| 334 | static struct drm_fb_helper_funcs radeon_fb_helper_funcs = { |
| 335 | .gamma_set = radeon_crtc_fb_gamma_set, |
| 336 | .gamma_get = radeon_crtc_fb_gamma_get, |
Daniel Vetter | cd5428a | 2013-01-21 23:42:49 +0100 | [diff] [blame] | 337 | .fb_probe = radeonfb_create, |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 338 | }; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 339 | |
| 340 | int radeon_fbdev_init(struct radeon_device *rdev) |
| 341 | { |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 342 | struct radeon_fbdev *rfbdev; |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 343 | int bpp_sel = 32; |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 344 | int ret; |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 345 | |
| 346 | /* select 8 bpp console on RN50 or 16MB cards */ |
| 347 | if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024)) |
| 348 | bpp_sel = 8; |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 349 | |
| 350 | rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL); |
| 351 | if (!rfbdev) |
| 352 | return -ENOMEM; |
| 353 | |
| 354 | rfbdev->rdev = rdev; |
| 355 | rdev->mode_info.rfbdev = rfbdev; |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 356 | rfbdev->helper.funcs = &radeon_fb_helper_funcs; |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 357 | |
Chris Wilson | 5a79395 | 2010-06-06 10:50:03 +0100 | [diff] [blame] | 358 | ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper, |
| 359 | rdev->num_crtc, |
| 360 | RADEONFB_CONN_LIMIT); |
| 361 | if (ret) { |
| 362 | kfree(rfbdev); |
| 363 | return ret; |
| 364 | } |
| 365 | |
Dave Airlie | 0b4c0f3 | 2010-03-30 05:34:15 +0000 | [diff] [blame] | 366 | drm_fb_helper_single_add_all_connectors(&rfbdev->helper); |
Daniel Vetter | 76a39db | 2013-01-20 23:12:54 +0100 | [diff] [blame] | 367 | |
| 368 | /* disable all the possible outputs/crtcs before entering KMS mode */ |
| 369 | drm_helper_disable_unused_functions(rdev->ddev); |
| 370 | |
Dave Airlie | 4abe352 | 2010-03-30 05:34:18 +0000 | [diff] [blame] | 371 | drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 372 | return 0; |
| 373 | } |
| 374 | |
| 375 | void radeon_fbdev_fini(struct radeon_device *rdev) |
| 376 | { |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 377 | if (!rdev->mode_info.rfbdev) |
| 378 | return; |
| 379 | |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 380 | radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev); |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 381 | kfree(rdev->mode_info.rfbdev); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 382 | rdev->mode_info.rfbdev = NULL; |
| 383 | } |
| 384 | |
| 385 | void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state) |
| 386 | { |
| 387 | fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state); |
| 388 | } |
| 389 | |
| 390 | int radeon_fbdev_total_size(struct radeon_device *rdev) |
| 391 | { |
| 392 | struct radeon_bo *robj; |
| 393 | int size = 0; |
| 394 | |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 395 | robj = gem_to_radeon_bo(rdev->mode_info.rfbdev->rfb.obj); |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 396 | size += radeon_bo_size(robj); |
| 397 | return size; |
| 398 | } |
| 399 | |
| 400 | bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj) |
| 401 | { |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 402 | if (robj == gem_to_radeon_bo(rdev->mode_info.rfbdev->rfb.obj)) |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 403 | return true; |
| 404 | return false; |
| 405 | } |