blob: 244b19bab2e72406648ef1b2eae8ef7965bfcf01 [file] [log] [blame]
Dave Airlie94bb5982006-12-19 17:49:08 +11001/* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
2/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
Dave Airlieb5e89ed2005-09-25 14:28:13 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
Jesse Barnes0a3e67a2008-09-30 12:14:26 -070030 * Michel D�zer <michel@daenzer.net>
Christian König14adc892013-01-21 13:58:46 +010031 *
32 * ------------------------ This file is DEPRECATED! -------------------------
Linus Torvalds1da177e2005-04-16 15:20:36 -070033 */
34
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/drmP.h>
36#include <drm/radeon_drm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070037#include "radeon_drv.h"
38
Jesse Barnes0a3e67a2008-09-30 12:14:26 -070039void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
Dave Airlie6921e332005-06-26 21:05:59 +100040{
Jesse Barnes0a3e67a2008-09-30 12:14:26 -070041 drm_radeon_private_t *dev_priv = dev->dev_private;
42
43 if (state)
44 dev_priv->irq_enable_reg |= mask;
45 else
46 dev_priv->irq_enable_reg &= ~mask;
47
Dave Airlie077ebed2008-12-22 17:11:02 +100048 if (dev->irq_enabled)
Dave Airliefae70432008-12-09 15:30:50 +100049 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -070050}
51
52static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
53{
54 drm_radeon_private_t *dev_priv = dev->dev_private;
55
56 if (state)
57 dev_priv->r500_disp_irq_reg |= mask;
58 else
59 dev_priv->r500_disp_irq_reg &= ~mask;
60
Dave Airlie077ebed2008-12-22 17:11:02 +100061 if (dev->irq_enabled)
Dave Airliefae70432008-12-09 15:30:50 +100062 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -070063}
64
65int radeon_enable_vblank(struct drm_device *dev, int crtc)
66{
67 drm_radeon_private_t *dev_priv = dev->dev_private;
68
Alex Deucher800b6992009-03-06 11:47:54 -050069 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
Jesse Barnes0a3e67a2008-09-30 12:14:26 -070070 switch (crtc) {
71 case 0:
72 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
73 break;
74 case 1:
75 r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
76 break;
77 default:
78 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
79 crtc);
Vasiliy Kulikov21e2eae2010-11-14 23:08:27 +030080 return -EINVAL;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -070081 }
82 } else {
83 switch (crtc) {
84 case 0:
85 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
86 break;
87 case 1:
88 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
89 break;
90 default:
91 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
92 crtc);
Vasiliy Kulikov21e2eae2010-11-14 23:08:27 +030093 return -EINVAL;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -070094 }
95 }
96
97 return 0;
98}
99
100void radeon_disable_vblank(struct drm_device *dev, int crtc)
101{
102 drm_radeon_private_t *dev_priv = dev->dev_private;
103
Alex Deucher800b6992009-03-06 11:47:54 -0500104 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700105 switch (crtc) {
106 case 0:
107 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
108 break;
109 case 1:
110 r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
111 break;
112 default:
113 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
114 crtc);
115 break;
116 }
117 } else {
118 switch (crtc) {
119 case 0:
120 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
121 break;
122 case 1:
123 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
124 break;
125 default:
126 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
127 crtc);
128 break;
129 }
130 }
131}
132
Andi Kleence580fa2011-10-13 16:08:47 -0700133static u32 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 *r500_disp_int)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700134{
135 u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
136 u32 irq_mask = RADEON_SW_INT_TEST;
137
138 *r500_disp_int = 0;
Alex Deucher800b6992009-03-06 11:47:54 -0500139 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700140 /* vbl interrupts in a different place */
141
142 if (irqs & R500_DISPLAY_INT_STATUS) {
143 /* if a display interrupt */
144 u32 disp_irq;
145
146 disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
147
148 *r500_disp_int = disp_irq;
149 if (disp_irq & R500_D1_VBLANK_INTERRUPT)
150 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
151 if (disp_irq & R500_D2_VBLANK_INTERRUPT)
152 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
153 }
154 irq_mask |= R500_DISPLAY_INT_STATUS;
155 } else
156 irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
157
158 irqs &= irq_mask;
159
Dave Airlie6921e332005-06-26 21:05:59 +1000160 if (irqs)
161 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700162
Dave Airlie6921e332005-06-26 21:05:59 +1000163 return irqs;
164}
165
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166/* Interrupts - Used for device synchronization and flushing in the
167 * following circumstances:
168 *
169 * - Exclusive FB access with hw idle:
170 * - Wait for GUI Idle (?) interrupt, then do normal flush.
171 *
172 * - Frame throttling, NV_fence:
173 * - Drop marker irq's into command stream ahead of time.
174 * - Wait on irq's with lock *not held*
175 * - Check each for termination condition
176 *
177 * - Internally in cp_getbuffer, etc:
178 * - as above, but wait with lock held???
179 *
180 * NOTE: These functions are misleadingly named -- the irq's aren't
181 * tied to dma at all, this is just a hangover from dri prehistory.
182 */
183
Daniel Vettere9f0d762013-12-11 11:34:42 +0100184irqreturn_t radeon_driver_irq_handler(int irq, void *arg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185{
Dave Airlie84b1fd12007-07-11 15:53:27 +1000186 struct drm_device *dev = (struct drm_device *) arg;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000187 drm_radeon_private_t *dev_priv =
188 (drm_radeon_private_t *) dev->dev_private;
189 u32 stat;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700190 u32 r500_disp_int;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191
Alex Deucherb15591f2009-09-17 14:25:12 -0400192 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
193 return IRQ_NONE;
194
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195 /* Only consider the bits we're interested in - others could be used
196 * outside the DRM
197 */
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700198 stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199 if (!stat)
200 return IRQ_NONE;
201
Dave Airlieddbee332007-07-11 12:16:01 +1000202 stat &= dev_priv->irq_enable_reg;
203
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204 /* SW interrupt */
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700205 if (stat & RADEON_SW_INT_TEST)
Daniel Vetter57ed0f72013-12-11 11:34:43 +0100206 wake_up(&dev_priv->swi_queue);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207
208 /* VBLANK interrupt */
Alex Deucher800b6992009-03-06 11:47:54 -0500209 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700210 if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
211 drm_handle_vblank(dev, 0);
212 if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
213 drm_handle_vblank(dev, 1);
214 } else {
215 if (stat & RADEON_CRTC_VBLANK_STAT)
216 drm_handle_vblank(dev, 0);
217 if (stat & RADEON_CRTC2_VBLANK_STAT)
218 drm_handle_vblank(dev, 1);
Dave Airlieaf6061a2008-05-07 12:15:39 +1000219 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220 return IRQ_HANDLED;
221}
222
Dave Airlie84b1fd12007-07-11 15:53:27 +1000223static int radeon_emit_irq(struct drm_device * dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224{
225 drm_radeon_private_t *dev_priv = dev->dev_private;
226 unsigned int ret;
227 RING_LOCALS;
228
229 atomic_inc(&dev_priv->swi_emitted);
230 ret = atomic_read(&dev_priv->swi_emitted);
231
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000232 BEGIN_RING(4);
233 OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
234 OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
235 ADVANCE_RING();
236 COMMIT_RING();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237
238 return ret;
239}
240
Dave Airlie84b1fd12007-07-11 15:53:27 +1000241static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242{
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000243 drm_radeon_private_t *dev_priv =
244 (drm_radeon_private_t *) dev->dev_private;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245 int ret = 0;
246
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000247 if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
248 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249
250 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
251
Daniel Vetterbfd83032013-12-11 11:34:41 +0100252 DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * HZ,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000253 RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254
255 return ret;
256}
257
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700258u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259{
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700260 drm_radeon_private_t *dev_priv = dev->dev_private;
261
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000262 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +1000263 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000264 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265 }
266
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700267 if (crtc < 0 || crtc > 1) {
268 DRM_ERROR("Invalid crtc %d\n", crtc);
Eric Anholt20caafa2007-08-25 19:22:43 +1000269 return -EINVAL;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700270 }
Dave Airlieddbee332007-07-11 12:16:01 +1000271
Alex Deucher800b6992009-03-06 11:47:54 -0500272 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700273 if (crtc == 0)
274 return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
275 else
276 return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
277 } else {
278 if (crtc == 0)
279 return RADEON_READ(RADEON_CRTC_CRNT_FRAME);
280 else
281 return RADEON_READ(RADEON_CRTC2_CRNT_FRAME);
282 }
Dave Airlieddbee332007-07-11 12:16:01 +1000283}
284
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285/* Needs the lock as it touches the ring.
286 */
Eric Anholtc153f452007-09-03 12:06:45 +1000287int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289 drm_radeon_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +1000290 drm_radeon_irq_emit_t *emit = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291 int result;
292
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000293 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +1000294 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000295 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296 }
297
Darren Jenkins65aa2f42009-12-30 12:16:35 +1100298 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
299 return -EINVAL;
300
301 LOCK_TEST_WITH_RETURN(dev, file_priv);
302
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000303 result = radeon_emit_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100305 if (copy_to_user(emit->irq_seq, &result, sizeof(int))) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000306 DRM_ERROR("copy_to_user\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000307 return -EFAULT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308 }
309
310 return 0;
311}
312
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313/* Doesn't need the hardware lock.
314 */
Eric Anholtc153f452007-09-03 12:06:45 +1000315int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700316{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317 drm_radeon_private_t *dev_priv = dev->dev_private;
Eric Anholtc153f452007-09-03 12:06:45 +1000318 drm_radeon_irq_wait_t *irqwait = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000320 if (!dev_priv) {
Márton Németh3e684ea2008-01-24 15:58:57 +1000321 DRM_ERROR("called with no initialization\n");
Eric Anholt20caafa2007-08-25 19:22:43 +1000322 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323 }
324
Alex Deucherb15591f2009-09-17 14:25:12 -0400325 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
326 return -EINVAL;
327
Eric Anholtc153f452007-09-03 12:06:45 +1000328 return radeon_wait_irq(dev, irqwait->irq_seq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329}
330
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331/* drm_dma.h hooks
332*/
Dave Airlie84b1fd12007-07-11 15:53:27 +1000333void radeon_driver_irq_preinstall(struct drm_device * dev)
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000334{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335 drm_radeon_private_t *dev_priv =
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000336 (drm_radeon_private_t *) dev->dev_private;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700337 u32 dummy;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338
Alex Deucherb15591f2009-09-17 14:25:12 -0400339 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
340 return;
341
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000342 /* Disable *all* interrupts */
Alex Deucher800b6992009-03-06 11:47:54 -0500343 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700344 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000345 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346
347 /* Clear bits if they're already high */
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700348 radeon_acknowledge_irqs(dev_priv, &dummy);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349}
350
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700351int radeon_driver_irq_postinstall(struct drm_device *dev)
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000352{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353 drm_radeon_private_t *dev_priv =
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000354 (drm_radeon_private_t *) dev->dev_private;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700355
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000356 atomic_set(&dev_priv->swi_emitted, 0);
Daniel Vetter57ed0f72013-12-11 11:34:43 +0100357 init_waitqueue_head(&dev_priv->swi_queue);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700359 dev->max_vblank_count = 0x001fffff;
360
Alex Deucherb15591f2009-09-17 14:25:12 -0400361 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
362 return 0;
363
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700364 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
365
366 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367}
368
Dave Airlie84b1fd12007-07-11 15:53:27 +1000369void radeon_driver_irq_uninstall(struct drm_device * dev)
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000370{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371 drm_radeon_private_t *dev_priv =
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000372 (drm_radeon_private_t *) dev->dev_private;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373 if (!dev_priv)
374 return;
375
Alex Deucherb15591f2009-09-17 14:25:12 -0400376 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
377 return;
378
Alex Deucher800b6992009-03-06 11:47:54 -0500379 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700380 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381 /* Disable *all* interrupts */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000382 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383}
Dave Airlieddbee332007-07-11 12:16:01 +1000384
385
Dave Airlie84b1fd12007-07-11 15:53:27 +1000386int radeon_vblank_crtc_get(struct drm_device *dev)
Dave Airlieddbee332007-07-11 12:16:01 +1000387{
388 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
Dave Airlieddbee332007-07-11 12:16:01 +1000389
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700390 return dev_priv->vblank_crtc;
Dave Airlieddbee332007-07-11 12:16:01 +1000391}
392
Dave Airlie84b1fd12007-07-11 15:53:27 +1000393int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
Dave Airlieddbee332007-07-11 12:16:01 +1000394{
395 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
396 if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
397 DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
Eric Anholt20caafa2007-08-25 19:22:43 +1000398 return -EINVAL;
Dave Airlieddbee332007-07-11 12:16:01 +1000399 }
400 dev_priv->vblank_crtc = (unsigned int)value;
Dave Airlieddbee332007-07-11 12:16:01 +1000401 return 0;
402}