blob: b5a17cb510a0b4ee71115973a7d73309e9061b03 [file] [log] [blame]
Takashi Iwai14752412015-04-14 12:15:47 +02001/*
2 * HD-audio controller helpers
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/export.h>
8#include <sound/core.h>
9#include <sound/hdaudio.h>
10#include <sound/hda_register.h>
11
12/* clear CORB read pointer properly */
13static void azx_clear_corbrp(struct hdac_bus *bus)
14{
15 int timeout;
16
17 for (timeout = 1000; timeout > 0; timeout--) {
18 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
19 break;
20 udelay(1);
21 }
22 if (timeout <= 0)
23 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
24 snd_hdac_chip_readw(bus, CORBRP));
25
26 snd_hdac_chip_writew(bus, CORBRP, 0);
27 for (timeout = 1000; timeout > 0; timeout--) {
28 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
29 break;
30 udelay(1);
31 }
32 if (timeout <= 0)
33 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
34 snd_hdac_chip_readw(bus, CORBRP));
35}
36
37/**
38 * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
39 * @bus: HD-audio core bus
40 */
41void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
42{
43 spin_lock_irq(&bus->reg_lock);
44 /* CORB set up */
45 bus->corb.addr = bus->rb.addr;
46 bus->corb.buf = (__le32 *)bus->rb.area;
47 snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
48 snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
49
50 /* set the corb size to 256 entries (ULI requires explicitly) */
51 snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
52 /* set the corb write pointer to 0 */
53 snd_hdac_chip_writew(bus, CORBWP, 0);
54
55 /* reset the corb hw read pointer */
56 snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
57 if (!bus->corbrp_self_clear)
58 azx_clear_corbrp(bus);
59
60 /* enable corb dma */
61 snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
62
63 /* RIRB set up */
64 bus->rirb.addr = bus->rb.addr + 2048;
65 bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
66 bus->rirb.wp = bus->rirb.rp = 0;
67 memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
68 snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
69 snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
70
71 /* set the rirb size to 256 entries (ULI requires explicitly) */
72 snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
73 /* reset the rirb hw write pointer */
74 snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
75 /* set N=1, get RIRB response interrupt for new entry */
76 snd_hdac_chip_writew(bus, RINTCNT, 1);
77 /* enable rirb dma and response irq */
78 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
79 spin_unlock_irq(&bus->reg_lock);
80}
81EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io);
82
83/**
84 * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers
85 * @bus: HD-audio core bus
86 */
87void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
88{
89 spin_lock_irq(&bus->reg_lock);
90 /* disable ringbuffer DMAs */
91 snd_hdac_chip_writeb(bus, RIRBCTL, 0);
92 snd_hdac_chip_writeb(bus, CORBCTL, 0);
93 /* disable unsolicited responses */
94 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
95 spin_unlock_irq(&bus->reg_lock);
96}
97EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io);
98
99static unsigned int azx_command_addr(u32 cmd)
100{
101 unsigned int addr = cmd >> 28;
102
103 if (snd_BUG_ON(addr >= HDA_MAX_CODECS))
104 addr = 0;
105 return addr;
106}
107
108/**
109 * snd_hdac_bus_send_cmd - send a command verb via CORB
110 * @bus: HD-audio core bus
111 * @val: encoded verb value to send
112 *
113 * Returns zero for success or a negative error code.
114 */
115int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
116{
117 unsigned int addr = azx_command_addr(val);
118 unsigned int wp, rp;
119
120 spin_lock_irq(&bus->reg_lock);
121
122 bus->last_cmd[azx_command_addr(val)] = val;
123
124 /* add command to corb */
125 wp = snd_hdac_chip_readw(bus, CORBWP);
126 if (wp == 0xffff) {
127 /* something wrong, controller likely turned to D3 */
128 spin_unlock_irq(&bus->reg_lock);
129 return -EIO;
130 }
131 wp++;
132 wp %= AZX_MAX_CORB_ENTRIES;
133
134 rp = snd_hdac_chip_readw(bus, CORBRP);
135 if (wp == rp) {
136 /* oops, it's full */
137 spin_unlock_irq(&bus->reg_lock);
138 return -EAGAIN;
139 }
140
141 bus->rirb.cmds[addr]++;
142 bus->corb.buf[wp] = cpu_to_le32(val);
143 snd_hdac_chip_writew(bus, CORBWP, wp);
144
145 spin_unlock_irq(&bus->reg_lock);
146
147 return 0;
148}
149EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd);
150
151#define AZX_RIRB_EX_UNSOL_EV (1<<4)
152
153/**
154 * snd_hdac_bus_update_rirb - retrieve RIRB entries
155 * @bus: HD-audio core bus
156 *
157 * Usually called from interrupt handler.
158 */
159void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
160{
161 unsigned int rp, wp;
162 unsigned int addr;
163 u32 res, res_ex;
164
165 wp = snd_hdac_chip_readw(bus, RIRBWP);
166 if (wp == 0xffff) {
167 /* something wrong, controller likely turned to D3 */
168 return;
169 }
170
171 if (wp == bus->rirb.wp)
172 return;
173 bus->rirb.wp = wp;
174
175 while (bus->rirb.rp != wp) {
176 bus->rirb.rp++;
177 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
178
179 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
180 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
181 res = le32_to_cpu(bus->rirb.buf[rp]);
182 addr = res_ex & 0xf;
183 if (addr >= HDA_MAX_CODECS) {
184 dev_err(bus->dev,
185 "spurious response %#x:%#x, rp = %d, wp = %d",
186 res, res_ex, bus->rirb.rp, wp);
187 snd_BUG();
188 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
189 snd_hdac_bus_queue_event(bus, res, res_ex);
190 else if (bus->rirb.cmds[addr]) {
191 bus->rirb.res[addr] = res;
192 bus->rirb.cmds[addr]--;
193 } else {
194 dev_err_ratelimited(bus->dev,
195 "spurious response %#x:%#x, last cmd=%#08x\n",
196 res, res_ex, bus->last_cmd[addr]);
197 }
198 }
199}
200EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb);
201
202/**
203 * snd_hdac_bus_get_response - receive a response via RIRB
204 * @bus: HD-audio core bus
205 * @addr: codec address
206 * @res: pointer to store the value, NULL when not needed
207 *
208 * Returns zero if a value is read, or a negative error code.
209 */
210int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
211 unsigned int *res)
212{
213 unsigned long timeout;
214 unsigned long loopcounter;
215
216 timeout = jiffies + msecs_to_jiffies(1000);
217
218 for (loopcounter = 0;; loopcounter++) {
219 spin_lock_irq(&bus->reg_lock);
220 if (!bus->rirb.cmds[addr]) {
221 if (res)
222 *res = bus->rirb.res[addr]; /* the last value */
223 spin_unlock_irq(&bus->reg_lock);
224 return 0;
225 }
226 spin_unlock_irq(&bus->reg_lock);
227 if (time_after(jiffies, timeout))
228 break;
229 if (loopcounter > 3000)
230 msleep(2); /* temporary workaround */
231 else {
232 udelay(10);
233 cond_resched();
234 }
235 }
236
237 return -EIO;
238}
239EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response);
240
241/*
242 * Lowlevel interface
243 */
244
245/**
246 * snd_hdac_bus_enter_link_reset - enter link reset
247 * @bus: HD-audio core bus
248 *
249 * Enter to the link reset state.
250 */
251void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
252{
253 unsigned long timeout;
254
255 /* reset controller */
256 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
257
258 timeout = jiffies + msecs_to_jiffies(100);
259 while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
260 time_before(jiffies, timeout))
261 usleep_range(500, 1000);
262}
263EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset);
264
265/**
266 * snd_hdac_bus_exit_link_reset - exit link reset
267 * @bus: HD-audio core bus
268 *
269 * Exit from the link reset state.
270 */
271void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
272{
273 unsigned long timeout;
274
275 snd_hdac_chip_updateb(bus, GCTL, 0, AZX_GCTL_RESET);
276
277 timeout = jiffies + msecs_to_jiffies(100);
278 while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
279 usleep_range(500, 1000);
280}
281EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset);
282
283/* reset codec link */
284static int azx_reset(struct hdac_bus *bus, bool full_reset)
285{
286 if (!full_reset)
287 goto skip_reset;
288
289 /* clear STATESTS */
290 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
291
292 /* reset controller */
293 snd_hdac_bus_enter_link_reset(bus);
294
295 /* delay for >= 100us for codec PLL to settle per spec
296 * Rev 0.9 section 5.5.1
297 */
298 usleep_range(500, 1000);
299
300 /* Bring controller out of reset */
301 snd_hdac_bus_exit_link_reset(bus);
302
303 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
304 usleep_range(1000, 1200);
305
306 skip_reset:
307 /* check to see if controller is ready */
308 if (!snd_hdac_chip_readb(bus, GCTL)) {
309 dev_dbg(bus->dev, "azx_reset: controller not ready!\n");
310 return -EBUSY;
311 }
312
313 /* Accept unsolicited responses */
314 snd_hdac_chip_updatel(bus, GCTL, 0, AZX_GCTL_UNSOL);
315
316 /* detect codecs */
317 if (!bus->codec_mask) {
318 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
319 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
320 }
321
322 return 0;
323}
324
325/* enable interrupts */
326static void azx_int_enable(struct hdac_bus *bus)
327{
328 /* enable controller CIE and GIE */
329 snd_hdac_chip_updatel(bus, INTCTL, 0, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
330}
331
332/* disable interrupts */
333static void azx_int_disable(struct hdac_bus *bus)
334{
335 struct hdac_stream *azx_dev;
336
337 /* disable interrupts in stream descriptor */
338 list_for_each_entry(azx_dev, &bus->stream_list, list)
339 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0);
340
341 /* disable SIE for all streams */
342 snd_hdac_chip_writeb(bus, INTCTL, 0);
343
344 /* disable controller CIE and GIE */
345 snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0);
346}
347
348/* clear interrupts */
349static void azx_int_clear(struct hdac_bus *bus)
350{
351 struct hdac_stream *azx_dev;
352
353 /* clear stream status */
354 list_for_each_entry(azx_dev, &bus->stream_list, list)
355 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
356
357 /* clear STATESTS */
358 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
359
360 /* clear rirb status */
361 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
362
363 /* clear int status */
364 snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
365}
366
367/**
368 * snd_hdac_bus_init_chip - reset and start the controller registers
369 * @bus: HD-audio core bus
370 * @full_reset: Do full reset
371 */
372bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
373{
374 if (bus->chip_init)
375 return false;
376
377 /* reset controller */
378 azx_reset(bus, full_reset);
379
380 /* initialize interrupts */
381 azx_int_clear(bus);
382 azx_int_enable(bus);
383
384 /* initialize the codec command I/O */
385 snd_hdac_bus_init_cmd_io(bus);
386
387 /* program the position buffer */
388 if (bus->use_posbuf && bus->posbuf.addr) {
389 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
390 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
391 }
392
393 bus->chip_init = true;
394 return true;
395}
396EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip);
397
398/**
399 * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os
400 * @bus: HD-audio core bus
401 */
402void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
403{
404 if (!bus->chip_init)
405 return;
406
407 /* disable interrupts */
408 azx_int_disable(bus);
409 azx_int_clear(bus);
410
411 /* disable CORB/RIRB */
412 snd_hdac_bus_stop_cmd_io(bus);
413
414 /* disable position buffer */
415 if (bus->posbuf.addr) {
416 snd_hdac_chip_writel(bus, DPLBASE, 0);
417 snd_hdac_chip_writel(bus, DPUBASE, 0);
418 }
419
420 bus->chip_init = false;
421}
422EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip);
423
424/**
425 * snd_hdac_bus_handle_stream_irq - interrupt handler for streams
426 * @bus: HD-audio core bus
427 * @status: INTSTS register value
428 * @ask: callback to be called for woken streams
429 */
430void snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
431 void (*ack)(struct hdac_bus *,
432 struct hdac_stream *))
433{
434 struct hdac_stream *azx_dev;
435 u8 sd_status;
436
437 list_for_each_entry(azx_dev, &bus->stream_list, list) {
438 if (status & azx_dev->sd_int_sta_mask) {
439 sd_status = snd_hdac_stream_readb(azx_dev, SD_STS);
440 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
441 if (!azx_dev->substream || !azx_dev->running ||
442 !(sd_status & SD_INT_COMPLETE))
443 continue;
444 if (ack)
445 ack(bus, azx_dev);
446 }
447 }
448}
449EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq);
Jeeja KP304dad32015-04-12 18:06:13 +0530450
451/**
452 * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers
453 * @bus: HD-audio core bus
454 *
455 * Call this after assigning the all streams.
456 * Returns zero for success, or a negative error code.
457 */
458int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
459{
460 struct hdac_stream *s;
461 int num_streams = 0;
462 int err;
463
464 list_for_each_entry(s, &bus->stream_list, list) {
465 /* allocate memory for the BDL for each stream */
466 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
467 BDL_SIZE, &s->bdl);
468 num_streams++;
469 if (err < 0)
470 return -ENOMEM;
471 }
472
473 if (WARN_ON(!num_streams))
474 return -EINVAL;
475 /* allocate memory for the position buffer */
476 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
477 num_streams * 8, &bus->posbuf);
478 if (err < 0)
479 return -ENOMEM;
480 list_for_each_entry(s, &bus->stream_list, list)
481 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
482
483 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
484 return bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
485 PAGE_SIZE, &bus->rb);
486}
487EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages);
488
489/**
490 * snd_hdac_bus_free_stream_pages - release BDL and other buffers
491 * @bus: HD-audio core bus
492 */
493void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
494{
495 struct hdac_stream *s;
496
497 list_for_each_entry(s, &bus->stream_list, list) {
498 if (s->bdl.area)
499 bus->io_ops->dma_free_pages(bus, &s->bdl);
500 }
501
502 if (bus->rb.area)
503 bus->io_ops->dma_free_pages(bus, &bus->rb);
504 if (bus->posbuf.area)
505 bus->io_ops->dma_free_pages(bus, &bus->posbuf);
506}
507EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages);