R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * Based on "omap4.dtsi" |
| 8 | */ |
| 9 | |
| 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 11 | #include <dt-bindings/pinctrl/dra.h> |
| 12 | |
| 13 | #include "skeleton.dtsi" |
| 14 | |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 15 | #define MAX_SOURCES 400 |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 16 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 17 | / { |
Lokesh Vutla | dae320e | 2016-02-24 15:41:04 +0530 | [diff] [blame] | 18 | #address-cells = <2>; |
| 19 | #size-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 20 | |
| 21 | compatible = "ti,dra7xx"; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 22 | interrupt-parent = <&crossbar_mpu>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 23 | |
| 24 | aliases { |
Nishanth Menon | 20b8094 | 2013-10-16 15:21:03 -0500 | [diff] [blame] | 25 | i2c0 = &i2c1; |
| 26 | i2c1 = &i2c2; |
| 27 | i2c2 = &i2c3; |
| 28 | i2c3 = &i2c4; |
| 29 | i2c4 = &i2c5; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 30 | serial0 = &uart1; |
| 31 | serial1 = &uart2; |
| 32 | serial2 = &uart3; |
| 33 | serial3 = &uart4; |
| 34 | serial4 = &uart5; |
| 35 | serial5 = &uart6; |
Nishanth Menon | 065bd7f | 2014-10-21 11:18:15 -0500 | [diff] [blame] | 36 | serial6 = &uart7; |
| 37 | serial7 = &uart8; |
| 38 | serial8 = &uart9; |
| 39 | serial9 = &uart10; |
Mugunthan V N | ef9c5b6 | 2014-10-21 15:31:00 +0530 | [diff] [blame] | 40 | ethernet0 = &cpsw_emac0; |
| 41 | ethernet1 = &cpsw_emac1; |
Roger Quadros | 9ec49b9 | 2014-08-15 16:08:36 +0300 | [diff] [blame] | 42 | d_can0 = &dcan1; |
| 43 | d_can1 = &dcan2; |
Mugunthan V N | 480b2b3 | 2015-11-19 12:31:01 +0530 | [diff] [blame] | 44 | spi0 = &qspi; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 45 | }; |
| 46 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 47 | timer { |
| 48 | compatible = "arm,armv7-timer"; |
| 49 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 50 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 51 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
| 52 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 53 | interrupt-parent = <&gic>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 54 | }; |
| 55 | |
| 56 | gic: interrupt-controller@48211000 { |
| 57 | compatible = "arm,cortex-a15-gic"; |
| 58 | interrupt-controller; |
| 59 | #interrupt-cells = <3>; |
Lokesh Vutla | dae320e | 2016-02-24 15:41:04 +0530 | [diff] [blame] | 60 | reg = <0x0 0x48211000 0x0 0x1000>, |
| 61 | <0x0 0x48212000 0x0 0x1000>, |
| 62 | <0x0 0x48214000 0x0 0x2000>, |
| 63 | <0x0 0x48216000 0x0 0x2000>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 64 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 65 | interrupt-parent = <&gic>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 66 | }; |
| 67 | |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 68 | wakeupgen: interrupt-controller@48281000 { |
| 69 | compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; |
| 70 | interrupt-controller; |
| 71 | #interrupt-cells = <3>; |
Lokesh Vutla | dae320e | 2016-02-24 15:41:04 +0530 | [diff] [blame] | 72 | reg = <0x0 0x48281000 0x0 0x1000>; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 73 | interrupt-parent = <&gic>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 74 | }; |
| 75 | |
| 76 | /* |
Geert Uytterhoeven | 5c5be9d | 2014-03-28 11:11:37 +0100 | [diff] [blame] | 77 | * The soc node represents the soc top level view. It is used for IPs |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 78 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 79 | */ |
| 80 | soc { |
| 81 | compatible = "ti,omap-infra"; |
| 82 | mpu { |
| 83 | compatible = "ti,omap5-mpu"; |
| 84 | ti,hwmods = "mpu"; |
| 85 | }; |
| 86 | }; |
| 87 | |
| 88 | /* |
| 89 | * XXX: Use a flat representation of the SOC interconnect. |
| 90 | * The real OMAP interconnect network is quite complex. |
Geert Uytterhoeven | b7ab524 | 2014-03-28 11:11:39 +0100 | [diff] [blame] | 91 | * Since it will not bring real advantage to represent that in DT for |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 92 | * the moment, just use a fake OCP bus entry to represent the whole bus |
| 93 | * hierarchy. |
| 94 | */ |
| 95 | ocp { |
Rajendra Nayak | fba387a | 2014-04-10 11:34:32 -0500 | [diff] [blame] | 96 | compatible = "ti,dra7-l3-noc", "simple-bus"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 97 | #address-cells = <1>; |
| 98 | #size-cells = <1>; |
Lokesh Vutla | dae320e | 2016-02-24 15:41:04 +0530 | [diff] [blame] | 99 | ranges = <0x0 0x0 0x0 0xc0000000>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 100 | ti,hwmods = "l3_main_1", "l3_main_2"; |
Lokesh Vutla | dae320e | 2016-02-24 15:41:04 +0530 | [diff] [blame] | 101 | reg = <0x0 0x44000000 0x0 0x1000000>, |
| 102 | <0x0 0x45000000 0x0 0x1000>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 103 | interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 104 | <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 105 | |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 106 | l4_cfg: l4@4a000000 { |
| 107 | compatible = "ti,dra7-l4-cfg", "simple-bus"; |
| 108 | #address-cells = <1>; |
| 109 | #size-cells = <1>; |
| 110 | ranges = <0 0x4a000000 0x22c000>; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 111 | |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 112 | scm: scm@2000 { |
| 113 | compatible = "ti,dra7-scm-core", "simple-bus"; |
| 114 | reg = <0x2000 0x2000>; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 115 | #address-cells = <1>; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 116 | #size-cells = <1>; |
| 117 | ranges = <0 0x2000 0x2000>; |
| 118 | |
| 119 | scm_conf: scm_conf@0 { |
Kishon Vijay Abraham I | cd45567 | 2015-07-27 17:46:41 +0530 | [diff] [blame] | 120 | compatible = "syscon", "simple-bus"; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 121 | reg = <0x0 0x1400>; |
| 122 | #address-cells = <1>; |
| 123 | #size-cells = <1>; |
Kishon Vijay Abraham I | 9a5e3f2 | 2015-09-04 17:38:24 +0530 | [diff] [blame] | 124 | ranges = <0 0x0 0x1400>; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 125 | |
| 126 | pbias_regulator: pbias_regulator { |
Kishon Vijay Abraham I | 737f146 | 2015-09-04 17:30:25 +0530 | [diff] [blame] | 127 | compatible = "ti,pbias-dra7", "ti,pbias-omap"; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 128 | reg = <0xe00 0x4>; |
| 129 | syscon = <&scm_conf>; |
| 130 | pbias_mmc_reg: pbias_mmc_omap5 { |
| 131 | regulator-name = "pbias_mmc_omap5"; |
| 132 | regulator-min-microvolt = <1800000>; |
| 133 | regulator-max-microvolt = <3000000>; |
| 134 | }; |
| 135 | }; |
Tomi Valkeinen | 2d5a3c8 | 2015-02-23 12:53:56 +0200 | [diff] [blame] | 136 | |
| 137 | scm_conf_clocks: clocks { |
| 138 | #address-cells = <1>; |
| 139 | #size-cells = <0>; |
| 140 | }; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 141 | }; |
| 142 | |
| 143 | dra7_pmx_core: pinmux@1400 { |
| 144 | compatible = "ti,dra7-padconf", |
| 145 | "pinctrl-single"; |
Roger Quadros | 1c5cb6f | 2015-07-27 13:27:29 +0300 | [diff] [blame] | 146 | reg = <0x1400 0x0468>; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 147 | #address-cells = <1>; |
| 148 | #size-cells = <0>; |
| 149 | #interrupt-cells = <1>; |
| 150 | interrupt-controller; |
| 151 | pinctrl-single,register-width = <32>; |
| 152 | pinctrl-single,function-mask = <0x3fffffff>; |
| 153 | }; |
Roger Quadros | 33cb3a1 | 2015-08-04 12:10:14 +0300 | [diff] [blame] | 154 | |
| 155 | scm_conf1: scm_conf@1c04 { |
| 156 | compatible = "syscon"; |
| 157 | reg = <0x1c04 0x0020>; |
| 158 | }; |
Kishon Vijay Abraham I | 43acf16 | 2015-12-21 14:43:18 +0530 | [diff] [blame] | 159 | |
| 160 | scm_conf_pcie: scm_conf@1c24 { |
| 161 | compatible = "syscon"; |
| 162 | reg = <0x1c24 0x0024>; |
| 163 | }; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 164 | }; |
| 165 | |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 166 | cm_core_aon: cm_core_aon@5000 { |
| 167 | compatible = "ti,dra7-cm-core-aon"; |
| 168 | reg = <0x5000 0x2000>; |
| 169 | |
| 170 | cm_core_aon_clocks: clocks { |
| 171 | #address-cells = <1>; |
| 172 | #size-cells = <0>; |
| 173 | }; |
| 174 | |
| 175 | cm_core_aon_clockdomains: clockdomains { |
| 176 | }; |
| 177 | }; |
| 178 | |
| 179 | cm_core: cm_core@8000 { |
| 180 | compatible = "ti,dra7-cm-core"; |
| 181 | reg = <0x8000 0x3000>; |
| 182 | |
| 183 | cm_core_clocks: clocks { |
| 184 | #address-cells = <1>; |
| 185 | #size-cells = <0>; |
| 186 | }; |
| 187 | |
| 188 | cm_core_clockdomains: clockdomains { |
| 189 | }; |
| 190 | }; |
| 191 | }; |
| 192 | |
| 193 | l4_wkup: l4@4ae00000 { |
| 194 | compatible = "ti,dra7-l4-wkup", "simple-bus"; |
| 195 | #address-cells = <1>; |
| 196 | #size-cells = <1>; |
| 197 | ranges = <0 0x4ae00000 0x3f000>; |
| 198 | |
| 199 | counter32k: counter@4000 { |
| 200 | compatible = "ti,omap-counter32k"; |
| 201 | reg = <0x4000 0x40>; |
| 202 | ti,hwmods = "counter_32k"; |
| 203 | }; |
| 204 | |
| 205 | prm: prm@6000 { |
| 206 | compatible = "ti,dra7-prm"; |
| 207 | reg = <0x6000 0x3000>; |
| 208 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| 209 | |
| 210 | prm_clocks: clocks { |
| 211 | #address-cells = <1>; |
| 212 | #size-cells = <0>; |
| 213 | }; |
| 214 | |
| 215 | prm_clockdomains: clockdomains { |
| 216 | }; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 217 | }; |
| 218 | }; |
| 219 | |
Kishon Vijay Abraham I | 18dcd79 | 2014-07-14 16:12:23 +0530 | [diff] [blame] | 220 | axi@0 { |
| 221 | compatible = "simple-bus"; |
| 222 | #size-cells = <1>; |
| 223 | #address-cells = <1>; |
| 224 | ranges = <0x51000000 0x51000000 0x3000 |
| 225 | 0x0 0x20000000 0x10000000>; |
Kishon Vijay Abraham I | 73c8f0c | 2015-07-28 19:09:10 +0530 | [diff] [blame] | 226 | pcie1: pcie@51000000 { |
Kishon Vijay Abraham I | 18dcd79 | 2014-07-14 16:12:23 +0530 | [diff] [blame] | 227 | compatible = "ti,dra7-pcie"; |
| 228 | reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; |
| 229 | reg-names = "rc_dbics", "ti_conf", "config"; |
| 230 | interrupts = <0 232 0x4>, <0 233 0x4>; |
| 231 | #address-cells = <3>; |
| 232 | #size-cells = <2>; |
| 233 | device_type = "pci"; |
| 234 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 |
| 235 | 0x82000000 0 0x20013000 0x13000 0 0xffed000>; |
| 236 | #interrupt-cells = <1>; |
| 237 | num-lanes = <1>; |
| 238 | ti,hwmods = "pcie1"; |
| 239 | phys = <&pcie1_phy>; |
| 240 | phy-names = "pcie-phy0"; |
| 241 | interrupt-map-mask = <0 0 0 7>; |
| 242 | interrupt-map = <0 0 0 1 &pcie1_intc 1>, |
| 243 | <0 0 0 2 &pcie1_intc 2>, |
| 244 | <0 0 0 3 &pcie1_intc 3>, |
| 245 | <0 0 0 4 &pcie1_intc 4>; |
| 246 | pcie1_intc: interrupt-controller { |
| 247 | interrupt-controller; |
| 248 | #address-cells = <0>; |
| 249 | #interrupt-cells = <1>; |
| 250 | }; |
| 251 | }; |
| 252 | }; |
| 253 | |
| 254 | axi@1 { |
| 255 | compatible = "simple-bus"; |
| 256 | #size-cells = <1>; |
| 257 | #address-cells = <1>; |
| 258 | ranges = <0x51800000 0x51800000 0x3000 |
| 259 | 0x0 0x30000000 0x10000000>; |
| 260 | status = "disabled"; |
| 261 | pcie@51000000 { |
| 262 | compatible = "ti,dra7-pcie"; |
| 263 | reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; |
| 264 | reg-names = "rc_dbics", "ti_conf", "config"; |
| 265 | interrupts = <0 355 0x4>, <0 356 0x4>; |
| 266 | #address-cells = <3>; |
| 267 | #size-cells = <2>; |
| 268 | device_type = "pci"; |
| 269 | ranges = <0x81000000 0 0 0x03000 0 0x00010000 |
| 270 | 0x82000000 0 0x30013000 0x13000 0 0xffed000>; |
| 271 | #interrupt-cells = <1>; |
| 272 | num-lanes = <1>; |
| 273 | ti,hwmods = "pcie2"; |
| 274 | phys = <&pcie2_phy>; |
| 275 | phy-names = "pcie-phy0"; |
| 276 | interrupt-map-mask = <0 0 0 7>; |
| 277 | interrupt-map = <0 0 0 1 &pcie2_intc 1>, |
| 278 | <0 0 0 2 &pcie2_intc 2>, |
| 279 | <0 0 0 3 &pcie2_intc 3>, |
| 280 | <0 0 0 4 &pcie2_intc 4>; |
| 281 | pcie2_intc: interrupt-controller { |
| 282 | interrupt-controller; |
| 283 | #address-cells = <0>; |
| 284 | #interrupt-cells = <1>; |
| 285 | }; |
| 286 | }; |
| 287 | }; |
| 288 | |
Keerthy | f7397ed | 2015-03-23 14:39:38 -0500 | [diff] [blame] | 289 | bandgap: bandgap@4a0021e0 { |
| 290 | reg = <0x4a0021e0 0xc |
| 291 | 0x4a00232c 0xc |
| 292 | 0x4a002380 0x2c |
| 293 | 0x4a0023C0 0x3c |
| 294 | 0x4a002564 0x8 |
| 295 | 0x4a002574 0x50>; |
| 296 | compatible = "ti,dra752-bandgap"; |
| 297 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
| 298 | #thermal-sensor-cells = <1>; |
| 299 | }; |
| 300 | |
Suman Anna | 99639ac | 2015-10-02 18:23:22 -0500 | [diff] [blame] | 301 | dsp1_system: dsp_system@40d00000 { |
| 302 | compatible = "syscon"; |
| 303 | reg = <0x40d00000 0x100>; |
| 304 | }; |
| 305 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 306 | sdma: dma-controller@4a056000 { |
| 307 | compatible = "ti,omap4430-sdma"; |
| 308 | reg = <0x4a056000 0x1000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 309 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
| 310 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| 311 | <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 312 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 313 | #dma-cells = <1>; |
Peter Ujfalusi | 08d9b32 | 2015-02-20 15:42:06 +0200 | [diff] [blame] | 314 | dma-channels = <32>; |
| 315 | dma-requests = <127>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 316 | }; |
| 317 | |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 318 | sdma_xbar: dma-router@4a002b78 { |
| 319 | compatible = "ti,dra7-dma-crossbar"; |
| 320 | reg = <0x4a002b78 0xfc>; |
| 321 | #dma-cells = <1>; |
| 322 | dma-requests = <205>; |
| 323 | ti,dma-safe-map = <0>; |
| 324 | dma-masters = <&sdma>; |
| 325 | }; |
| 326 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 327 | gpio1: gpio@4ae10000 { |
| 328 | compatible = "ti,omap4-gpio"; |
| 329 | reg = <0x4ae10000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 330 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 331 | ti,hwmods = "gpio1"; |
| 332 | gpio-controller; |
| 333 | #gpio-cells = <2>; |
| 334 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 335 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 336 | }; |
| 337 | |
| 338 | gpio2: gpio@48055000 { |
| 339 | compatible = "ti,omap4-gpio"; |
| 340 | reg = <0x48055000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 341 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 342 | ti,hwmods = "gpio2"; |
| 343 | gpio-controller; |
| 344 | #gpio-cells = <2>; |
| 345 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 346 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 347 | }; |
| 348 | |
| 349 | gpio3: gpio@48057000 { |
| 350 | compatible = "ti,omap4-gpio"; |
| 351 | reg = <0x48057000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 352 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 353 | ti,hwmods = "gpio3"; |
| 354 | gpio-controller; |
| 355 | #gpio-cells = <2>; |
| 356 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 357 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 358 | }; |
| 359 | |
| 360 | gpio4: gpio@48059000 { |
| 361 | compatible = "ti,omap4-gpio"; |
| 362 | reg = <0x48059000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 363 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 364 | ti,hwmods = "gpio4"; |
| 365 | gpio-controller; |
| 366 | #gpio-cells = <2>; |
| 367 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 368 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 369 | }; |
| 370 | |
| 371 | gpio5: gpio@4805b000 { |
| 372 | compatible = "ti,omap4-gpio"; |
| 373 | reg = <0x4805b000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 374 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 375 | ti,hwmods = "gpio5"; |
| 376 | gpio-controller; |
| 377 | #gpio-cells = <2>; |
| 378 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 379 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 380 | }; |
| 381 | |
| 382 | gpio6: gpio@4805d000 { |
| 383 | compatible = "ti,omap4-gpio"; |
| 384 | reg = <0x4805d000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 385 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 386 | ti,hwmods = "gpio6"; |
| 387 | gpio-controller; |
| 388 | #gpio-cells = <2>; |
| 389 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 390 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 391 | }; |
| 392 | |
| 393 | gpio7: gpio@48051000 { |
| 394 | compatible = "ti,omap4-gpio"; |
| 395 | reg = <0x48051000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 396 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 397 | ti,hwmods = "gpio7"; |
| 398 | gpio-controller; |
| 399 | #gpio-cells = <2>; |
| 400 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 401 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 402 | }; |
| 403 | |
| 404 | gpio8: gpio@48053000 { |
| 405 | compatible = "ti,omap4-gpio"; |
| 406 | reg = <0x48053000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 407 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 408 | ti,hwmods = "gpio8"; |
| 409 | gpio-controller; |
| 410 | #gpio-cells = <2>; |
| 411 | interrupt-controller; |
Nishanth Menon | e49d519 | 2014-08-25 16:15:34 -0700 | [diff] [blame] | 412 | #interrupt-cells = <2>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 413 | }; |
| 414 | |
| 415 | uart1: serial@4806a000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 416 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 417 | reg = <0x4806a000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 418 | interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 419 | ti,hwmods = "uart1"; |
| 420 | clock-frequency = <48000000>; |
| 421 | status = "disabled"; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 422 | dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 423 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 424 | }; |
| 425 | |
| 426 | uart2: serial@4806c000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 427 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 428 | reg = <0x4806c000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 429 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 430 | ti,hwmods = "uart2"; |
| 431 | clock-frequency = <48000000>; |
| 432 | status = "disabled"; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 433 | dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 434 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 435 | }; |
| 436 | |
| 437 | uart3: serial@48020000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 438 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 439 | reg = <0x48020000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 440 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 441 | ti,hwmods = "uart3"; |
| 442 | clock-frequency = <48000000>; |
| 443 | status = "disabled"; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 444 | dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 445 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 446 | }; |
| 447 | |
| 448 | uart4: serial@4806e000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 449 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 450 | reg = <0x4806e000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 451 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 452 | ti,hwmods = "uart4"; |
| 453 | clock-frequency = <48000000>; |
| 454 | status = "disabled"; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 455 | dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 456 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 457 | }; |
| 458 | |
| 459 | uart5: serial@48066000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 460 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 461 | reg = <0x48066000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 462 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 463 | ti,hwmods = "uart5"; |
| 464 | clock-frequency = <48000000>; |
| 465 | status = "disabled"; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 466 | dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 467 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 468 | }; |
| 469 | |
| 470 | uart6: serial@48068000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 471 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 472 | reg = <0x48068000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 473 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 474 | ti,hwmods = "uart6"; |
| 475 | clock-frequency = <48000000>; |
| 476 | status = "disabled"; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 477 | dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; |
Sebastian Andrzej Siewior | f0199a2 | 2014-09-29 20:06:47 +0200 | [diff] [blame] | 478 | dma-names = "tx", "rx"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 479 | }; |
| 480 | |
| 481 | uart7: serial@48420000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 482 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 483 | reg = <0x48420000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 484 | interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 485 | ti,hwmods = "uart7"; |
| 486 | clock-frequency = <48000000>; |
| 487 | status = "disabled"; |
| 488 | }; |
| 489 | |
| 490 | uart8: serial@48422000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 491 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 492 | reg = <0x48422000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 493 | interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 494 | ti,hwmods = "uart8"; |
| 495 | clock-frequency = <48000000>; |
| 496 | status = "disabled"; |
| 497 | }; |
| 498 | |
| 499 | uart9: serial@48424000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 500 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 501 | reg = <0x48424000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 502 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 503 | ti,hwmods = "uart9"; |
| 504 | clock-frequency = <48000000>; |
| 505 | status = "disabled"; |
| 506 | }; |
| 507 | |
| 508 | uart10: serial@4ae2b000 { |
Sekhar Nori | 2a0e5ef | 2015-07-30 18:27:47 +0530 | [diff] [blame] | 509 | compatible = "ti,dra742-uart", "ti,omap4-uart"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 510 | reg = <0x4ae2b000 0x100>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 511 | interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 512 | ti,hwmods = "uart10"; |
| 513 | clock-frequency = <48000000>; |
| 514 | status = "disabled"; |
| 515 | }; |
| 516 | |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 517 | mailbox1: mailbox@4a0f4000 { |
| 518 | compatible = "ti,omap4-mailbox"; |
| 519 | reg = <0x4a0f4000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 520 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, |
| 521 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 522 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 523 | ti,hwmods = "mailbox1"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 524 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 525 | ti,mbox-num-users = <3>; |
| 526 | ti,mbox-num-fifos = <8>; |
| 527 | status = "disabled"; |
| 528 | }; |
| 529 | |
| 530 | mailbox2: mailbox@4883a000 { |
| 531 | compatible = "ti,omap4-mailbox"; |
| 532 | reg = <0x4883a000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 533 | interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, |
| 534 | <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, |
| 535 | <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, |
| 536 | <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 537 | ti,hwmods = "mailbox2"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 538 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 539 | ti,mbox-num-users = <4>; |
| 540 | ti,mbox-num-fifos = <12>; |
| 541 | status = "disabled"; |
| 542 | }; |
| 543 | |
| 544 | mailbox3: mailbox@4883c000 { |
| 545 | compatible = "ti,omap4-mailbox"; |
| 546 | reg = <0x4883c000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 547 | interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, |
| 548 | <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, |
| 549 | <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, |
| 550 | <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 551 | ti,hwmods = "mailbox3"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 552 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 553 | ti,mbox-num-users = <4>; |
| 554 | ti,mbox-num-fifos = <12>; |
| 555 | status = "disabled"; |
| 556 | }; |
| 557 | |
| 558 | mailbox4: mailbox@4883e000 { |
| 559 | compatible = "ti,omap4-mailbox"; |
| 560 | reg = <0x4883e000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 561 | interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, |
| 562 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, |
| 563 | <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, |
| 564 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 565 | ti,hwmods = "mailbox4"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 566 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 567 | ti,mbox-num-users = <4>; |
| 568 | ti,mbox-num-fifos = <12>; |
| 569 | status = "disabled"; |
| 570 | }; |
| 571 | |
| 572 | mailbox5: mailbox@48840000 { |
| 573 | compatible = "ti,omap4-mailbox"; |
| 574 | reg = <0x48840000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 575 | interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, |
| 576 | <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, |
| 577 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, |
| 578 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 579 | ti,hwmods = "mailbox5"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 580 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 581 | ti,mbox-num-users = <4>; |
| 582 | ti,mbox-num-fifos = <12>; |
| 583 | status = "disabled"; |
| 584 | }; |
| 585 | |
| 586 | mailbox6: mailbox@48842000 { |
| 587 | compatible = "ti,omap4-mailbox"; |
| 588 | reg = <0x48842000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 589 | interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
| 590 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, |
| 591 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, |
| 592 | <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 593 | ti,hwmods = "mailbox6"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 594 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 595 | ti,mbox-num-users = <4>; |
| 596 | ti,mbox-num-fifos = <12>; |
| 597 | status = "disabled"; |
| 598 | }; |
| 599 | |
| 600 | mailbox7: mailbox@48844000 { |
| 601 | compatible = "ti,omap4-mailbox"; |
| 602 | reg = <0x48844000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 603 | interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, |
| 604 | <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, |
| 605 | <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, |
| 606 | <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 607 | ti,hwmods = "mailbox7"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 608 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 609 | ti,mbox-num-users = <4>; |
| 610 | ti,mbox-num-fifos = <12>; |
| 611 | status = "disabled"; |
| 612 | }; |
| 613 | |
| 614 | mailbox8: mailbox@48846000 { |
| 615 | compatible = "ti,omap4-mailbox"; |
| 616 | reg = <0x48846000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 617 | interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, |
| 618 | <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, |
| 619 | <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, |
| 620 | <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 621 | ti,hwmods = "mailbox8"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 622 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 623 | ti,mbox-num-users = <4>; |
| 624 | ti,mbox-num-fifos = <12>; |
| 625 | status = "disabled"; |
| 626 | }; |
| 627 | |
| 628 | mailbox9: mailbox@4885e000 { |
| 629 | compatible = "ti,omap4-mailbox"; |
| 630 | reg = <0x4885e000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 631 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, |
| 632 | <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, |
| 633 | <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, |
| 634 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 635 | ti,hwmods = "mailbox9"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 636 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 637 | ti,mbox-num-users = <4>; |
| 638 | ti,mbox-num-fifos = <12>; |
| 639 | status = "disabled"; |
| 640 | }; |
| 641 | |
| 642 | mailbox10: mailbox@48860000 { |
| 643 | compatible = "ti,omap4-mailbox"; |
| 644 | reg = <0x48860000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 645 | interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, |
| 646 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, |
| 647 | <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, |
| 648 | <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 649 | ti,hwmods = "mailbox10"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 650 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 651 | ti,mbox-num-users = <4>; |
| 652 | ti,mbox-num-fifos = <12>; |
| 653 | status = "disabled"; |
| 654 | }; |
| 655 | |
| 656 | mailbox11: mailbox@48862000 { |
| 657 | compatible = "ti,omap4-mailbox"; |
| 658 | reg = <0x48862000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 659 | interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, |
| 660 | <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, |
| 661 | <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, |
| 662 | <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 663 | ti,hwmods = "mailbox11"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 664 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 665 | ti,mbox-num-users = <4>; |
| 666 | ti,mbox-num-fifos = <12>; |
| 667 | status = "disabled"; |
| 668 | }; |
| 669 | |
| 670 | mailbox12: mailbox@48864000 { |
| 671 | compatible = "ti,omap4-mailbox"; |
| 672 | reg = <0x48864000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 673 | interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, |
| 674 | <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, |
| 675 | <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, |
| 676 | <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 677 | ti,hwmods = "mailbox12"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 678 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 679 | ti,mbox-num-users = <4>; |
| 680 | ti,mbox-num-fifos = <12>; |
| 681 | status = "disabled"; |
| 682 | }; |
| 683 | |
| 684 | mailbox13: mailbox@48802000 { |
| 685 | compatible = "ti,omap4-mailbox"; |
| 686 | reg = <0x48802000 0x200>; |
Suman Anna | b46a6ae | 2014-11-03 17:07:34 -0600 | [diff] [blame] | 687 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, |
| 688 | <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, |
| 689 | <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, |
| 690 | <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 691 | ti,hwmods = "mailbox13"; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 692 | #mbox-cells = <1>; |
Suman Anna | 38baefb | 2014-07-11 16:44:38 -0500 | [diff] [blame] | 693 | ti,mbox-num-users = <4>; |
| 694 | ti,mbox-num-fifos = <12>; |
| 695 | status = "disabled"; |
| 696 | }; |
| 697 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 698 | timer1: timer@4ae18000 { |
| 699 | compatible = "ti,omap5430-timer"; |
| 700 | reg = <0x4ae18000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 701 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 702 | ti,hwmods = "timer1"; |
| 703 | ti,timer-alwon; |
| 704 | }; |
| 705 | |
| 706 | timer2: timer@48032000 { |
| 707 | compatible = "ti,omap5430-timer"; |
| 708 | reg = <0x48032000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 709 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 710 | ti,hwmods = "timer2"; |
| 711 | }; |
| 712 | |
| 713 | timer3: timer@48034000 { |
| 714 | compatible = "ti,omap5430-timer"; |
| 715 | reg = <0x48034000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 716 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 717 | ti,hwmods = "timer3"; |
| 718 | }; |
| 719 | |
| 720 | timer4: timer@48036000 { |
| 721 | compatible = "ti,omap5430-timer"; |
| 722 | reg = <0x48036000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 723 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 724 | ti,hwmods = "timer4"; |
| 725 | }; |
| 726 | |
| 727 | timer5: timer@48820000 { |
| 728 | compatible = "ti,omap5430-timer"; |
| 729 | reg = <0x48820000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 730 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 731 | ti,hwmods = "timer5"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 732 | }; |
| 733 | |
| 734 | timer6: timer@48822000 { |
| 735 | compatible = "ti,omap5430-timer"; |
| 736 | reg = <0x48822000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 737 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 738 | ti,hwmods = "timer6"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 739 | }; |
| 740 | |
| 741 | timer7: timer@48824000 { |
| 742 | compatible = "ti,omap5430-timer"; |
| 743 | reg = <0x48824000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 744 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 745 | ti,hwmods = "timer7"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 746 | }; |
| 747 | |
| 748 | timer8: timer@48826000 { |
| 749 | compatible = "ti,omap5430-timer"; |
| 750 | reg = <0x48826000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 751 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 752 | ti,hwmods = "timer8"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 753 | }; |
| 754 | |
| 755 | timer9: timer@4803e000 { |
| 756 | compatible = "ti,omap5430-timer"; |
| 757 | reg = <0x4803e000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 758 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 759 | ti,hwmods = "timer9"; |
| 760 | }; |
| 761 | |
| 762 | timer10: timer@48086000 { |
| 763 | compatible = "ti,omap5430-timer"; |
| 764 | reg = <0x48086000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 765 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 766 | ti,hwmods = "timer10"; |
| 767 | }; |
| 768 | |
| 769 | timer11: timer@48088000 { |
| 770 | compatible = "ti,omap5430-timer"; |
| 771 | reg = <0x48088000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 772 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 773 | ti,hwmods = "timer11"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 774 | }; |
| 775 | |
| 776 | timer13: timer@48828000 { |
| 777 | compatible = "ti,omap5430-timer"; |
| 778 | reg = <0x48828000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 779 | interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 780 | ti,hwmods = "timer13"; |
| 781 | status = "disabled"; |
| 782 | }; |
| 783 | |
| 784 | timer14: timer@4882a000 { |
| 785 | compatible = "ti,omap5430-timer"; |
| 786 | reg = <0x4882a000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 787 | interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 788 | ti,hwmods = "timer14"; |
| 789 | status = "disabled"; |
| 790 | }; |
| 791 | |
| 792 | timer15: timer@4882c000 { |
| 793 | compatible = "ti,omap5430-timer"; |
| 794 | reg = <0x4882c000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 795 | interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 796 | ti,hwmods = "timer15"; |
| 797 | status = "disabled"; |
| 798 | }; |
| 799 | |
| 800 | timer16: timer@4882e000 { |
| 801 | compatible = "ti,omap5430-timer"; |
| 802 | reg = <0x4882e000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 803 | interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 804 | ti,hwmods = "timer16"; |
| 805 | status = "disabled"; |
| 806 | }; |
| 807 | |
| 808 | wdt2: wdt@4ae14000 { |
Lokesh Vutla | be66883 | 2014-11-12 10:54:15 +0530 | [diff] [blame] | 809 | compatible = "ti,omap3-wdt"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 810 | reg = <0x4ae14000 0x80>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 811 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 812 | ti,hwmods = "wd_timer2"; |
| 813 | }; |
| 814 | |
Suman Anna | dbd7c19 | 2014-01-13 18:26:46 -0600 | [diff] [blame] | 815 | hwspinlock: spinlock@4a0f6000 { |
| 816 | compatible = "ti,omap4-hwspinlock"; |
| 817 | reg = <0x4a0f6000 0x1000>; |
| 818 | ti,hwmods = "spinlock"; |
| 819 | #hwlock-cells = <1>; |
| 820 | }; |
| 821 | |
Archit Taneja | 1a5fe3c | 2013-12-17 15:32:21 +0530 | [diff] [blame] | 822 | dmm@4e000000 { |
| 823 | compatible = "ti,omap5-dmm"; |
| 824 | reg = <0x4e000000 0x800>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 825 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
Archit Taneja | 1a5fe3c | 2013-12-17 15:32:21 +0530 | [diff] [blame] | 826 | ti,hwmods = "dmm"; |
| 827 | }; |
| 828 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 829 | i2c1: i2c@48070000 { |
| 830 | compatible = "ti,omap4-i2c"; |
| 831 | reg = <0x48070000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 832 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 833 | #address-cells = <1>; |
| 834 | #size-cells = <0>; |
| 835 | ti,hwmods = "i2c1"; |
| 836 | status = "disabled"; |
| 837 | }; |
| 838 | |
| 839 | i2c2: i2c@48072000 { |
| 840 | compatible = "ti,omap4-i2c"; |
| 841 | reg = <0x48072000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 842 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 843 | #address-cells = <1>; |
| 844 | #size-cells = <0>; |
| 845 | ti,hwmods = "i2c2"; |
| 846 | status = "disabled"; |
| 847 | }; |
| 848 | |
| 849 | i2c3: i2c@48060000 { |
| 850 | compatible = "ti,omap4-i2c"; |
| 851 | reg = <0x48060000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 852 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 853 | #address-cells = <1>; |
| 854 | #size-cells = <0>; |
| 855 | ti,hwmods = "i2c3"; |
| 856 | status = "disabled"; |
| 857 | }; |
| 858 | |
| 859 | i2c4: i2c@4807a000 { |
| 860 | compatible = "ti,omap4-i2c"; |
| 861 | reg = <0x4807a000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 862 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 863 | #address-cells = <1>; |
| 864 | #size-cells = <0>; |
| 865 | ti,hwmods = "i2c4"; |
| 866 | status = "disabled"; |
| 867 | }; |
| 868 | |
| 869 | i2c5: i2c@4807c000 { |
| 870 | compatible = "ti,omap4-i2c"; |
| 871 | reg = <0x4807c000 0x100>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 872 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 873 | #address-cells = <1>; |
| 874 | #size-cells = <0>; |
| 875 | ti,hwmods = "i2c5"; |
| 876 | status = "disabled"; |
| 877 | }; |
| 878 | |
| 879 | mmc1: mmc@4809c000 { |
| 880 | compatible = "ti,omap4-hsmmc"; |
| 881 | reg = <0x4809c000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 882 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 883 | ti,hwmods = "mmc1"; |
| 884 | ti,dual-volt; |
| 885 | ti,needs-special-reset; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 886 | dmas = <&sdma_xbar 61>, <&sdma_xbar 62>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 887 | dma-names = "tx", "rx"; |
| 888 | status = "disabled"; |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 889 | pbias-supply = <&pbias_mmc_reg>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 890 | }; |
| 891 | |
| 892 | mmc2: mmc@480b4000 { |
| 893 | compatible = "ti,omap4-hsmmc"; |
| 894 | reg = <0x480b4000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 895 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 896 | ti,hwmods = "mmc2"; |
| 897 | ti,needs-special-reset; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 898 | dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 899 | dma-names = "tx", "rx"; |
| 900 | status = "disabled"; |
| 901 | }; |
| 902 | |
| 903 | mmc3: mmc@480ad000 { |
| 904 | compatible = "ti,omap4-hsmmc"; |
| 905 | reg = <0x480ad000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 906 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 907 | ti,hwmods = "mmc3"; |
| 908 | ti,needs-special-reset; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 909 | dmas = <&sdma_xbar 77>, <&sdma_xbar 78>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 910 | dma-names = "tx", "rx"; |
| 911 | status = "disabled"; |
| 912 | }; |
| 913 | |
| 914 | mmc4: mmc@480d1000 { |
| 915 | compatible = "ti,omap4-hsmmc"; |
| 916 | reg = <0x480d1000 0x400>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 917 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 918 | ti,hwmods = "mmc4"; |
| 919 | ti,needs-special-reset; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 920 | dmas = <&sdma_xbar 57>, <&sdma_xbar 58>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 921 | dma-names = "tx", "rx"; |
| 922 | status = "disabled"; |
| 923 | }; |
| 924 | |
Suman Anna | 2c7e07c5 | 2015-10-02 18:23:24 -0500 | [diff] [blame] | 925 | mmu0_dsp1: mmu@40d01000 { |
| 926 | compatible = "ti,dra7-dsp-iommu"; |
| 927 | reg = <0x40d01000 0x100>; |
| 928 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| 929 | ti,hwmods = "mmu0_dsp1"; |
| 930 | #iommu-cells = <0>; |
| 931 | ti,syscon-mmuconfig = <&dsp1_system 0x0>; |
| 932 | status = "disabled"; |
| 933 | }; |
| 934 | |
| 935 | mmu1_dsp1: mmu@40d02000 { |
| 936 | compatible = "ti,dra7-dsp-iommu"; |
| 937 | reg = <0x40d02000 0x100>; |
| 938 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
| 939 | ti,hwmods = "mmu1_dsp1"; |
| 940 | #iommu-cells = <0>; |
| 941 | ti,syscon-mmuconfig = <&dsp1_system 0x1>; |
| 942 | status = "disabled"; |
| 943 | }; |
| 944 | |
| 945 | mmu_ipu1: mmu@58882000 { |
| 946 | compatible = "ti,dra7-iommu"; |
| 947 | reg = <0x58882000 0x100>; |
| 948 | interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; |
| 949 | ti,hwmods = "mmu_ipu1"; |
| 950 | #iommu-cells = <0>; |
| 951 | ti,iommu-bus-err-back; |
| 952 | status = "disabled"; |
| 953 | }; |
| 954 | |
| 955 | mmu_ipu2: mmu@55082000 { |
| 956 | compatible = "ti,dra7-iommu"; |
| 957 | reg = <0x55082000 0x100>; |
| 958 | interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; |
| 959 | ti,hwmods = "mmu_ipu2"; |
| 960 | #iommu-cells = <0>; |
| 961 | ti,iommu-bus-err-back; |
| 962 | status = "disabled"; |
| 963 | }; |
| 964 | |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 965 | abb_mpu: regulator-abb-mpu { |
| 966 | compatible = "ti,abb-v3"; |
| 967 | regulator-name = "abb_mpu"; |
| 968 | #address-cells = <0>; |
| 969 | #size-cells = <0>; |
| 970 | clocks = <&sys_clkin1>; |
| 971 | ti,settling-time = <50>; |
| 972 | ti,clock-cycles = <16>; |
| 973 | |
| 974 | reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, |
Nishanth Menon | 1822734 | 2015-04-16 16:56:33 -0500 | [diff] [blame] | 975 | <0x4ae06014 0x4>, <0x4a003b20 0xc>, |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 976 | <0x4ae0c158 0x4>; |
| 977 | reg-names = "setup-address", "control-address", |
| 978 | "int-address", "efuse-address", |
| 979 | "ldo-address"; |
| 980 | ti,tranxdone-status-mask = <0x80>; |
| 981 | /* LDOVBBMPU_FBB_MUX_CTRL */ |
| 982 | ti,ldovbb-override-mask = <0x400>; |
| 983 | /* LDOVBBMPU_FBB_VSET_OUT */ |
| 984 | ti,ldovbb-vset-mask = <0x1F>; |
| 985 | |
| 986 | /* |
| 987 | * NOTE: only FBB mode used but actual vset will |
| 988 | * determine final biasing |
| 989 | */ |
| 990 | ti,abb_info = < |
| 991 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 992 | 1060000 0 0x0 0 0x02000000 0x01F00000 |
| 993 | 1160000 0 0x4 0 0x02000000 0x01F00000 |
| 994 | 1210000 0 0x8 0 0x02000000 0x01F00000 |
| 995 | >; |
| 996 | }; |
| 997 | |
| 998 | abb_ivahd: regulator-abb-ivahd { |
| 999 | compatible = "ti,abb-v3"; |
| 1000 | regulator-name = "abb_ivahd"; |
| 1001 | #address-cells = <0>; |
| 1002 | #size-cells = <0>; |
| 1003 | clocks = <&sys_clkin1>; |
| 1004 | ti,settling-time = <50>; |
| 1005 | ti,clock-cycles = <16>; |
| 1006 | |
| 1007 | reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, |
Nishanth Menon | 1822734 | 2015-04-16 16:56:33 -0500 | [diff] [blame] | 1008 | <0x4ae06010 0x4>, <0x4a0025cc 0xc>, |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 1009 | <0x4a002470 0x4>; |
| 1010 | reg-names = "setup-address", "control-address", |
| 1011 | "int-address", "efuse-address", |
| 1012 | "ldo-address"; |
| 1013 | ti,tranxdone-status-mask = <0x40000000>; |
| 1014 | /* LDOVBBIVA_FBB_MUX_CTRL */ |
| 1015 | ti,ldovbb-override-mask = <0x400>; |
| 1016 | /* LDOVBBIVA_FBB_VSET_OUT */ |
| 1017 | ti,ldovbb-vset-mask = <0x1F>; |
| 1018 | |
| 1019 | /* |
| 1020 | * NOTE: only FBB mode used but actual vset will |
| 1021 | * determine final biasing |
| 1022 | */ |
| 1023 | ti,abb_info = < |
| 1024 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1025 | 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 1026 | 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 1027 | 1250000 0 0x8 0 0x02000000 0x01F00000 |
| 1028 | >; |
| 1029 | }; |
| 1030 | |
| 1031 | abb_dspeve: regulator-abb-dspeve { |
| 1032 | compatible = "ti,abb-v3"; |
| 1033 | regulator-name = "abb_dspeve"; |
| 1034 | #address-cells = <0>; |
| 1035 | #size-cells = <0>; |
| 1036 | clocks = <&sys_clkin1>; |
| 1037 | ti,settling-time = <50>; |
| 1038 | ti,clock-cycles = <16>; |
| 1039 | |
| 1040 | reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, |
Nishanth Menon | 1822734 | 2015-04-16 16:56:33 -0500 | [diff] [blame] | 1041 | <0x4ae06010 0x4>, <0x4a0025e0 0xc>, |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 1042 | <0x4a00246c 0x4>; |
| 1043 | reg-names = "setup-address", "control-address", |
| 1044 | "int-address", "efuse-address", |
| 1045 | "ldo-address"; |
| 1046 | ti,tranxdone-status-mask = <0x20000000>; |
| 1047 | /* LDOVBBDSPEVE_FBB_MUX_CTRL */ |
| 1048 | ti,ldovbb-override-mask = <0x400>; |
| 1049 | /* LDOVBBDSPEVE_FBB_VSET_OUT */ |
| 1050 | ti,ldovbb-vset-mask = <0x1F>; |
| 1051 | |
| 1052 | /* |
| 1053 | * NOTE: only FBB mode used but actual vset will |
| 1054 | * determine final biasing |
| 1055 | */ |
| 1056 | ti,abb_info = < |
| 1057 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1058 | 1055000 0 0x0 0 0x02000000 0x01F00000 |
| 1059 | 1150000 0 0x4 0 0x02000000 0x01F00000 |
| 1060 | 1250000 0 0x8 0 0x02000000 0x01F00000 |
| 1061 | >; |
| 1062 | }; |
| 1063 | |
| 1064 | abb_gpu: regulator-abb-gpu { |
| 1065 | compatible = "ti,abb-v3"; |
| 1066 | regulator-name = "abb_gpu"; |
| 1067 | #address-cells = <0>; |
| 1068 | #size-cells = <0>; |
| 1069 | clocks = <&sys_clkin1>; |
| 1070 | ti,settling-time = <50>; |
| 1071 | ti,clock-cycles = <16>; |
| 1072 | |
| 1073 | reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, |
Nishanth Menon | 1822734 | 2015-04-16 16:56:33 -0500 | [diff] [blame] | 1074 | <0x4ae06010 0x4>, <0x4a003b08 0xc>, |
Nishanth Menon | a1b8ee1 | 2014-03-03 20:20:23 +0530 | [diff] [blame] | 1075 | <0x4ae0c154 0x4>; |
| 1076 | reg-names = "setup-address", "control-address", |
| 1077 | "int-address", "efuse-address", |
| 1078 | "ldo-address"; |
| 1079 | ti,tranxdone-status-mask = <0x10000000>; |
| 1080 | /* LDOVBBGPU_FBB_MUX_CTRL */ |
| 1081 | ti,ldovbb-override-mask = <0x400>; |
| 1082 | /* LDOVBBGPU_FBB_VSET_OUT */ |
| 1083 | ti,ldovbb-vset-mask = <0x1F>; |
| 1084 | |
| 1085 | /* |
| 1086 | * NOTE: only FBB mode used but actual vset will |
| 1087 | * determine final biasing |
| 1088 | */ |
| 1089 | ti,abb_info = < |
| 1090 | /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1091 | 1090000 0 0x0 0 0x02000000 0x01F00000 |
| 1092 | 1210000 0 0x4 0 0x02000000 0x01F00000 |
| 1093 | 1280000 0 0x8 0 0x02000000 0x01F00000 |
| 1094 | >; |
| 1095 | }; |
| 1096 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1097 | mcspi1: spi@48098000 { |
| 1098 | compatible = "ti,omap4-mcspi"; |
| 1099 | reg = <0x48098000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1100 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1101 | #address-cells = <1>; |
| 1102 | #size-cells = <0>; |
| 1103 | ti,hwmods = "mcspi1"; |
| 1104 | ti,spi-num-cs = <4>; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 1105 | dmas = <&sdma_xbar 35>, |
| 1106 | <&sdma_xbar 36>, |
| 1107 | <&sdma_xbar 37>, |
| 1108 | <&sdma_xbar 38>, |
| 1109 | <&sdma_xbar 39>, |
| 1110 | <&sdma_xbar 40>, |
| 1111 | <&sdma_xbar 41>, |
| 1112 | <&sdma_xbar 42>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1113 | dma-names = "tx0", "rx0", "tx1", "rx1", |
| 1114 | "tx2", "rx2", "tx3", "rx3"; |
| 1115 | status = "disabled"; |
| 1116 | }; |
| 1117 | |
| 1118 | mcspi2: spi@4809a000 { |
| 1119 | compatible = "ti,omap4-mcspi"; |
| 1120 | reg = <0x4809a000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1121 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1122 | #address-cells = <1>; |
| 1123 | #size-cells = <0>; |
| 1124 | ti,hwmods = "mcspi2"; |
| 1125 | ti,spi-num-cs = <2>; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 1126 | dmas = <&sdma_xbar 43>, |
| 1127 | <&sdma_xbar 44>, |
| 1128 | <&sdma_xbar 45>, |
| 1129 | <&sdma_xbar 46>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1130 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
| 1131 | status = "disabled"; |
| 1132 | }; |
| 1133 | |
| 1134 | mcspi3: spi@480b8000 { |
| 1135 | compatible = "ti,omap4-mcspi"; |
| 1136 | reg = <0x480b8000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1137 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1138 | #address-cells = <1>; |
| 1139 | #size-cells = <0>; |
| 1140 | ti,hwmods = "mcspi3"; |
| 1141 | ti,spi-num-cs = <2>; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 1142 | dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1143 | dma-names = "tx0", "rx0"; |
| 1144 | status = "disabled"; |
| 1145 | }; |
| 1146 | |
| 1147 | mcspi4: spi@480ba000 { |
| 1148 | compatible = "ti,omap4-mcspi"; |
| 1149 | reg = <0x480ba000 0x200>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1150 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1151 | #address-cells = <1>; |
| 1152 | #size-cells = <0>; |
| 1153 | ti,hwmods = "mcspi4"; |
| 1154 | ti,spi-num-cs = <1>; |
Peter Ujfalusi | 3a0830d | 2015-04-09 12:35:54 +0300 | [diff] [blame] | 1155 | dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1156 | dma-names = "tx0", "rx0"; |
| 1157 | status = "disabled"; |
| 1158 | }; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 1159 | |
| 1160 | qspi: qspi@4b300000 { |
| 1161 | compatible = "ti,dra7xxx-qspi"; |
Vignesh R | 1929d0b | 2015-12-11 09:39:59 +0530 | [diff] [blame] | 1162 | reg = <0x4b300000 0x100>, |
| 1163 | <0x5c000000 0x4000000>; |
| 1164 | reg-names = "qspi_base", "qspi_mmap"; |
| 1165 | syscon-chipselects = <&scm_conf 0x558>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 1166 | #address-cells = <1>; |
| 1167 | #size-cells = <0>; |
| 1168 | ti,hwmods = "qspi"; |
| 1169 | clocks = <&qspi_gfclk_div>; |
| 1170 | clock-names = "fck"; |
| 1171 | num-cs = <4>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1172 | interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 1173 | status = "disabled"; |
| 1174 | }; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1175 | |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1176 | /* OCP2SCP3 */ |
| 1177 | ocp2scp@4a090000 { |
| 1178 | compatible = "ti,omap-ocp2scp"; |
| 1179 | #address-cells = <1>; |
| 1180 | #size-cells = <1>; |
| 1181 | ranges; |
| 1182 | reg = <0x4a090000 0x20>; |
| 1183 | ti,hwmods = "ocp2scp3"; |
| 1184 | sata_phy: phy@4A096000 { |
| 1185 | compatible = "ti,phy-pipe3-sata"; |
| 1186 | reg = <0x4A096000 0x80>, /* phy_rx */ |
| 1187 | <0x4A096400 0x64>, /* phy_tx */ |
| 1188 | <0x4A096800 0x40>; /* pll_ctrl */ |
| 1189 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
Kishon Vijay Abraham I | 2338c76 | 2015-12-21 14:43:21 +0530 | [diff] [blame] | 1190 | syscon-phy-power = <&scm_conf 0x374>; |
Roger Quadros | 773c5a0 | 2015-01-13 14:23:21 +0200 | [diff] [blame] | 1191 | clocks = <&sys_clkin1>, <&sata_ref_clk>; |
| 1192 | clock-names = "sysclk", "refclk"; |
Roger Quadros | 257d5d9 | 2015-07-17 16:47:23 +0300 | [diff] [blame] | 1193 | syscon-pllreset = <&scm_conf 0x3fc>; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1194 | #phy-cells = <0>; |
| 1195 | }; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1196 | |
| 1197 | pcie1_phy: pciephy@4a094000 { |
| 1198 | compatible = "ti,phy-pipe3-pcie"; |
| 1199 | reg = <0x4a094000 0x80>, /* phy_rx */ |
| 1200 | <0x4a094400 0x64>; /* phy_tx */ |
| 1201 | reg-names = "phy_rx", "phy_tx"; |
Kishon Vijay Abraham I | 6921e58 | 2015-12-21 14:43:19 +0530 | [diff] [blame] | 1202 | syscon-phy-power = <&scm_conf_pcie 0x1c>; |
| 1203 | syscon-pcs = <&scm_conf_pcie 0x10>; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1204 | clocks = <&dpll_pcie_ref_ck>, |
| 1205 | <&dpll_pcie_ref_m2ldo_ck>, |
| 1206 | <&optfclk_pciephy1_32khz>, |
| 1207 | <&optfclk_pciephy1_clk>, |
| 1208 | <&optfclk_pciephy1_div_clk>, |
Kishon Vijay Abraham I | 6921e58 | 2015-12-21 14:43:19 +0530 | [diff] [blame] | 1209 | <&optfclk_pciephy_div>, |
| 1210 | <&sys_clkin1>; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1211 | clock-names = "dpll_ref", "dpll_ref_m2", |
| 1212 | "wkupclk", "refclk", |
Kishon Vijay Abraham I | 6921e58 | 2015-12-21 14:43:19 +0530 | [diff] [blame] | 1213 | "div-clk", "phy-div", "sysclk"; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1214 | #phy-cells = <0>; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1215 | }; |
| 1216 | |
| 1217 | pcie2_phy: pciephy@4a095000 { |
| 1218 | compatible = "ti,phy-pipe3-pcie"; |
| 1219 | reg = <0x4a095000 0x80>, /* phy_rx */ |
| 1220 | <0x4a095400 0x64>; /* phy_tx */ |
| 1221 | reg-names = "phy_rx", "phy_tx"; |
Kishon Vijay Abraham I | 6921e58 | 2015-12-21 14:43:19 +0530 | [diff] [blame] | 1222 | syscon-phy-power = <&scm_conf_pcie 0x20>; |
| 1223 | syscon-pcs = <&scm_conf_pcie 0x10>; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1224 | clocks = <&dpll_pcie_ref_ck>, |
| 1225 | <&dpll_pcie_ref_m2ldo_ck>, |
| 1226 | <&optfclk_pciephy2_32khz>, |
| 1227 | <&optfclk_pciephy2_clk>, |
| 1228 | <&optfclk_pciephy2_div_clk>, |
Kishon Vijay Abraham I | 6921e58 | 2015-12-21 14:43:19 +0530 | [diff] [blame] | 1229 | <&optfclk_pciephy_div>, |
| 1230 | <&sys_clkin1>; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1231 | clock-names = "dpll_ref", "dpll_ref_m2", |
| 1232 | "wkupclk", "refclk", |
Kishon Vijay Abraham I | 6921e58 | 2015-12-21 14:43:19 +0530 | [diff] [blame] | 1233 | "div-clk", "phy-div", "sysclk"; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1234 | #phy-cells = <0>; |
Kishon Vijay Abraham I | 692df0e | 2014-07-14 16:12:22 +0530 | [diff] [blame] | 1235 | status = "disabled"; |
| 1236 | }; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1237 | }; |
| 1238 | |
| 1239 | sata: sata@4a141100 { |
| 1240 | compatible = "snps,dwc-ahci"; |
| 1241 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1242 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
Balaji T K | 7be8056 | 2014-05-07 14:58:58 +0300 | [diff] [blame] | 1243 | phys = <&sata_phy>; |
| 1244 | phy-names = "sata-phy"; |
| 1245 | clocks = <&sata_ref_clk>; |
| 1246 | ti,hwmods = "sata"; |
| 1247 | }; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1248 | |
Nishanth Menon | 00edd31 | 2015-04-08 18:56:27 -0500 | [diff] [blame] | 1249 | rtc: rtc@48838000 { |
Lokesh Vutla | bc07831 | 2014-11-19 17:53:08 +0530 | [diff] [blame] | 1250 | compatible = "ti,am3352-rtc"; |
| 1251 | reg = <0x48838000 0x100>; |
| 1252 | interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, |
| 1253 | <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; |
| 1254 | ti,hwmods = "rtcss"; |
| 1255 | clocks = <&sys_32k_ck>; |
| 1256 | }; |
| 1257 | |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1258 | /* OCP2SCP1 */ |
| 1259 | ocp2scp@4a080000 { |
| 1260 | compatible = "ti,omap-ocp2scp"; |
| 1261 | #address-cells = <1>; |
| 1262 | #size-cells = <1>; |
| 1263 | ranges; |
| 1264 | reg = <0x4a080000 0x20>; |
| 1265 | ti,hwmods = "ocp2scp1"; |
| 1266 | |
| 1267 | usb2_phy1: phy@4a084000 { |
| 1268 | compatible = "ti,omap-usb2"; |
| 1269 | reg = <0x4a084000 0x400>; |
Kishon Vijay Abraham I | 2338c76 | 2015-12-21 14:43:21 +0530 | [diff] [blame] | 1270 | syscon-phy-power = <&scm_conf 0x300>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1271 | clocks = <&usb_phy1_always_on_clk32k>, |
| 1272 | <&usb_otg_ss1_refclk960m>; |
| 1273 | clock-names = "wkupclk", |
| 1274 | "refclk"; |
| 1275 | #phy-cells = <0>; |
| 1276 | }; |
| 1277 | |
| 1278 | usb2_phy2: phy@4a085000 { |
Kishon Vijay Abraham I | 4b4f52e | 2015-12-21 14:43:20 +0530 | [diff] [blame] | 1279 | compatible = "ti,dra7x-usb2-phy2", |
| 1280 | "ti,omap-usb2"; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1281 | reg = <0x4a085000 0x400>; |
Kishon Vijay Abraham I | 2338c76 | 2015-12-21 14:43:21 +0530 | [diff] [blame] | 1282 | syscon-phy-power = <&scm_conf 0xe74>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1283 | clocks = <&usb_phy2_always_on_clk32k>, |
| 1284 | <&usb_otg_ss2_refclk960m>; |
| 1285 | clock-names = "wkupclk", |
| 1286 | "refclk"; |
| 1287 | #phy-cells = <0>; |
| 1288 | }; |
| 1289 | |
| 1290 | usb3_phy1: phy@4a084400 { |
| 1291 | compatible = "ti,omap-usb3"; |
| 1292 | reg = <0x4a084400 0x80>, |
| 1293 | <0x4a084800 0x64>, |
| 1294 | <0x4a084c00 0x40>; |
| 1295 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
Kishon Vijay Abraham I | 2338c76 | 2015-12-21 14:43:21 +0530 | [diff] [blame] | 1296 | syscon-phy-power = <&scm_conf 0x370>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1297 | clocks = <&usb_phy3_always_on_clk32k>, |
| 1298 | <&sys_clkin1>, |
| 1299 | <&usb_otg_ss1_refclk960m>; |
| 1300 | clock-names = "wkupclk", |
| 1301 | "sysclk", |
| 1302 | "refclk"; |
| 1303 | #phy-cells = <0>; |
| 1304 | }; |
| 1305 | }; |
| 1306 | |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1307 | omap_dwc3_1: omap_dwc3_1@48880000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1308 | compatible = "ti,dwc3"; |
| 1309 | ti,hwmods = "usb_otg_ss1"; |
| 1310 | reg = <0x48880000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1311 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1312 | #address-cells = <1>; |
| 1313 | #size-cells = <1>; |
| 1314 | utmi-mode = <2>; |
| 1315 | ranges; |
| 1316 | usb1: usb@48890000 { |
| 1317 | compatible = "snps,dwc3"; |
| 1318 | reg = <0x48890000 0x17000>; |
Roger Quadros | 964927f | 2015-07-08 13:42:32 +0300 | [diff] [blame] | 1319 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, |
| 1320 | <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, |
| 1321 | <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| 1322 | interrupt-names = "peripheral", |
| 1323 | "host", |
| 1324 | "otg"; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1325 | phys = <&usb2_phy1>, <&usb3_phy1>; |
| 1326 | phy-names = "usb2-phy", "usb3-phy"; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1327 | maximum-speed = "super-speed"; |
| 1328 | dr_mode = "otg"; |
Felipe Balbi | 8c60673 | 2015-01-15 09:38:03 -0600 | [diff] [blame] | 1329 | snps,dis_u3_susphy_quirk; |
| 1330 | snps,dis_u2_susphy_quirk; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1331 | }; |
| 1332 | }; |
| 1333 | |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1334 | omap_dwc3_2: omap_dwc3_2@488c0000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1335 | compatible = "ti,dwc3"; |
| 1336 | ti,hwmods = "usb_otg_ss2"; |
| 1337 | reg = <0x488c0000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1338 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1339 | #address-cells = <1>; |
| 1340 | #size-cells = <1>; |
| 1341 | utmi-mode = <2>; |
| 1342 | ranges; |
| 1343 | usb2: usb@488d0000 { |
| 1344 | compatible = "snps,dwc3"; |
| 1345 | reg = <0x488d0000 0x17000>; |
Roger Quadros | 964927f | 2015-07-08 13:42:32 +0300 | [diff] [blame] | 1346 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, |
| 1347 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, |
| 1348 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
| 1349 | interrupt-names = "peripheral", |
| 1350 | "host", |
| 1351 | "otg"; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1352 | phys = <&usb2_phy2>; |
| 1353 | phy-names = "usb2-phy"; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1354 | maximum-speed = "high-speed"; |
| 1355 | dr_mode = "otg"; |
Felipe Balbi | 8c60673 | 2015-01-15 09:38:03 -0600 | [diff] [blame] | 1356 | snps,dis_u3_susphy_quirk; |
| 1357 | snps,dis_u2_susphy_quirk; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1358 | }; |
| 1359 | }; |
| 1360 | |
| 1361 | /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ |
Felipe Balbi | 4f6dec7 | 2014-11-03 10:28:42 -0600 | [diff] [blame] | 1362 | omap_dwc3_3: omap_dwc3_3@48900000 { |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1363 | compatible = "ti,dwc3"; |
| 1364 | ti,hwmods = "usb_otg_ss3"; |
| 1365 | reg = <0x48900000 0x10000>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1366 | interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1367 | #address-cells = <1>; |
| 1368 | #size-cells = <1>; |
| 1369 | utmi-mode = <2>; |
| 1370 | ranges; |
| 1371 | status = "disabled"; |
| 1372 | usb3: usb@48910000 { |
| 1373 | compatible = "snps,dwc3"; |
| 1374 | reg = <0x48910000 0x17000>; |
Roger Quadros | 964927f | 2015-07-08 13:42:32 +0300 | [diff] [blame] | 1375 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, |
| 1376 | <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, |
| 1377 | <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; |
| 1378 | interrupt-names = "peripheral", |
| 1379 | "host", |
| 1380 | "otg"; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1381 | maximum-speed = "high-speed"; |
| 1382 | dr_mode = "otg"; |
Felipe Balbi | 8c60673 | 2015-01-15 09:38:03 -0600 | [diff] [blame] | 1383 | snps,dis_u3_susphy_quirk; |
| 1384 | snps,dis_u2_susphy_quirk; |
Roger Quadros | fbf3e55 | 2014-05-05 12:54:45 +0300 | [diff] [blame] | 1385 | }; |
| 1386 | }; |
| 1387 | |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1388 | elm: elm@48078000 { |
| 1389 | compatible = "ti,am3352-elm"; |
| 1390 | reg = <0x48078000 0xfc0>; /* device IO registers */ |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1391 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1392 | ti,hwmods = "elm"; |
| 1393 | status = "disabled"; |
| 1394 | }; |
| 1395 | |
| 1396 | gpmc: gpmc@50000000 { |
| 1397 | compatible = "ti,am3352-gpmc"; |
| 1398 | ti,hwmods = "gpmc"; |
| 1399 | reg = <0x50000000 0x37c>; /* device IO registers */ |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1400 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1401 | gpmc,num-cs = <8>; |
| 1402 | gpmc,num-waitpins = <2>; |
| 1403 | #address-cells = <2>; |
| 1404 | #size-cells = <1>; |
Roger Quadros | 488f270 | 2016-02-23 18:37:17 +0200 | [diff] [blame] | 1405 | interrupt-controller; |
| 1406 | #interrupt-cells = <2>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 1407 | status = "disabled"; |
| 1408 | }; |
Peter Ujfalusi | 2ca0945 | 2014-05-07 13:20:48 +0300 | [diff] [blame] | 1409 | |
| 1410 | atl: atl@4843c000 { |
| 1411 | compatible = "ti,dra7-atl"; |
| 1412 | reg = <0x4843c000 0x3ff>; |
| 1413 | ti,hwmods = "atl"; |
| 1414 | ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, |
| 1415 | <&atl_clkin2_ck>, <&atl_clkin3_ck>; |
| 1416 | clocks = <&atl_gfclk_mux>; |
| 1417 | clock-names = "fck"; |
| 1418 | status = "disabled"; |
| 1419 | }; |
Olof Johansson | 412a9bb | 2014-07-18 22:16:15 -0700 | [diff] [blame] | 1420 | |
Peter Ujfalusi | 026d4d6 | 2015-08-24 10:19:58 +0300 | [diff] [blame] | 1421 | mcasp3: mcasp@48468000 { |
| 1422 | compatible = "ti,dra7-mcasp-audio"; |
| 1423 | ti,hwmods = "mcasp3"; |
| 1424 | reg = <0x48468000 0x2000>; |
| 1425 | reg-names = "mpu"; |
| 1426 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, |
| 1427 | <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; |
| 1428 | interrupt-names = "tx", "rx"; |
| 1429 | dmas = <&sdma_xbar 133>, <&sdma_xbar 132>; |
| 1430 | dma-names = "tx", "rx"; |
Peter Ujfalusi | bf05c2c | 2015-11-12 09:32:57 +0200 | [diff] [blame] | 1431 | clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>; |
| 1432 | clock-names = "fck", "ahclkx"; |
Peter Ujfalusi | 026d4d6 | 2015-08-24 10:19:58 +0300 | [diff] [blame] | 1433 | status = "disabled"; |
| 1434 | }; |
| 1435 | |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 1436 | crossbar_mpu: crossbar@4a002a48 { |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1437 | compatible = "ti,irq-crossbar"; |
| 1438 | reg = <0x4a002a48 0x130>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 1439 | interrupt-controller; |
Marc Zyngier | 7136d45 | 2015-03-11 15:43:49 +0000 | [diff] [blame] | 1440 | interrupt-parent = <&wakeupgen>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 1441 | #interrupt-cells = <3>; |
R Sricharan | a46631c | 2014-06-26 12:55:31 +0530 | [diff] [blame] | 1442 | ti,max-irqs = <160>; |
| 1443 | ti,max-crossbar-sources = <MAX_SOURCES>; |
| 1444 | ti,reg-size = <2>; |
| 1445 | ti,irqs-reserved = <0 1 2 3 5 6 131 132>; |
| 1446 | ti,irqs-skip = <10 133 139 140>; |
| 1447 | ti,irqs-safe-map = <0>; |
| 1448 | }; |
Mugunthan V N | ef9c5b6 | 2014-10-21 15:31:00 +0530 | [diff] [blame] | 1449 | |
Vishal Mahaveer | c263a5b | 2015-08-25 13:57:49 -0500 | [diff] [blame] | 1450 | mac: ethernet@48484000 { |
Mugunthan V N | e209531 | 2015-08-12 15:22:54 +0530 | [diff] [blame] | 1451 | compatible = "ti,dra7-cpsw","ti,cpsw"; |
Mugunthan V N | ef9c5b6 | 2014-10-21 15:31:00 +0530 | [diff] [blame] | 1452 | ti,hwmods = "gmac"; |
| 1453 | clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; |
| 1454 | clock-names = "fck", "cpts"; |
| 1455 | cpdma_channels = <8>; |
| 1456 | ale_entries = <1024>; |
| 1457 | bd_ram_size = <0x2000>; |
| 1458 | no_bd_ram = <0>; |
| 1459 | rx_descs = <64>; |
| 1460 | mac_control = <0x20>; |
| 1461 | slaves = <2>; |
| 1462 | active_slave = <0>; |
| 1463 | cpts_clock_mult = <0x80000000>; |
| 1464 | cpts_clock_shift = <29>; |
| 1465 | reg = <0x48484000 0x1000 |
| 1466 | 0x48485200 0x2E00>; |
| 1467 | #address-cells = <1>; |
| 1468 | #size-cells = <1>; |
Mugunthan V N | 0f514e6 | 2016-03-07 01:41:22 -0700 | [diff] [blame] | 1469 | |
| 1470 | /* |
| 1471 | * Do not allow gating of cpsw clock as workaround |
| 1472 | * for errata i877. Keeping internal clock disabled |
| 1473 | * causes the device switching characteristics |
| 1474 | * to degrade over time and eventually fail to meet |
| 1475 | * the data manual delay time/skew specs. |
| 1476 | */ |
| 1477 | ti,no-idle; |
| 1478 | |
Mugunthan V N | ef9c5b6 | 2014-10-21 15:31:00 +0530 | [diff] [blame] | 1479 | /* |
| 1480 | * rx_thresh_pend |
| 1481 | * rx_pend |
| 1482 | * tx_pend |
| 1483 | * misc_pend |
| 1484 | */ |
| 1485 | interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, |
| 1486 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, |
| 1487 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, |
| 1488 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; |
| 1489 | ranges; |
Mugunthan V N | a084e13 | 2015-09-21 15:56:52 +0530 | [diff] [blame] | 1490 | syscon = <&scm_conf>; |
Mugunthan V N | ef9c5b6 | 2014-10-21 15:31:00 +0530 | [diff] [blame] | 1491 | status = "disabled"; |
| 1492 | |
| 1493 | davinci_mdio: mdio@48485000 { |
| 1494 | compatible = "ti,davinci_mdio"; |
| 1495 | #address-cells = <1>; |
| 1496 | #size-cells = <0>; |
| 1497 | ti,hwmods = "davinci_mdio"; |
| 1498 | bus_freq = <1000000>; |
| 1499 | reg = <0x48485000 0x100>; |
| 1500 | }; |
| 1501 | |
| 1502 | cpsw_emac0: slave@48480200 { |
| 1503 | /* Filled in by U-Boot */ |
| 1504 | mac-address = [ 00 00 00 00 00 00 ]; |
| 1505 | }; |
| 1506 | |
| 1507 | cpsw_emac1: slave@48480300 { |
| 1508 | /* Filled in by U-Boot */ |
| 1509 | mac-address = [ 00 00 00 00 00 00 ]; |
| 1510 | }; |
| 1511 | |
| 1512 | phy_sel: cpsw-phy-sel@4a002554 { |
| 1513 | compatible = "ti,dra7xx-cpsw-phy-sel"; |
| 1514 | reg= <0x4a002554 0x4>; |
| 1515 | reg-names = "gmii-sel"; |
| 1516 | }; |
| 1517 | }; |
| 1518 | |
Roger Quadros | 9ec49b9 | 2014-08-15 16:08:36 +0300 | [diff] [blame] | 1519 | dcan1: can@481cc000 { |
| 1520 | compatible = "ti,dra7-d_can"; |
| 1521 | ti,hwmods = "dcan1"; |
| 1522 | reg = <0x4ae3c000 0x2000>; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 1523 | syscon-raminit = <&scm_conf 0x558 0>; |
Roger Quadros | 9ec49b9 | 2014-08-15 16:08:36 +0300 | [diff] [blame] | 1524 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; |
| 1525 | clocks = <&dcan1_sys_clk_mux>; |
| 1526 | status = "disabled"; |
| 1527 | }; |
| 1528 | |
| 1529 | dcan2: can@481d0000 { |
| 1530 | compatible = "ti,dra7-d_can"; |
| 1531 | ti,hwmods = "dcan2"; |
| 1532 | reg = <0x48480000 0x2000>; |
Tero Kristo | d919501 | 2015-02-12 11:37:13 +0200 | [diff] [blame] | 1533 | syscon-raminit = <&scm_conf 0x558 1>; |
Roger Quadros | 9ec49b9 | 2014-08-15 16:08:36 +0300 | [diff] [blame] | 1534 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
| 1535 | clocks = <&sys_clkin1>; |
| 1536 | status = "disabled"; |
| 1537 | }; |
Tomi Valkeinen | 95c1cd1 | 2014-07-09 16:15:18 +0530 | [diff] [blame] | 1538 | |
| 1539 | dss: dss@58000000 { |
| 1540 | compatible = "ti,dra7-dss"; |
| 1541 | /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ |
| 1542 | /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ |
| 1543 | status = "disabled"; |
| 1544 | ti,hwmods = "dss_core"; |
| 1545 | /* CTRL_CORE_DSS_PLL_CONTROL */ |
| 1546 | syscon-pll-ctrl = <&scm_conf 0x538>; |
| 1547 | #address-cells = <1>; |
| 1548 | #size-cells = <1>; |
| 1549 | ranges; |
| 1550 | |
| 1551 | dispc@58001000 { |
| 1552 | compatible = "ti,dra7-dispc"; |
| 1553 | reg = <0x58001000 0x1000>; |
| 1554 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 1555 | ti,hwmods = "dss_dispc"; |
| 1556 | clocks = <&dss_dss_clk>; |
| 1557 | clock-names = "fck"; |
| 1558 | /* CTRL_CORE_SMA_SW_1 */ |
| 1559 | syscon-pol = <&scm_conf 0x534>; |
| 1560 | }; |
| 1561 | |
| 1562 | hdmi: encoder@58060000 { |
| 1563 | compatible = "ti,dra7-hdmi"; |
| 1564 | reg = <0x58040000 0x200>, |
| 1565 | <0x58040200 0x80>, |
| 1566 | <0x58040300 0x80>, |
| 1567 | <0x58060000 0x19000>; |
| 1568 | reg-names = "wp", "pll", "phy", "core"; |
| 1569 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| 1570 | status = "disabled"; |
| 1571 | ti,hwmods = "dss_hdmi"; |
| 1572 | clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>; |
| 1573 | clock-names = "fck", "sys_clk"; |
| 1574 | }; |
| 1575 | }; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1576 | }; |
Keerthy | f7397ed | 2015-03-23 14:39:38 -0500 | [diff] [blame] | 1577 | |
| 1578 | thermal_zones: thermal-zones { |
| 1579 | #include "omap4-cpu-thermal.dtsi" |
| 1580 | #include "omap5-gpu-thermal.dtsi" |
| 1581 | #include "omap5-core-thermal.dtsi" |
Keerthy | 667f259 | 2016-02-08 14:46:30 +0530 | [diff] [blame] | 1582 | #include "dra7-dspeve-thermal.dtsi" |
| 1583 | #include "dra7-iva-thermal.dtsi" |
Keerthy | f7397ed | 2015-03-23 14:39:38 -0500 | [diff] [blame] | 1584 | }; |
| 1585 | |
| 1586 | }; |
| 1587 | |
| 1588 | &cpu_thermal { |
| 1589 | polling-delay = <500>; /* milliseconds */ |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1590 | }; |
Tero Kristo | ee6c750 | 2013-07-18 17:18:33 +0300 | [diff] [blame] | 1591 | |
| 1592 | /include/ "dra7xx-clocks.dtsi" |