blob: 2f33c463cbce4f1eff456ea75666b22efb3ae5cc [file] [log] [blame]
Frank Li5db106b2015-05-19 02:45:05 +08001/*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44
Stefan Agnera67970a2016-06-26 01:47:53 -070045#include "imx7d.dtsi"
Frank Li5db106b2015-05-19 02:45:05 +080046
47/ {
48 model = "Freescale i.MX7 SabreSD Board";
49 compatible = "fsl,imx7d-sdb", "fsl,imx7d";
50
51 memory {
52 reg = <0x80000000 0x80000000>;
53 };
54
55 regulators {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <0>;
59
60 reg_usb_otg1_vbus: regulator@0 {
61 compatible = "regulator-fixed";
62 reg = <0>;
63 regulator-name = "usb_otg1_vbus";
64 regulator-min-microvolt = <5000000>;
65 regulator-max-microvolt = <5000000>;
66 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
67 enable-active-high;
68 };
69
70 reg_usb_otg2_vbus: regulator@1 {
71 compatible = "regulator-fixed";
72 reg = <1>;
73 regulator-name = "usb_otg2_vbus";
74 regulator-min-microvolt = <5000000>;
75 regulator-max-microvolt = <5000000>;
76 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
77 enable-active-high;
78 };
79
80 reg_can2_3v3: regulator@2 {
81 compatible = "regulator-fixed";
82 reg = <2>;
83 regulator-name = "can2-3v3";
84 regulator-min-microvolt = <3300000>;
85 regulator-max-microvolt = <3300000>;
86 gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
87 };
88
89 reg_vref_1v8: regulator@3 {
90 compatible = "regulator-fixed";
91 reg = <3>;
92 regulator-name = "vref-1v8";
93 regulator-min-microvolt = <1800000>;
94 regulator-max-microvolt = <1800000>;
95 };
96 };
97};
98
Haibo Chen64b83432015-12-08 18:26:23 +080099&adc1 {
100 vref-supply = <&reg_vref_1v8>;
101 status = "okay";
102};
103
104&adc2 {
105 vref-supply = <&reg_vref_1v8>;
106 status = "okay";
107};
108
Frank Li5db106b2015-05-19 02:45:05 +0800109&cpu0 {
110 arm-supply = <&sw1a_reg>;
111};
112
Diego Dortad09e6bea2016-06-22 16:37:09 -0300113&ecspi3 {
114 fsl,spi-num-chipselects = <1>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_ecspi3>;
117 cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
118 status = "okay";
119
120 tsc2046@0 {
121 compatible = "ti,tsc2046";
122 reg = <0>;
123 spi-max-frequency = <1000000>;
124 pinctrl-names ="default";
125 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
126 interrupt-parent = <&gpio2>;
127 interrupts = <29 0>;
128 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
129 ti,x-min = /bits/ 16 <0>;
130 ti,x-max = /bits/ 16 <0>;
131 ti,y-min = /bits/ 16 <0>;
132 ti,y-max = /bits/ 16 <0>;
133 ti,pressure-max = /bits/ 16 <0>;
Vladimir Zapolskiyf7d35862016-08-29 04:41:50 +0300134 ti,x-plate-ohms = /bits/ 16 <400>;
Diego Dortad09e6bea2016-06-22 16:37:09 -0300135 wakeup-source;
136 };
137};
138
Fugang Duan47bcc8c2015-09-07 10:55:02 +0800139&fec1 {
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_enet1>;
142 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
143 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
144 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
145 assigned-clock-rates = <0>, <100000000>;
146 phy-mode = "rgmii";
147 phy-handle = <&ethphy0>;
148 fsl,magic-packet;
149 status = "okay";
150
151 mdio {
152 #address-cells = <1>;
153 #size-cells = <0>;
154
155 ethphy0: ethernet-phy@0 {
156 reg = <0>;
157 };
158
159 ethphy1: ethernet-phy@1 {
160 reg = <1>;
161 };
162 };
163};
164
165&fec2 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_enet2>;
168 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
169 <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
170 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
171 assigned-clock-rates = <0>, <100000000>;
172 phy-mode = "rgmii";
173 phy-handle = <&ethphy1>;
174 fsl,magic-packet;
175 status = "okay";
176};
177
Frank Li5db106b2015-05-19 02:45:05 +0800178&i2c1 {
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_i2c1>;
181 status = "okay";
182
183 pmic: pfuze3000@08 {
184 compatible = "fsl,pfuze3000";
185 reg = <0x08>;
186
187 regulators {
188 sw1a_reg: sw1a {
189 regulator-min-microvolt = <700000>;
190 regulator-max-microvolt = <1475000>;
191 regulator-boot-on;
192 regulator-always-on;
193 regulator-ramp-delay = <6250>;
194 };
195
196 /* use sw1c_reg to align with pfuze100/pfuze200 */
197 sw1c_reg: sw1b {
198 regulator-min-microvolt = <700000>;
199 regulator-max-microvolt = <1475000>;
200 regulator-boot-on;
201 regulator-always-on;
202 regulator-ramp-delay = <6250>;
203 };
204
205 sw2_reg: sw2 {
206 regulator-min-microvolt = <1500000>;
207 regulator-max-microvolt = <1850000>;
208 regulator-boot-on;
209 regulator-always-on;
210 };
211
212 sw3a_reg: sw3 {
213 regulator-min-microvolt = <900000>;
214 regulator-max-microvolt = <1650000>;
215 regulator-boot-on;
216 regulator-always-on;
217 };
218
219 swbst_reg: swbst {
220 regulator-min-microvolt = <5000000>;
221 regulator-max-microvolt = <5150000>;
222 };
223
224 snvs_reg: vsnvs {
225 regulator-min-microvolt = <1000000>;
226 regulator-max-microvolt = <3000000>;
227 regulator-boot-on;
228 regulator-always-on;
229 };
230
231 vref_reg: vrefddr {
232 regulator-boot-on;
233 regulator-always-on;
234 };
235
236 vgen1_reg: vldo1 {
237 regulator-min-microvolt = <1800000>;
238 regulator-max-microvolt = <3300000>;
239 regulator-always-on;
240 };
241
242 vgen2_reg: vldo2 {
243 regulator-min-microvolt = <800000>;
244 regulator-max-microvolt = <1550000>;
245 };
246
247 vgen3_reg: vccsd {
248 regulator-min-microvolt = <2850000>;
249 regulator-max-microvolt = <3300000>;
250 regulator-always-on;
251 };
252
253 vgen4_reg: v33 {
254 regulator-min-microvolt = <2850000>;
255 regulator-max-microvolt = <3300000>;
256 regulator-always-on;
257 };
258
259 vgen5_reg: vldo3 {
260 regulator-min-microvolt = <1800000>;
261 regulator-max-microvolt = <3300000>;
262 regulator-always-on;
263 };
264
265 vgen6_reg: vldo4 {
266 regulator-min-microvolt = <1800000>;
267 regulator-max-microvolt = <3300000>;
268 regulator-always-on;
269 };
270 };
271 };
272};
273
274&i2c2 {
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_i2c2>;
277 status = "okay";
278};
279
280&i2c3 {
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_i2c3>;
283 status = "okay";
284};
285
286&i2c4 {
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_i2c4>;
289 status = "okay";
290
291 codec: wm8960@1a {
292 compatible = "wlf,wm8960";
293 reg = <0x1a>;
294 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
295 clock-names = "mclk";
296 wlf,shared-lrclk;
297 };
298};
299
Diego Dorta41969052016-06-22 16:37:08 -0300300&lcdif {
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_lcdif>;
303 display = <&display0>;
304 status = "okay";
305
306 display0: display {
307 bits-per-pixel = <16>;
308 bus-width = <24>;
309
310 display-timings {
311 native-mode = <&timing0>;
312
313 timing0: timing0 {
314 clock-frequency = <9200000>;
315 hactive = <480>;
316 vactive = <272>;
317 hfront-porch = <8>;
318 hback-porch = <4>;
319 hsync-len = <41>;
320 vback-porch = <2>;
321 vfront-porch = <4>;
322 vsync-len = <10>;
323 hsync-active = <0>;
324 vsync-active = <0>;
325 de-active = <1>;
326 pixelclk-active = <0>;
327 };
328 };
329 };
330};
331
332&pwm1 {
333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_pwm1>;
335 status = "okay";
336};
337
Frank Li5db106b2015-05-19 02:45:05 +0800338&uart1 {
339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_uart1>;
341 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
342 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
343 status = "okay";
344};
345
Fabio Estevama81fd342015-09-07 22:57:12 -0300346&usbotg1 {
347 vbus-supply = <&reg_usb_otg1_vbus>;
348 status = "okay";
349};
350
351&usbotg2 {
352 vbus-supply = <&reg_usb_otg2_vbus>;
353 dr_mode = "host";
354 status = "okay";
355};
356
Frank Li5db106b2015-05-19 02:45:05 +0800357&usdhc1 {
358 pinctrl-names = "default";
359 pinctrl-0 = <&pinctrl_usdhc1>;
Dong Aisheng1cd55942015-07-22 20:53:04 +0800360 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
361 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
Sudeep Holla26cefdd2015-10-21 11:10:08 +0100362 wakeup-source;
Frank Li5db106b2015-05-19 02:45:05 +0800363 keep-power-in-suspend;
364 status = "okay";
365};
366
Haibo Chenf651d782015-08-11 19:38:29 +0800367&usdhc3 {
368 pinctrl-names = "default", "state_100mhz", "state_200mhz";
369 pinctrl-0 = <&pinctrl_usdhc3>;
370 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
371 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
372 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
373 assigned-clock-rates = <400000000>;
374 bus-width = <8>;
375 fsl,tuning-step = <2>;
376 non-removable;
377 status = "okay";
378};
379
Fabio Estevam51fd0322016-06-13 22:07:57 -0300380&wdog1 {
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_wdog>;
383 fsl,ext-reset-output;
384};
385
Frank Li5db106b2015-05-19 02:45:05 +0800386&iomuxc {
387 pinctrl-names = "default";
388 pinctrl-0 = <&pinctrl_hog>;
389
390 imx7d-sdb {
Diego Dortad09e6bea2016-06-22 16:37:09 -0300391 pinctrl_ecspi3: ecspi3grp {
392 fsl,pins = <
393 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2
394 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2
395 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2
396 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59
397 >;
398 };
399
Fugang Duan47bcc8c2015-09-07 10:55:02 +0800400 pinctrl_enet1: enet1grp {
401 fsl,pins = <
402 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
403 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
404 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
405 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
406 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
407 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
408 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
409 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
410 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
411 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
412 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
413 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
414 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
415 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
416 >;
417 };
418
419 pinctrl_enet2: enet2grp {
420 fsl,pins = <
421 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
422 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
423 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
424 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
425 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
426 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
427 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
428 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
429 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
430 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
431 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
432 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
433 >;
434 };
435
Frank Li5db106b2015-05-19 02:45:05 +0800436 pinctrl_hog: hoggrp {
437 fsl,pins = <
438 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
439 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */
440 >;
441 };
442
443 pinctrl_i2c1: i2c1grp {
444 fsl,pins = <
445 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
446 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
447 >;
448 };
449
450 pinctrl_i2c2: i2c2grp {
451 fsl,pins = <
452 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
453 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
454 >;
455 };
456
457 pinctrl_i2c3: i2c3grp {
458 fsl,pins = <
459 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
460 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
461 >;
462 };
463
464 pinctrl_i2c4: i2c4grp {
465 fsl,pins = <
466 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
467 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
468 >;
469 };
470
Diego Dorta41969052016-06-22 16:37:08 -0300471 pinctrl_lcdif: lcdifgrp {
472 fsl,pins = <
473 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
474 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
475 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
476 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
477 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
478 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
479 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
480 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
481 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
482 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
483 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
484 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
485 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
486 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
487 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
488 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
489 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
490 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
491 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
492 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
493 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
494 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
495 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
496 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
497 MX7D_PAD_LCD_CLK__LCD_CLK 0x79
498 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
499 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
500 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
501 MX7D_PAD_LCD_RESET__LCD_RESET 0x79
502 >;
503 };
504
505 pinctrl_pwm1: pwm1grp {
506 fsl,pins = <
507 MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x110b0
508 >;
509 };
510
Diego Dortad09e6bea2016-06-22 16:37:09 -0300511 pinctrl_tsc2046_pendown: tsc2046_pendown {
512 fsl,pins = <
513 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59
514 >;
515 };
516
Frank Li5db106b2015-05-19 02:45:05 +0800517 pinctrl_uart1: uart1grp {
518 fsl,pins = <
519 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
520 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
521 >;
522 };
523
524 pinctrl_uart5: uart5grp {
525 fsl,pins = <
526 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79
527 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79
528 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79
529 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79
530 >;
531 };
532
533 pinctrl_uart6: uart6grp {
534 fsl,pins = <
535 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
536 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
537 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
538 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
539 >;
540 };
541
542 pinctrl_usdhc1: usdhc1grp {
543 fsl,pins = <
544 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
545 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
546 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
547 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
548 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
549 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
550 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
551 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
552 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
553 >;
554 };
555
556 pinctrl_usdhc2: usdhc2grp {
557 fsl,pins = <
558 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
559 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
560 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
561 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
562 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
563 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
564 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59 /* WL_REG_ON */
565 >;
566 };
567
568 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
569 fsl,pins = <
570 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
571 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
572 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
573 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
574 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
575 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
576 >;
577 };
578
579 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
580 fsl,pins = <
581 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
582 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
583 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
584 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
585 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
586 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
587 >;
588 };
589
590
591 pinctrl_usdhc3: usdhc3grp {
592 fsl,pins = <
593 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
594 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
595 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
596 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
597 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
598 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
599 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
600 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
601 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
602 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
603 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
604 >;
605 };
606
607 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
608 fsl,pins = <
609 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
610 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
611 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
612 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
613 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
614 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
615 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
616 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
617 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
618 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
619 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
620 >;
621 };
622
623 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
624 fsl,pins = <
625 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
626 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
627 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
628 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
629 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
630 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
631 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
632 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
633 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
634 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
635 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
636 >;
637 };
638
Fabio Estevam51fd0322016-06-13 22:07:57 -0300639 pinctrl_wdog: wdoggrp {
640 fsl,pins = <
641 MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74
642 >;
643 };
Frank Li5db106b2015-05-19 02:45:05 +0800644 };
645};