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Joe.C0c3fb202014-11-11 15:53:43 +08001/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Joe.C <yingjoe.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
James Liao3cc17a52015-07-07 14:45:10 +020015#include <dt-bindings/clock/mt8135-clk.h>
Joe.C0c3fb202014-11-11 15:53:43 +080016#include <dt-bindings/interrupt-controller/irq.h>
17#include <dt-bindings/interrupt-controller/arm-gic.h>
Philipp Zabel967313e2015-11-20 12:42:44 +010018#include <dt-bindings/reset/mt8135-resets.h>
Joe.C0c3fb202014-11-11 15:53:43 +080019#include "skeleton64.dtsi"
Hongzhou Yangcfb11672015-05-01 14:49:30 +080020#include "mt8135-pinfunc.h"
Joe.C0c3fb202014-11-11 15:53:43 +080021
22/ {
23 compatible = "mediatek,mt8135";
Yingjoe Chene0bed072014-11-25 09:04:00 +010024 interrupt-parent = <&sysirq>;
Joe.C0c3fb202014-11-11 15:53:43 +080025
26 cpu-map {
27 cluster0 {
28 core0 {
29 cpu = <&cpu0>;
30 };
31 core1 {
32 cpu = <&cpu1>;
33 };
34 };
35
36 cluster1 {
37 core0 {
38 cpu = <&cpu2>;
39 };
40 core1 {
41 cpu = <&cpu3>;
42 };
43 };
44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
Yingjoe Chend186a392015-10-02 23:19:40 +080049 enable-method = "mediatek,mt81xx-tz-smp";
Joe.C0c3fb202014-11-11 15:53:43 +080050
51 cpu0: cpu@0 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a7";
54 reg = <0x000>;
55 };
56
57 cpu1: cpu@1 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a7";
60 reg = <0x001>;
61 };
62
63 cpu2: cpu@100 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a15";
66 reg = <0x100>;
67 };
68
69 cpu3: cpu@101 {
70 device_type = "cpu";
71 compatible = "arm,cortex-a15";
72 reg = <0x101>;
73 };
74 };
75
Yingjoe Chend186a392015-10-02 23:19:40 +080076 reserved-memory {
77 #address-cells = <2>;
78 #size-cells = <2>;
79 ranges;
80
81 trustzone-bootinfo@80002000 {
82 compatible = "mediatek,trustzone-bootinfo";
83 reg = <0 0x80002000 0 0x1000>;
84 };
85 };
86
Joe.C0c3fb202014-11-11 15:53:43 +080087 clocks {
88 #address-cells = <2>;
89 #size-cells = <2>;
90 compatible = "simple-bus";
91 ranges;
92
93 system_clk: dummy13m {
94 compatible = "fixed-clock";
95 clock-frequency = <13000000>;
96 #clock-cells = <0>;
97 };
98
99 rtc_clk: dummy32k {
100 compatible = "fixed-clock";
101 clock-frequency = <32000>;
102 #clock-cells = <0>;
103 };
Eddie Huang07149472014-10-22 15:12:00 +0200104
James Liao3cc17a52015-07-07 14:45:10 +0200105 clk26m: clk26m {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <26000000>;
109 };
Joe.C0c3fb202014-11-11 15:53:43 +0800110 };
111
Yingjoe Chend186a392015-10-02 23:19:40 +0800112 timer {
113 compatible = "arm,armv7-timer";
114 interrupt-parent = <&gic>;
115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
116 IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
118 IRQ_TYPE_LEVEL_LOW)>,
119 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
120 IRQ_TYPE_LEVEL_LOW)>,
121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
122 IRQ_TYPE_LEVEL_LOW)>;
123 clock-frequency = <13000000>;
124 arm,cpu-registers-not-fw-configured;
125 };
126
Joe.C0c3fb202014-11-11 15:53:43 +0800127 soc {
128 #address-cells = <2>;
129 #size-cells = <2>;
130 compatible = "simple-bus";
131 ranges;
132
James Liao3cc17a52015-07-07 14:45:10 +0200133 topckgen: topckgen@10000000 {
134 compatible = "mediatek,mt8135-topckgen";
135 reg = <0 0x10000000 0 0x1000>;
136 #clock-cells = <1>;
137 };
138
139 infracfg: infracfg@10001000 {
140 #reset-cells = <1>;
141 #clock-cells = <1>;
142 compatible = "mediatek,mt8135-infracfg", "syscon";
143 reg = <0 0x10001000 0 0x1000>;
144 };
145
146 pericfg: pericfg@10003000 {
147 #reset-cells = <1>;
148 #clock-cells = <1>;
149 compatible = "mediatek,mt8135-pericfg", "syscon";
150 reg = <0 0x10003000 0 0x1000>;
151 };
152
Hongzhou Yangcfb11672015-05-01 14:49:30 +0800153 /*
154 * Pinctrl access register at 0x10005000 and 0x1020c000 through
155 * regmap. Register 0x1000b000 is used by EINT.
156 */
157 pio: pinctrl@10005000 {
158 compatible = "mediatek,mt8135-pinctrl";
159 reg = <0 0x1000b000 0 0x1000>;
160 mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
161 pins-are-numbered;
162 gpio-controller;
163 #gpio-cells = <2>;
164 interrupt-controller;
165 #interrupt-cells = <2>;
166 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
169 };
170
171 syscfg_pctl_a: syscfg_pctl_a@10005000 {
172 compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
173 reg = <0 0x10005000 0 0x1000>;
174 };
175
Joe.C0c3fb202014-11-11 15:53:43 +0800176 timer: timer@10008000 {
177 compatible = "mediatek,mt8135-timer",
178 "mediatek,mt6577-timer";
179 reg = <0 0x10008000 0 0x80>;
Yingjoe Chene0bed072014-11-25 09:04:00 +0100180 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
Joe.C0c3fb202014-11-11 15:53:43 +0800181 clocks = <&system_clk>, <&rtc_clk>;
182 clock-names = "system-clk", "rtc-clk";
183 };
184
Sascha Hauer8dd29d22015-07-07 14:45:11 +0200185 pwrap: pwrap@1000f000 {
186 compatible = "mediatek,mt8135-pwrap";
187 reg = <0 0x1000f000 0 0x1000>,
188 <0 0x11017000 0 0x1000>;
189 reg-names = "pwrap", "pwrap-bridge";
190 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
191 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
192 <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
193 reset-names = "pwrap", "pwrap-bridge";
194 clocks = <&clk26m>, <&clk26m>;
195 clock-names = "spi", "wrap";
196 };
197
Yingjoe Chene0bed072014-11-25 09:04:00 +0100198 sysirq: interrupt-controller@10200030 {
199 compatible = "mediatek,mt8135-sysirq",
200 "mediatek,mt6577-sysirq";
201 interrupt-controller;
202 #interrupt-cells = <3>;
203 interrupt-parent = <&gic>;
204 reg = <0 0x10200030 0 0x1c>;
205 };
206
James Liao3cc17a52015-07-07 14:45:10 +0200207 apmixedsys: apmixedsys@10209000 {
208 compatible = "mediatek,mt8135-apmixedsys";
209 reg = <0 0x10209000 0 0x1000>;
210 #clock-cells = <1>;
211 };
212
Hongzhou Yangcfb11672015-05-01 14:49:30 +0800213 syscfg_pctl_b: syscfg_pctl_b@1020c000 {
214 compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
215 reg = <0 0x1020c000 0 0x1000>;
216 };
217
Joe.C0c3fb202014-11-11 15:53:43 +0800218 gic: interrupt-controller@10211000 {
219 compatible = "arm,cortex-a15-gic";
220 interrupt-controller;
221 #interrupt-cells = <3>;
Yingjoe Chene0bed072014-11-25 09:04:00 +0100222 interrupt-parent = <&gic>;
Joe.C0c3fb202014-11-11 15:53:43 +0800223 reg = <0 0x10211000 0 0x1000>,
224 <0 0x10212000 0 0x1000>,
225 <0 0x10214000 0 0x2000>,
226 <0 0x10216000 0 0x2000>;
227 };
Eddie Huang07149472014-10-22 15:12:00 +0200228
229 uart0: serial@11006000 {
230 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
231 reg = <0 0x11006000 0 0x400>;
232 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
Sascha Hauerd57b1d22015-07-07 14:45:13 +0200233 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
234 clock-names = "baud", "bus";
Eddie Huang07149472014-10-22 15:12:00 +0200235 status = "disabled";
236 };
237
238 uart1: serial@11007000 {
239 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
240 reg = <0 0x11007000 0 0x400>;
241 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
Sascha Hauerd57b1d22015-07-07 14:45:13 +0200242 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
243 clock-names = "baud", "bus";
Eddie Huang07149472014-10-22 15:12:00 +0200244 status = "disabled";
245 };
246
247 uart2: serial@11008000 {
248 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
249 reg = <0 0x11008000 0 0x400>;
250 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
Sascha Hauerd57b1d22015-07-07 14:45:13 +0200251 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
252 clock-names = "baud", "bus";
Eddie Huang07149472014-10-22 15:12:00 +0200253 status = "disabled";
254 };
255
256 uart3: serial@11009000 {
257 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
258 reg = <0 0x11009000 0 0x400>;
259 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
Sascha Hauerd57b1d22015-07-07 14:45:13 +0200260 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
261 clock-names = "baud", "bus";
Eddie Huang07149472014-10-22 15:12:00 +0200262 status = "disabled";
263 };
264
Joe.C0c3fb202014-11-11 15:53:43 +0800265 };
266};