blob: bc3af78a869ff52881077b89cf6e5e544b6e8a91 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
Matt Carlsonba5b0bf2010-01-12 10:11:40 +00007 * Copyright (C) 2005-2010 Broadcom Corporation.
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * Firmware is:
Michael Chan49cabf42005-06-06 15:15:17 -070010 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
Linus Torvalds1da177e2005-04-16 15:20:36 -070016 */
17
Linus Torvalds1da177e2005-04-16 15:20:36 -070018
19#include <linux/module.h>
20#include <linux/moduleparam.h>
Matt Carlson6867c842010-07-11 09:31:44 +000021#include <linux/stringify.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
Arnaldo Carvalho de Melo14c85022005-12-27 02:43:12 -020027#include <linux/in.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <linux/init.h>
29#include <linux/ioport.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/ethtool.h>
35#include <linux/mii.h>
Matt Carlson158d7ab2008-05-29 01:37:54 -070036#include <linux/phy.h>
Matt Carlsona9daf362008-05-25 23:49:44 -070037#include <linux/brcmphy.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#include <linux/if_vlan.h>
39#include <linux/ip.h>
40#include <linux/tcp.h>
41#include <linux/workqueue.h>
Michael Chan61487482005-09-05 17:53:19 -070042#include <linux/prefetch.h>
Tobias Klauserf9a5f7d2005-10-29 15:09:26 +020043#include <linux/dma-mapping.h>
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -080044#include <linux/firmware.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045
46#include <net/checksum.h>
Arnaldo Carvalho de Meloc9bdd4b2007-03-12 20:09:15 -030047#include <net/ip.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
49#include <asm/system.h>
50#include <asm/io.h>
51#include <asm/byteorder.h>
52#include <asm/uaccess.h>
53
David S. Miller49b6e95f2007-03-29 01:38:42 -070054#ifdef CONFIG_SPARC
Linus Torvalds1da177e2005-04-16 15:20:36 -070055#include <asm/idprom.h>
David S. Miller49b6e95f2007-03-29 01:38:42 -070056#include <asm/prom.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070057#endif
58
Matt Carlson63532392008-11-03 16:49:57 -080059#define BAR_0 0
60#define BAR_2 2
61
Linus Torvalds1da177e2005-04-16 15:20:36 -070062#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
63#define TG3_VLAN_TAG_USED 1
64#else
65#define TG3_VLAN_TAG_USED 0
66#endif
67
Linus Torvalds1da177e2005-04-16 15:20:36 -070068#include "tg3.h"
69
70#define DRV_MODULE_NAME "tg3"
Matt Carlson6867c842010-07-11 09:31:44 +000071#define TG3_MAJ_NUM 3
Matt Carlson9ed6eda2010-08-02 11:26:08 +000072#define TG3_MIN_NUM 113
Matt Carlson6867c842010-07-11 09:31:44 +000073#define DRV_MODULE_VERSION \
74 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
Matt Carlson9ed6eda2010-08-02 11:26:08 +000075#define DRV_MODULE_RELDATE "August 2, 2010"
Linus Torvalds1da177e2005-04-16 15:20:36 -070076
77#define TG3_DEF_MAC_MODE 0
78#define TG3_DEF_RX_MODE 0
79#define TG3_DEF_TX_MODE 0
80#define TG3_DEF_MSG_ENABLE \
81 (NETIF_MSG_DRV | \
82 NETIF_MSG_PROBE | \
83 NETIF_MSG_LINK | \
84 NETIF_MSG_TIMER | \
85 NETIF_MSG_IFDOWN | \
86 NETIF_MSG_IFUP | \
87 NETIF_MSG_RX_ERR | \
88 NETIF_MSG_TX_ERR)
89
90/* length of time before we decide the hardware is borked,
91 * and dev->tx_timeout() should be called to fix the problem
92 */
93#define TG3_TX_TIMEOUT (5 * HZ)
94
95/* hardware minimum and maximum for a single frame's data payload */
96#define TG3_MIN_MTU 60
97#define TG3_MAX_MTU(tp) \
Matt Carlson8f666b02009-08-28 13:58:24 +000098 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
Linus Torvalds1da177e2005-04-16 15:20:36 -070099
100/* These numbers seem to be hard coded in the NIC firmware somehow.
101 * You can't change the ring sizes, but you can change where you place
102 * them in the NIC onboard memory.
103 */
104#define TG3_RX_RING_SIZE 512
105#define TG3_DEF_RX_RING_PENDING 200
106#define TG3_RX_JUMBO_RING_SIZE 256
107#define TG3_DEF_RX_JUMBO_RING_PENDING 100
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000108#define TG3_RSS_INDIR_TBL_SIZE 128
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109
110/* Do not place this n-ring entries value into the tp struct itself,
111 * we really want to expose these constants to GCC so that modulo et
112 * al. operations are done with shifts and masks instead of with
113 * hw multiply/modulo instructions. Another solution would be to
114 * replace things like '% foo' with '& (foo - 1)'.
115 */
116#define TG3_RX_RCB_RING_SIZE(tp) \
Matt Carlsonf6eb9b12009-09-01 13:19:53 +0000117 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
Matt Carlson5ea1c502009-09-11 16:50:16 -0700118 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119
120#define TG3_TX_RING_SIZE 512
121#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
122
123#define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
124 TG3_RX_RING_SIZE)
Matt Carlson79ed5ac2009-08-28 14:00:55 +0000125#define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
126 TG3_RX_JUMBO_RING_SIZE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127#define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
Matt Carlson79ed5ac2009-08-28 14:00:55 +0000128 TG3_RX_RCB_RING_SIZE(tp))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
130 TG3_TX_RING_SIZE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
132
Matt Carlson9dc7a112010-04-12 06:58:28 +0000133#define TG3_RX_DMA_ALIGN 16
134#define TG3_RX_HEADROOM ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
135
Matt Carlson287be122009-08-28 13:58:46 +0000136#define TG3_DMA_BYTE_ENAB 64
137
138#define TG3_RX_STD_DMA_SZ 1536
139#define TG3_RX_JMB_DMA_SZ 9046
140
141#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
142
143#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
144#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145
Matt Carlson2b2cdb62009-11-13 13:03:48 +0000146#define TG3_RX_STD_BUFF_RING_SIZE \
147 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
148
149#define TG3_RX_JMB_BUFF_RING_SIZE \
150 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
151
Matt Carlsond2757fc2010-04-12 06:58:27 +0000152/* Due to a hardware bug, the 5701 can only DMA to memory addresses
153 * that are at least dword aligned when used in PCIX mode. The driver
154 * works around this bug by double copying the packet. This workaround
155 * is built into the normal double copy length check for efficiency.
156 *
157 * However, the double copy is only necessary on those architectures
158 * where unaligned memory accesses are inefficient. For those architectures
159 * where unaligned memory accesses incur little penalty, we can reintegrate
160 * the 5701 in the normal rx path. Doing so saves a device structure
161 * dereference by hardcoding the double copy threshold in place.
162 */
163#define TG3_RX_COPY_THRESHOLD 256
164#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
165 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
166#else
167 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
168#endif
169
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170/* minimum number of free TX descriptors required to wake up TX process */
Matt Carlsonf3f3f272009-08-28 14:03:21 +0000171#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172
Matt Carlsonad829262008-11-21 17:16:16 -0800173#define TG3_RAW_IP_ALIGN 2
174
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175/* number of ETHTOOL_GSTATS u64's */
176#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
177
Michael Chan4cafd3f2005-05-29 14:56:34 -0700178#define TG3_NUM_TEST 6
179
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000180#define TG3_FW_UPDATE_TIMEOUT_SEC 5
181
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -0800182#define FIRMWARE_TG3 "tigon/tg3.bin"
183#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
184#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
185
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186static char version[] __devinitdata =
Joe Perches05dbe002010-02-17 19:44:19 +0000187 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188
189MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
190MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
191MODULE_LICENSE("GPL");
192MODULE_VERSION(DRV_MODULE_VERSION);
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -0800193MODULE_FIRMWARE(FIRMWARE_TG3);
194MODULE_FIRMWARE(FIRMWARE_TG3TSO);
195MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
196
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
198module_param(tg3_debug, int, 0);
199MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
200
Alexey Dobriyana3aa1882010-01-07 11:58:11 +0000201static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
Michael Chan126a3362006-09-27 16:03:07 -0700225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
Michael Chan126a3362006-09-27 16:03:07 -0700238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
Michael Chan676917d2006-12-07 00:20:22 -0800242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
Michael Chanb5d37722006-09-27 16:06:21 -0700250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
Matt Carlsond30cdd22007-10-07 23:28:35 -0700252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
Matt Carlson6c7af272007-10-21 16:12:02 -0700254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
Matt Carlson9936bcf2007-10-10 18:03:07 -0700255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
Matt Carlsonc88e6682008-11-03 16:49:18 -0800257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
Matt Carlson2befdce2009-08-28 12:28:45 +0000259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
Matt Carlson321d32a2008-11-21 17:22:19 -0800261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
Matt Carlson5e7ccf22009-08-25 10:08:42 +0000264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
Matt Carlson5001e2f2009-11-13 13:03:51 +0000265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
Matt Carlsonb0f75222010-01-20 16:58:11 +0000268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
Matt Carlson302b5002010-06-05 17:24:38 +0000274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700275 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
276 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
277 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
278 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
279 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
280 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
281 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
282 {}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283};
284
285MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
286
Andreas Mohr50da8592006-08-14 23:54:30 -0700287static const struct {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288 const char string[ETH_GSTRING_LEN];
289} ethtool_stats_keys[TG3_NUM_STATS] = {
290 { "rx_octets" },
291 { "rx_fragments" },
292 { "rx_ucast_packets" },
293 { "rx_mcast_packets" },
294 { "rx_bcast_packets" },
295 { "rx_fcs_errors" },
296 { "rx_align_errors" },
297 { "rx_xon_pause_rcvd" },
298 { "rx_xoff_pause_rcvd" },
299 { "rx_mac_ctrl_rcvd" },
300 { "rx_xoff_entered" },
301 { "rx_frame_too_long_errors" },
302 { "rx_jabbers" },
303 { "rx_undersize_packets" },
304 { "rx_in_length_errors" },
305 { "rx_out_length_errors" },
306 { "rx_64_or_less_octet_packets" },
307 { "rx_65_to_127_octet_packets" },
308 { "rx_128_to_255_octet_packets" },
309 { "rx_256_to_511_octet_packets" },
310 { "rx_512_to_1023_octet_packets" },
311 { "rx_1024_to_1522_octet_packets" },
312 { "rx_1523_to_2047_octet_packets" },
313 { "rx_2048_to_4095_octet_packets" },
314 { "rx_4096_to_8191_octet_packets" },
315 { "rx_8192_to_9022_octet_packets" },
316
317 { "tx_octets" },
318 { "tx_collisions" },
319
320 { "tx_xon_sent" },
321 { "tx_xoff_sent" },
322 { "tx_flow_control" },
323 { "tx_mac_errors" },
324 { "tx_single_collisions" },
325 { "tx_mult_collisions" },
326 { "tx_deferred" },
327 { "tx_excessive_collisions" },
328 { "tx_late_collisions" },
329 { "tx_collide_2times" },
330 { "tx_collide_3times" },
331 { "tx_collide_4times" },
332 { "tx_collide_5times" },
333 { "tx_collide_6times" },
334 { "tx_collide_7times" },
335 { "tx_collide_8times" },
336 { "tx_collide_9times" },
337 { "tx_collide_10times" },
338 { "tx_collide_11times" },
339 { "tx_collide_12times" },
340 { "tx_collide_13times" },
341 { "tx_collide_14times" },
342 { "tx_collide_15times" },
343 { "tx_ucast_packets" },
344 { "tx_mcast_packets" },
345 { "tx_bcast_packets" },
346 { "tx_carrier_sense_errors" },
347 { "tx_discards" },
348 { "tx_errors" },
349
350 { "dma_writeq_full" },
351 { "dma_write_prioq_full" },
352 { "rxbds_empty" },
353 { "rx_discards" },
354 { "rx_errors" },
355 { "rx_threshold_hit" },
356
357 { "dma_readq_full" },
358 { "dma_read_prioq_full" },
359 { "tx_comp_queue_full" },
360
361 { "ring_set_send_prod_index" },
362 { "ring_status_update" },
363 { "nic_irqs" },
364 { "nic_avoided_irqs" },
365 { "nic_tx_threshold_hit" }
366};
367
Andreas Mohr50da8592006-08-14 23:54:30 -0700368static const struct {
Michael Chan4cafd3f2005-05-29 14:56:34 -0700369 const char string[ETH_GSTRING_LEN];
370} ethtool_test_keys[TG3_NUM_TEST] = {
371 { "nvram test (online) " },
372 { "link test (online) " },
373 { "register test (offline)" },
374 { "memory test (offline)" },
375 { "loopback test (offline)" },
376 { "interrupt test (offline)" },
377};
378
Michael Chanb401e9e2005-12-19 16:27:04 -0800379static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
380{
381 writel(val, tp->regs + off);
382}
383
384static u32 tg3_read32(struct tg3 *tp, u32 off)
385{
Matt Carlsonde6f31e2010-04-12 06:58:30 +0000386 return readl(tp->regs + off);
Michael Chanb401e9e2005-12-19 16:27:04 -0800387}
388
Matt Carlson0d3031d2007-10-10 18:02:43 -0700389static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
390{
391 writel(val, tp->aperegs + off);
392}
393
394static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
395{
Matt Carlsonde6f31e2010-04-12 06:58:30 +0000396 return readl(tp->aperegs + off);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700397}
398
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
400{
Michael Chan68929142005-08-09 20:17:14 -0700401 unsigned long flags;
402
403 spin_lock_irqsave(&tp->indirect_lock, flags);
Michael Chan1ee582d2005-08-09 20:16:46 -0700404 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
405 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
Michael Chan68929142005-08-09 20:17:14 -0700406 spin_unlock_irqrestore(&tp->indirect_lock, flags);
Michael Chan1ee582d2005-08-09 20:16:46 -0700407}
408
409static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
410{
411 writel(val, tp->regs + off);
412 readl(tp->regs + off);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413}
414
Michael Chan68929142005-08-09 20:17:14 -0700415static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
416{
417 unsigned long flags;
418 u32 val;
419
420 spin_lock_irqsave(&tp->indirect_lock, flags);
421 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
422 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
423 spin_unlock_irqrestore(&tp->indirect_lock, flags);
424 return val;
425}
426
427static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
428{
429 unsigned long flags;
430
431 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
432 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
433 TG3_64BIT_REG_LOW, val);
434 return;
435 }
Matt Carlson66711e62009-11-13 13:03:49 +0000436 if (off == TG3_RX_STD_PROD_IDX_REG) {
Michael Chan68929142005-08-09 20:17:14 -0700437 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
438 TG3_64BIT_REG_LOW, val);
439 return;
440 }
441
442 spin_lock_irqsave(&tp->indirect_lock, flags);
443 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
444 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
445 spin_unlock_irqrestore(&tp->indirect_lock, flags);
446
447 /* In indirect mode when disabling interrupts, we also need
448 * to clear the interrupt bit in the GRC local ctrl register.
449 */
450 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
451 (val == 0x1)) {
452 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
453 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
454 }
455}
456
457static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
458{
459 unsigned long flags;
460 u32 val;
461
462 spin_lock_irqsave(&tp->indirect_lock, flags);
463 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
464 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
465 spin_unlock_irqrestore(&tp->indirect_lock, flags);
466 return val;
467}
468
Michael Chanb401e9e2005-12-19 16:27:04 -0800469/* usec_wait specifies the wait time in usec when writing to certain registers
470 * where it is unsafe to read back the register without some delay.
471 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
472 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
473 */
474static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475{
Michael Chanb401e9e2005-12-19 16:27:04 -0800476 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
477 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
478 /* Non-posted methods */
479 tp->write32(tp, off, val);
480 else {
481 /* Posted method */
482 tg3_write32(tp, off, val);
483 if (usec_wait)
484 udelay(usec_wait);
485 tp->read32(tp, off);
486 }
487 /* Wait again after the read for the posted method to guarantee that
488 * the wait time is met.
489 */
490 if (usec_wait)
491 udelay(usec_wait);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492}
493
Michael Chan09ee9292005-08-09 20:17:00 -0700494static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
495{
496 tp->write32_mbox(tp, off, val);
Michael Chan68929142005-08-09 20:17:14 -0700497 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
498 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
499 tp->read32_mbox(tp, off);
Michael Chan09ee9292005-08-09 20:17:00 -0700500}
501
Michael Chan20094932005-08-09 20:16:32 -0700502static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503{
504 void __iomem *mbox = tp->regs + off;
505 writel(val, mbox);
506 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
507 writel(val, mbox);
508 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
509 readl(mbox);
510}
511
Michael Chanb5d37722006-09-27 16:06:21 -0700512static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
513{
Matt Carlsonde6f31e2010-04-12 06:58:30 +0000514 return readl(tp->regs + off + GRCMBOX_BASE);
Michael Chanb5d37722006-09-27 16:06:21 -0700515}
516
517static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
518{
519 writel(val, tp->regs + off + GRCMBOX_BASE);
520}
521
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000522#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
Michael Chan09ee9292005-08-09 20:17:00 -0700523#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000524#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
525#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
526#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
Michael Chan20094932005-08-09 20:16:32 -0700527
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000528#define tw32(reg, val) tp->write32(tp, reg, val)
529#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
530#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
531#define tr32(reg) tp->read32(tp, reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700532
533static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
534{
Michael Chan68929142005-08-09 20:17:14 -0700535 unsigned long flags;
536
Michael Chanb5d37722006-09-27 16:06:21 -0700537 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
538 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
539 return;
540
Michael Chan68929142005-08-09 20:17:14 -0700541 spin_lock_irqsave(&tp->indirect_lock, flags);
Michael Chanbbadf502006-04-06 21:46:34 -0700542 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
543 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
544 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700545
Michael Chanbbadf502006-04-06 21:46:34 -0700546 /* Always leave this as zero. */
547 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
548 } else {
549 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
550 tw32_f(TG3PCI_MEM_WIN_DATA, val);
551
552 /* Always leave this as zero. */
553 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
554 }
Michael Chan68929142005-08-09 20:17:14 -0700555 spin_unlock_irqrestore(&tp->indirect_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556}
557
558static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
559{
Michael Chan68929142005-08-09 20:17:14 -0700560 unsigned long flags;
561
Michael Chanb5d37722006-09-27 16:06:21 -0700562 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
563 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
564 *val = 0;
565 return;
566 }
567
Michael Chan68929142005-08-09 20:17:14 -0700568 spin_lock_irqsave(&tp->indirect_lock, flags);
Michael Chanbbadf502006-04-06 21:46:34 -0700569 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
570 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
571 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700572
Michael Chanbbadf502006-04-06 21:46:34 -0700573 /* Always leave this as zero. */
574 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
575 } else {
576 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
577 *val = tr32(TG3PCI_MEM_WIN_DATA);
578
579 /* Always leave this as zero. */
580 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
581 }
Michael Chan68929142005-08-09 20:17:14 -0700582 spin_unlock_irqrestore(&tp->indirect_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700583}
584
Matt Carlson0d3031d2007-10-10 18:02:43 -0700585static void tg3_ape_lock_init(struct tg3 *tp)
586{
587 int i;
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000588 u32 regbase;
589
590 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
591 regbase = TG3_APE_LOCK_GRANT;
592 else
593 regbase = TG3_APE_PER_LOCK_GRANT;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700594
595 /* Make sure the driver hasn't any stale locks. */
596 for (i = 0; i < 8; i++)
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000597 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700598}
599
600static int tg3_ape_lock(struct tg3 *tp, int locknum)
601{
602 int i, off;
603 int ret = 0;
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000604 u32 status, req, gnt;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700605
606 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
607 return 0;
608
609 switch (locknum) {
Matt Carlson33f401a2010-04-05 10:19:27 +0000610 case TG3_APE_LOCK_GRC:
611 case TG3_APE_LOCK_MEM:
612 break;
613 default:
614 return -EINVAL;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700615 }
616
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000617 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
618 req = TG3_APE_LOCK_REQ;
619 gnt = TG3_APE_LOCK_GRANT;
620 } else {
621 req = TG3_APE_PER_LOCK_REQ;
622 gnt = TG3_APE_PER_LOCK_GRANT;
623 }
624
Matt Carlson0d3031d2007-10-10 18:02:43 -0700625 off = 4 * locknum;
626
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000627 tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700628
629 /* Wait for up to 1 millisecond to acquire lock. */
630 for (i = 0; i < 100; i++) {
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000631 status = tg3_ape_read32(tp, gnt + off);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700632 if (status == APE_LOCK_GRANT_DRIVER)
633 break;
634 udelay(10);
635 }
636
637 if (status != APE_LOCK_GRANT_DRIVER) {
638 /* Revoke the lock request. */
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000639 tg3_ape_write32(tp, gnt + off,
Matt Carlson0d3031d2007-10-10 18:02:43 -0700640 APE_LOCK_GRANT_DRIVER);
641
642 ret = -EBUSY;
643 }
644
645 return ret;
646}
647
648static void tg3_ape_unlock(struct tg3 *tp, int locknum)
649{
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000650 u32 gnt;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700651
652 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
653 return;
654
655 switch (locknum) {
Matt Carlson33f401a2010-04-05 10:19:27 +0000656 case TG3_APE_LOCK_GRC:
657 case TG3_APE_LOCK_MEM:
658 break;
659 default:
660 return;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700661 }
662
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000663 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
664 gnt = TG3_APE_LOCK_GRANT;
665 else
666 gnt = TG3_APE_PER_LOCK_GRANT;
667
668 tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700669}
670
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671static void tg3_disable_ints(struct tg3 *tp)
672{
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000673 int i;
674
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675 tw32(TG3PCI_MISC_HOST_CTRL,
676 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000677 for (i = 0; i < tp->irq_max; i++)
678 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679}
680
Linus Torvalds1da177e2005-04-16 15:20:36 -0700681static void tg3_enable_ints(struct tg3 *tp)
682{
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000683 int i;
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000684
Michael Chanbbe832c2005-06-24 20:20:04 -0700685 tp->irq_sync = 0;
686 wmb();
687
Linus Torvalds1da177e2005-04-16 15:20:36 -0700688 tw32(TG3PCI_MISC_HOST_CTRL,
689 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
Matt Carlsonf19af9c2009-09-01 12:47:49 +0000690
Matt Carlsonf89f38b2010-02-12 14:47:07 +0000691 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000692 for (i = 0; i < tp->irq_cnt; i++) {
693 struct tg3_napi *tnapi = &tp->napi[i];
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000694
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000695 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
696 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
697 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
698
Matt Carlsonf89f38b2010-02-12 14:47:07 +0000699 tp->coal_now |= tnapi->coal_now;
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000700 }
Matt Carlsonf19af9c2009-09-01 12:47:49 +0000701
702 /* Force an initial interrupt */
703 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
704 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
705 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
706 else
Matt Carlsonf89f38b2010-02-12 14:47:07 +0000707 tw32(HOSTCC_MODE, tp->coal_now);
708
709 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700710}
711
Matt Carlson17375d22009-08-28 14:02:18 +0000712static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
Michael Chan04237dd2005-04-25 15:17:17 -0700713{
Matt Carlson17375d22009-08-28 14:02:18 +0000714 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +0000715 struct tg3_hw_status *sblk = tnapi->hw_status;
Michael Chan04237dd2005-04-25 15:17:17 -0700716 unsigned int work_exists = 0;
717
718 /* check for phy events */
719 if (!(tp->tg3_flags &
720 (TG3_FLAG_USE_LINKCHG_REG |
721 TG3_FLAG_POLL_SERDES))) {
722 if (sblk->status & SD_STATUS_LINK_CHG)
723 work_exists = 1;
724 }
725 /* check for RX/TX work to do */
Matt Carlsonf3f3f272009-08-28 14:03:21 +0000726 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
Matt Carlson8d9d7cf2009-09-01 13:19:05 +0000727 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
Michael Chan04237dd2005-04-25 15:17:17 -0700728 work_exists = 1;
729
730 return work_exists;
731}
732
Matt Carlson17375d22009-08-28 14:02:18 +0000733/* tg3_int_reenable
Michael Chan04237dd2005-04-25 15:17:17 -0700734 * similar to tg3_enable_ints, but it accurately determines whether there
735 * is new work pending and can return without flushing the PIO write
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400736 * which reenables interrupts
Linus Torvalds1da177e2005-04-16 15:20:36 -0700737 */
Matt Carlson17375d22009-08-28 14:02:18 +0000738static void tg3_int_reenable(struct tg3_napi *tnapi)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700739{
Matt Carlson17375d22009-08-28 14:02:18 +0000740 struct tg3 *tp = tnapi->tp;
741
Matt Carlson898a56f2009-08-28 14:02:40 +0000742 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700743 mmiowb();
744
David S. Millerfac9b832005-05-18 22:46:34 -0700745 /* When doing tagged status, this work check is unnecessary.
746 * The last_tag we write above tells the chip which piece of
747 * work we've completed.
748 */
749 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
Matt Carlson17375d22009-08-28 14:02:18 +0000750 tg3_has_work(tnapi))
Michael Chan04237dd2005-04-25 15:17:17 -0700751 tw32(HOSTCC_MODE, tp->coalesce_mode |
Matt Carlsonfd2ce372009-09-01 12:51:13 +0000752 HOSTCC_MODE_ENABLE | tnapi->coal_now);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700753}
754
Matt Carlsonfed97812009-09-01 13:10:19 +0000755static void tg3_napi_disable(struct tg3 *tp)
756{
757 int i;
758
759 for (i = tp->irq_cnt - 1; i >= 0; i--)
760 napi_disable(&tp->napi[i].napi);
761}
762
763static void tg3_napi_enable(struct tg3 *tp)
764{
765 int i;
766
767 for (i = 0; i < tp->irq_cnt; i++)
768 napi_enable(&tp->napi[i].napi);
769}
770
Linus Torvalds1da177e2005-04-16 15:20:36 -0700771static inline void tg3_netif_stop(struct tg3 *tp)
772{
Michael Chanbbe832c2005-06-24 20:20:04 -0700773 tp->dev->trans_start = jiffies; /* prevent tx timeout */
Matt Carlsonfed97812009-09-01 13:10:19 +0000774 tg3_napi_disable(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700775 netif_tx_disable(tp->dev);
776}
777
778static inline void tg3_netif_start(struct tg3 *tp)
779{
Matt Carlsonfe5f5782009-09-01 13:09:39 +0000780 /* NOTE: unconditional netif_tx_wake_all_queues is only
781 * appropriate so long as all callers are assured to
782 * have free tx slots (such as after tg3_init_hw)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783 */
Matt Carlsonfe5f5782009-09-01 13:09:39 +0000784 netif_tx_wake_all_queues(tp->dev);
785
Matt Carlsonfed97812009-09-01 13:10:19 +0000786 tg3_napi_enable(tp);
787 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
David S. Millerf47c11e2005-06-24 20:18:35 -0700788 tg3_enable_ints(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700789}
790
791static void tg3_switch_clocks(struct tg3 *tp)
792{
Matt Carlsonf6eb9b12009-09-01 13:19:53 +0000793 u32 clock_ctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794 u32 orig_clock_ctrl;
795
Matt Carlson795d01c2007-10-07 23:28:17 -0700796 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
797 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
Michael Chan4cf78e42005-07-25 12:29:19 -0700798 return;
799
Matt Carlsonf6eb9b12009-09-01 13:19:53 +0000800 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
801
Linus Torvalds1da177e2005-04-16 15:20:36 -0700802 orig_clock_ctrl = clock_ctrl;
803 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
804 CLOCK_CTRL_CLKRUN_OENABLE |
805 0x1f);
806 tp->pci_clock_ctrl = clock_ctrl;
807
808 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
809 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
Michael Chanb401e9e2005-12-19 16:27:04 -0800810 tw32_wait_f(TG3PCI_CLOCK_CTRL,
811 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700812 }
813 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
Michael Chanb401e9e2005-12-19 16:27:04 -0800814 tw32_wait_f(TG3PCI_CLOCK_CTRL,
815 clock_ctrl |
816 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
817 40);
818 tw32_wait_f(TG3PCI_CLOCK_CTRL,
819 clock_ctrl | (CLOCK_CTRL_ALTCLK),
820 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700821 }
Michael Chanb401e9e2005-12-19 16:27:04 -0800822 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700823}
824
825#define PHY_BUSY_LOOPS 5000
826
827static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
828{
829 u32 frame_val;
830 unsigned int loops;
831 int ret;
832
833 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
834 tw32_f(MAC_MI_MODE,
835 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
836 udelay(80);
837 }
838
839 *val = 0x0;
840
Matt Carlson882e9792009-09-01 13:21:36 +0000841 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842 MI_COM_PHY_ADDR_MASK);
843 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
844 MI_COM_REG_ADDR_MASK);
845 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400846
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847 tw32_f(MAC_MI_COM, frame_val);
848
849 loops = PHY_BUSY_LOOPS;
850 while (loops != 0) {
851 udelay(10);
852 frame_val = tr32(MAC_MI_COM);
853
854 if ((frame_val & MI_COM_BUSY) == 0) {
855 udelay(5);
856 frame_val = tr32(MAC_MI_COM);
857 break;
858 }
859 loops -= 1;
860 }
861
862 ret = -EBUSY;
863 if (loops != 0) {
864 *val = frame_val & MI_COM_DATA_MASK;
865 ret = 0;
866 }
867
868 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
869 tw32_f(MAC_MI_MODE, tp->mi_mode);
870 udelay(80);
871 }
872
873 return ret;
874}
875
876static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
877{
878 u32 frame_val;
879 unsigned int loops;
880 int ret;
881
Matt Carlsonf07e9af2010-08-02 11:26:07 +0000882 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
Michael Chanb5d37722006-09-27 16:06:21 -0700883 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
884 return 0;
885
Linus Torvalds1da177e2005-04-16 15:20:36 -0700886 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
887 tw32_f(MAC_MI_MODE,
888 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
889 udelay(80);
890 }
891
Matt Carlson882e9792009-09-01 13:21:36 +0000892 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
Linus Torvalds1da177e2005-04-16 15:20:36 -0700893 MI_COM_PHY_ADDR_MASK);
894 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
895 MI_COM_REG_ADDR_MASK);
896 frame_val |= (val & MI_COM_DATA_MASK);
897 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400898
Linus Torvalds1da177e2005-04-16 15:20:36 -0700899 tw32_f(MAC_MI_COM, frame_val);
900
901 loops = PHY_BUSY_LOOPS;
902 while (loops != 0) {
903 udelay(10);
904 frame_val = tr32(MAC_MI_COM);
905 if ((frame_val & MI_COM_BUSY) == 0) {
906 udelay(5);
907 frame_val = tr32(MAC_MI_COM);
908 break;
909 }
910 loops -= 1;
911 }
912
913 ret = -EBUSY;
914 if (loops != 0)
915 ret = 0;
916
917 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
918 tw32_f(MAC_MI_MODE, tp->mi_mode);
919 udelay(80);
920 }
921
922 return ret;
923}
924
Matt Carlson95e28692008-05-25 23:44:14 -0700925static int tg3_bmcr_reset(struct tg3 *tp)
926{
927 u32 phy_control;
928 int limit, err;
929
930 /* OK, reset it, and poll the BMCR_RESET bit until it
931 * clears or we time out.
932 */
933 phy_control = BMCR_RESET;
934 err = tg3_writephy(tp, MII_BMCR, phy_control);
935 if (err != 0)
936 return -EBUSY;
937
938 limit = 5000;
939 while (limit--) {
940 err = tg3_readphy(tp, MII_BMCR, &phy_control);
941 if (err != 0)
942 return -EBUSY;
943
944 if ((phy_control & BMCR_RESET) == 0) {
945 udelay(40);
946 break;
947 }
948 udelay(10);
949 }
Roel Kluind4675b52009-02-12 16:33:27 -0800950 if (limit < 0)
Matt Carlson95e28692008-05-25 23:44:14 -0700951 return -EBUSY;
952
953 return 0;
954}
955
Matt Carlson158d7ab2008-05-29 01:37:54 -0700956static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
957{
Francois Romieu3d165432009-01-19 16:56:50 -0800958 struct tg3 *tp = bp->priv;
Matt Carlson158d7ab2008-05-29 01:37:54 -0700959 u32 val;
960
Matt Carlson24bb4fb2009-10-05 17:55:29 +0000961 spin_lock_bh(&tp->lock);
Matt Carlson158d7ab2008-05-29 01:37:54 -0700962
963 if (tg3_readphy(tp, reg, &val))
Matt Carlson24bb4fb2009-10-05 17:55:29 +0000964 val = -EIO;
965
966 spin_unlock_bh(&tp->lock);
Matt Carlson158d7ab2008-05-29 01:37:54 -0700967
968 return val;
969}
970
971static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
972{
Francois Romieu3d165432009-01-19 16:56:50 -0800973 struct tg3 *tp = bp->priv;
Matt Carlson24bb4fb2009-10-05 17:55:29 +0000974 u32 ret = 0;
Matt Carlson158d7ab2008-05-29 01:37:54 -0700975
Matt Carlson24bb4fb2009-10-05 17:55:29 +0000976 spin_lock_bh(&tp->lock);
Matt Carlson158d7ab2008-05-29 01:37:54 -0700977
978 if (tg3_writephy(tp, reg, val))
Matt Carlson24bb4fb2009-10-05 17:55:29 +0000979 ret = -EIO;
Matt Carlson158d7ab2008-05-29 01:37:54 -0700980
Matt Carlson24bb4fb2009-10-05 17:55:29 +0000981 spin_unlock_bh(&tp->lock);
982
983 return ret;
Matt Carlson158d7ab2008-05-29 01:37:54 -0700984}
985
986static int tg3_mdio_reset(struct mii_bus *bp)
987{
988 return 0;
989}
990
Matt Carlson9c61d6b2008-11-03 16:54:56 -0800991static void tg3_mdio_config_5785(struct tg3 *tp)
Matt Carlsona9daf362008-05-25 23:49:44 -0700992{
993 u32 val;
Matt Carlsonfcb389d2008-11-03 16:55:44 -0800994 struct phy_device *phydev;
Matt Carlsona9daf362008-05-25 23:49:44 -0700995
Matt Carlson3f0e3ad2009-11-02 14:24:36 +0000996 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonfcb389d2008-11-03 16:55:44 -0800997 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
Matt Carlson6a443a02010-02-17 15:17:04 +0000998 case PHY_ID_BCM50610:
999 case PHY_ID_BCM50610M:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001000 val = MAC_PHYCFG2_50610_LED_MODES;
1001 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001002 case PHY_ID_BCMAC131:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001003 val = MAC_PHYCFG2_AC131_LED_MODES;
1004 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001005 case PHY_ID_RTL8211C:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001006 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1007 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001008 case PHY_ID_RTL8201E:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001009 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1010 break;
1011 default:
Matt Carlsona9daf362008-05-25 23:49:44 -07001012 return;
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001013 }
1014
1015 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1016 tw32(MAC_PHYCFG2, val);
1017
1018 val = tr32(MAC_PHYCFG1);
Matt Carlsonbb85fbb2009-08-25 10:09:07 +00001019 val &= ~(MAC_PHYCFG1_RGMII_INT |
1020 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1021 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001022 tw32(MAC_PHYCFG1, val);
1023
1024 return;
1025 }
1026
Matt Carlson14417062010-02-17 15:16:59 +00001027 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001028 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1029 MAC_PHYCFG2_FMODE_MASK_MASK |
1030 MAC_PHYCFG2_GMODE_MASK_MASK |
1031 MAC_PHYCFG2_ACT_MASK_MASK |
1032 MAC_PHYCFG2_QUAL_MASK_MASK |
1033 MAC_PHYCFG2_INBAND_ENABLE;
1034
1035 tw32(MAC_PHYCFG2, val);
Matt Carlsona9daf362008-05-25 23:49:44 -07001036
Matt Carlsonbb85fbb2009-08-25 10:09:07 +00001037 val = tr32(MAC_PHYCFG1);
1038 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1039 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
Matt Carlson14417062010-02-17 15:16:59 +00001040 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
Matt Carlsona9daf362008-05-25 23:49:44 -07001041 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1042 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1043 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1044 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1045 }
Matt Carlsonbb85fbb2009-08-25 10:09:07 +00001046 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1047 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1048 tw32(MAC_PHYCFG1, val);
Matt Carlsona9daf362008-05-25 23:49:44 -07001049
Matt Carlsona9daf362008-05-25 23:49:44 -07001050 val = tr32(MAC_EXT_RGMII_MODE);
1051 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1052 MAC_RGMII_MODE_RX_QUALITY |
1053 MAC_RGMII_MODE_RX_ACTIVITY |
1054 MAC_RGMII_MODE_RX_ENG_DET |
1055 MAC_RGMII_MODE_TX_ENABLE |
1056 MAC_RGMII_MODE_TX_LOWPWR |
1057 MAC_RGMII_MODE_TX_RESET);
Matt Carlson14417062010-02-17 15:16:59 +00001058 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
Matt Carlsona9daf362008-05-25 23:49:44 -07001059 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1060 val |= MAC_RGMII_MODE_RX_INT_B |
1061 MAC_RGMII_MODE_RX_QUALITY |
1062 MAC_RGMII_MODE_RX_ACTIVITY |
1063 MAC_RGMII_MODE_RX_ENG_DET;
1064 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1065 val |= MAC_RGMII_MODE_TX_ENABLE |
1066 MAC_RGMII_MODE_TX_LOWPWR |
1067 MAC_RGMII_MODE_TX_RESET;
1068 }
1069 tw32(MAC_EXT_RGMII_MODE, val);
1070}
1071
Matt Carlson158d7ab2008-05-29 01:37:54 -07001072static void tg3_mdio_start(struct tg3 *tp)
1073{
Matt Carlson158d7ab2008-05-29 01:37:54 -07001074 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1075 tw32_f(MAC_MI_MODE, tp->mi_mode);
1076 udelay(80);
Matt Carlsona9daf362008-05-25 23:49:44 -07001077
Matt Carlson9ea48182010-02-17 15:17:01 +00001078 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1079 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1080 tg3_mdio_config_5785(tp);
1081}
1082
1083static int tg3_mdio_init(struct tg3 *tp)
1084{
1085 int i;
1086 u32 reg;
1087 struct phy_device *phydev;
1088
Matt Carlsona50d0792010-06-05 17:24:37 +00001089 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1090 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
Matt Carlson9c7df912010-06-05 17:24:36 +00001091 u32 is_serdes;
Matt Carlson882e9792009-09-01 13:21:36 +00001092
Matt Carlson9c7df912010-06-05 17:24:36 +00001093 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
Matt Carlson882e9792009-09-01 13:21:36 +00001094
Matt Carlsond1ec96a2010-01-12 10:11:38 +00001095 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1096 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1097 else
1098 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1099 TG3_CPMU_PHY_STRAP_IS_SERDES;
Matt Carlson882e9792009-09-01 13:21:36 +00001100 if (is_serdes)
1101 tp->phy_addr += 7;
1102 } else
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001103 tp->phy_addr = TG3_PHY_MII_ADDR;
Matt Carlson882e9792009-09-01 13:21:36 +00001104
Matt Carlson158d7ab2008-05-29 01:37:54 -07001105 tg3_mdio_start(tp);
1106
1107 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1108 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1109 return 0;
1110
Lennert Buytenhek298cf9be2008-10-08 16:29:57 -07001111 tp->mdio_bus = mdiobus_alloc();
1112 if (tp->mdio_bus == NULL)
1113 return -ENOMEM;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001114
Lennert Buytenhek298cf9be2008-10-08 16:29:57 -07001115 tp->mdio_bus->name = "tg3 mdio bus";
1116 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
Matt Carlson158d7ab2008-05-29 01:37:54 -07001117 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
Lennert Buytenhek298cf9be2008-10-08 16:29:57 -07001118 tp->mdio_bus->priv = tp;
1119 tp->mdio_bus->parent = &tp->pdev->dev;
1120 tp->mdio_bus->read = &tg3_mdio_read;
1121 tp->mdio_bus->write = &tg3_mdio_write;
1122 tp->mdio_bus->reset = &tg3_mdio_reset;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001123 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
Lennert Buytenhek298cf9be2008-10-08 16:29:57 -07001124 tp->mdio_bus->irq = &tp->mdio_irq[0];
Matt Carlson158d7ab2008-05-29 01:37:54 -07001125
1126 for (i = 0; i < PHY_MAX_ADDR; i++)
Lennert Buytenhek298cf9be2008-10-08 16:29:57 -07001127 tp->mdio_bus->irq[i] = PHY_POLL;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001128
1129 /* The bus registration will look for all the PHYs on the mdio bus.
1130 * Unfortunately, it does not ensure the PHY is powered up before
1131 * accessing the PHY ID registers. A chip reset is the
1132 * quickest way to bring the device back to an operational state..
1133 */
1134 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1135 tg3_bmcr_reset(tp);
1136
Lennert Buytenhek298cf9be2008-10-08 16:29:57 -07001137 i = mdiobus_register(tp->mdio_bus);
Matt Carlsona9daf362008-05-25 23:49:44 -07001138 if (i) {
Matt Carlsonab96b242010-04-05 10:19:22 +00001139 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001140 mdiobus_free(tp->mdio_bus);
Matt Carlsona9daf362008-05-25 23:49:44 -07001141 return i;
1142 }
Matt Carlson158d7ab2008-05-29 01:37:54 -07001143
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001144 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsona9daf362008-05-25 23:49:44 -07001145
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001146 if (!phydev || !phydev->drv) {
Matt Carlsonab96b242010-04-05 10:19:22 +00001147 dev_warn(&tp->pdev->dev, "No PHY devices\n");
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001148 mdiobus_unregister(tp->mdio_bus);
1149 mdiobus_free(tp->mdio_bus);
1150 return -ENODEV;
1151 }
1152
1153 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
Matt Carlson6a443a02010-02-17 15:17:04 +00001154 case PHY_ID_BCM57780:
Matt Carlson321d32a2008-11-21 17:22:19 -08001155 phydev->interface = PHY_INTERFACE_MODE_GMII;
Matt Carlsonc704dc22009-11-02 14:32:12 +00001156 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
Matt Carlson321d32a2008-11-21 17:22:19 -08001157 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001158 case PHY_ID_BCM50610:
1159 case PHY_ID_BCM50610M:
Matt Carlson32e5a8d2009-11-02 14:31:39 +00001160 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
Matt Carlsonc704dc22009-11-02 14:32:12 +00001161 PHY_BRCM_RX_REFCLK_UNUSED |
Matt Carlson52fae082009-11-02 14:32:38 +00001162 PHY_BRCM_DIS_TXCRXC_NOENRGY |
Matt Carlsonc704dc22009-11-02 14:32:12 +00001163 PHY_BRCM_AUTO_PWRDWN_ENABLE;
Matt Carlson14417062010-02-17 15:16:59 +00001164 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
Matt Carlsona9daf362008-05-25 23:49:44 -07001165 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1166 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1167 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1168 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1169 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001170 /* fallthru */
Matt Carlson6a443a02010-02-17 15:17:04 +00001171 case PHY_ID_RTL8211C:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001172 phydev->interface = PHY_INTERFACE_MODE_RGMII;
Matt Carlsona9daf362008-05-25 23:49:44 -07001173 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001174 case PHY_ID_RTL8201E:
1175 case PHY_ID_BCMAC131:
Matt Carlsona9daf362008-05-25 23:49:44 -07001176 phydev->interface = PHY_INTERFACE_MODE_MII;
Matt Carlsoncdd4e09d2009-11-02 14:31:11 +00001177 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001178 tp->phy_flags |= TG3_PHYFLG_IS_FET;
Matt Carlsona9daf362008-05-25 23:49:44 -07001179 break;
1180 }
1181
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001182 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1183
1184 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1185 tg3_mdio_config_5785(tp);
Matt Carlsona9daf362008-05-25 23:49:44 -07001186
1187 return 0;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001188}
1189
1190static void tg3_mdio_fini(struct tg3 *tp)
1191{
1192 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1193 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
Lennert Buytenhek298cf9be2008-10-08 16:29:57 -07001194 mdiobus_unregister(tp->mdio_bus);
1195 mdiobus_free(tp->mdio_bus);
Matt Carlson158d7ab2008-05-29 01:37:54 -07001196 }
1197}
1198
Matt Carlson95e28692008-05-25 23:44:14 -07001199/* tp->lock is held. */
Matt Carlson4ba526c2008-08-15 14:10:04 -07001200static inline void tg3_generate_fw_event(struct tg3 *tp)
1201{
1202 u32 val;
1203
1204 val = tr32(GRC_RX_CPU_EVENT);
1205 val |= GRC_RX_CPU_DRIVER_EVENT;
1206 tw32_f(GRC_RX_CPU_EVENT, val);
1207
1208 tp->last_event_jiffies = jiffies;
1209}
1210
1211#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1212
1213/* tp->lock is held. */
Matt Carlson95e28692008-05-25 23:44:14 -07001214static void tg3_wait_for_event_ack(struct tg3 *tp)
1215{
1216 int i;
Matt Carlson4ba526c2008-08-15 14:10:04 -07001217 unsigned int delay_cnt;
1218 long time_remain;
Matt Carlson95e28692008-05-25 23:44:14 -07001219
Matt Carlson4ba526c2008-08-15 14:10:04 -07001220 /* If enough time has passed, no wait is necessary. */
1221 time_remain = (long)(tp->last_event_jiffies + 1 +
1222 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1223 (long)jiffies;
1224 if (time_remain < 0)
1225 return;
1226
1227 /* Check if we can shorten the wait time. */
1228 delay_cnt = jiffies_to_usecs(time_remain);
1229 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1230 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1231 delay_cnt = (delay_cnt >> 3) + 1;
1232
1233 for (i = 0; i < delay_cnt; i++) {
Matt Carlson95e28692008-05-25 23:44:14 -07001234 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1235 break;
Matt Carlson4ba526c2008-08-15 14:10:04 -07001236 udelay(8);
Matt Carlson95e28692008-05-25 23:44:14 -07001237 }
1238}
1239
1240/* tp->lock is held. */
1241static void tg3_ump_link_report(struct tg3 *tp)
1242{
1243 u32 reg;
1244 u32 val;
1245
1246 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1247 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1248 return;
1249
1250 tg3_wait_for_event_ack(tp);
1251
1252 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1253
1254 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1255
1256 val = 0;
1257 if (!tg3_readphy(tp, MII_BMCR, &reg))
1258 val = reg << 16;
1259 if (!tg3_readphy(tp, MII_BMSR, &reg))
1260 val |= (reg & 0xffff);
1261 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1262
1263 val = 0;
1264 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1265 val = reg << 16;
1266 if (!tg3_readphy(tp, MII_LPA, &reg))
1267 val |= (reg & 0xffff);
1268 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1269
1270 val = 0;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001271 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
Matt Carlson95e28692008-05-25 23:44:14 -07001272 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1273 val = reg << 16;
1274 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1275 val |= (reg & 0xffff);
1276 }
1277 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1278
1279 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1280 val = reg << 16;
1281 else
1282 val = 0;
1283 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1284
Matt Carlson4ba526c2008-08-15 14:10:04 -07001285 tg3_generate_fw_event(tp);
Matt Carlson95e28692008-05-25 23:44:14 -07001286}
1287
1288static void tg3_link_report(struct tg3 *tp)
1289{
1290 if (!netif_carrier_ok(tp->dev)) {
Joe Perches05dbe002010-02-17 19:44:19 +00001291 netif_info(tp, link, tp->dev, "Link is down\n");
Matt Carlson95e28692008-05-25 23:44:14 -07001292 tg3_ump_link_report(tp);
1293 } else if (netif_msg_link(tp)) {
Joe Perches05dbe002010-02-17 19:44:19 +00001294 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1295 (tp->link_config.active_speed == SPEED_1000 ?
1296 1000 :
1297 (tp->link_config.active_speed == SPEED_100 ?
1298 100 : 10)),
1299 (tp->link_config.active_duplex == DUPLEX_FULL ?
1300 "full" : "half"));
Matt Carlson95e28692008-05-25 23:44:14 -07001301
Joe Perches05dbe002010-02-17 19:44:19 +00001302 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1303 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1304 "on" : "off",
1305 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1306 "on" : "off");
Matt Carlson95e28692008-05-25 23:44:14 -07001307 tg3_ump_link_report(tp);
1308 }
1309}
1310
1311static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1312{
1313 u16 miireg;
1314
Steve Glendinninge18ce342008-12-16 02:00:00 -08001315 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
Matt Carlson95e28692008-05-25 23:44:14 -07001316 miireg = ADVERTISE_PAUSE_CAP;
Steve Glendinninge18ce342008-12-16 02:00:00 -08001317 else if (flow_ctrl & FLOW_CTRL_TX)
Matt Carlson95e28692008-05-25 23:44:14 -07001318 miireg = ADVERTISE_PAUSE_ASYM;
Steve Glendinninge18ce342008-12-16 02:00:00 -08001319 else if (flow_ctrl & FLOW_CTRL_RX)
Matt Carlson95e28692008-05-25 23:44:14 -07001320 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1321 else
1322 miireg = 0;
1323
1324 return miireg;
1325}
1326
1327static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1328{
1329 u16 miireg;
1330
Steve Glendinninge18ce342008-12-16 02:00:00 -08001331 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
Matt Carlson95e28692008-05-25 23:44:14 -07001332 miireg = ADVERTISE_1000XPAUSE;
Steve Glendinninge18ce342008-12-16 02:00:00 -08001333 else if (flow_ctrl & FLOW_CTRL_TX)
Matt Carlson95e28692008-05-25 23:44:14 -07001334 miireg = ADVERTISE_1000XPSE_ASYM;
Steve Glendinninge18ce342008-12-16 02:00:00 -08001335 else if (flow_ctrl & FLOW_CTRL_RX)
Matt Carlson95e28692008-05-25 23:44:14 -07001336 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1337 else
1338 miireg = 0;
1339
1340 return miireg;
1341}
1342
Matt Carlson95e28692008-05-25 23:44:14 -07001343static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1344{
1345 u8 cap = 0;
1346
1347 if (lcladv & ADVERTISE_1000XPAUSE) {
1348 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1349 if (rmtadv & LPA_1000XPAUSE)
Steve Glendinninge18ce342008-12-16 02:00:00 -08001350 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
Matt Carlson95e28692008-05-25 23:44:14 -07001351 else if (rmtadv & LPA_1000XPAUSE_ASYM)
Steve Glendinninge18ce342008-12-16 02:00:00 -08001352 cap = FLOW_CTRL_RX;
Matt Carlson95e28692008-05-25 23:44:14 -07001353 } else {
1354 if (rmtadv & LPA_1000XPAUSE)
Steve Glendinninge18ce342008-12-16 02:00:00 -08001355 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
Matt Carlson95e28692008-05-25 23:44:14 -07001356 }
1357 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1358 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
Steve Glendinninge18ce342008-12-16 02:00:00 -08001359 cap = FLOW_CTRL_TX;
Matt Carlson95e28692008-05-25 23:44:14 -07001360 }
1361
1362 return cap;
1363}
1364
Matt Carlsonf51f3562008-05-25 23:45:08 -07001365static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
Matt Carlson95e28692008-05-25 23:44:14 -07001366{
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001367 u8 autoneg;
Matt Carlsonf51f3562008-05-25 23:45:08 -07001368 u8 flowctrl = 0;
Matt Carlson95e28692008-05-25 23:44:14 -07001369 u32 old_rx_mode = tp->rx_mode;
1370 u32 old_tx_mode = tp->tx_mode;
1371
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001372 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001373 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001374 else
1375 autoneg = tp->link_config.autoneg;
1376
1377 if (autoneg == AUTONEG_ENABLE &&
Matt Carlson95e28692008-05-25 23:44:14 -07001378 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001379 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
Matt Carlsonf51f3562008-05-25 23:45:08 -07001380 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
Matt Carlson95e28692008-05-25 23:44:14 -07001381 else
Steve Glendinningbc02ff92008-12-16 02:00:48 -08001382 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
Matt Carlsonf51f3562008-05-25 23:45:08 -07001383 } else
1384 flowctrl = tp->link_config.flowctrl;
Matt Carlson95e28692008-05-25 23:44:14 -07001385
Matt Carlsonf51f3562008-05-25 23:45:08 -07001386 tp->link_config.active_flowctrl = flowctrl;
Matt Carlson95e28692008-05-25 23:44:14 -07001387
Steve Glendinninge18ce342008-12-16 02:00:00 -08001388 if (flowctrl & FLOW_CTRL_RX)
Matt Carlson95e28692008-05-25 23:44:14 -07001389 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1390 else
1391 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1392
Matt Carlsonf51f3562008-05-25 23:45:08 -07001393 if (old_rx_mode != tp->rx_mode)
Matt Carlson95e28692008-05-25 23:44:14 -07001394 tw32_f(MAC_RX_MODE, tp->rx_mode);
Matt Carlson95e28692008-05-25 23:44:14 -07001395
Steve Glendinninge18ce342008-12-16 02:00:00 -08001396 if (flowctrl & FLOW_CTRL_TX)
Matt Carlson95e28692008-05-25 23:44:14 -07001397 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1398 else
1399 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1400
Matt Carlsonf51f3562008-05-25 23:45:08 -07001401 if (old_tx_mode != tp->tx_mode)
Matt Carlson95e28692008-05-25 23:44:14 -07001402 tw32_f(MAC_TX_MODE, tp->tx_mode);
Matt Carlson95e28692008-05-25 23:44:14 -07001403}
1404
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001405static void tg3_adjust_link(struct net_device *dev)
1406{
1407 u8 oldflowctrl, linkmesg = 0;
1408 u32 mac_mode, lcl_adv, rmt_adv;
1409 struct tg3 *tp = netdev_priv(dev);
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001410 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001411
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001412 spin_lock_bh(&tp->lock);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001413
1414 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1415 MAC_MODE_HALF_DUPLEX);
1416
1417 oldflowctrl = tp->link_config.active_flowctrl;
1418
1419 if (phydev->link) {
1420 lcl_adv = 0;
1421 rmt_adv = 0;
1422
1423 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1424 mac_mode |= MAC_MODE_PORT_MODE_MII;
Matt Carlsonc3df0742009-11-02 14:27:02 +00001425 else if (phydev->speed == SPEED_1000 ||
1426 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001427 mac_mode |= MAC_MODE_PORT_MODE_GMII;
Matt Carlsonc3df0742009-11-02 14:27:02 +00001428 else
1429 mac_mode |= MAC_MODE_PORT_MODE_MII;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001430
1431 if (phydev->duplex == DUPLEX_HALF)
1432 mac_mode |= MAC_MODE_HALF_DUPLEX;
1433 else {
1434 lcl_adv = tg3_advert_flowctrl_1000T(
1435 tp->link_config.flowctrl);
1436
1437 if (phydev->pause)
1438 rmt_adv = LPA_PAUSE_CAP;
1439 if (phydev->asym_pause)
1440 rmt_adv |= LPA_PAUSE_ASYM;
1441 }
1442
1443 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1444 } else
1445 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1446
1447 if (mac_mode != tp->mac_mode) {
1448 tp->mac_mode = mac_mode;
1449 tw32_f(MAC_MODE, tp->mac_mode);
1450 udelay(40);
1451 }
1452
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001453 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1454 if (phydev->speed == SPEED_10)
1455 tw32(MAC_MI_STAT,
1456 MAC_MI_STAT_10MBPS_MODE |
1457 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1458 else
1459 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1460 }
1461
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001462 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1463 tw32(MAC_TX_LENGTHS,
1464 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1465 (6 << TX_LENGTHS_IPG_SHIFT) |
1466 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1467 else
1468 tw32(MAC_TX_LENGTHS,
1469 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1470 (6 << TX_LENGTHS_IPG_SHIFT) |
1471 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1472
1473 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1474 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1475 phydev->speed != tp->link_config.active_speed ||
1476 phydev->duplex != tp->link_config.active_duplex ||
1477 oldflowctrl != tp->link_config.active_flowctrl)
Matt Carlsonc6cdf432010-04-05 10:19:26 +00001478 linkmesg = 1;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001479
1480 tp->link_config.active_speed = phydev->speed;
1481 tp->link_config.active_duplex = phydev->duplex;
1482
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001483 spin_unlock_bh(&tp->lock);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001484
1485 if (linkmesg)
1486 tg3_link_report(tp);
1487}
1488
1489static int tg3_phy_init(struct tg3 *tp)
1490{
1491 struct phy_device *phydev;
1492
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001493 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001494 return 0;
1495
1496 /* Bring the PHY back to a known state. */
1497 tg3_bmcr_reset(tp);
1498
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001499 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001500
1501 /* Attach the MAC to the PHY. */
Kay Sieversfb28ad32008-11-10 13:55:14 -08001502 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
Matt Carlsona9daf362008-05-25 23:49:44 -07001503 phydev->dev_flags, phydev->interface);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001504 if (IS_ERR(phydev)) {
Matt Carlsonab96b242010-04-05 10:19:22 +00001505 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001506 return PTR_ERR(phydev);
1507 }
1508
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001509 /* Mask with MAC supported features. */
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001510 switch (phydev->interface) {
1511 case PHY_INTERFACE_MODE_GMII:
1512 case PHY_INTERFACE_MODE_RGMII:
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001513 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
Matt Carlson321d32a2008-11-21 17:22:19 -08001514 phydev->supported &= (PHY_GBIT_FEATURES |
1515 SUPPORTED_Pause |
1516 SUPPORTED_Asym_Pause);
1517 break;
1518 }
1519 /* fallthru */
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001520 case PHY_INTERFACE_MODE_MII:
1521 phydev->supported &= (PHY_BASIC_FEATURES |
1522 SUPPORTED_Pause |
1523 SUPPORTED_Asym_Pause);
1524 break;
1525 default:
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001526 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001527 return -EINVAL;
1528 }
1529
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001530 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001531
1532 phydev->advertising = phydev->supported;
1533
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001534 return 0;
1535}
1536
1537static void tg3_phy_start(struct tg3 *tp)
1538{
1539 struct phy_device *phydev;
1540
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001541 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001542 return;
1543
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001544 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001545
Matt Carlson800960682010-08-02 11:26:06 +00001546 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1547 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001548 phydev->speed = tp->link_config.orig_speed;
1549 phydev->duplex = tp->link_config.orig_duplex;
1550 phydev->autoneg = tp->link_config.orig_autoneg;
1551 phydev->advertising = tp->link_config.orig_advertising;
1552 }
1553
1554 phy_start(phydev);
1555
1556 phy_start_aneg(phydev);
1557}
1558
1559static void tg3_phy_stop(struct tg3 *tp)
1560{
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001561 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001562 return;
1563
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001564 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001565}
1566
1567static void tg3_phy_fini(struct tg3 *tp)
1568{
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001569 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001570 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001571 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001572 }
1573}
1574
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00001575static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001576{
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00001577 int err;
1578
1579 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1580 if (!err)
1581 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1582
1583 return err;
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001584}
1585
Matt Carlson7f97a4b2009-08-25 10:10:03 +00001586static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1587{
1588 u32 phytest;
1589
1590 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1591 u32 phy;
1592
1593 tg3_writephy(tp, MII_TG3_FET_TEST,
1594 phytest | MII_TG3_FET_SHADOW_EN);
1595 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1596 if (enable)
1597 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1598 else
1599 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1600 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1601 }
1602 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1603 }
1604}
1605
Matt Carlson6833c042008-11-21 17:18:59 -08001606static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1607{
1608 u32 reg;
1609
Matt Carlsonecf14102010-01-20 16:58:05 +00001610 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
Matt Carlsona50d0792010-06-05 17:24:37 +00001611 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1612 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001613 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
Matt Carlson6833c042008-11-21 17:18:59 -08001614 return;
1615
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001616 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Matt Carlson7f97a4b2009-08-25 10:10:03 +00001617 tg3_phy_fet_toggle_apd(tp, enable);
1618 return;
1619 }
1620
Matt Carlson6833c042008-11-21 17:18:59 -08001621 reg = MII_TG3_MISC_SHDW_WREN |
1622 MII_TG3_MISC_SHDW_SCR5_SEL |
1623 MII_TG3_MISC_SHDW_SCR5_LPED |
1624 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1625 MII_TG3_MISC_SHDW_SCR5_SDTL |
1626 MII_TG3_MISC_SHDW_SCR5_C125OE;
1627 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1628 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1629
1630 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1631
1632
1633 reg = MII_TG3_MISC_SHDW_WREN |
1634 MII_TG3_MISC_SHDW_APD_SEL |
1635 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1636 if (enable)
1637 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1638
1639 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1640}
1641
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001642static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1643{
1644 u32 phy;
1645
1646 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001647 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001648 return;
1649
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001650 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001651 u32 ephy;
1652
Matt Carlson535ef6e2009-08-25 10:09:36 +00001653 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1654 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1655
1656 tg3_writephy(tp, MII_TG3_FET_TEST,
1657 ephy | MII_TG3_FET_SHADOW_EN);
1658 if (!tg3_readphy(tp, reg, &phy)) {
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001659 if (enable)
Matt Carlson535ef6e2009-08-25 10:09:36 +00001660 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001661 else
Matt Carlson535ef6e2009-08-25 10:09:36 +00001662 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1663 tg3_writephy(tp, reg, phy);
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001664 }
Matt Carlson535ef6e2009-08-25 10:09:36 +00001665 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
Matt Carlson9ef8ca92007-07-11 19:48:29 -07001666 }
1667 } else {
1668 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1669 MII_TG3_AUXCTL_SHDWSEL_MISC;
1670 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1671 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1672 if (enable)
1673 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1674 else
1675 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1676 phy |= MII_TG3_AUXCTL_MISC_WREN;
1677 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1678 }
1679 }
1680}
1681
Linus Torvalds1da177e2005-04-16 15:20:36 -07001682static void tg3_phy_set_wirespeed(struct tg3 *tp)
1683{
1684 u32 val;
1685
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001686 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001687 return;
1688
1689 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1690 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1691 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1692 (val | (1 << 15) | (1 << 4)));
1693}
1694
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001695static void tg3_phy_apply_otp(struct tg3 *tp)
1696{
1697 u32 otp, phy;
1698
1699 if (!tp->phy_otp)
1700 return;
1701
1702 otp = tp->phy_otp;
1703
1704 /* Enable SM_DSP clock and tx 6dB coding. */
1705 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1706 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1707 MII_TG3_AUXCTL_ACTL_TX_6DB;
1708 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1709
1710 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1711 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1712 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1713
1714 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1715 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1716 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1717
1718 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1719 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1720 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1721
1722 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1723 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1724
1725 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1726 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1727
1728 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1729 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1730 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1731
1732 /* Turn off SM_DSP clock. */
1733 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1734 MII_TG3_AUXCTL_ACTL_TX_6DB;
1735 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1736}
1737
Linus Torvalds1da177e2005-04-16 15:20:36 -07001738static int tg3_wait_macro_done(struct tg3 *tp)
1739{
1740 int limit = 100;
1741
1742 while (limit--) {
1743 u32 tmp32;
1744
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00001745 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001746 if ((tmp32 & 0x1000) == 0)
1747 break;
1748 }
1749 }
Roel Kluind4675b52009-02-12 16:33:27 -08001750 if (limit < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001751 return -EBUSY;
1752
1753 return 0;
1754}
1755
1756static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1757{
1758 static const u32 test_pat[4][6] = {
1759 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1760 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1761 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1762 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1763 };
1764 int chan;
1765
1766 for (chan = 0; chan < 4; chan++) {
1767 int i;
1768
1769 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1770 (chan * 0x2000) | 0x0200);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00001771 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001772
1773 for (i = 0; i < 6; i++)
1774 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1775 test_pat[chan][i]);
1776
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00001777 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001778 if (tg3_wait_macro_done(tp)) {
1779 *resetp = 1;
1780 return -EBUSY;
1781 }
1782
1783 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1784 (chan * 0x2000) | 0x0200);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00001785 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001786 if (tg3_wait_macro_done(tp)) {
1787 *resetp = 1;
1788 return -EBUSY;
1789 }
1790
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00001791 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001792 if (tg3_wait_macro_done(tp)) {
1793 *resetp = 1;
1794 return -EBUSY;
1795 }
1796
1797 for (i = 0; i < 6; i += 2) {
1798 u32 low, high;
1799
1800 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1801 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1802 tg3_wait_macro_done(tp)) {
1803 *resetp = 1;
1804 return -EBUSY;
1805 }
1806 low &= 0x7fff;
1807 high &= 0x000f;
1808 if (low != test_pat[chan][i] ||
1809 high != test_pat[chan][i+1]) {
1810 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1811 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1812 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1813
1814 return -EBUSY;
1815 }
1816 }
1817 }
1818
1819 return 0;
1820}
1821
1822static int tg3_phy_reset_chanpat(struct tg3 *tp)
1823{
1824 int chan;
1825
1826 for (chan = 0; chan < 4; chan++) {
1827 int i;
1828
1829 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1830 (chan * 0x2000) | 0x0200);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00001831 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001832 for (i = 0; i < 6; i++)
1833 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00001834 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001835 if (tg3_wait_macro_done(tp))
1836 return -EBUSY;
1837 }
1838
1839 return 0;
1840}
1841
1842static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1843{
1844 u32 reg32, phy9_orig;
1845 int retries, do_phy_reset, err;
1846
1847 retries = 10;
1848 do_phy_reset = 1;
1849 do {
1850 if (do_phy_reset) {
1851 err = tg3_bmcr_reset(tp);
1852 if (err)
1853 return err;
1854 do_phy_reset = 0;
1855 }
1856
1857 /* Disable transmitter and interrupt. */
1858 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1859 continue;
1860
1861 reg32 |= 0x3000;
1862 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1863
1864 /* Set full-duplex, 1000 mbps. */
1865 tg3_writephy(tp, MII_BMCR,
1866 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1867
1868 /* Set to master mode. */
1869 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1870 continue;
1871
1872 tg3_writephy(tp, MII_TG3_CTRL,
1873 (MII_TG3_CTRL_AS_MASTER |
1874 MII_TG3_CTRL_ENABLE_AS_MASTER));
1875
1876 /* Enable SM_DSP_CLOCK and 6dB. */
1877 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1878
1879 /* Block the PHY control access. */
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00001880 tg3_phydsp_write(tp, 0x8005, 0x0800);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001881
1882 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1883 if (!err)
1884 break;
1885 } while (--retries);
1886
1887 err = tg3_phy_reset_chanpat(tp);
1888 if (err)
1889 return err;
1890
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00001891 tg3_phydsp_write(tp, 0x8005, 0x0000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001892
1893 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00001894 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001895
1896 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1897 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1898 /* Set Extended packet length bit for jumbo frames */
1899 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
Matt Carlson859a588792010-04-05 10:19:28 +00001900 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001901 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1902 }
1903
1904 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1905
1906 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1907 reg32 &= ~0x3000;
1908 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1909 } else if (!err)
1910 err = -EBUSY;
1911
1912 return err;
1913}
1914
1915/* This will reset the tigon3 PHY if there is no valid
1916 * link unless the FORCE argument is non-zero.
1917 */
1918static int tg3_phy_reset(struct tg3 *tp)
1919{
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001920 u32 cpmuctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001921 u32 phy_status;
1922 int err;
1923
Michael Chan60189dd2006-12-17 17:08:07 -08001924 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1925 u32 val;
1926
1927 val = tr32(GRC_MISC_CFG);
1928 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1929 udelay(40);
1930 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001931 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1932 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1933 if (err != 0)
1934 return -EBUSY;
1935
Michael Chanc8e1e822006-04-29 18:55:17 -07001936 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1937 netif_carrier_off(tp->dev);
1938 tg3_link_report(tp);
1939 }
1940
Linus Torvalds1da177e2005-04-16 15:20:36 -07001941 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1942 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1943 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1944 err = tg3_phy_reset_5703_4_5(tp);
1945 if (err)
1946 return err;
1947 goto out;
1948 }
1949
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001950 cpmuctrl = 0;
1951 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1952 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1953 cpmuctrl = tr32(TG3_CPMU_CTRL);
1954 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1955 tw32(TG3_CPMU_CTRL,
1956 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1957 }
1958
Linus Torvalds1da177e2005-04-16 15:20:36 -07001959 err = tg3_bmcr_reset(tp);
1960 if (err)
1961 return err;
1962
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001963 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1964 u32 phy;
1965
1966 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1967 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1968
1969 tw32(TG3_CPMU_CTRL, cpmuctrl);
1970 }
1971
Matt Carlsonbcb37f62008-11-03 16:52:09 -08001972 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1973 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
Matt Carlsonce057f02007-11-12 21:08:03 -08001974 u32 val;
1975
1976 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1977 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1978 CPMU_LSPD_1000MB_MACCLK_12_5) {
1979 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1980 udelay(40);
1981 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1982 }
1983 }
1984
Matt Carlsona50d0792010-06-05 17:24:37 +00001985 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001987 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
Matt Carlsonecf14102010-01-20 16:58:05 +00001988 return 0;
1989
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001990 tg3_phy_apply_otp(tp);
1991
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001992 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
Matt Carlson6833c042008-11-21 17:18:59 -08001993 tg3_phy_toggle_apd(tp, true);
1994 else
1995 tg3_phy_toggle_apd(tp, false);
1996
Linus Torvalds1da177e2005-04-16 15:20:36 -07001997out:
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001998 if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001999 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00002000 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2001 tg3_phydsp_write(tp, 0x000a, 0x0323);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002002 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2003 }
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002004 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002005 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2006 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002007 }
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002008 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002009 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00002010 tg3_phydsp_write(tp, 0x000a, 0x310b);
2011 tg3_phydsp_write(tp, 0x201f, 0x9506);
2012 tg3_phydsp_write(tp, 0x401f, 0x14e2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002013 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002014 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
Michael Chanc424cb22006-04-29 18:56:34 -07002015 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2016 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002017 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
Michael Chanc1d2a192007-01-08 19:57:20 -08002018 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2019 tg3_writephy(tp, MII_TG3_TEST1,
2020 MII_TG3_TEST1_TRIM_EN | 0x4);
2021 } else
2022 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
Michael Chanc424cb22006-04-29 18:56:34 -07002023 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2024 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002025 /* Set Extended packet length bit (bit 14) on all chips that */
2026 /* support jumbo frames */
Matt Carlson79eb6902010-02-17 15:17:03 +00002027 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002028 /* Cannot do read-modify-write on 5401 */
2029 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
Matt Carlson8f666b02009-08-28 13:58:24 +00002030 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002031 u32 phy_reg;
2032
2033 /* Set bit 14 with read-modify-write to preserve other bits */
2034 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2035 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2036 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2037 }
2038
2039 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2040 * jumbo frames transmission.
2041 */
Matt Carlson8f666b02009-08-28 13:58:24 +00002042 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002043 u32 phy_reg;
2044
2045 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
Matt Carlsonc6cdf432010-04-05 10:19:26 +00002046 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2047 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002048 }
2049
Michael Chan715116a2006-09-27 16:09:25 -07002050 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chan715116a2006-09-27 16:09:25 -07002051 /* adjust output voltage */
Matt Carlson535ef6e2009-08-25 10:09:36 +00002052 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
Michael Chan715116a2006-09-27 16:09:25 -07002053 }
2054
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002055 tg3_phy_toggle_automdix(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002056 tg3_phy_set_wirespeed(tp);
2057 return 0;
2058}
2059
2060static void tg3_frob_aux_power(struct tg3 *tp)
2061{
2062 struct tg3 *tp_peer = tp;
2063
Matt Carlson334355a2010-01-20 16:58:10 +00002064 /* The GPIOs do something completely different on 57765. */
2065 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
Matt Carlsona50d0792010-06-05 17:24:37 +00002066 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
Matt Carlson334355a2010-01-20 16:58:10 +00002067 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002068 return;
2069
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00002070 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2071 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2072 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
Michael Chan8c2dc7e2005-12-19 16:26:02 -08002073 struct net_device *dev_peer;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002074
Michael Chan8c2dc7e2005-12-19 16:26:02 -08002075 dev_peer = pci_get_drvdata(tp->pdev_peer);
Michael Chanbc1c7562006-03-20 17:48:03 -08002076 /* remove_one() may have been run on the peer. */
Michael Chan8c2dc7e2005-12-19 16:26:02 -08002077 if (!dev_peer)
Michael Chanbc1c7562006-03-20 17:48:03 -08002078 tp_peer = tp;
2079 else
2080 tp_peer = netdev_priv(dev_peer);
Michael Chan8c2dc7e2005-12-19 16:26:02 -08002081 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002082
2083 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
Michael Chan6921d202005-12-13 21:15:53 -08002084 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2085 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2086 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002087 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2088 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
Michael Chanb401e9e2005-12-19 16:27:04 -08002089 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2090 (GRC_LCLCTRL_GPIO_OE0 |
2091 GRC_LCLCTRL_GPIO_OE1 |
2092 GRC_LCLCTRL_GPIO_OE2 |
2093 GRC_LCLCTRL_GPIO_OUTPUT0 |
2094 GRC_LCLCTRL_GPIO_OUTPUT1),
2095 100);
Matt Carlson8d519ab2009-04-20 06:58:01 +00002096 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2097 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
Matt Carlson5f0c4a32008-06-09 15:41:12 -07002098 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2099 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2100 GRC_LCLCTRL_GPIO_OE1 |
2101 GRC_LCLCTRL_GPIO_OE2 |
2102 GRC_LCLCTRL_GPIO_OUTPUT0 |
2103 GRC_LCLCTRL_GPIO_OUTPUT1 |
2104 tp->grc_local_ctrl;
2105 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2106
2107 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2108 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2109
2110 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2111 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002112 } else {
2113 u32 no_gpio2;
Michael Chandc56b7d2005-12-19 16:26:28 -08002114 u32 grc_local_ctrl = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002115
2116 if (tp_peer != tp &&
2117 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2118 return;
2119
Michael Chandc56b7d2005-12-19 16:26:28 -08002120 /* Workaround to prevent overdrawing Amps. */
2121 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2122 ASIC_REV_5714) {
2123 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
Michael Chanb401e9e2005-12-19 16:27:04 -08002124 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2125 grc_local_ctrl, 100);
Michael Chandc56b7d2005-12-19 16:26:28 -08002126 }
2127
Linus Torvalds1da177e2005-04-16 15:20:36 -07002128 /* On 5753 and variants, GPIO2 cannot be used. */
2129 no_gpio2 = tp->nic_sram_data_cfg &
2130 NIC_SRAM_DATA_CFG_NO_GPIO2;
2131
Michael Chandc56b7d2005-12-19 16:26:28 -08002132 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
Linus Torvalds1da177e2005-04-16 15:20:36 -07002133 GRC_LCLCTRL_GPIO_OE1 |
2134 GRC_LCLCTRL_GPIO_OE2 |
2135 GRC_LCLCTRL_GPIO_OUTPUT1 |
2136 GRC_LCLCTRL_GPIO_OUTPUT2;
2137 if (no_gpio2) {
2138 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2139 GRC_LCLCTRL_GPIO_OUTPUT2);
2140 }
Michael Chanb401e9e2005-12-19 16:27:04 -08002141 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2142 grc_local_ctrl, 100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002143
2144 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2145
Michael Chanb401e9e2005-12-19 16:27:04 -08002146 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2147 grc_local_ctrl, 100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002148
2149 if (!no_gpio2) {
2150 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
Michael Chanb401e9e2005-12-19 16:27:04 -08002151 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2152 grc_local_ctrl, 100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002153 }
2154 }
2155 } else {
2156 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2157 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2158 if (tp_peer != tp &&
2159 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2160 return;
2161
Michael Chanb401e9e2005-12-19 16:27:04 -08002162 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2163 (GRC_LCLCTRL_GPIO_OE1 |
2164 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002165
Michael Chanb401e9e2005-12-19 16:27:04 -08002166 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2167 GRC_LCLCTRL_GPIO_OE1, 100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002168
Michael Chanb401e9e2005-12-19 16:27:04 -08002169 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2170 (GRC_LCLCTRL_GPIO_OE1 |
2171 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002172 }
2173 }
2174}
2175
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07002176static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2177{
2178 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2179 return 1;
Matt Carlson79eb6902010-02-17 15:17:03 +00002180 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07002181 if (speed != SPEED_10)
2182 return 1;
2183 } else if (speed == SPEED_10)
2184 return 1;
2185
2186 return 0;
2187}
2188
Linus Torvalds1da177e2005-04-16 15:20:36 -07002189static int tg3_setup_phy(struct tg3 *, int);
2190
2191#define RESET_KIND_SHUTDOWN 0
2192#define RESET_KIND_INIT 1
2193#define RESET_KIND_SUSPEND 2
2194
2195static void tg3_write_sig_post_reset(struct tg3 *, int);
2196static int tg3_halt_cpu(struct tg3 *, u32);
2197
Matt Carlson0a459aa2008-11-03 16:54:15 -08002198static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
Michael Chan15c3b692006-03-22 01:06:52 -08002199{
Matt Carlsonce057f02007-11-12 21:08:03 -08002200 u32 val;
2201
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002202 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
Michael Chan51297242007-02-13 12:17:57 -08002203 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2204 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2205 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2206
2207 sg_dig_ctrl |=
2208 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2209 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2210 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2211 }
Michael Chan3f7045c2006-09-27 16:02:29 -07002212 return;
Michael Chan51297242007-02-13 12:17:57 -08002213 }
Michael Chan3f7045c2006-09-27 16:02:29 -07002214
Michael Chan60189dd2006-12-17 17:08:07 -08002215 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chan60189dd2006-12-17 17:08:07 -08002216 tg3_bmcr_reset(tp);
2217 val = tr32(GRC_MISC_CFG);
2218 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2219 udelay(40);
2220 return;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002221 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Matt Carlson0e5f7842009-11-02 14:26:38 +00002222 u32 phytest;
2223 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2224 u32 phy;
2225
2226 tg3_writephy(tp, MII_ADVERTISE, 0);
2227 tg3_writephy(tp, MII_BMCR,
2228 BMCR_ANENABLE | BMCR_ANRESTART);
2229
2230 tg3_writephy(tp, MII_TG3_FET_TEST,
2231 phytest | MII_TG3_FET_SHADOW_EN);
2232 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2233 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2234 tg3_writephy(tp,
2235 MII_TG3_FET_SHDW_AUXMODE4,
2236 phy);
2237 }
2238 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2239 }
2240 return;
Matt Carlson0a459aa2008-11-03 16:54:15 -08002241 } else if (do_low_power) {
Michael Chan715116a2006-09-27 16:09:25 -07002242 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2243 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
Matt Carlson0a459aa2008-11-03 16:54:15 -08002244
2245 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2246 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2247 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2248 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2249 MII_TG3_AUXCTL_PCTL_VREG_11V);
Michael Chan715116a2006-09-27 16:09:25 -07002250 }
Michael Chan3f7045c2006-09-27 16:02:29 -07002251
Michael Chan15c3b692006-03-22 01:06:52 -08002252 /* The PHY should not be powered down on some chips because
2253 * of bugs.
2254 */
2255 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2256 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2257 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002258 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
Michael Chan15c3b692006-03-22 01:06:52 -08002259 return;
Matt Carlsonce057f02007-11-12 21:08:03 -08002260
Matt Carlsonbcb37f62008-11-03 16:52:09 -08002261 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2262 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
Matt Carlsonce057f02007-11-12 21:08:03 -08002263 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2264 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2265 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2266 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2267 }
2268
Michael Chan15c3b692006-03-22 01:06:52 -08002269 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2270}
2271
Matt Carlson3f007892008-11-03 16:51:36 -08002272/* tp->lock is held. */
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002273static int tg3_nvram_lock(struct tg3 *tp)
2274{
2275 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2276 int i;
2277
2278 if (tp->nvram_lock_cnt == 0) {
2279 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2280 for (i = 0; i < 8000; i++) {
2281 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2282 break;
2283 udelay(20);
2284 }
2285 if (i == 8000) {
2286 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2287 return -ENODEV;
2288 }
2289 }
2290 tp->nvram_lock_cnt++;
2291 }
2292 return 0;
2293}
2294
2295/* tp->lock is held. */
2296static void tg3_nvram_unlock(struct tg3 *tp)
2297{
2298 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2299 if (tp->nvram_lock_cnt > 0)
2300 tp->nvram_lock_cnt--;
2301 if (tp->nvram_lock_cnt == 0)
2302 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2303 }
2304}
2305
2306/* tp->lock is held. */
2307static void tg3_enable_nvram_access(struct tg3 *tp)
2308{
2309 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
Matt Carlsonf66a29b2009-11-13 13:03:36 +00002310 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002311 u32 nvaccess = tr32(NVRAM_ACCESS);
2312
2313 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2314 }
2315}
2316
2317/* tp->lock is held. */
2318static void tg3_disable_nvram_access(struct tg3 *tp)
2319{
2320 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
Matt Carlsonf66a29b2009-11-13 13:03:36 +00002321 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002322 u32 nvaccess = tr32(NVRAM_ACCESS);
2323
2324 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2325 }
2326}
2327
2328static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2329 u32 offset, u32 *val)
2330{
2331 u32 tmp;
2332 int i;
2333
2334 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2335 return -EINVAL;
2336
2337 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2338 EEPROM_ADDR_DEVID_MASK |
2339 EEPROM_ADDR_READ);
2340 tw32(GRC_EEPROM_ADDR,
2341 tmp |
2342 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2343 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2344 EEPROM_ADDR_ADDR_MASK) |
2345 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2346
2347 for (i = 0; i < 1000; i++) {
2348 tmp = tr32(GRC_EEPROM_ADDR);
2349
2350 if (tmp & EEPROM_ADDR_COMPLETE)
2351 break;
2352 msleep(1);
2353 }
2354 if (!(tmp & EEPROM_ADDR_COMPLETE))
2355 return -EBUSY;
2356
Matt Carlson62cedd12009-04-20 14:52:29 -07002357 tmp = tr32(GRC_EEPROM_DATA);
2358
2359 /*
2360 * The data will always be opposite the native endian
2361 * format. Perform a blind byteswap to compensate.
2362 */
2363 *val = swab32(tmp);
2364
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002365 return 0;
2366}
2367
2368#define NVRAM_CMD_TIMEOUT 10000
2369
2370static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2371{
2372 int i;
2373
2374 tw32(NVRAM_CMD, nvram_cmd);
2375 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2376 udelay(10);
2377 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2378 udelay(10);
2379 break;
2380 }
2381 }
2382
2383 if (i == NVRAM_CMD_TIMEOUT)
2384 return -EBUSY;
2385
2386 return 0;
2387}
2388
2389static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2390{
2391 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2392 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2393 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2394 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2395 (tp->nvram_jedecnum == JEDEC_ATMEL))
2396
2397 addr = ((addr / tp->nvram_pagesize) <<
2398 ATMEL_AT45DB0X1B_PAGE_POS) +
2399 (addr % tp->nvram_pagesize);
2400
2401 return addr;
2402}
2403
2404static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2405{
2406 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2407 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2408 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2409 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2410 (tp->nvram_jedecnum == JEDEC_ATMEL))
2411
2412 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2413 tp->nvram_pagesize) +
2414 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2415
2416 return addr;
2417}
2418
Matt Carlsone4f34112009-02-25 14:25:00 +00002419/* NOTE: Data read in from NVRAM is byteswapped according to
2420 * the byteswapping settings for all other register accesses.
2421 * tg3 devices are BE devices, so on a BE machine, the data
2422 * returned will be exactly as it is seen in NVRAM. On a LE
2423 * machine, the 32-bit value will be byteswapped.
2424 */
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002425static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2426{
2427 int ret;
2428
2429 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2430 return tg3_nvram_read_using_eeprom(tp, offset, val);
2431
2432 offset = tg3_nvram_phys_addr(tp, offset);
2433
2434 if (offset > NVRAM_ADDR_MSK)
2435 return -EINVAL;
2436
2437 ret = tg3_nvram_lock(tp);
2438 if (ret)
2439 return ret;
2440
2441 tg3_enable_nvram_access(tp);
2442
2443 tw32(NVRAM_ADDR, offset);
2444 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2445 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2446
2447 if (ret == 0)
Matt Carlsone4f34112009-02-25 14:25:00 +00002448 *val = tr32(NVRAM_RDDATA);
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002449
2450 tg3_disable_nvram_access(tp);
2451
2452 tg3_nvram_unlock(tp);
2453
2454 return ret;
2455}
2456
Matt Carlsona9dc5292009-02-25 14:25:30 +00002457/* Ensures NVRAM data is in bytestream format. */
2458static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002459{
2460 u32 v;
Matt Carlsona9dc5292009-02-25 14:25:30 +00002461 int res = tg3_nvram_read(tp, offset, &v);
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002462 if (!res)
Matt Carlsona9dc5292009-02-25 14:25:30 +00002463 *val = cpu_to_be32(v);
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002464 return res;
2465}
2466
2467/* tp->lock is held. */
Matt Carlson3f007892008-11-03 16:51:36 -08002468static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2469{
2470 u32 addr_high, addr_low;
2471 int i;
2472
2473 addr_high = ((tp->dev->dev_addr[0] << 8) |
2474 tp->dev->dev_addr[1]);
2475 addr_low = ((tp->dev->dev_addr[2] << 24) |
2476 (tp->dev->dev_addr[3] << 16) |
2477 (tp->dev->dev_addr[4] << 8) |
2478 (tp->dev->dev_addr[5] << 0));
2479 for (i = 0; i < 4; i++) {
2480 if (i == 1 && skip_mac_1)
2481 continue;
2482 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2483 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2484 }
2485
2486 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2487 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2488 for (i = 0; i < 12; i++) {
2489 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2490 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2491 }
2492 }
2493
2494 addr_high = (tp->dev->dev_addr[0] +
2495 tp->dev->dev_addr[1] +
2496 tp->dev->dev_addr[2] +
2497 tp->dev->dev_addr[3] +
2498 tp->dev->dev_addr[4] +
2499 tp->dev->dev_addr[5]) &
2500 TX_BACKOFF_SEED_MASK;
2501 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2502}
2503
Michael Chanbc1c7562006-03-20 17:48:03 -08002504static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002505{
2506 u32 misc_host_ctrl;
Matt Carlson0a459aa2008-11-03 16:54:15 -08002507 bool device_should_wake, do_low_power;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002508
2509 /* Make sure register accesses (indirect or otherwise)
2510 * will function correctly.
2511 */
2512 pci_write_config_dword(tp->pdev,
2513 TG3PCI_MISC_HOST_CTRL,
2514 tp->misc_host_ctrl);
2515
Linus Torvalds1da177e2005-04-16 15:20:36 -07002516 switch (state) {
Michael Chanbc1c7562006-03-20 17:48:03 -08002517 case PCI_D0:
Rafael J. Wysocki12dac072008-07-30 16:37:33 -07002518 pci_enable_wake(tp->pdev, state, false);
2519 pci_set_power_state(tp->pdev, PCI_D0);
Michael Chan8c6bda12005-04-21 17:09:08 -07002520
Michael Chan9d26e212006-12-07 00:21:14 -08002521 /* Switch out of Vaux if it is a NIC */
2522 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
Michael Chanb401e9e2005-12-19 16:27:04 -08002523 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002524
2525 return 0;
2526
Michael Chanbc1c7562006-03-20 17:48:03 -08002527 case PCI_D1:
Michael Chanbc1c7562006-03-20 17:48:03 -08002528 case PCI_D2:
Michael Chanbc1c7562006-03-20 17:48:03 -08002529 case PCI_D3hot:
Linus Torvalds1da177e2005-04-16 15:20:36 -07002530 break;
2531
2532 default:
Joe Perches05dbe002010-02-17 19:44:19 +00002533 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2534 state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002535 return -EINVAL;
Stephen Hemminger855e1112008-04-16 16:37:28 -07002536 }
Matt Carlson5e7dfd02008-11-21 17:18:16 -08002537
2538 /* Restore the CLKREQ setting. */
2539 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2540 u16 lnkctl;
2541
2542 pci_read_config_word(tp->pdev,
2543 tp->pcie_cap + PCI_EXP_LNKCTL,
2544 &lnkctl);
2545 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2546 pci_write_config_word(tp->pdev,
2547 tp->pcie_cap + PCI_EXP_LNKCTL,
2548 lnkctl);
2549 }
2550
Linus Torvalds1da177e2005-04-16 15:20:36 -07002551 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2552 tw32(TG3PCI_MISC_HOST_CTRL,
2553 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2554
Matt Carlson05ac4cb2008-11-03 16:53:46 -08002555 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2556 device_may_wakeup(&tp->pdev->dev) &&
2557 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2558
Matt Carlsondd477002008-05-25 23:45:58 -07002559 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
Matt Carlson0a459aa2008-11-03 16:54:15 -08002560 do_low_power = false;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002561 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
Matt Carlson800960682010-08-02 11:26:06 +00002562 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002563 struct phy_device *phydev;
Matt Carlson0a459aa2008-11-03 16:54:15 -08002564 u32 phyid, advertising;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002565
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00002566 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002567
Matt Carlson800960682010-08-02 11:26:06 +00002568 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002569
2570 tp->link_config.orig_speed = phydev->speed;
2571 tp->link_config.orig_duplex = phydev->duplex;
2572 tp->link_config.orig_autoneg = phydev->autoneg;
2573 tp->link_config.orig_advertising = phydev->advertising;
2574
2575 advertising = ADVERTISED_TP |
2576 ADVERTISED_Pause |
2577 ADVERTISED_Autoneg |
2578 ADVERTISED_10baseT_Half;
2579
2580 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
Matt Carlson05ac4cb2008-11-03 16:53:46 -08002581 device_should_wake) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002582 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2583 advertising |=
2584 ADVERTISED_100baseT_Half |
2585 ADVERTISED_100baseT_Full |
2586 ADVERTISED_10baseT_Full;
2587 else
2588 advertising |= ADVERTISED_10baseT_Full;
2589 }
2590
2591 phydev->advertising = advertising;
2592
2593 phy_start_aneg(phydev);
Matt Carlson0a459aa2008-11-03 16:54:15 -08002594
2595 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
Matt Carlson6a443a02010-02-17 15:17:04 +00002596 if (phyid != PHY_ID_BCMAC131) {
2597 phyid &= PHY_BCM_OUI_MASK;
2598 if (phyid == PHY_BCM_OUI_1 ||
2599 phyid == PHY_BCM_OUI_2 ||
2600 phyid == PHY_BCM_OUI_3)
Matt Carlson0a459aa2008-11-03 16:54:15 -08002601 do_low_power = true;
2602 }
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002603 }
Matt Carlsondd477002008-05-25 23:45:58 -07002604 } else {
Matt Carlson20232762008-12-21 20:18:56 -08002605 do_low_power = true;
Matt Carlson0a459aa2008-11-03 16:54:15 -08002606
Matt Carlson800960682010-08-02 11:26:06 +00002607 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2608 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
Matt Carlsondd477002008-05-25 23:45:58 -07002609 tp->link_config.orig_speed = tp->link_config.speed;
2610 tp->link_config.orig_duplex = tp->link_config.duplex;
2611 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2612 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002613
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002614 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
Matt Carlsondd477002008-05-25 23:45:58 -07002615 tp->link_config.speed = SPEED_10;
2616 tp->link_config.duplex = DUPLEX_HALF;
2617 tp->link_config.autoneg = AUTONEG_ENABLE;
2618 tg3_setup_phy(tp, 0);
2619 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002620 }
2621
Michael Chanb5d37722006-09-27 16:06:21 -07002622 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2623 u32 val;
2624
2625 val = tr32(GRC_VCPU_EXT_CTRL);
2626 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2627 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
Michael Chan6921d202005-12-13 21:15:53 -08002628 int i;
2629 u32 val;
2630
2631 for (i = 0; i < 200; i++) {
2632 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2633 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2634 break;
2635 msleep(1);
2636 }
2637 }
Gary Zambranoa85feb82007-05-05 11:52:19 -07002638 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2639 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2640 WOL_DRV_STATE_SHUTDOWN |
2641 WOL_DRV_WOL |
2642 WOL_SET_MAGIC_PKT);
Michael Chan6921d202005-12-13 21:15:53 -08002643
Matt Carlson05ac4cb2008-11-03 16:53:46 -08002644 if (device_should_wake) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002645 u32 mac_mode;
2646
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002647 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
Matt Carlson0a459aa2008-11-03 16:54:15 -08002648 if (do_low_power) {
Matt Carlsondd477002008-05-25 23:45:58 -07002649 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2650 udelay(40);
2651 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002652
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002653 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
Michael Chan3f7045c2006-09-27 16:02:29 -07002654 mac_mode = MAC_MODE_PORT_MODE_GMII;
2655 else
2656 mac_mode = MAC_MODE_PORT_MODE_MII;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002657
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07002658 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2659 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2660 ASIC_REV_5700) {
2661 u32 speed = (tp->tg3_flags &
2662 TG3_FLAG_WOL_SPEED_100MB) ?
2663 SPEED_100 : SPEED_10;
2664 if (tg3_5700_link_polarity(tp, speed))
2665 mac_mode |= MAC_MODE_LINK_POLARITY;
2666 else
2667 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2668 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002669 } else {
2670 mac_mode = MAC_MODE_PORT_MODE_TBI;
2671 }
2672
John W. Linvillecbf46852005-04-21 17:01:29 -07002673 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07002674 tw32(MAC_LED_CTRL, tp->led_ctrl);
2675
Matt Carlson05ac4cb2008-11-03 16:53:46 -08002676 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2677 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2678 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2679 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2680 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2681 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002682
Matt Carlson3bda1252008-08-15 14:08:22 -07002683 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2684 mac_mode |= tp->mac_mode &
2685 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2686 if (mac_mode & MAC_MODE_APE_TX_EN)
2687 mac_mode |= MAC_MODE_TDE_ENABLE;
2688 }
2689
Linus Torvalds1da177e2005-04-16 15:20:36 -07002690 tw32_f(MAC_MODE, mac_mode);
2691 udelay(100);
2692
2693 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2694 udelay(10);
2695 }
2696
2697 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2698 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2699 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2700 u32 base_val;
2701
2702 base_val = tp->pci_clock_ctrl;
2703 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2704 CLOCK_CTRL_TXCLK_DISABLE);
2705
Michael Chanb401e9e2005-12-19 16:27:04 -08002706 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2707 CLOCK_CTRL_PWRDOWN_PLL133, 40);
Michael Chand7b0a852007-02-13 12:17:38 -08002708 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
Matt Carlson795d01c2007-10-07 23:28:17 -07002709 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
Michael Chand7b0a852007-02-13 12:17:38 -08002710 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
Michael Chan4cf78e42005-07-25 12:29:19 -07002711 /* do nothing */
Michael Chan85e94ce2005-04-21 17:05:28 -07002712 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07002713 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2714 u32 newbits1, newbits2;
2715
2716 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2717 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2718 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2719 CLOCK_CTRL_TXCLK_DISABLE |
2720 CLOCK_CTRL_ALTCLK);
2721 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2722 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2723 newbits1 = CLOCK_CTRL_625_CORE;
2724 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2725 } else {
2726 newbits1 = CLOCK_CTRL_ALTCLK;
2727 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2728 }
2729
Michael Chanb401e9e2005-12-19 16:27:04 -08002730 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2731 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002732
Michael Chanb401e9e2005-12-19 16:27:04 -08002733 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2734 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002735
2736 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2737 u32 newbits3;
2738
2739 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2740 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2741 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2742 CLOCK_CTRL_TXCLK_DISABLE |
2743 CLOCK_CTRL_44MHZ_CORE);
2744 } else {
2745 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2746 }
2747
Michael Chanb401e9e2005-12-19 16:27:04 -08002748 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2749 tp->pci_clock_ctrl | newbits3, 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002750 }
2751 }
2752
Matt Carlson05ac4cb2008-11-03 16:53:46 -08002753 if (!(device_should_wake) &&
Matt Carlson22435842008-11-21 17:21:13 -08002754 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
Matt Carlson0a459aa2008-11-03 16:54:15 -08002755 tg3_power_down_phy(tp, do_low_power);
Michael Chan6921d202005-12-13 21:15:53 -08002756
Linus Torvalds1da177e2005-04-16 15:20:36 -07002757 tg3_frob_aux_power(tp);
2758
2759 /* Workaround for unstable PLL clock */
2760 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2761 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2762 u32 val = tr32(0x7d00);
2763
2764 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2765 tw32(0x7d00, val);
Michael Chan6921d202005-12-13 21:15:53 -08002766 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
Michael Chanec41c7d2006-01-17 02:40:55 -08002767 int err;
2768
2769 err = tg3_nvram_lock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002770 tg3_halt_cpu(tp, RX_CPU_BASE);
Michael Chanec41c7d2006-01-17 02:40:55 -08002771 if (!err)
2772 tg3_nvram_unlock(tp);
Michael Chan6921d202005-12-13 21:15:53 -08002773 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002774 }
2775
Michael Chanbbadf502006-04-06 21:46:34 -07002776 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2777
Matt Carlson05ac4cb2008-11-03 16:53:46 -08002778 if (device_should_wake)
Rafael J. Wysocki12dac072008-07-30 16:37:33 -07002779 pci_enable_wake(tp->pdev, state, true);
2780
Linus Torvalds1da177e2005-04-16 15:20:36 -07002781 /* Finally, set the new power state. */
Rafael J. Wysocki12dac072008-07-30 16:37:33 -07002782 pci_set_power_state(tp->pdev, state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002783
Linus Torvalds1da177e2005-04-16 15:20:36 -07002784 return 0;
2785}
2786
Linus Torvalds1da177e2005-04-16 15:20:36 -07002787static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2788{
2789 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2790 case MII_TG3_AUX_STAT_10HALF:
2791 *speed = SPEED_10;
2792 *duplex = DUPLEX_HALF;
2793 break;
2794
2795 case MII_TG3_AUX_STAT_10FULL:
2796 *speed = SPEED_10;
2797 *duplex = DUPLEX_FULL;
2798 break;
2799
2800 case MII_TG3_AUX_STAT_100HALF:
2801 *speed = SPEED_100;
2802 *duplex = DUPLEX_HALF;
2803 break;
2804
2805 case MII_TG3_AUX_STAT_100FULL:
2806 *speed = SPEED_100;
2807 *duplex = DUPLEX_FULL;
2808 break;
2809
2810 case MII_TG3_AUX_STAT_1000HALF:
2811 *speed = SPEED_1000;
2812 *duplex = DUPLEX_HALF;
2813 break;
2814
2815 case MII_TG3_AUX_STAT_1000FULL:
2816 *speed = SPEED_1000;
2817 *duplex = DUPLEX_FULL;
2818 break;
2819
2820 default:
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002821 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Michael Chan715116a2006-09-27 16:09:25 -07002822 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2823 SPEED_10;
2824 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2825 DUPLEX_HALF;
2826 break;
2827 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002828 *speed = SPEED_INVALID;
2829 *duplex = DUPLEX_INVALID;
2830 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07002831 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002832}
2833
2834static void tg3_phy_copper_begin(struct tg3 *tp)
2835{
2836 u32 new_adv;
2837 int i;
2838
Matt Carlson800960682010-08-02 11:26:06 +00002839 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002840 /* Entering low power mode. Disable gigabit and
2841 * 100baseT advertisements.
2842 */
2843 tg3_writephy(tp, MII_TG3_CTRL, 0);
2844
2845 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2846 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2847 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2848 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2849
2850 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2851 } else if (tp->link_config.speed == SPEED_INVALID) {
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002852 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002853 tp->link_config.advertising &=
2854 ~(ADVERTISED_1000baseT_Half |
2855 ADVERTISED_1000baseT_Full);
2856
Matt Carlsonba4d07a2007-12-20 20:08:00 -08002857 new_adv = ADVERTISE_CSMA;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002858 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2859 new_adv |= ADVERTISE_10HALF;
2860 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2861 new_adv |= ADVERTISE_10FULL;
2862 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2863 new_adv |= ADVERTISE_100HALF;
2864 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2865 new_adv |= ADVERTISE_100FULL;
Matt Carlsonba4d07a2007-12-20 20:08:00 -08002866
2867 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2868
Linus Torvalds1da177e2005-04-16 15:20:36 -07002869 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2870
2871 if (tp->link_config.advertising &
2872 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2873 new_adv = 0;
2874 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2875 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2876 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2877 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002878 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07002879 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2880 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2881 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2882 MII_TG3_CTRL_ENABLE_AS_MASTER);
2883 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2884 } else {
2885 tg3_writephy(tp, MII_TG3_CTRL, 0);
2886 }
2887 } else {
Matt Carlsonba4d07a2007-12-20 20:08:00 -08002888 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2889 new_adv |= ADVERTISE_CSMA;
2890
Linus Torvalds1da177e2005-04-16 15:20:36 -07002891 /* Asking for a specific link mode. */
2892 if (tp->link_config.speed == SPEED_1000) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002893 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2894
2895 if (tp->link_config.duplex == DUPLEX_FULL)
2896 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2897 else
2898 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2899 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2900 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2901 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2902 MII_TG3_CTRL_ENABLE_AS_MASTER);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002903 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002904 if (tp->link_config.speed == SPEED_100) {
2905 if (tp->link_config.duplex == DUPLEX_FULL)
2906 new_adv |= ADVERTISE_100FULL;
2907 else
2908 new_adv |= ADVERTISE_100HALF;
2909 } else {
2910 if (tp->link_config.duplex == DUPLEX_FULL)
2911 new_adv |= ADVERTISE_10FULL;
2912 else
2913 new_adv |= ADVERTISE_10HALF;
2914 }
2915 tg3_writephy(tp, MII_ADVERTISE, new_adv);
Matt Carlsonba4d07a2007-12-20 20:08:00 -08002916
2917 new_adv = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002918 }
Matt Carlsonba4d07a2007-12-20 20:08:00 -08002919
2920 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002921 }
2922
2923 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2924 tp->link_config.speed != SPEED_INVALID) {
2925 u32 bmcr, orig_bmcr;
2926
2927 tp->link_config.active_speed = tp->link_config.speed;
2928 tp->link_config.active_duplex = tp->link_config.duplex;
2929
2930 bmcr = 0;
2931 switch (tp->link_config.speed) {
2932 default:
2933 case SPEED_10:
2934 break;
2935
2936 case SPEED_100:
2937 bmcr |= BMCR_SPEED100;
2938 break;
2939
2940 case SPEED_1000:
2941 bmcr |= TG3_BMCR_SPEED1000;
2942 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07002943 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002944
2945 if (tp->link_config.duplex == DUPLEX_FULL)
2946 bmcr |= BMCR_FULLDPLX;
2947
2948 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2949 (bmcr != orig_bmcr)) {
2950 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2951 for (i = 0; i < 1500; i++) {
2952 u32 tmp;
2953
2954 udelay(10);
2955 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2956 tg3_readphy(tp, MII_BMSR, &tmp))
2957 continue;
2958 if (!(tmp & BMSR_LSTATUS)) {
2959 udelay(40);
2960 break;
2961 }
2962 }
2963 tg3_writephy(tp, MII_BMCR, bmcr);
2964 udelay(40);
2965 }
2966 } else {
2967 tg3_writephy(tp, MII_BMCR,
2968 BMCR_ANENABLE | BMCR_ANRESTART);
2969 }
2970}
2971
2972static int tg3_init_5401phy_dsp(struct tg3 *tp)
2973{
2974 int err;
2975
2976 /* Turn off tap power management. */
2977 /* Set Extended packet length bit */
2978 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2979
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00002980 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
2981 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
2982 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
2983 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
2984 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002985
2986 udelay(40);
2987
2988 return err;
2989}
2990
Michael Chan3600d912006-12-07 00:21:48 -08002991static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002992{
Michael Chan3600d912006-12-07 00:21:48 -08002993 u32 adv_reg, all_mask = 0;
2994
2995 if (mask & ADVERTISED_10baseT_Half)
2996 all_mask |= ADVERTISE_10HALF;
2997 if (mask & ADVERTISED_10baseT_Full)
2998 all_mask |= ADVERTISE_10FULL;
2999 if (mask & ADVERTISED_100baseT_Half)
3000 all_mask |= ADVERTISE_100HALF;
3001 if (mask & ADVERTISED_100baseT_Full)
3002 all_mask |= ADVERTISE_100FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003003
3004 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3005 return 0;
3006
Linus Torvalds1da177e2005-04-16 15:20:36 -07003007 if ((adv_reg & all_mask) != all_mask)
3008 return 0;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003009 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003010 u32 tg3_ctrl;
3011
Michael Chan3600d912006-12-07 00:21:48 -08003012 all_mask = 0;
3013 if (mask & ADVERTISED_1000baseT_Half)
3014 all_mask |= ADVERTISE_1000HALF;
3015 if (mask & ADVERTISED_1000baseT_Full)
3016 all_mask |= ADVERTISE_1000FULL;
3017
Linus Torvalds1da177e2005-04-16 15:20:36 -07003018 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3019 return 0;
3020
Linus Torvalds1da177e2005-04-16 15:20:36 -07003021 if ((tg3_ctrl & all_mask) != all_mask)
3022 return 0;
3023 }
3024 return 1;
3025}
3026
Matt Carlsonef167e22007-12-20 20:10:01 -08003027static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3028{
3029 u32 curadv, reqadv;
3030
3031 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3032 return 1;
3033
3034 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3035 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3036
3037 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3038 if (curadv != reqadv)
3039 return 0;
3040
3041 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3042 tg3_readphy(tp, MII_LPA, rmtadv);
3043 } else {
3044 /* Reprogram the advertisement register, even if it
3045 * does not affect the current link. If the link
3046 * gets renegotiated in the future, we can save an
3047 * additional renegotiation cycle by advertising
3048 * it correctly in the first place.
3049 */
3050 if (curadv != reqadv) {
3051 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3052 ADVERTISE_PAUSE_ASYM);
3053 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3054 }
3055 }
3056
3057 return 1;
3058}
3059
Linus Torvalds1da177e2005-04-16 15:20:36 -07003060static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3061{
3062 int current_link_up;
3063 u32 bmsr, dummy;
Matt Carlsonef167e22007-12-20 20:10:01 -08003064 u32 lcl_adv, rmt_adv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003065 u16 current_speed;
3066 u8 current_duplex;
3067 int i, err;
3068
3069 tw32(MAC_EVENT, 0);
3070
3071 tw32_f(MAC_STATUS,
3072 (MAC_STATUS_SYNC_CHANGED |
3073 MAC_STATUS_CFG_CHANGED |
3074 MAC_STATUS_MI_COMPLETION |
3075 MAC_STATUS_LNKSTATE_CHANGED));
3076 udelay(40);
3077
Matt Carlson8ef21422008-05-02 16:47:53 -07003078 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3079 tw32_f(MAC_MI_MODE,
3080 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3081 udelay(80);
3082 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003083
3084 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3085
3086 /* Some third-party PHYs need to be reset on link going
3087 * down.
3088 */
3089 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3090 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3091 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3092 netif_carrier_ok(tp->dev)) {
3093 tg3_readphy(tp, MII_BMSR, &bmsr);
3094 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3095 !(bmsr & BMSR_LSTATUS))
3096 force_reset = 1;
3097 }
3098 if (force_reset)
3099 tg3_phy_reset(tp);
3100
Matt Carlson79eb6902010-02-17 15:17:03 +00003101 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003102 tg3_readphy(tp, MII_BMSR, &bmsr);
3103 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3104 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3105 bmsr = 0;
3106
3107 if (!(bmsr & BMSR_LSTATUS)) {
3108 err = tg3_init_5401phy_dsp(tp);
3109 if (err)
3110 return err;
3111
3112 tg3_readphy(tp, MII_BMSR, &bmsr);
3113 for (i = 0; i < 1000; i++) {
3114 udelay(10);
3115 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3116 (bmsr & BMSR_LSTATUS)) {
3117 udelay(40);
3118 break;
3119 }
3120 }
3121
Matt Carlson79eb6902010-02-17 15:17:03 +00003122 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3123 TG3_PHY_REV_BCM5401_B0 &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07003124 !(bmsr & BMSR_LSTATUS) &&
3125 tp->link_config.active_speed == SPEED_1000) {
3126 err = tg3_phy_reset(tp);
3127 if (!err)
3128 err = tg3_init_5401phy_dsp(tp);
3129 if (err)
3130 return err;
3131 }
3132 }
3133 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3134 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3135 /* 5701 {A0,B0} CRC bug workaround */
3136 tg3_writephy(tp, 0x15, 0x0a75);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00003137 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3138 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3139 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003140 }
3141
3142 /* Clear pending interrupts... */
3143 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3144 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3145
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003146 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003147 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003148 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
Linus Torvalds1da177e2005-04-16 15:20:36 -07003149 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3150
3151 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3152 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3153 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3154 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3155 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3156 else
3157 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3158 }
3159
3160 current_link_up = 0;
3161 current_speed = SPEED_INVALID;
3162 current_duplex = DUPLEX_INVALID;
3163
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003164 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003165 u32 val;
3166
3167 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3168 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3169 if (!(val & (1 << 10))) {
3170 val |= (1 << 10);
3171 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3172 goto relink;
3173 }
3174 }
3175
3176 bmsr = 0;
3177 for (i = 0; i < 100; i++) {
3178 tg3_readphy(tp, MII_BMSR, &bmsr);
3179 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3180 (bmsr & BMSR_LSTATUS))
3181 break;
3182 udelay(40);
3183 }
3184
3185 if (bmsr & BMSR_LSTATUS) {
3186 u32 aux_stat, bmcr;
3187
3188 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3189 for (i = 0; i < 2000; i++) {
3190 udelay(10);
3191 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3192 aux_stat)
3193 break;
3194 }
3195
3196 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3197 &current_speed,
3198 &current_duplex);
3199
3200 bmcr = 0;
3201 for (i = 0; i < 200; i++) {
3202 tg3_readphy(tp, MII_BMCR, &bmcr);
3203 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3204 continue;
3205 if (bmcr && bmcr != 0x7fff)
3206 break;
3207 udelay(10);
3208 }
3209
Matt Carlsonef167e22007-12-20 20:10:01 -08003210 lcl_adv = 0;
3211 rmt_adv = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003212
Matt Carlsonef167e22007-12-20 20:10:01 -08003213 tp->link_config.active_speed = current_speed;
3214 tp->link_config.active_duplex = current_duplex;
3215
3216 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3217 if ((bmcr & BMCR_ANENABLE) &&
3218 tg3_copper_is_advertising_all(tp,
3219 tp->link_config.advertising)) {
3220 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3221 &rmt_adv))
3222 current_link_up = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003223 }
3224 } else {
3225 if (!(bmcr & BMCR_ANENABLE) &&
3226 tp->link_config.speed == current_speed &&
Matt Carlsonef167e22007-12-20 20:10:01 -08003227 tp->link_config.duplex == current_duplex &&
3228 tp->link_config.flowctrl ==
3229 tp->link_config.active_flowctrl) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003230 current_link_up = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003231 }
3232 }
3233
Matt Carlsonef167e22007-12-20 20:10:01 -08003234 if (current_link_up == 1 &&
3235 tp->link_config.active_duplex == DUPLEX_FULL)
3236 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003237 }
3238
Linus Torvalds1da177e2005-04-16 15:20:36 -07003239relink:
Matt Carlson800960682010-08-02 11:26:06 +00003240 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003241 u32 tmp;
3242
3243 tg3_phy_copper_begin(tp);
3244
3245 tg3_readphy(tp, MII_BMSR, &tmp);
3246 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3247 (tmp & BMSR_LSTATUS))
3248 current_link_up = 1;
3249 }
3250
3251 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3252 if (current_link_up == 1) {
3253 if (tp->link_config.active_speed == SPEED_100 ||
3254 tp->link_config.active_speed == SPEED_10)
3255 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3256 else
3257 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003258 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
Matt Carlson7f97a4b2009-08-25 10:10:03 +00003259 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3260 else
Linus Torvalds1da177e2005-04-16 15:20:36 -07003261 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3262
3263 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3264 if (tp->link_config.active_duplex == DUPLEX_HALF)
3265 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3266
Linus Torvalds1da177e2005-04-16 15:20:36 -07003267 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07003268 if (current_link_up == 1 &&
3269 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
Linus Torvalds1da177e2005-04-16 15:20:36 -07003270 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07003271 else
3272 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003273 }
3274
3275 /* ??? Without this setting Netgear GA302T PHY does not
3276 * ??? send/receive packets...
3277 */
Matt Carlson79eb6902010-02-17 15:17:03 +00003278 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07003279 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3280 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3281 tw32_f(MAC_MI_MODE, tp->mi_mode);
3282 udelay(80);
3283 }
3284
3285 tw32_f(MAC_MODE, tp->mac_mode);
3286 udelay(40);
3287
3288 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3289 /* Polled via timer. */
3290 tw32_f(MAC_EVENT, 0);
3291 } else {
3292 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3293 }
3294 udelay(40);
3295
3296 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3297 current_link_up == 1 &&
3298 tp->link_config.active_speed == SPEED_1000 &&
3299 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3300 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3301 udelay(120);
3302 tw32_f(MAC_STATUS,
3303 (MAC_STATUS_SYNC_CHANGED |
3304 MAC_STATUS_CFG_CHANGED));
3305 udelay(40);
3306 tg3_write_mem(tp,
3307 NIC_SRAM_FIRMWARE_MBOX,
3308 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3309 }
3310
Matt Carlson5e7dfd02008-11-21 17:18:16 -08003311 /* Prevent send BD corruption. */
3312 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3313 u16 oldlnkctl, newlnkctl;
3314
3315 pci_read_config_word(tp->pdev,
3316 tp->pcie_cap + PCI_EXP_LNKCTL,
3317 &oldlnkctl);
3318 if (tp->link_config.active_speed == SPEED_100 ||
3319 tp->link_config.active_speed == SPEED_10)
3320 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3321 else
3322 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3323 if (newlnkctl != oldlnkctl)
3324 pci_write_config_word(tp->pdev,
3325 tp->pcie_cap + PCI_EXP_LNKCTL,
3326 newlnkctl);
3327 }
3328
Linus Torvalds1da177e2005-04-16 15:20:36 -07003329 if (current_link_up != netif_carrier_ok(tp->dev)) {
3330 if (current_link_up)
3331 netif_carrier_on(tp->dev);
3332 else
3333 netif_carrier_off(tp->dev);
3334 tg3_link_report(tp);
3335 }
3336
3337 return 0;
3338}
3339
3340struct tg3_fiber_aneginfo {
3341 int state;
3342#define ANEG_STATE_UNKNOWN 0
3343#define ANEG_STATE_AN_ENABLE 1
3344#define ANEG_STATE_RESTART_INIT 2
3345#define ANEG_STATE_RESTART 3
3346#define ANEG_STATE_DISABLE_LINK_OK 4
3347#define ANEG_STATE_ABILITY_DETECT_INIT 5
3348#define ANEG_STATE_ABILITY_DETECT 6
3349#define ANEG_STATE_ACK_DETECT_INIT 7
3350#define ANEG_STATE_ACK_DETECT 8
3351#define ANEG_STATE_COMPLETE_ACK_INIT 9
3352#define ANEG_STATE_COMPLETE_ACK 10
3353#define ANEG_STATE_IDLE_DETECT_INIT 11
3354#define ANEG_STATE_IDLE_DETECT 12
3355#define ANEG_STATE_LINK_OK 13
3356#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3357#define ANEG_STATE_NEXT_PAGE_WAIT 15
3358
3359 u32 flags;
3360#define MR_AN_ENABLE 0x00000001
3361#define MR_RESTART_AN 0x00000002
3362#define MR_AN_COMPLETE 0x00000004
3363#define MR_PAGE_RX 0x00000008
3364#define MR_NP_LOADED 0x00000010
3365#define MR_TOGGLE_TX 0x00000020
3366#define MR_LP_ADV_FULL_DUPLEX 0x00000040
3367#define MR_LP_ADV_HALF_DUPLEX 0x00000080
3368#define MR_LP_ADV_SYM_PAUSE 0x00000100
3369#define MR_LP_ADV_ASYM_PAUSE 0x00000200
3370#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3371#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3372#define MR_LP_ADV_NEXT_PAGE 0x00001000
3373#define MR_TOGGLE_RX 0x00002000
3374#define MR_NP_RX 0x00004000
3375
3376#define MR_LINK_OK 0x80000000
3377
3378 unsigned long link_time, cur_time;
3379
3380 u32 ability_match_cfg;
3381 int ability_match_count;
3382
3383 char ability_match, idle_match, ack_match;
3384
3385 u32 txconfig, rxconfig;
3386#define ANEG_CFG_NP 0x00000080
3387#define ANEG_CFG_ACK 0x00000040
3388#define ANEG_CFG_RF2 0x00000020
3389#define ANEG_CFG_RF1 0x00000010
3390#define ANEG_CFG_PS2 0x00000001
3391#define ANEG_CFG_PS1 0x00008000
3392#define ANEG_CFG_HD 0x00004000
3393#define ANEG_CFG_FD 0x00002000
3394#define ANEG_CFG_INVAL 0x00001f06
3395
3396};
3397#define ANEG_OK 0
3398#define ANEG_DONE 1
3399#define ANEG_TIMER_ENAB 2
3400#define ANEG_FAILED -1
3401
3402#define ANEG_STATE_SETTLE_TIME 10000
3403
3404static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3405 struct tg3_fiber_aneginfo *ap)
3406{
Matt Carlson5be73b42007-12-20 20:09:29 -08003407 u16 flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003408 unsigned long delta;
3409 u32 rx_cfg_reg;
3410 int ret;
3411
3412 if (ap->state == ANEG_STATE_UNKNOWN) {
3413 ap->rxconfig = 0;
3414 ap->link_time = 0;
3415 ap->cur_time = 0;
3416 ap->ability_match_cfg = 0;
3417 ap->ability_match_count = 0;
3418 ap->ability_match = 0;
3419 ap->idle_match = 0;
3420 ap->ack_match = 0;
3421 }
3422 ap->cur_time++;
3423
3424 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3425 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3426
3427 if (rx_cfg_reg != ap->ability_match_cfg) {
3428 ap->ability_match_cfg = rx_cfg_reg;
3429 ap->ability_match = 0;
3430 ap->ability_match_count = 0;
3431 } else {
3432 if (++ap->ability_match_count > 1) {
3433 ap->ability_match = 1;
3434 ap->ability_match_cfg = rx_cfg_reg;
3435 }
3436 }
3437 if (rx_cfg_reg & ANEG_CFG_ACK)
3438 ap->ack_match = 1;
3439 else
3440 ap->ack_match = 0;
3441
3442 ap->idle_match = 0;
3443 } else {
3444 ap->idle_match = 1;
3445 ap->ability_match_cfg = 0;
3446 ap->ability_match_count = 0;
3447 ap->ability_match = 0;
3448 ap->ack_match = 0;
3449
3450 rx_cfg_reg = 0;
3451 }
3452
3453 ap->rxconfig = rx_cfg_reg;
3454 ret = ANEG_OK;
3455
Matt Carlson33f401a2010-04-05 10:19:27 +00003456 switch (ap->state) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003457 case ANEG_STATE_UNKNOWN:
3458 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3459 ap->state = ANEG_STATE_AN_ENABLE;
3460
3461 /* fallthru */
3462 case ANEG_STATE_AN_ENABLE:
3463 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3464 if (ap->flags & MR_AN_ENABLE) {
3465 ap->link_time = 0;
3466 ap->cur_time = 0;
3467 ap->ability_match_cfg = 0;
3468 ap->ability_match_count = 0;
3469 ap->ability_match = 0;
3470 ap->idle_match = 0;
3471 ap->ack_match = 0;
3472
3473 ap->state = ANEG_STATE_RESTART_INIT;
3474 } else {
3475 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3476 }
3477 break;
3478
3479 case ANEG_STATE_RESTART_INIT:
3480 ap->link_time = ap->cur_time;
3481 ap->flags &= ~(MR_NP_LOADED);
3482 ap->txconfig = 0;
3483 tw32(MAC_TX_AUTO_NEG, 0);
3484 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3485 tw32_f(MAC_MODE, tp->mac_mode);
3486 udelay(40);
3487
3488 ret = ANEG_TIMER_ENAB;
3489 ap->state = ANEG_STATE_RESTART;
3490
3491 /* fallthru */
3492 case ANEG_STATE_RESTART:
3493 delta = ap->cur_time - ap->link_time;
Matt Carlson859a588792010-04-05 10:19:28 +00003494 if (delta > ANEG_STATE_SETTLE_TIME)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003495 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
Matt Carlson859a588792010-04-05 10:19:28 +00003496 else
Linus Torvalds1da177e2005-04-16 15:20:36 -07003497 ret = ANEG_TIMER_ENAB;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003498 break;
3499
3500 case ANEG_STATE_DISABLE_LINK_OK:
3501 ret = ANEG_DONE;
3502 break;
3503
3504 case ANEG_STATE_ABILITY_DETECT_INIT:
3505 ap->flags &= ~(MR_TOGGLE_TX);
Matt Carlson5be73b42007-12-20 20:09:29 -08003506 ap->txconfig = ANEG_CFG_FD;
3507 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3508 if (flowctrl & ADVERTISE_1000XPAUSE)
3509 ap->txconfig |= ANEG_CFG_PS1;
3510 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3511 ap->txconfig |= ANEG_CFG_PS2;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003512 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3513 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3514 tw32_f(MAC_MODE, tp->mac_mode);
3515 udelay(40);
3516
3517 ap->state = ANEG_STATE_ABILITY_DETECT;
3518 break;
3519
3520 case ANEG_STATE_ABILITY_DETECT:
Matt Carlson859a588792010-04-05 10:19:28 +00003521 if (ap->ability_match != 0 && ap->rxconfig != 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003522 ap->state = ANEG_STATE_ACK_DETECT_INIT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003523 break;
3524
3525 case ANEG_STATE_ACK_DETECT_INIT:
3526 ap->txconfig |= ANEG_CFG_ACK;
3527 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3528 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3529 tw32_f(MAC_MODE, tp->mac_mode);
3530 udelay(40);
3531
3532 ap->state = ANEG_STATE_ACK_DETECT;
3533
3534 /* fallthru */
3535 case ANEG_STATE_ACK_DETECT:
3536 if (ap->ack_match != 0) {
3537 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3538 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3539 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3540 } else {
3541 ap->state = ANEG_STATE_AN_ENABLE;
3542 }
3543 } else if (ap->ability_match != 0 &&
3544 ap->rxconfig == 0) {
3545 ap->state = ANEG_STATE_AN_ENABLE;
3546 }
3547 break;
3548
3549 case ANEG_STATE_COMPLETE_ACK_INIT:
3550 if (ap->rxconfig & ANEG_CFG_INVAL) {
3551 ret = ANEG_FAILED;
3552 break;
3553 }
3554 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3555 MR_LP_ADV_HALF_DUPLEX |
3556 MR_LP_ADV_SYM_PAUSE |
3557 MR_LP_ADV_ASYM_PAUSE |
3558 MR_LP_ADV_REMOTE_FAULT1 |
3559 MR_LP_ADV_REMOTE_FAULT2 |
3560 MR_LP_ADV_NEXT_PAGE |
3561 MR_TOGGLE_RX |
3562 MR_NP_RX);
3563 if (ap->rxconfig & ANEG_CFG_FD)
3564 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3565 if (ap->rxconfig & ANEG_CFG_HD)
3566 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3567 if (ap->rxconfig & ANEG_CFG_PS1)
3568 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3569 if (ap->rxconfig & ANEG_CFG_PS2)
3570 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3571 if (ap->rxconfig & ANEG_CFG_RF1)
3572 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3573 if (ap->rxconfig & ANEG_CFG_RF2)
3574 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3575 if (ap->rxconfig & ANEG_CFG_NP)
3576 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3577
3578 ap->link_time = ap->cur_time;
3579
3580 ap->flags ^= (MR_TOGGLE_TX);
3581 if (ap->rxconfig & 0x0008)
3582 ap->flags |= MR_TOGGLE_RX;
3583 if (ap->rxconfig & ANEG_CFG_NP)
3584 ap->flags |= MR_NP_RX;
3585 ap->flags |= MR_PAGE_RX;
3586
3587 ap->state = ANEG_STATE_COMPLETE_ACK;
3588 ret = ANEG_TIMER_ENAB;
3589 break;
3590
3591 case ANEG_STATE_COMPLETE_ACK:
3592 if (ap->ability_match != 0 &&
3593 ap->rxconfig == 0) {
3594 ap->state = ANEG_STATE_AN_ENABLE;
3595 break;
3596 }
3597 delta = ap->cur_time - ap->link_time;
3598 if (delta > ANEG_STATE_SETTLE_TIME) {
3599 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3600 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3601 } else {
3602 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3603 !(ap->flags & MR_NP_RX)) {
3604 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3605 } else {
3606 ret = ANEG_FAILED;
3607 }
3608 }
3609 }
3610 break;
3611
3612 case ANEG_STATE_IDLE_DETECT_INIT:
3613 ap->link_time = ap->cur_time;
3614 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3615 tw32_f(MAC_MODE, tp->mac_mode);
3616 udelay(40);
3617
3618 ap->state = ANEG_STATE_IDLE_DETECT;
3619 ret = ANEG_TIMER_ENAB;
3620 break;
3621
3622 case ANEG_STATE_IDLE_DETECT:
3623 if (ap->ability_match != 0 &&
3624 ap->rxconfig == 0) {
3625 ap->state = ANEG_STATE_AN_ENABLE;
3626 break;
3627 }
3628 delta = ap->cur_time - ap->link_time;
3629 if (delta > ANEG_STATE_SETTLE_TIME) {
3630 /* XXX another gem from the Broadcom driver :( */
3631 ap->state = ANEG_STATE_LINK_OK;
3632 }
3633 break;
3634
3635 case ANEG_STATE_LINK_OK:
3636 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3637 ret = ANEG_DONE;
3638 break;
3639
3640 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3641 /* ??? unimplemented */
3642 break;
3643
3644 case ANEG_STATE_NEXT_PAGE_WAIT:
3645 /* ??? unimplemented */
3646 break;
3647
3648 default:
3649 ret = ANEG_FAILED;
3650 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07003651 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003652
3653 return ret;
3654}
3655
Matt Carlson5be73b42007-12-20 20:09:29 -08003656static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003657{
3658 int res = 0;
3659 struct tg3_fiber_aneginfo aninfo;
3660 int status = ANEG_FAILED;
3661 unsigned int tick;
3662 u32 tmp;
3663
3664 tw32_f(MAC_TX_AUTO_NEG, 0);
3665
3666 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3667 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3668 udelay(40);
3669
3670 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3671 udelay(40);
3672
3673 memset(&aninfo, 0, sizeof(aninfo));
3674 aninfo.flags |= MR_AN_ENABLE;
3675 aninfo.state = ANEG_STATE_UNKNOWN;
3676 aninfo.cur_time = 0;
3677 tick = 0;
3678 while (++tick < 195000) {
3679 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3680 if (status == ANEG_DONE || status == ANEG_FAILED)
3681 break;
3682
3683 udelay(1);
3684 }
3685
3686 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3687 tw32_f(MAC_MODE, tp->mac_mode);
3688 udelay(40);
3689
Matt Carlson5be73b42007-12-20 20:09:29 -08003690 *txflags = aninfo.txconfig;
3691 *rxflags = aninfo.flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003692
3693 if (status == ANEG_DONE &&
3694 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3695 MR_LP_ADV_FULL_DUPLEX)))
3696 res = 1;
3697
3698 return res;
3699}
3700
3701static void tg3_init_bcm8002(struct tg3 *tp)
3702{
3703 u32 mac_status = tr32(MAC_STATUS);
3704 int i;
3705
3706 /* Reset when initting first time or we have a link. */
3707 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3708 !(mac_status & MAC_STATUS_PCS_SYNCED))
3709 return;
3710
3711 /* Set PLL lock range. */
3712 tg3_writephy(tp, 0x16, 0x8007);
3713
3714 /* SW reset */
3715 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3716
3717 /* Wait for reset to complete. */
3718 /* XXX schedule_timeout() ... */
3719 for (i = 0; i < 500; i++)
3720 udelay(10);
3721
3722 /* Config mode; select PMA/Ch 1 regs. */
3723 tg3_writephy(tp, 0x10, 0x8411);
3724
3725 /* Enable auto-lock and comdet, select txclk for tx. */
3726 tg3_writephy(tp, 0x11, 0x0a10);
3727
3728 tg3_writephy(tp, 0x18, 0x00a0);
3729 tg3_writephy(tp, 0x16, 0x41ff);
3730
3731 /* Assert and deassert POR. */
3732 tg3_writephy(tp, 0x13, 0x0400);
3733 udelay(40);
3734 tg3_writephy(tp, 0x13, 0x0000);
3735
3736 tg3_writephy(tp, 0x11, 0x0a50);
3737 udelay(40);
3738 tg3_writephy(tp, 0x11, 0x0a10);
3739
3740 /* Wait for signal to stabilize */
3741 /* XXX schedule_timeout() ... */
3742 for (i = 0; i < 15000; i++)
3743 udelay(10);
3744
3745 /* Deselect the channel register so we can read the PHYID
3746 * later.
3747 */
3748 tg3_writephy(tp, 0x10, 0x8011);
3749}
3750
3751static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3752{
Matt Carlson82cd3d12007-12-20 20:09:00 -08003753 u16 flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003754 u32 sg_dig_ctrl, sg_dig_status;
3755 u32 serdes_cfg, expected_sg_dig_ctrl;
3756 int workaround, port_a;
3757 int current_link_up;
3758
3759 serdes_cfg = 0;
3760 expected_sg_dig_ctrl = 0;
3761 workaround = 0;
3762 port_a = 1;
3763 current_link_up = 0;
3764
3765 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3766 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3767 workaround = 1;
3768 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3769 port_a = 0;
3770
3771 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3772 /* preserve bits 20-23 for voltage regulator */
3773 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3774 }
3775
3776 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3777
3778 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003779 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003780 if (workaround) {
3781 u32 val = serdes_cfg;
3782
3783 if (port_a)
3784 val |= 0xc010000;
3785 else
3786 val |= 0x4010000;
3787 tw32_f(MAC_SERDES_CFG, val);
3788 }
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003789
3790 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003791 }
3792 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3793 tg3_setup_flow_control(tp, 0, 0);
3794 current_link_up = 1;
3795 }
3796 goto out;
3797 }
3798
3799 /* Want auto-negotiation. */
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003800 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003801
Matt Carlson82cd3d12007-12-20 20:09:00 -08003802 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3803 if (flowctrl & ADVERTISE_1000XPAUSE)
3804 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3805 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3806 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003807
3808 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003809 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
Michael Chan3d3ebe72006-09-27 15:59:15 -07003810 tp->serdes_counter &&
3811 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3812 MAC_STATUS_RCVD_CFG)) ==
3813 MAC_STATUS_PCS_SYNCED)) {
3814 tp->serdes_counter--;
3815 current_link_up = 1;
3816 goto out;
3817 }
3818restart_autoneg:
Linus Torvalds1da177e2005-04-16 15:20:36 -07003819 if (workaround)
3820 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003821 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003822 udelay(5);
3823 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3824
Michael Chan3d3ebe72006-09-27 15:59:15 -07003825 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003826 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003827 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3828 MAC_STATUS_SIGNAL_DET)) {
Michael Chan3d3ebe72006-09-27 15:59:15 -07003829 sg_dig_status = tr32(SG_DIG_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003830 mac_status = tr32(MAC_STATUS);
3831
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003832 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07003833 (mac_status & MAC_STATUS_PCS_SYNCED)) {
Matt Carlson82cd3d12007-12-20 20:09:00 -08003834 u32 local_adv = 0, remote_adv = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003835
Matt Carlson82cd3d12007-12-20 20:09:00 -08003836 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3837 local_adv |= ADVERTISE_1000XPAUSE;
3838 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3839 local_adv |= ADVERTISE_1000XPSE_ASYM;
3840
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003841 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
Matt Carlson82cd3d12007-12-20 20:09:00 -08003842 remote_adv |= LPA_1000XPAUSE;
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003843 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
Matt Carlson82cd3d12007-12-20 20:09:00 -08003844 remote_adv |= LPA_1000XPAUSE_ASYM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003845
3846 tg3_setup_flow_control(tp, local_adv, remote_adv);
3847 current_link_up = 1;
Michael Chan3d3ebe72006-09-27 15:59:15 -07003848 tp->serdes_counter = 0;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003849 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003850 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
Michael Chan3d3ebe72006-09-27 15:59:15 -07003851 if (tp->serdes_counter)
3852 tp->serdes_counter--;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003853 else {
3854 if (workaround) {
3855 u32 val = serdes_cfg;
3856
3857 if (port_a)
3858 val |= 0xc010000;
3859 else
3860 val |= 0x4010000;
3861
3862 tw32_f(MAC_SERDES_CFG, val);
3863 }
3864
Matt Carlsonc98f6e32007-12-20 20:08:32 -08003865 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003866 udelay(40);
3867
3868 /* Link parallel detection - link is up */
3869 /* only if we have PCS_SYNC and not */
3870 /* receiving config code words */
3871 mac_status = tr32(MAC_STATUS);
3872 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3873 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3874 tg3_setup_flow_control(tp, 0, 0);
3875 current_link_up = 1;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003876 tp->phy_flags |=
3877 TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan3d3ebe72006-09-27 15:59:15 -07003878 tp->serdes_counter =
3879 SERDES_PARALLEL_DET_TIMEOUT;
3880 } else
3881 goto restart_autoneg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003882 }
3883 }
Michael Chan3d3ebe72006-09-27 15:59:15 -07003884 } else {
3885 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003886 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003887 }
3888
3889out:
3890 return current_link_up;
3891}
3892
3893static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3894{
3895 int current_link_up = 0;
3896
Michael Chan5cf64b8a2007-05-05 12:11:21 -07003897 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
Linus Torvalds1da177e2005-04-16 15:20:36 -07003898 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003899
3900 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
Matt Carlson5be73b42007-12-20 20:09:29 -08003901 u32 txflags, rxflags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003902 int i;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003903
Matt Carlson5be73b42007-12-20 20:09:29 -08003904 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3905 u32 local_adv = 0, remote_adv = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003906
Matt Carlson5be73b42007-12-20 20:09:29 -08003907 if (txflags & ANEG_CFG_PS1)
3908 local_adv |= ADVERTISE_1000XPAUSE;
3909 if (txflags & ANEG_CFG_PS2)
3910 local_adv |= ADVERTISE_1000XPSE_ASYM;
3911
3912 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3913 remote_adv |= LPA_1000XPAUSE;
3914 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3915 remote_adv |= LPA_1000XPAUSE_ASYM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003916
3917 tg3_setup_flow_control(tp, local_adv, remote_adv);
3918
Linus Torvalds1da177e2005-04-16 15:20:36 -07003919 current_link_up = 1;
3920 }
3921 for (i = 0; i < 30; i++) {
3922 udelay(20);
3923 tw32_f(MAC_STATUS,
3924 (MAC_STATUS_SYNC_CHANGED |
3925 MAC_STATUS_CFG_CHANGED));
3926 udelay(40);
3927 if ((tr32(MAC_STATUS) &
3928 (MAC_STATUS_SYNC_CHANGED |
3929 MAC_STATUS_CFG_CHANGED)) == 0)
3930 break;
3931 }
3932
3933 mac_status = tr32(MAC_STATUS);
3934 if (current_link_up == 0 &&
3935 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3936 !(mac_status & MAC_STATUS_RCVD_CFG))
3937 current_link_up = 1;
3938 } else {
Matt Carlson5be73b42007-12-20 20:09:29 -08003939 tg3_setup_flow_control(tp, 0, 0);
3940
Linus Torvalds1da177e2005-04-16 15:20:36 -07003941 /* Forcing 1000FD link up. */
3942 current_link_up = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003943
3944 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3945 udelay(40);
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07003946
3947 tw32_f(MAC_MODE, tp->mac_mode);
3948 udelay(40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003949 }
3950
3951out:
3952 return current_link_up;
3953}
3954
3955static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3956{
3957 u32 orig_pause_cfg;
3958 u16 orig_active_speed;
3959 u8 orig_active_duplex;
3960 u32 mac_status;
3961 int current_link_up;
3962 int i;
3963
Matt Carlson8d018622007-12-20 20:05:44 -08003964 orig_pause_cfg = tp->link_config.active_flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003965 orig_active_speed = tp->link_config.active_speed;
3966 orig_active_duplex = tp->link_config.active_duplex;
3967
3968 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3969 netif_carrier_ok(tp->dev) &&
3970 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3971 mac_status = tr32(MAC_STATUS);
3972 mac_status &= (MAC_STATUS_PCS_SYNCED |
3973 MAC_STATUS_SIGNAL_DET |
3974 MAC_STATUS_CFG_CHANGED |
3975 MAC_STATUS_RCVD_CFG);
3976 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3977 MAC_STATUS_SIGNAL_DET)) {
3978 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3979 MAC_STATUS_CFG_CHANGED));
3980 return 0;
3981 }
3982 }
3983
3984 tw32_f(MAC_TX_AUTO_NEG, 0);
3985
3986 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3987 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3988 tw32_f(MAC_MODE, tp->mac_mode);
3989 udelay(40);
3990
Matt Carlson79eb6902010-02-17 15:17:03 +00003991 if (tp->phy_id == TG3_PHY_ID_BCM8002)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003992 tg3_init_bcm8002(tp);
3993
3994 /* Enable link change event even when serdes polling. */
3995 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3996 udelay(40);
3997
3998 current_link_up = 0;
3999 mac_status = tr32(MAC_STATUS);
4000
4001 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4002 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4003 else
4004 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4005
Matt Carlson898a56f2009-08-28 14:02:40 +00004006 tp->napi[0].hw_status->status =
Linus Torvalds1da177e2005-04-16 15:20:36 -07004007 (SD_STATUS_UPDATED |
Matt Carlson898a56f2009-08-28 14:02:40 +00004008 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004009
4010 for (i = 0; i < 100; i++) {
4011 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4012 MAC_STATUS_CFG_CHANGED));
4013 udelay(5);
4014 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
Michael Chan3d3ebe72006-09-27 15:59:15 -07004015 MAC_STATUS_CFG_CHANGED |
4016 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004017 break;
4018 }
4019
4020 mac_status = tr32(MAC_STATUS);
4021 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4022 current_link_up = 0;
Michael Chan3d3ebe72006-09-27 15:59:15 -07004023 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4024 tp->serdes_counter == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004025 tw32_f(MAC_MODE, (tp->mac_mode |
4026 MAC_MODE_SEND_CONFIGS));
4027 udelay(1);
4028 tw32_f(MAC_MODE, tp->mac_mode);
4029 }
4030 }
4031
4032 if (current_link_up == 1) {
4033 tp->link_config.active_speed = SPEED_1000;
4034 tp->link_config.active_duplex = DUPLEX_FULL;
4035 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4036 LED_CTRL_LNKLED_OVERRIDE |
4037 LED_CTRL_1000MBPS_ON));
4038 } else {
4039 tp->link_config.active_speed = SPEED_INVALID;
4040 tp->link_config.active_duplex = DUPLEX_INVALID;
4041 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4042 LED_CTRL_LNKLED_OVERRIDE |
4043 LED_CTRL_TRAFFIC_OVERRIDE));
4044 }
4045
4046 if (current_link_up != netif_carrier_ok(tp->dev)) {
4047 if (current_link_up)
4048 netif_carrier_on(tp->dev);
4049 else
4050 netif_carrier_off(tp->dev);
4051 tg3_link_report(tp);
4052 } else {
Matt Carlson8d018622007-12-20 20:05:44 -08004053 u32 now_pause_cfg = tp->link_config.active_flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004054 if (orig_pause_cfg != now_pause_cfg ||
4055 orig_active_speed != tp->link_config.active_speed ||
4056 orig_active_duplex != tp->link_config.active_duplex)
4057 tg3_link_report(tp);
4058 }
4059
4060 return 0;
4061}
4062
Michael Chan747e8f82005-07-25 12:33:22 -07004063static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4064{
4065 int current_link_up, err = 0;
4066 u32 bmsr, bmcr;
4067 u16 current_speed;
4068 u8 current_duplex;
Matt Carlsonef167e22007-12-20 20:10:01 -08004069 u32 local_adv, remote_adv;
Michael Chan747e8f82005-07-25 12:33:22 -07004070
4071 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4072 tw32_f(MAC_MODE, tp->mac_mode);
4073 udelay(40);
4074
4075 tw32(MAC_EVENT, 0);
4076
4077 tw32_f(MAC_STATUS,
4078 (MAC_STATUS_SYNC_CHANGED |
4079 MAC_STATUS_CFG_CHANGED |
4080 MAC_STATUS_MI_COMPLETION |
4081 MAC_STATUS_LNKSTATE_CHANGED));
4082 udelay(40);
4083
4084 if (force_reset)
4085 tg3_phy_reset(tp);
4086
4087 current_link_up = 0;
4088 current_speed = SPEED_INVALID;
4089 current_duplex = DUPLEX_INVALID;
4090
4091 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4092 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
Michael Chand4d2c552006-03-20 17:47:20 -08004093 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4094 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4095 bmsr |= BMSR_LSTATUS;
4096 else
4097 bmsr &= ~BMSR_LSTATUS;
4098 }
Michael Chan747e8f82005-07-25 12:33:22 -07004099
4100 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4101
4102 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004103 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
Michael Chan747e8f82005-07-25 12:33:22 -07004104 /* do nothing, just check for link up at the end */
4105 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4106 u32 adv, new_adv;
4107
4108 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4109 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4110 ADVERTISE_1000XPAUSE |
4111 ADVERTISE_1000XPSE_ASYM |
4112 ADVERTISE_SLCT);
4113
Matt Carlsonba4d07a2007-12-20 20:08:00 -08004114 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
Michael Chan747e8f82005-07-25 12:33:22 -07004115
4116 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4117 new_adv |= ADVERTISE_1000XHALF;
4118 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4119 new_adv |= ADVERTISE_1000XFULL;
4120
4121 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4122 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4123 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4124 tg3_writephy(tp, MII_BMCR, bmcr);
4125
4126 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
Michael Chan3d3ebe72006-09-27 15:59:15 -07004127 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004128 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07004129
4130 return err;
4131 }
4132 } else {
4133 u32 new_bmcr;
4134
4135 bmcr &= ~BMCR_SPEED1000;
4136 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4137
4138 if (tp->link_config.duplex == DUPLEX_FULL)
4139 new_bmcr |= BMCR_FULLDPLX;
4140
4141 if (new_bmcr != bmcr) {
4142 /* BMCR_SPEED1000 is a reserved bit that needs
4143 * to be set on write.
4144 */
4145 new_bmcr |= BMCR_SPEED1000;
4146
4147 /* Force a linkdown */
4148 if (netif_carrier_ok(tp->dev)) {
4149 u32 adv;
4150
4151 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4152 adv &= ~(ADVERTISE_1000XFULL |
4153 ADVERTISE_1000XHALF |
4154 ADVERTISE_SLCT);
4155 tg3_writephy(tp, MII_ADVERTISE, adv);
4156 tg3_writephy(tp, MII_BMCR, bmcr |
4157 BMCR_ANRESTART |
4158 BMCR_ANENABLE);
4159 udelay(10);
4160 netif_carrier_off(tp->dev);
4161 }
4162 tg3_writephy(tp, MII_BMCR, new_bmcr);
4163 bmcr = new_bmcr;
4164 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4165 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
Michael Chand4d2c552006-03-20 17:47:20 -08004166 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4167 ASIC_REV_5714) {
4168 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4169 bmsr |= BMSR_LSTATUS;
4170 else
4171 bmsr &= ~BMSR_LSTATUS;
4172 }
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004173 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07004174 }
4175 }
4176
4177 if (bmsr & BMSR_LSTATUS) {
4178 current_speed = SPEED_1000;
4179 current_link_up = 1;
4180 if (bmcr & BMCR_FULLDPLX)
4181 current_duplex = DUPLEX_FULL;
4182 else
4183 current_duplex = DUPLEX_HALF;
4184
Matt Carlsonef167e22007-12-20 20:10:01 -08004185 local_adv = 0;
4186 remote_adv = 0;
4187
Michael Chan747e8f82005-07-25 12:33:22 -07004188 if (bmcr & BMCR_ANENABLE) {
Matt Carlsonef167e22007-12-20 20:10:01 -08004189 u32 common;
Michael Chan747e8f82005-07-25 12:33:22 -07004190
4191 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4192 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4193 common = local_adv & remote_adv;
4194 if (common & (ADVERTISE_1000XHALF |
4195 ADVERTISE_1000XFULL)) {
4196 if (common & ADVERTISE_1000XFULL)
4197 current_duplex = DUPLEX_FULL;
4198 else
4199 current_duplex = DUPLEX_HALF;
Matt Carlson57d8b882010-06-05 17:24:35 +00004200 } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4201 /* Link is up via parallel detect */
Matt Carlson859a588792010-04-05 10:19:28 +00004202 } else {
Michael Chan747e8f82005-07-25 12:33:22 -07004203 current_link_up = 0;
Matt Carlson859a588792010-04-05 10:19:28 +00004204 }
Michael Chan747e8f82005-07-25 12:33:22 -07004205 }
4206 }
4207
Matt Carlsonef167e22007-12-20 20:10:01 -08004208 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4209 tg3_setup_flow_control(tp, local_adv, remote_adv);
4210
Michael Chan747e8f82005-07-25 12:33:22 -07004211 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4212 if (tp->link_config.active_duplex == DUPLEX_HALF)
4213 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4214
4215 tw32_f(MAC_MODE, tp->mac_mode);
4216 udelay(40);
4217
4218 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4219
4220 tp->link_config.active_speed = current_speed;
4221 tp->link_config.active_duplex = current_duplex;
4222
4223 if (current_link_up != netif_carrier_ok(tp->dev)) {
4224 if (current_link_up)
4225 netif_carrier_on(tp->dev);
4226 else {
4227 netif_carrier_off(tp->dev);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004228 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07004229 }
4230 tg3_link_report(tp);
4231 }
4232 return err;
4233}
4234
4235static void tg3_serdes_parallel_detect(struct tg3 *tp)
4236{
Michael Chan3d3ebe72006-09-27 15:59:15 -07004237 if (tp->serdes_counter) {
Michael Chan747e8f82005-07-25 12:33:22 -07004238 /* Give autoneg time to complete. */
Michael Chan3d3ebe72006-09-27 15:59:15 -07004239 tp->serdes_counter--;
Michael Chan747e8f82005-07-25 12:33:22 -07004240 return;
4241 }
Matt Carlsonc6cdf432010-04-05 10:19:26 +00004242
Michael Chan747e8f82005-07-25 12:33:22 -07004243 if (!netif_carrier_ok(tp->dev) &&
4244 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4245 u32 bmcr;
4246
4247 tg3_readphy(tp, MII_BMCR, &bmcr);
4248 if (bmcr & BMCR_ANENABLE) {
4249 u32 phy1, phy2;
4250
4251 /* Select shadow register 0x1f */
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00004252 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4253 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
Michael Chan747e8f82005-07-25 12:33:22 -07004254
4255 /* Select expansion interrupt status register */
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00004256 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4257 MII_TG3_DSP_EXP1_INT_STAT);
4258 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4259 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
Michael Chan747e8f82005-07-25 12:33:22 -07004260
4261 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4262 /* We have signal detect and not receiving
4263 * config code words, link is up by parallel
4264 * detection.
4265 */
4266
4267 bmcr &= ~BMCR_ANENABLE;
4268 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4269 tg3_writephy(tp, MII_BMCR, bmcr);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004270 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07004271 }
4272 }
Matt Carlson859a588792010-04-05 10:19:28 +00004273 } else if (netif_carrier_ok(tp->dev) &&
4274 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004275 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
Michael Chan747e8f82005-07-25 12:33:22 -07004276 u32 phy2;
4277
4278 /* Select expansion interrupt status register */
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00004279 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4280 MII_TG3_DSP_EXP1_INT_STAT);
4281 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
Michael Chan747e8f82005-07-25 12:33:22 -07004282 if (phy2 & 0x20) {
4283 u32 bmcr;
4284
4285 /* Config code words received, turn on autoneg. */
4286 tg3_readphy(tp, MII_BMCR, &bmcr);
4287 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4288
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004289 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07004290
4291 }
4292 }
4293}
4294
Linus Torvalds1da177e2005-04-16 15:20:36 -07004295static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4296{
4297 int err;
4298
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004299 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004300 err = tg3_setup_fiber_phy(tp, force_reset);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004301 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
Michael Chan747e8f82005-07-25 12:33:22 -07004302 err = tg3_setup_fiber_mii_phy(tp, force_reset);
Matt Carlson859a588792010-04-05 10:19:28 +00004303 else
Linus Torvalds1da177e2005-04-16 15:20:36 -07004304 err = tg3_setup_copper_phy(tp, force_reset);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004305
Matt Carlsonbcb37f62008-11-03 16:52:09 -08004306 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
Matt Carlsonaa6c91f2007-11-12 21:18:04 -08004307 u32 val, scale;
4308
4309 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4310 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4311 scale = 65;
4312 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4313 scale = 6;
4314 else
4315 scale = 12;
4316
4317 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4318 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4319 tw32(GRC_MISC_CFG, val);
4320 }
4321
Linus Torvalds1da177e2005-04-16 15:20:36 -07004322 if (tp->link_config.active_speed == SPEED_1000 &&
4323 tp->link_config.active_duplex == DUPLEX_HALF)
4324 tw32(MAC_TX_LENGTHS,
4325 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4326 (6 << TX_LENGTHS_IPG_SHIFT) |
4327 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4328 else
4329 tw32(MAC_TX_LENGTHS,
4330 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4331 (6 << TX_LENGTHS_IPG_SHIFT) |
4332 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4333
4334 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4335 if (netif_carrier_ok(tp->dev)) {
4336 tw32(HOSTCC_STAT_COAL_TICKS,
David S. Miller15f98502005-05-18 22:49:26 -07004337 tp->coal.stats_block_coalesce_usecs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004338 } else {
4339 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4340 }
4341 }
4342
Matt Carlson8ed5d972007-05-07 00:25:49 -07004343 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4344 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4345 if (!netif_carrier_ok(tp->dev))
4346 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4347 tp->pwrmgmt_thresh;
4348 else
4349 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4350 tw32(PCIE_PWR_MGMT_THRESH, val);
4351 }
4352
Linus Torvalds1da177e2005-04-16 15:20:36 -07004353 return err;
4354}
4355
Michael Chandf3e6542006-05-26 17:48:07 -07004356/* This is called whenever we suspect that the system chipset is re-
4357 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4358 * is bogus tx completions. We try to recover by setting the
4359 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4360 * in the workqueue.
4361 */
4362static void tg3_tx_recover(struct tg3 *tp)
4363{
4364 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4365 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4366
Matt Carlson5129c3a2010-04-05 10:19:23 +00004367 netdev_warn(tp->dev,
4368 "The system may be re-ordering memory-mapped I/O "
4369 "cycles to the network device, attempting to recover. "
4370 "Please report the problem to the driver maintainer "
4371 "and include system chipset information.\n");
Michael Chandf3e6542006-05-26 17:48:07 -07004372
4373 spin_lock(&tp->lock);
Michael Chandf3e6542006-05-26 17:48:07 -07004374 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
Michael Chandf3e6542006-05-26 17:48:07 -07004375 spin_unlock(&tp->lock);
4376}
4377
Matt Carlsonf3f3f272009-08-28 14:03:21 +00004378static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
Michael Chan1b2a7202006-08-07 21:46:02 -07004379{
Matt Carlsonf65aac12010-08-02 11:26:03 +00004380 /* Tell compiler to fetch tx indices from memory. */
4381 barrier();
Matt Carlsonf3f3f272009-08-28 14:03:21 +00004382 return tnapi->tx_pending -
4383 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
Michael Chan1b2a7202006-08-07 21:46:02 -07004384}
4385
Linus Torvalds1da177e2005-04-16 15:20:36 -07004386/* Tigon3 never reports partial packet sends. So we do not
4387 * need special logic to handle SKBs that have not had all
4388 * of their frags sent yet, like SunGEM does.
4389 */
Matt Carlson17375d22009-08-28 14:02:18 +00004390static void tg3_tx(struct tg3_napi *tnapi)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004391{
Matt Carlson17375d22009-08-28 14:02:18 +00004392 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +00004393 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
Matt Carlsonf3f3f272009-08-28 14:03:21 +00004394 u32 sw_idx = tnapi->tx_cons;
Matt Carlsonfe5f5782009-09-01 13:09:39 +00004395 struct netdev_queue *txq;
4396 int index = tnapi - tp->napi;
4397
Matt Carlson19cfaec2009-12-03 08:36:20 +00004398 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
Matt Carlsonfe5f5782009-09-01 13:09:39 +00004399 index--;
4400
4401 txq = netdev_get_tx_queue(tp->dev, index);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004402
4403 while (sw_idx != hw_idx) {
Alexander Duyckf4188d82009-12-02 16:48:38 +00004404 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07004405 struct sk_buff *skb = ri->skb;
Michael Chandf3e6542006-05-26 17:48:07 -07004406 int i, tx_bug = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004407
Michael Chandf3e6542006-05-26 17:48:07 -07004408 if (unlikely(skb == NULL)) {
4409 tg3_tx_recover(tp);
4410 return;
4411 }
4412
Alexander Duyckf4188d82009-12-02 16:48:38 +00004413 pci_unmap_single(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00004414 dma_unmap_addr(ri, mapping),
Alexander Duyckf4188d82009-12-02 16:48:38 +00004415 skb_headlen(skb),
4416 PCI_DMA_TODEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004417
4418 ri->skb = NULL;
4419
4420 sw_idx = NEXT_TX(sw_idx);
4421
4422 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
Matt Carlsonf3f3f272009-08-28 14:03:21 +00004423 ri = &tnapi->tx_buffers[sw_idx];
Michael Chandf3e6542006-05-26 17:48:07 -07004424 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4425 tx_bug = 1;
Alexander Duyckf4188d82009-12-02 16:48:38 +00004426
4427 pci_unmap_page(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00004428 dma_unmap_addr(ri, mapping),
Alexander Duyckf4188d82009-12-02 16:48:38 +00004429 skb_shinfo(skb)->frags[i].size,
4430 PCI_DMA_TODEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004431 sw_idx = NEXT_TX(sw_idx);
4432 }
4433
David S. Millerf47c11e2005-06-24 20:18:35 -07004434 dev_kfree_skb(skb);
Michael Chandf3e6542006-05-26 17:48:07 -07004435
4436 if (unlikely(tx_bug)) {
4437 tg3_tx_recover(tp);
4438 return;
4439 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004440 }
4441
Matt Carlsonf3f3f272009-08-28 14:03:21 +00004442 tnapi->tx_cons = sw_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004443
Michael Chan1b2a7202006-08-07 21:46:02 -07004444 /* Need to make the tx_cons update visible to tg3_start_xmit()
4445 * before checking for netif_queue_stopped(). Without the
4446 * memory barrier, there is a small possibility that tg3_start_xmit()
4447 * will miss it and cause the queue to be stopped forever.
4448 */
4449 smp_mb();
4450
Matt Carlsonfe5f5782009-09-01 13:09:39 +00004451 if (unlikely(netif_tx_queue_stopped(txq) &&
Matt Carlsonf3f3f272009-08-28 14:03:21 +00004452 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
Matt Carlsonfe5f5782009-09-01 13:09:39 +00004453 __netif_tx_lock(txq, smp_processor_id());
4454 if (netif_tx_queue_stopped(txq) &&
Matt Carlsonf3f3f272009-08-28 14:03:21 +00004455 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
Matt Carlsonfe5f5782009-09-01 13:09:39 +00004456 netif_tx_wake_queue(txq);
4457 __netif_tx_unlock(txq);
Michael Chan51b91462005-09-01 17:41:28 -07004458 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004459}
4460
Matt Carlson2b2cdb62009-11-13 13:03:48 +00004461static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4462{
4463 if (!ri->skb)
4464 return;
4465
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00004466 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
Matt Carlson2b2cdb62009-11-13 13:03:48 +00004467 map_sz, PCI_DMA_FROMDEVICE);
4468 dev_kfree_skb_any(ri->skb);
4469 ri->skb = NULL;
4470}
4471
Linus Torvalds1da177e2005-04-16 15:20:36 -07004472/* Returns size of skb allocated or < 0 on error.
4473 *
4474 * We only need to fill in the address because the other members
4475 * of the RX descriptor are invariant, see tg3_init_rings.
4476 *
4477 * Note the purposeful assymetry of cpu vs. chip accesses. For
4478 * posting buffers we only dirty the first cache line of the RX
4479 * descriptor (containing the address). Whereas for the RX status
4480 * buffers the cpu only reads the last cacheline of the RX descriptor
4481 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4482 */
Matt Carlson86b21e52009-11-13 13:03:45 +00004483static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
Matt Carlsona3896162009-11-13 13:03:44 +00004484 u32 opaque_key, u32 dest_idx_unmasked)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004485{
4486 struct tg3_rx_buffer_desc *desc;
4487 struct ring_info *map, *src_map;
4488 struct sk_buff *skb;
4489 dma_addr_t mapping;
4490 int skb_size, dest_idx;
4491
4492 src_map = NULL;
4493 switch (opaque_key) {
4494 case RXD_OPAQUE_RING_STD:
4495 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
Matt Carlson21f581a2009-08-28 14:00:25 +00004496 desc = &tpr->rx_std[dest_idx];
4497 map = &tpr->rx_std_buffers[dest_idx];
Matt Carlson287be122009-08-28 13:58:46 +00004498 skb_size = tp->rx_pkt_map_sz;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004499 break;
4500
4501 case RXD_OPAQUE_RING_JUMBO:
4502 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
Matt Carlson79ed5ac2009-08-28 14:00:55 +00004503 desc = &tpr->rx_jmb[dest_idx].std;
Matt Carlson21f581a2009-08-28 14:00:25 +00004504 map = &tpr->rx_jmb_buffers[dest_idx];
Matt Carlson287be122009-08-28 13:58:46 +00004505 skb_size = TG3_RX_JMB_MAP_SZ;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004506 break;
4507
4508 default:
4509 return -EINVAL;
Stephen Hemminger855e1112008-04-16 16:37:28 -07004510 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004511
4512 /* Do not overwrite any of the map or rp information
4513 * until we are sure we can commit to a new buffer.
4514 *
4515 * Callers depend upon this behavior and assume that
4516 * we leave everything unchanged if we fail.
4517 */
Matt Carlson287be122009-08-28 13:58:46 +00004518 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004519 if (skb == NULL)
4520 return -ENOMEM;
4521
Linus Torvalds1da177e2005-04-16 15:20:36 -07004522 skb_reserve(skb, tp->rx_offset);
4523
Matt Carlson287be122009-08-28 13:58:46 +00004524 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004525 PCI_DMA_FROMDEVICE);
Matt Carlsona21771d2009-11-02 14:25:31 +00004526 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4527 dev_kfree_skb(skb);
4528 return -EIO;
4529 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004530
4531 map->skb = skb;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00004532 dma_unmap_addr_set(map, mapping, mapping);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004533
Linus Torvalds1da177e2005-04-16 15:20:36 -07004534 desc->addr_hi = ((u64)mapping >> 32);
4535 desc->addr_lo = ((u64)mapping & 0xffffffff);
4536
4537 return skb_size;
4538}
4539
4540/* We only need to move over in the address because the other
4541 * members of the RX descriptor are invariant. See notes above
4542 * tg3_alloc_rx_skb for full details.
4543 */
Matt Carlsona3896162009-11-13 13:03:44 +00004544static void tg3_recycle_rx(struct tg3_napi *tnapi,
4545 struct tg3_rx_prodring_set *dpr,
4546 u32 opaque_key, int src_idx,
4547 u32 dest_idx_unmasked)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004548{
Matt Carlson17375d22009-08-28 14:02:18 +00004549 struct tg3 *tp = tnapi->tp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004550 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4551 struct ring_info *src_map, *dest_map;
Matt Carlsona3896162009-11-13 13:03:44 +00004552 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
Matt Carlsonc6cdf432010-04-05 10:19:26 +00004553 int dest_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004554
4555 switch (opaque_key) {
4556 case RXD_OPAQUE_RING_STD:
4557 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
Matt Carlsona3896162009-11-13 13:03:44 +00004558 dest_desc = &dpr->rx_std[dest_idx];
4559 dest_map = &dpr->rx_std_buffers[dest_idx];
4560 src_desc = &spr->rx_std[src_idx];
4561 src_map = &spr->rx_std_buffers[src_idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07004562 break;
4563
4564 case RXD_OPAQUE_RING_JUMBO:
4565 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
Matt Carlsona3896162009-11-13 13:03:44 +00004566 dest_desc = &dpr->rx_jmb[dest_idx].std;
4567 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4568 src_desc = &spr->rx_jmb[src_idx].std;
4569 src_map = &spr->rx_jmb_buffers[src_idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07004570 break;
4571
4572 default:
4573 return;
Stephen Hemminger855e1112008-04-16 16:37:28 -07004574 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004575
4576 dest_map->skb = src_map->skb;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00004577 dma_unmap_addr_set(dest_map, mapping,
4578 dma_unmap_addr(src_map, mapping));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004579 dest_desc->addr_hi = src_desc->addr_hi;
4580 dest_desc->addr_lo = src_desc->addr_lo;
Matt Carlsone92967b2010-02-12 14:47:06 +00004581
4582 /* Ensure that the update to the skb happens after the physical
4583 * addresses have been transferred to the new BD location.
4584 */
4585 smp_wmb();
4586
Linus Torvalds1da177e2005-04-16 15:20:36 -07004587 src_map->skb = NULL;
4588}
4589
Linus Torvalds1da177e2005-04-16 15:20:36 -07004590/* The RX ring scheme is composed of multiple rings which post fresh
4591 * buffers to the chip, and one special ring the chip uses to report
4592 * status back to the host.
4593 *
4594 * The special ring reports the status of received packets to the
4595 * host. The chip does not write into the original descriptor the
4596 * RX buffer was obtained from. The chip simply takes the original
4597 * descriptor as provided by the host, updates the status and length
4598 * field, then writes this into the next status ring entry.
4599 *
4600 * Each ring the host uses to post buffers to the chip is described
4601 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4602 * it is first placed into the on-chip ram. When the packet's length
4603 * is known, it walks down the TG3_BDINFO entries to select the ring.
4604 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4605 * which is within the range of the new packet's length is chosen.
4606 *
4607 * The "separate ring for rx status" scheme may sound queer, but it makes
4608 * sense from a cache coherency perspective. If only the host writes
4609 * to the buffer post rings, and only the chip writes to the rx status
4610 * rings, then cache lines never move beyond shared-modified state.
4611 * If both the host and chip were to write into the same ring, cache line
4612 * eviction could occur since both entities want it in an exclusive state.
4613 */
Matt Carlson17375d22009-08-28 14:02:18 +00004614static int tg3_rx(struct tg3_napi *tnapi, int budget)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004615{
Matt Carlson17375d22009-08-28 14:02:18 +00004616 struct tg3 *tp = tnapi->tp;
Michael Chanf92905d2006-06-29 20:14:29 -07004617 u32 work_mask, rx_std_posted = 0;
Matt Carlson43619352009-11-13 13:03:47 +00004618 u32 std_prod_idx, jmb_prod_idx;
Matt Carlson72334482009-08-28 14:03:01 +00004619 u32 sw_idx = tnapi->rx_rcb_ptr;
Michael Chan483ba502005-04-25 15:14:03 -07004620 u16 hw_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004621 int received;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00004622 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004623
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00004624 hw_idx = *(tnapi->rx_rcb_prod_idx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004625 /*
4626 * We need to order the read of hw_idx and the read of
4627 * the opaque cookie.
4628 */
4629 rmb();
Linus Torvalds1da177e2005-04-16 15:20:36 -07004630 work_mask = 0;
4631 received = 0;
Matt Carlson43619352009-11-13 13:03:47 +00004632 std_prod_idx = tpr->rx_std_prod_idx;
4633 jmb_prod_idx = tpr->rx_jmb_prod_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004634 while (sw_idx != hw_idx && budget > 0) {
Matt Carlsonafc081f2009-11-13 13:03:43 +00004635 struct ring_info *ri;
Matt Carlson72334482009-08-28 14:03:01 +00004636 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07004637 unsigned int len;
4638 struct sk_buff *skb;
4639 dma_addr_t dma_addr;
4640 u32 opaque_key, desc_idx, *post_ptr;
Matt Carlson9dc7a112010-04-12 06:58:28 +00004641 bool hw_vlan __maybe_unused = false;
4642 u16 vtag __maybe_unused = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004643
4644 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4645 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4646 if (opaque_key == RXD_OPAQUE_RING_STD) {
Matt Carlsonb196c7e2009-11-13 13:03:50 +00004647 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00004648 dma_addr = dma_unmap_addr(ri, mapping);
Matt Carlson21f581a2009-08-28 14:00:25 +00004649 skb = ri->skb;
Matt Carlson43619352009-11-13 13:03:47 +00004650 post_ptr = &std_prod_idx;
Michael Chanf92905d2006-06-29 20:14:29 -07004651 rx_std_posted++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004652 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
Matt Carlsonb196c7e2009-11-13 13:03:50 +00004653 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00004654 dma_addr = dma_unmap_addr(ri, mapping);
Matt Carlson21f581a2009-08-28 14:00:25 +00004655 skb = ri->skb;
Matt Carlson43619352009-11-13 13:03:47 +00004656 post_ptr = &jmb_prod_idx;
Matt Carlson21f581a2009-08-28 14:00:25 +00004657 } else
Linus Torvalds1da177e2005-04-16 15:20:36 -07004658 goto next_pkt_nopost;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004659
4660 work_mask |= opaque_key;
4661
4662 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4663 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4664 drop_it:
Matt Carlsona3896162009-11-13 13:03:44 +00004665 tg3_recycle_rx(tnapi, tpr, opaque_key,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004666 desc_idx, *post_ptr);
4667 drop_it_no_recycle:
4668 /* Other statistics kept track of by card. */
4669 tp->net_stats.rx_dropped++;
4670 goto next_pkt;
4671 }
4672
Matt Carlsonad829262008-11-21 17:16:16 -08004673 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4674 ETH_FCS_LEN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004675
Matt Carlsond2757fc2010-04-12 06:58:27 +00004676 if (len > TG3_RX_COPY_THRESH(tp)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004677 int skb_size;
4678
Matt Carlson86b21e52009-11-13 13:03:45 +00004679 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
Matt Carlsonafc081f2009-11-13 13:03:43 +00004680 *post_ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004681 if (skb_size < 0)
4682 goto drop_it;
4683
Matt Carlson287be122009-08-28 13:58:46 +00004684 pci_unmap_single(tp->pdev, dma_addr, skb_size,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004685 PCI_DMA_FROMDEVICE);
4686
Matt Carlson61e800c2010-02-17 15:16:54 +00004687 /* Ensure that the update to the skb happens
4688 * after the usage of the old DMA mapping.
4689 */
4690 smp_wmb();
4691
4692 ri->skb = NULL;
4693
Linus Torvalds1da177e2005-04-16 15:20:36 -07004694 skb_put(skb, len);
4695 } else {
4696 struct sk_buff *copy_skb;
4697
Matt Carlsona3896162009-11-13 13:03:44 +00004698 tg3_recycle_rx(tnapi, tpr, opaque_key,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004699 desc_idx, *post_ptr);
4700
Matt Carlson9dc7a112010-04-12 06:58:28 +00004701 copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4702 TG3_RAW_IP_ALIGN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004703 if (copy_skb == NULL)
4704 goto drop_it_no_recycle;
4705
Matt Carlson9dc7a112010-04-12 06:58:28 +00004706 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004707 skb_put(copy_skb, len);
4708 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melod626f622007-03-27 18:55:52 -03004709 skb_copy_from_linear_data(skb, copy_skb->data, len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004710 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4711
4712 /* We'll reuse the original ring buffer. */
4713 skb = copy_skb;
4714 }
4715
4716 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4717 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4718 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4719 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4720 skb->ip_summed = CHECKSUM_UNNECESSARY;
4721 else
4722 skb->ip_summed = CHECKSUM_NONE;
4723
4724 skb->protocol = eth_type_trans(skb, tp->dev);
Matt Carlsonf7b493e2009-02-25 14:21:52 +00004725
4726 if (len > (tp->dev->mtu + ETH_HLEN) &&
4727 skb->protocol != htons(ETH_P_8021Q)) {
4728 dev_kfree_skb(skb);
4729 goto next_pkt;
4730 }
4731
Matt Carlson9dc7a112010-04-12 06:58:28 +00004732 if (desc->type_flags & RXD_FLAG_VLAN &&
4733 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4734 vtag = desc->err_vlan & RXD_VLAN_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004735#if TG3_VLAN_TAG_USED
Matt Carlson9dc7a112010-04-12 06:58:28 +00004736 if (tp->vlgrp)
4737 hw_vlan = true;
4738 else
4739#endif
4740 {
4741 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4742 __skb_push(skb, VLAN_HLEN);
4743
4744 memmove(ve, skb->data + VLAN_HLEN,
4745 ETH_ALEN * 2);
4746 ve->h_vlan_proto = htons(ETH_P_8021Q);
4747 ve->h_vlan_TCI = htons(vtag);
4748 }
4749 }
4750
4751#if TG3_VLAN_TAG_USED
4752 if (hw_vlan)
4753 vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4754 else
Linus Torvalds1da177e2005-04-16 15:20:36 -07004755#endif
Matt Carlson17375d22009-08-28 14:02:18 +00004756 napi_gro_receive(&tnapi->napi, skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004757
Linus Torvalds1da177e2005-04-16 15:20:36 -07004758 received++;
4759 budget--;
4760
4761next_pkt:
4762 (*post_ptr)++;
Michael Chanf92905d2006-06-29 20:14:29 -07004763
4764 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
Matt Carlson86cfe4f2010-01-12 10:11:37 +00004765 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4766 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4767 tpr->rx_std_prod_idx);
Michael Chanf92905d2006-06-29 20:14:29 -07004768 work_mask &= ~RXD_OPAQUE_RING_STD;
4769 rx_std_posted = 0;
4770 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004771next_pkt_nopost:
Michael Chan483ba502005-04-25 15:14:03 -07004772 sw_idx++;
Eric Dumazet6b31a512007-02-06 13:29:21 -08004773 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
Michael Chan52f6d692005-04-25 15:14:32 -07004774
4775 /* Refresh hw_idx to see if there is new work */
4776 if (sw_idx == hw_idx) {
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00004777 hw_idx = *(tnapi->rx_rcb_prod_idx);
Michael Chan52f6d692005-04-25 15:14:32 -07004778 rmb();
4779 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004780 }
4781
4782 /* ACK the status ring. */
Matt Carlson72334482009-08-28 14:03:01 +00004783 tnapi->rx_rcb_ptr = sw_idx;
4784 tw32_rx_mbox(tnapi->consmbox, sw_idx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004785
4786 /* Refill RX ring(s). */
Matt Carlsone4af1af2010-02-12 14:47:05 +00004787 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
Matt Carlsonb196c7e2009-11-13 13:03:50 +00004788 if (work_mask & RXD_OPAQUE_RING_STD) {
4789 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4790 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4791 tpr->rx_std_prod_idx);
4792 }
4793 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4794 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4795 TG3_RX_JUMBO_RING_SIZE;
4796 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4797 tpr->rx_jmb_prod_idx);
4798 }
4799 mmiowb();
4800 } else if (work_mask) {
4801 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4802 * updated before the producer indices can be updated.
4803 */
4804 smp_wmb();
4805
Matt Carlson43619352009-11-13 13:03:47 +00004806 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
Matt Carlson43619352009-11-13 13:03:47 +00004807 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00004808
Matt Carlsone4af1af2010-02-12 14:47:05 +00004809 if (tnapi != &tp->napi[1])
4810 napi_schedule(&tp->napi[1].napi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004811 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004812
4813 return received;
4814}
4815
Matt Carlson35f2d7d2009-11-13 13:03:41 +00004816static void tg3_poll_link(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004817{
Linus Torvalds1da177e2005-04-16 15:20:36 -07004818 /* handle link change and other phy events */
4819 if (!(tp->tg3_flags &
4820 (TG3_FLAG_USE_LINKCHG_REG |
4821 TG3_FLAG_POLL_SERDES))) {
Matt Carlson35f2d7d2009-11-13 13:03:41 +00004822 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4823
Linus Torvalds1da177e2005-04-16 15:20:36 -07004824 if (sblk->status & SD_STATUS_LINK_CHG) {
4825 sblk->status = SD_STATUS_UPDATED |
Matt Carlson35f2d7d2009-11-13 13:03:41 +00004826 (sblk->status & ~SD_STATUS_LINK_CHG);
David S. Millerf47c11e2005-06-24 20:18:35 -07004827 spin_lock(&tp->lock);
Matt Carlsondd477002008-05-25 23:45:58 -07004828 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4829 tw32_f(MAC_STATUS,
4830 (MAC_STATUS_SYNC_CHANGED |
4831 MAC_STATUS_CFG_CHANGED |
4832 MAC_STATUS_MI_COMPLETION |
4833 MAC_STATUS_LNKSTATE_CHANGED));
4834 udelay(40);
4835 } else
4836 tg3_setup_phy(tp, 0);
David S. Millerf47c11e2005-06-24 20:18:35 -07004837 spin_unlock(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004838 }
4839 }
Matt Carlson35f2d7d2009-11-13 13:03:41 +00004840}
4841
Matt Carlsonf89f38b2010-02-12 14:47:07 +00004842static int tg3_rx_prodring_xfer(struct tg3 *tp,
4843 struct tg3_rx_prodring_set *dpr,
4844 struct tg3_rx_prodring_set *spr)
Matt Carlsonb196c7e2009-11-13 13:03:50 +00004845{
4846 u32 si, di, cpycnt, src_prod_idx;
Matt Carlsonf89f38b2010-02-12 14:47:07 +00004847 int i, err = 0;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00004848
4849 while (1) {
4850 src_prod_idx = spr->rx_std_prod_idx;
4851
4852 /* Make sure updates to the rx_std_buffers[] entries and the
4853 * standard producer index are seen in the correct order.
4854 */
4855 smp_rmb();
4856
4857 if (spr->rx_std_cons_idx == src_prod_idx)
4858 break;
4859
4860 if (spr->rx_std_cons_idx < src_prod_idx)
4861 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4862 else
4863 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4864
4865 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4866
4867 si = spr->rx_std_cons_idx;
4868 di = dpr->rx_std_prod_idx;
4869
Matt Carlsone92967b2010-02-12 14:47:06 +00004870 for (i = di; i < di + cpycnt; i++) {
4871 if (dpr->rx_std_buffers[i].skb) {
4872 cpycnt = i - di;
Matt Carlsonf89f38b2010-02-12 14:47:07 +00004873 err = -ENOSPC;
Matt Carlsone92967b2010-02-12 14:47:06 +00004874 break;
4875 }
4876 }
4877
4878 if (!cpycnt)
4879 break;
4880
4881 /* Ensure that updates to the rx_std_buffers ring and the
4882 * shadowed hardware producer ring from tg3_recycle_skb() are
4883 * ordered correctly WRT the skb check above.
4884 */
4885 smp_rmb();
4886
Matt Carlsonb196c7e2009-11-13 13:03:50 +00004887 memcpy(&dpr->rx_std_buffers[di],
4888 &spr->rx_std_buffers[si],
4889 cpycnt * sizeof(struct ring_info));
4890
4891 for (i = 0; i < cpycnt; i++, di++, si++) {
4892 struct tg3_rx_buffer_desc *sbd, *dbd;
4893 sbd = &spr->rx_std[si];
4894 dbd = &dpr->rx_std[di];
4895 dbd->addr_hi = sbd->addr_hi;
4896 dbd->addr_lo = sbd->addr_lo;
4897 }
4898
4899 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4900 TG3_RX_RING_SIZE;
4901 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4902 TG3_RX_RING_SIZE;
4903 }
4904
4905 while (1) {
4906 src_prod_idx = spr->rx_jmb_prod_idx;
4907
4908 /* Make sure updates to the rx_jmb_buffers[] entries and
4909 * the jumbo producer index are seen in the correct order.
4910 */
4911 smp_rmb();
4912
4913 if (spr->rx_jmb_cons_idx == src_prod_idx)
4914 break;
4915
4916 if (spr->rx_jmb_cons_idx < src_prod_idx)
4917 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4918 else
4919 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4920
4921 cpycnt = min(cpycnt,
4922 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4923
4924 si = spr->rx_jmb_cons_idx;
4925 di = dpr->rx_jmb_prod_idx;
4926
Matt Carlsone92967b2010-02-12 14:47:06 +00004927 for (i = di; i < di + cpycnt; i++) {
4928 if (dpr->rx_jmb_buffers[i].skb) {
4929 cpycnt = i - di;
Matt Carlsonf89f38b2010-02-12 14:47:07 +00004930 err = -ENOSPC;
Matt Carlsone92967b2010-02-12 14:47:06 +00004931 break;
4932 }
4933 }
4934
4935 if (!cpycnt)
4936 break;
4937
4938 /* Ensure that updates to the rx_jmb_buffers ring and the
4939 * shadowed hardware producer ring from tg3_recycle_skb() are
4940 * ordered correctly WRT the skb check above.
4941 */
4942 smp_rmb();
4943
Matt Carlsonb196c7e2009-11-13 13:03:50 +00004944 memcpy(&dpr->rx_jmb_buffers[di],
4945 &spr->rx_jmb_buffers[si],
4946 cpycnt * sizeof(struct ring_info));
4947
4948 for (i = 0; i < cpycnt; i++, di++, si++) {
4949 struct tg3_rx_buffer_desc *sbd, *dbd;
4950 sbd = &spr->rx_jmb[si].std;
4951 dbd = &dpr->rx_jmb[di].std;
4952 dbd->addr_hi = sbd->addr_hi;
4953 dbd->addr_lo = sbd->addr_lo;
4954 }
4955
4956 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4957 TG3_RX_JUMBO_RING_SIZE;
4958 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4959 TG3_RX_JUMBO_RING_SIZE;
4960 }
Matt Carlsonf89f38b2010-02-12 14:47:07 +00004961
4962 return err;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00004963}
4964
Matt Carlson35f2d7d2009-11-13 13:03:41 +00004965static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4966{
4967 struct tg3 *tp = tnapi->tp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004968
4969 /* run TX completion thread */
Matt Carlsonf3f3f272009-08-28 14:03:21 +00004970 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
Matt Carlson17375d22009-08-28 14:02:18 +00004971 tg3_tx(tnapi);
David S. Miller6f535762007-10-11 18:08:29 -07004972 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
Michael Chan4fd7ab52007-10-12 01:39:50 -07004973 return work_done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004974 }
4975
Linus Torvalds1da177e2005-04-16 15:20:36 -07004976 /* run RX thread, within the bounds set by NAPI.
4977 * All RX "locking" is done by ensuring outside
Stephen Hemmingerbea33482007-10-03 16:41:36 -07004978 * code synchronizes with tg3->napi.poll()
Linus Torvalds1da177e2005-04-16 15:20:36 -07004979 */
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00004980 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
Matt Carlson17375d22009-08-28 14:02:18 +00004981 work_done += tg3_rx(tnapi, budget - work_done);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004982
Matt Carlsonb196c7e2009-11-13 13:03:50 +00004983 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
Matt Carlsone4af1af2010-02-12 14:47:05 +00004984 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
Matt Carlsonf89f38b2010-02-12 14:47:07 +00004985 int i, err = 0;
Matt Carlsone4af1af2010-02-12 14:47:05 +00004986 u32 std_prod_idx = dpr->rx_std_prod_idx;
4987 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00004988
Matt Carlsone4af1af2010-02-12 14:47:05 +00004989 for (i = 1; i < tp->irq_cnt; i++)
Matt Carlsonf89f38b2010-02-12 14:47:07 +00004990 err |= tg3_rx_prodring_xfer(tp, dpr,
4991 tp->napi[i].prodring);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00004992
4993 wmb();
4994
Matt Carlsone4af1af2010-02-12 14:47:05 +00004995 if (std_prod_idx != dpr->rx_std_prod_idx)
4996 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4997 dpr->rx_std_prod_idx);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00004998
Matt Carlsone4af1af2010-02-12 14:47:05 +00004999 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5000 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5001 dpr->rx_jmb_prod_idx);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005002
5003 mmiowb();
Matt Carlsonf89f38b2010-02-12 14:47:07 +00005004
5005 if (err)
5006 tw32_f(HOSTCC_MODE, tp->coal_now);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005007 }
5008
David S. Miller6f535762007-10-11 18:08:29 -07005009 return work_done;
5010}
David S. Millerf7383c22005-05-18 22:50:53 -07005011
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005012static int tg3_poll_msix(struct napi_struct *napi, int budget)
5013{
5014 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5015 struct tg3 *tp = tnapi->tp;
5016 int work_done = 0;
5017 struct tg3_hw_status *sblk = tnapi->hw_status;
5018
5019 while (1) {
5020 work_done = tg3_poll_work(tnapi, work_done, budget);
5021
5022 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5023 goto tx_recovery;
5024
5025 if (unlikely(work_done >= budget))
5026 break;
5027
Matt Carlsonc6cdf432010-04-05 10:19:26 +00005028 /* tp->last_tag is used in tg3_int_reenable() below
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005029 * to tell the hw how much work has been processed,
5030 * so we must read it before checking for more work.
5031 */
5032 tnapi->last_tag = sblk->status_tag;
5033 tnapi->last_irq_tag = tnapi->last_tag;
5034 rmb();
5035
5036 /* check for RX/TX work to do */
Matt Carlson6d40db72010-04-05 10:19:20 +00005037 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5038 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005039 napi_complete(napi);
5040 /* Reenable interrupts. */
5041 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5042 mmiowb();
5043 break;
5044 }
5045 }
5046
5047 return work_done;
5048
5049tx_recovery:
5050 /* work_done is guaranteed to be less than budget. */
5051 napi_complete(napi);
5052 schedule_work(&tp->reset_task);
5053 return work_done;
5054}
5055
David S. Miller6f535762007-10-11 18:08:29 -07005056static int tg3_poll(struct napi_struct *napi, int budget)
5057{
Matt Carlson8ef04422009-08-28 14:01:37 +00005058 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5059 struct tg3 *tp = tnapi->tp;
David S. Miller6f535762007-10-11 18:08:29 -07005060 int work_done = 0;
Matt Carlson898a56f2009-08-28 14:02:40 +00005061 struct tg3_hw_status *sblk = tnapi->hw_status;
David S. Miller6f535762007-10-11 18:08:29 -07005062
5063 while (1) {
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005064 tg3_poll_link(tp);
5065
Matt Carlson17375d22009-08-28 14:02:18 +00005066 work_done = tg3_poll_work(tnapi, work_done, budget);
David S. Miller6f535762007-10-11 18:08:29 -07005067
5068 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5069 goto tx_recovery;
5070
5071 if (unlikely(work_done >= budget))
5072 break;
5073
Michael Chan4fd7ab52007-10-12 01:39:50 -07005074 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
Matt Carlson17375d22009-08-28 14:02:18 +00005075 /* tp->last_tag is used in tg3_int_reenable() below
Michael Chan4fd7ab52007-10-12 01:39:50 -07005076 * to tell the hw how much work has been processed,
5077 * so we must read it before checking for more work.
5078 */
Matt Carlson898a56f2009-08-28 14:02:40 +00005079 tnapi->last_tag = sblk->status_tag;
5080 tnapi->last_irq_tag = tnapi->last_tag;
Michael Chan4fd7ab52007-10-12 01:39:50 -07005081 rmb();
5082 } else
5083 sblk->status &= ~SD_STATUS_UPDATED;
5084
Matt Carlson17375d22009-08-28 14:02:18 +00005085 if (likely(!tg3_has_work(tnapi))) {
Ben Hutchings288379f2009-01-19 16:43:59 -08005086 napi_complete(napi);
Matt Carlson17375d22009-08-28 14:02:18 +00005087 tg3_int_reenable(tnapi);
David S. Miller6f535762007-10-11 18:08:29 -07005088 break;
5089 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005090 }
5091
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005092 return work_done;
David S. Miller6f535762007-10-11 18:08:29 -07005093
5094tx_recovery:
Michael Chan4fd7ab52007-10-12 01:39:50 -07005095 /* work_done is guaranteed to be less than budget. */
Ben Hutchings288379f2009-01-19 16:43:59 -08005096 napi_complete(napi);
David S. Miller6f535762007-10-11 18:08:29 -07005097 schedule_work(&tp->reset_task);
Michael Chan4fd7ab52007-10-12 01:39:50 -07005098 return work_done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005099}
5100
David S. Millerf47c11e2005-06-24 20:18:35 -07005101static void tg3_irq_quiesce(struct tg3 *tp)
5102{
Matt Carlson4f125f42009-09-01 12:55:02 +00005103 int i;
5104
David S. Millerf47c11e2005-06-24 20:18:35 -07005105 BUG_ON(tp->irq_sync);
5106
5107 tp->irq_sync = 1;
5108 smp_mb();
5109
Matt Carlson4f125f42009-09-01 12:55:02 +00005110 for (i = 0; i < tp->irq_cnt; i++)
5111 synchronize_irq(tp->napi[i].irq_vec);
David S. Millerf47c11e2005-06-24 20:18:35 -07005112}
5113
5114static inline int tg3_irq_sync(struct tg3 *tp)
5115{
5116 return tp->irq_sync;
5117}
5118
5119/* Fully shutdown all tg3 driver activity elsewhere in the system.
5120 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5121 * with as well. Most of the time, this is not necessary except when
5122 * shutting down the device.
5123 */
5124static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5125{
Michael Chan46966542007-07-11 19:47:19 -07005126 spin_lock_bh(&tp->lock);
David S. Millerf47c11e2005-06-24 20:18:35 -07005127 if (irq_sync)
5128 tg3_irq_quiesce(tp);
David S. Millerf47c11e2005-06-24 20:18:35 -07005129}
5130
5131static inline void tg3_full_unlock(struct tg3 *tp)
5132{
David S. Millerf47c11e2005-06-24 20:18:35 -07005133 spin_unlock_bh(&tp->lock);
5134}
5135
Michael Chanfcfa0a32006-03-20 22:28:41 -08005136/* One-shot MSI handler - Chip automatically disables interrupt
5137 * after sending MSI so driver doesn't have to do it.
5138 */
David Howells7d12e782006-10-05 14:55:46 +01005139static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
Michael Chanfcfa0a32006-03-20 22:28:41 -08005140{
Matt Carlson09943a12009-08-28 14:01:57 +00005141 struct tg3_napi *tnapi = dev_id;
5142 struct tg3 *tp = tnapi->tp;
Michael Chanfcfa0a32006-03-20 22:28:41 -08005143
Matt Carlson898a56f2009-08-28 14:02:40 +00005144 prefetch(tnapi->hw_status);
Matt Carlson0c1d0e22009-09-01 13:16:33 +00005145 if (tnapi->rx_rcb)
5146 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
Michael Chanfcfa0a32006-03-20 22:28:41 -08005147
5148 if (likely(!tg3_irq_sync(tp)))
Matt Carlson09943a12009-08-28 14:01:57 +00005149 napi_schedule(&tnapi->napi);
Michael Chanfcfa0a32006-03-20 22:28:41 -08005150
5151 return IRQ_HANDLED;
5152}
5153
Michael Chan88b06bc22005-04-21 17:13:25 -07005154/* MSI ISR - No need to check for interrupt sharing and no need to
5155 * flush status block and interrupt mailbox. PCI ordering rules
5156 * guarantee that MSI will arrive after the status block.
5157 */
David Howells7d12e782006-10-05 14:55:46 +01005158static irqreturn_t tg3_msi(int irq, void *dev_id)
Michael Chan88b06bc22005-04-21 17:13:25 -07005159{
Matt Carlson09943a12009-08-28 14:01:57 +00005160 struct tg3_napi *tnapi = dev_id;
5161 struct tg3 *tp = tnapi->tp;
Michael Chan88b06bc22005-04-21 17:13:25 -07005162
Matt Carlson898a56f2009-08-28 14:02:40 +00005163 prefetch(tnapi->hw_status);
Matt Carlson0c1d0e22009-09-01 13:16:33 +00005164 if (tnapi->rx_rcb)
5165 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
Michael Chan88b06bc22005-04-21 17:13:25 -07005166 /*
David S. Millerfac9b832005-05-18 22:46:34 -07005167 * Writing any value to intr-mbox-0 clears PCI INTA# and
Michael Chan88b06bc22005-04-21 17:13:25 -07005168 * chip-internal interrupt pending events.
David S. Millerfac9b832005-05-18 22:46:34 -07005169 * Writing non-zero to intr-mbox-0 additional tells the
Michael Chan88b06bc22005-04-21 17:13:25 -07005170 * NIC to stop sending us irqs, engaging "in-intr-handler"
5171 * event coalescing.
5172 */
5173 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
Michael Chan61487482005-09-05 17:53:19 -07005174 if (likely(!tg3_irq_sync(tp)))
Matt Carlson09943a12009-08-28 14:01:57 +00005175 napi_schedule(&tnapi->napi);
Michael Chan61487482005-09-05 17:53:19 -07005176
Michael Chan88b06bc22005-04-21 17:13:25 -07005177 return IRQ_RETVAL(1);
5178}
5179
David Howells7d12e782006-10-05 14:55:46 +01005180static irqreturn_t tg3_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005181{
Matt Carlson09943a12009-08-28 14:01:57 +00005182 struct tg3_napi *tnapi = dev_id;
5183 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +00005184 struct tg3_hw_status *sblk = tnapi->hw_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005185 unsigned int handled = 1;
5186
Linus Torvalds1da177e2005-04-16 15:20:36 -07005187 /* In INTx mode, it is possible for the interrupt to arrive at
5188 * the CPU before the status block posted prior to the interrupt.
5189 * Reading the PCI State register will confirm whether the
5190 * interrupt is ours and will flush the status block.
5191 */
Michael Chand18edcb2007-03-24 20:57:11 -07005192 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5193 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5194 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5195 handled = 0;
David S. Millerf47c11e2005-06-24 20:18:35 -07005196 goto out;
David S. Millerfac9b832005-05-18 22:46:34 -07005197 }
Michael Chand18edcb2007-03-24 20:57:11 -07005198 }
5199
5200 /*
5201 * Writing any value to intr-mbox-0 clears PCI INTA# and
5202 * chip-internal interrupt pending events.
5203 * Writing non-zero to intr-mbox-0 additional tells the
5204 * NIC to stop sending us irqs, engaging "in-intr-handler"
5205 * event coalescing.
Michael Chanc04cb342007-05-07 00:26:15 -07005206 *
5207 * Flush the mailbox to de-assert the IRQ immediately to prevent
5208 * spurious interrupts. The flush impacts performance but
5209 * excessive spurious interrupts can be worse in some cases.
Michael Chand18edcb2007-03-24 20:57:11 -07005210 */
Michael Chanc04cb342007-05-07 00:26:15 -07005211 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
Michael Chand18edcb2007-03-24 20:57:11 -07005212 if (tg3_irq_sync(tp))
5213 goto out;
5214 sblk->status &= ~SD_STATUS_UPDATED;
Matt Carlson17375d22009-08-28 14:02:18 +00005215 if (likely(tg3_has_work(tnapi))) {
Matt Carlson72334482009-08-28 14:03:01 +00005216 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
Matt Carlson09943a12009-08-28 14:01:57 +00005217 napi_schedule(&tnapi->napi);
Michael Chand18edcb2007-03-24 20:57:11 -07005218 } else {
5219 /* No work, shared interrupt perhaps? re-enable
5220 * interrupts, and flush that PCI write
5221 */
5222 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5223 0x00000000);
David S. Millerfac9b832005-05-18 22:46:34 -07005224 }
David S. Millerf47c11e2005-06-24 20:18:35 -07005225out:
David S. Millerfac9b832005-05-18 22:46:34 -07005226 return IRQ_RETVAL(handled);
5227}
5228
David Howells7d12e782006-10-05 14:55:46 +01005229static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
David S. Millerfac9b832005-05-18 22:46:34 -07005230{
Matt Carlson09943a12009-08-28 14:01:57 +00005231 struct tg3_napi *tnapi = dev_id;
5232 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +00005233 struct tg3_hw_status *sblk = tnapi->hw_status;
David S. Millerfac9b832005-05-18 22:46:34 -07005234 unsigned int handled = 1;
5235
David S. Millerfac9b832005-05-18 22:46:34 -07005236 /* In INTx mode, it is possible for the interrupt to arrive at
5237 * the CPU before the status block posted prior to the interrupt.
5238 * Reading the PCI State register will confirm whether the
5239 * interrupt is ours and will flush the status block.
5240 */
Matt Carlson898a56f2009-08-28 14:02:40 +00005241 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
Michael Chand18edcb2007-03-24 20:57:11 -07005242 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5243 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5244 handled = 0;
David S. Millerf47c11e2005-06-24 20:18:35 -07005245 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005246 }
Michael Chand18edcb2007-03-24 20:57:11 -07005247 }
5248
5249 /*
5250 * writing any value to intr-mbox-0 clears PCI INTA# and
5251 * chip-internal interrupt pending events.
5252 * writing non-zero to intr-mbox-0 additional tells the
5253 * NIC to stop sending us irqs, engaging "in-intr-handler"
5254 * event coalescing.
Michael Chanc04cb342007-05-07 00:26:15 -07005255 *
5256 * Flush the mailbox to de-assert the IRQ immediately to prevent
5257 * spurious interrupts. The flush impacts performance but
5258 * excessive spurious interrupts can be worse in some cases.
Michael Chand18edcb2007-03-24 20:57:11 -07005259 */
Michael Chanc04cb342007-05-07 00:26:15 -07005260 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
Matt Carlson624f8e52009-04-20 06:55:01 +00005261
5262 /*
5263 * In a shared interrupt configuration, sometimes other devices'
5264 * interrupts will scream. We record the current status tag here
5265 * so that the above check can report that the screaming interrupts
5266 * are unhandled. Eventually they will be silenced.
5267 */
Matt Carlson898a56f2009-08-28 14:02:40 +00005268 tnapi->last_irq_tag = sblk->status_tag;
Matt Carlson624f8e52009-04-20 06:55:01 +00005269
Michael Chand18edcb2007-03-24 20:57:11 -07005270 if (tg3_irq_sync(tp))
5271 goto out;
Matt Carlson624f8e52009-04-20 06:55:01 +00005272
Matt Carlson72334482009-08-28 14:03:01 +00005273 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
Matt Carlson624f8e52009-04-20 06:55:01 +00005274
Matt Carlson09943a12009-08-28 14:01:57 +00005275 napi_schedule(&tnapi->napi);
Matt Carlson624f8e52009-04-20 06:55:01 +00005276
David S. Millerf47c11e2005-06-24 20:18:35 -07005277out:
Linus Torvalds1da177e2005-04-16 15:20:36 -07005278 return IRQ_RETVAL(handled);
5279}
5280
Michael Chan79381092005-04-21 17:13:59 -07005281/* ISR for interrupt test */
David Howells7d12e782006-10-05 14:55:46 +01005282static irqreturn_t tg3_test_isr(int irq, void *dev_id)
Michael Chan79381092005-04-21 17:13:59 -07005283{
Matt Carlson09943a12009-08-28 14:01:57 +00005284 struct tg3_napi *tnapi = dev_id;
5285 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +00005286 struct tg3_hw_status *sblk = tnapi->hw_status;
Michael Chan79381092005-04-21 17:13:59 -07005287
Michael Chanf9804dd2005-09-27 12:13:10 -07005288 if ((sblk->status & SD_STATUS_UPDATED) ||
5289 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
Michael Chanb16250e2006-09-27 16:10:14 -07005290 tg3_disable_ints(tp);
Michael Chan79381092005-04-21 17:13:59 -07005291 return IRQ_RETVAL(1);
5292 }
5293 return IRQ_RETVAL(0);
5294}
5295
Gary Zambrano8e7a22e2006-04-29 18:59:13 -07005296static int tg3_init_hw(struct tg3 *, int);
Michael Chan944d9802005-05-29 14:57:48 -07005297static int tg3_halt(struct tg3 *, int, int);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005298
Michael Chanb9ec6c12006-07-25 16:37:27 -07005299/* Restart hardware after configuration changes, self-test, etc.
5300 * Invoked with tp->lock held.
5301 */
5302static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
Eric Dumazet78c61462008-04-24 23:33:06 -07005303 __releases(tp->lock)
5304 __acquires(tp->lock)
Michael Chanb9ec6c12006-07-25 16:37:27 -07005305{
5306 int err;
5307
5308 err = tg3_init_hw(tp, reset_phy);
5309 if (err) {
Matt Carlson5129c3a2010-04-05 10:19:23 +00005310 netdev_err(tp->dev,
5311 "Failed to re-initialize device, aborting\n");
Michael Chanb9ec6c12006-07-25 16:37:27 -07005312 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5313 tg3_full_unlock(tp);
5314 del_timer_sync(&tp->timer);
5315 tp->irq_sync = 0;
Matt Carlsonfed97812009-09-01 13:10:19 +00005316 tg3_napi_enable(tp);
Michael Chanb9ec6c12006-07-25 16:37:27 -07005317 dev_close(tp->dev);
5318 tg3_full_lock(tp, 0);
5319 }
5320 return err;
5321}
5322
Linus Torvalds1da177e2005-04-16 15:20:36 -07005323#ifdef CONFIG_NET_POLL_CONTROLLER
5324static void tg3_poll_controller(struct net_device *dev)
5325{
Matt Carlson4f125f42009-09-01 12:55:02 +00005326 int i;
Michael Chan88b06bc22005-04-21 17:13:25 -07005327 struct tg3 *tp = netdev_priv(dev);
5328
Matt Carlson4f125f42009-09-01 12:55:02 +00005329 for (i = 0; i < tp->irq_cnt; i++)
Louis Rillingfe234f02010-03-09 06:14:41 +00005330 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005331}
5332#endif
5333
David Howellsc4028952006-11-22 14:57:56 +00005334static void tg3_reset_task(struct work_struct *work)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005335{
David Howellsc4028952006-11-22 14:57:56 +00005336 struct tg3 *tp = container_of(work, struct tg3, reset_task);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07005337 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005338 unsigned int restart_timer;
5339
Michael Chan7faa0062006-02-02 17:29:28 -08005340 tg3_full_lock(tp, 0);
Michael Chan7faa0062006-02-02 17:29:28 -08005341
5342 if (!netif_running(tp->dev)) {
Michael Chan7faa0062006-02-02 17:29:28 -08005343 tg3_full_unlock(tp);
5344 return;
5345 }
5346
5347 tg3_full_unlock(tp);
5348
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07005349 tg3_phy_stop(tp);
5350
Linus Torvalds1da177e2005-04-16 15:20:36 -07005351 tg3_netif_stop(tp);
5352
David S. Millerf47c11e2005-06-24 20:18:35 -07005353 tg3_full_lock(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005354
5355 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5356 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5357
Michael Chandf3e6542006-05-26 17:48:07 -07005358 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5359 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5360 tp->write32_rx_mbox = tg3_write_flush_reg32;
5361 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5362 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5363 }
5364
Michael Chan944d9802005-05-29 14:57:48 -07005365 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07005366 err = tg3_init_hw(tp, 1);
5367 if (err)
Michael Chanb9ec6c12006-07-25 16:37:27 -07005368 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005369
5370 tg3_netif_start(tp);
5371
Linus Torvalds1da177e2005-04-16 15:20:36 -07005372 if (restart_timer)
5373 mod_timer(&tp->timer, jiffies + 1);
Michael Chan7faa0062006-02-02 17:29:28 -08005374
Michael Chanb9ec6c12006-07-25 16:37:27 -07005375out:
Michael Chan7faa0062006-02-02 17:29:28 -08005376 tg3_full_unlock(tp);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07005377
5378 if (!err)
5379 tg3_phy_start(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005380}
5381
Michael Chanb0408752007-02-13 12:18:30 -08005382static void tg3_dump_short_state(struct tg3 *tp)
5383{
Joe Perches05dbe002010-02-17 19:44:19 +00005384 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5385 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5386 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5387 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
Michael Chanb0408752007-02-13 12:18:30 -08005388}
5389
Linus Torvalds1da177e2005-04-16 15:20:36 -07005390static void tg3_tx_timeout(struct net_device *dev)
5391{
5392 struct tg3 *tp = netdev_priv(dev);
5393
Michael Chanb0408752007-02-13 12:18:30 -08005394 if (netif_msg_tx_err(tp)) {
Joe Perches05dbe002010-02-17 19:44:19 +00005395 netdev_err(dev, "transmit timed out, resetting\n");
Michael Chanb0408752007-02-13 12:18:30 -08005396 tg3_dump_short_state(tp);
5397 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005398
5399 schedule_work(&tp->reset_task);
5400}
5401
Michael Chanc58ec932005-09-17 00:46:27 -07005402/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5403static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5404{
5405 u32 base = (u32) mapping & 0xffffffff;
5406
5407 return ((base > 0xffffdcc0) &&
5408 (base + len + 8 < base));
5409}
5410
Michael Chan72f2afb2006-03-06 19:28:35 -08005411/* Test for DMA addresses > 40-bit */
5412static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5413 int len)
5414{
5415#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
Michael Chan6728a8e2006-03-27 23:16:49 -08005416 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
Yang Hongyang50cf1562009-04-06 19:01:14 -07005417 return (((u64) mapping + len) > DMA_BIT_MASK(40));
Michael Chan72f2afb2006-03-06 19:28:35 -08005418 return 0;
5419#else
5420 return 0;
5421#endif
5422}
5423
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005424static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005425
Michael Chan72f2afb2006-03-06 19:28:35 -08005426/* Workaround 4GB and 40-bit hardware DMA bugs. */
Matt Carlson24f4efd2009-11-13 13:03:35 +00005427static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5428 struct sk_buff *skb, u32 last_plus_one,
5429 u32 *start, u32 base_flags, u32 mss)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005430{
Matt Carlson24f4efd2009-11-13 13:03:35 +00005431 struct tg3 *tp = tnapi->tp;
Matt Carlson41588ba2008-04-19 18:12:33 -07005432 struct sk_buff *new_skb;
Michael Chanc58ec932005-09-17 00:46:27 -07005433 dma_addr_t new_addr = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005434 u32 entry = *start;
Michael Chanc58ec932005-09-17 00:46:27 -07005435 int i, ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005436
Matt Carlson41588ba2008-04-19 18:12:33 -07005437 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5438 new_skb = skb_copy(skb, GFP_ATOMIC);
5439 else {
5440 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5441
5442 new_skb = skb_copy_expand(skb,
5443 skb_headroom(skb) + more_headroom,
5444 skb_tailroom(skb), GFP_ATOMIC);
5445 }
5446
Linus Torvalds1da177e2005-04-16 15:20:36 -07005447 if (!new_skb) {
Michael Chanc58ec932005-09-17 00:46:27 -07005448 ret = -1;
5449 } else {
5450 /* New SKB is guaranteed to be linear. */
5451 entry = *start;
Alexander Duyckf4188d82009-12-02 16:48:38 +00005452 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5453 PCI_DMA_TODEVICE);
5454 /* Make sure the mapping succeeded */
5455 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5456 ret = -1;
5457 dev_kfree_skb(new_skb);
5458 new_skb = NULL;
David S. Miller90079ce2008-09-11 04:52:51 -07005459
Michael Chanc58ec932005-09-17 00:46:27 -07005460 /* Make sure new skb does not cross any 4G boundaries.
5461 * Drop the packet if it does.
5462 */
Alexander Duyckf4188d82009-12-02 16:48:38 +00005463 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5464 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5465 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5466 PCI_DMA_TODEVICE);
Michael Chanc58ec932005-09-17 00:46:27 -07005467 ret = -1;
5468 dev_kfree_skb(new_skb);
5469 new_skb = NULL;
5470 } else {
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005471 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
Michael Chanc58ec932005-09-17 00:46:27 -07005472 base_flags, 1 | (mss << 1));
5473 *start = NEXT_TX(entry);
5474 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005475 }
5476
Linus Torvalds1da177e2005-04-16 15:20:36 -07005477 /* Now clean up the sw ring entries. */
5478 i = 0;
5479 while (entry != last_plus_one) {
Alexander Duyckf4188d82009-12-02 16:48:38 +00005480 int len;
5481
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005482 if (i == 0)
Alexander Duyckf4188d82009-12-02 16:48:38 +00005483 len = skb_headlen(skb);
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005484 else
Alexander Duyckf4188d82009-12-02 16:48:38 +00005485 len = skb_shinfo(skb)->frags[i-1].size;
5486
5487 pci_unmap_single(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005488 dma_unmap_addr(&tnapi->tx_buffers[entry],
Alexander Duyckf4188d82009-12-02 16:48:38 +00005489 mapping),
5490 len, PCI_DMA_TODEVICE);
5491 if (i == 0) {
5492 tnapi->tx_buffers[entry].skb = new_skb;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005493 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
Alexander Duyckf4188d82009-12-02 16:48:38 +00005494 new_addr);
5495 } else {
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005496 tnapi->tx_buffers[entry].skb = NULL;
Alexander Duyckf4188d82009-12-02 16:48:38 +00005497 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005498 entry = NEXT_TX(entry);
5499 i++;
5500 }
5501
5502 dev_kfree_skb(skb);
5503
Michael Chanc58ec932005-09-17 00:46:27 -07005504 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005505}
5506
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005507static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005508 dma_addr_t mapping, int len, u32 flags,
5509 u32 mss_and_is_end)
5510{
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005511 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
Linus Torvalds1da177e2005-04-16 15:20:36 -07005512 int is_end = (mss_and_is_end & 0x1);
5513 u32 mss = (mss_and_is_end >> 1);
5514 u32 vlan_tag = 0;
5515
5516 if (is_end)
5517 flags |= TXD_FLAG_END;
5518 if (flags & TXD_FLAG_VLAN) {
5519 vlan_tag = flags >> 16;
5520 flags &= 0xffff;
5521 }
5522 vlan_tag |= (mss << TXD_MSS_SHIFT);
5523
5524 txd->addr_hi = ((u64) mapping >> 32);
5525 txd->addr_lo = ((u64) mapping & 0xffffffff);
5526 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5527 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5528}
5529
Michael Chan5a6f3072006-03-20 22:28:05 -08005530/* hard_start_xmit for devices that don't have any bugs and
Matt Carlsone849cdc2009-11-13 13:03:38 +00005531 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
Michael Chan5a6f3072006-03-20 22:28:05 -08005532 */
Stephen Hemminger613573252009-08-31 19:50:58 +00005533static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5534 struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005535{
5536 struct tg3 *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005537 u32 len, entry, base_flags, mss;
David S. Miller90079ce2008-09-11 04:52:51 -07005538 dma_addr_t mapping;
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005539 struct tg3_napi *tnapi;
5540 struct netdev_queue *txq;
Alexander Duyckf4188d82009-12-02 16:48:38 +00005541 unsigned int i, last;
5542
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005543 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5544 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
Matt Carlson19cfaec2009-12-03 08:36:20 +00005545 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005546 tnapi++;
Michael Chan5a6f3072006-03-20 22:28:05 -08005547
Michael Chan00b70502006-06-17 21:58:45 -07005548 /* We are running in BH disabled context with netif_tx_lock
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005549 * and TX reclaim runs via tp->napi.poll inside of a software
Michael Chan5a6f3072006-03-20 22:28:05 -08005550 * interrupt. Furthermore, IRQ processing runs lockless so we have
5551 * no IRQ context deadlocks to worry about either. Rejoice!
5552 */
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005553 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005554 if (!netif_tx_queue_stopped(txq)) {
5555 netif_tx_stop_queue(txq);
Michael Chan5a6f3072006-03-20 22:28:05 -08005556
5557 /* This is a hard error, log it. */
Matt Carlson5129c3a2010-04-05 10:19:23 +00005558 netdev_err(dev,
5559 "BUG! Tx Ring full when queue awake!\n");
Michael Chan5a6f3072006-03-20 22:28:05 -08005560 }
Michael Chan5a6f3072006-03-20 22:28:05 -08005561 return NETDEV_TX_BUSY;
5562 }
5563
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005564 entry = tnapi->tx_prod;
Michael Chan5a6f3072006-03-20 22:28:05 -08005565 base_flags = 0;
Matt Carlsonbe98da62010-07-11 09:31:46 +00005566 mss = skb_shinfo(skb)->gso_size;
5567 if (mss) {
Michael Chan5a6f3072006-03-20 22:28:05 -08005568 int tcp_opt_len, ip_tcp_len;
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00005569 u32 hdrlen;
Michael Chan5a6f3072006-03-20 22:28:05 -08005570
5571 if (skb_header_cloned(skb) &&
5572 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5573 dev_kfree_skb(skb);
5574 goto out_unlock;
5575 }
5576
Michael Chanb0026622006-07-03 19:42:14 -07005577 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00005578 hdrlen = skb_headlen(skb) - ETH_HLEN;
Michael Chanb0026622006-07-03 19:42:14 -07005579 else {
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07005580 struct iphdr *iph = ip_hdr(skb);
5581
Arnaldo Carvalho de Meloab6a5bb2007-03-18 17:43:48 -07005582 tcp_opt_len = tcp_optlen(skb);
Arnaldo Carvalho de Meloc9bdd4b2007-03-12 20:09:15 -03005583 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
Michael Chanb0026622006-07-03 19:42:14 -07005584
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07005585 iph->check = 0;
5586 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00005587 hdrlen = ip_tcp_len + tcp_opt_len;
Michael Chanb0026622006-07-03 19:42:14 -07005588 }
Michael Chan5a6f3072006-03-20 22:28:05 -08005589
Matt Carlsone849cdc2009-11-13 13:03:38 +00005590 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00005591 mss |= (hdrlen & 0xc) << 12;
5592 if (hdrlen & 0x10)
5593 base_flags |= 0x00000010;
5594 base_flags |= (hdrlen & 0x3e0) << 5;
5595 } else
5596 mss |= hdrlen << 9;
5597
Michael Chan5a6f3072006-03-20 22:28:05 -08005598 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5599 TXD_FLAG_CPU_POST_DMA);
5600
Arnaldo Carvalho de Meloaa8223c2007-04-10 21:04:22 -07005601 tcp_hdr(skb)->check = 0;
Michael Chan5a6f3072006-03-20 22:28:05 -08005602
Matt Carlson859a588792010-04-05 10:19:28 +00005603 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
Michael Chan5a6f3072006-03-20 22:28:05 -08005604 base_flags |= TXD_FLAG_TCPUDP_CSUM;
Matt Carlson859a588792010-04-05 10:19:28 +00005605 }
5606
Michael Chan5a6f3072006-03-20 22:28:05 -08005607#if TG3_VLAN_TAG_USED
5608 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5609 base_flags |= (TXD_FLAG_VLAN |
5610 (vlan_tx_tag_get(skb) << 16));
5611#endif
5612
Alexander Duyckf4188d82009-12-02 16:48:38 +00005613 len = skb_headlen(skb);
5614
5615 /* Queue skb data, a.k.a. the main skb fragment. */
5616 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5617 if (pci_dma_mapping_error(tp->pdev, mapping)) {
David S. Miller90079ce2008-09-11 04:52:51 -07005618 dev_kfree_skb(skb);
5619 goto out_unlock;
5620 }
5621
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005622 tnapi->tx_buffers[entry].skb = skb;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005623 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005624
Matt Carlsonb703df62009-12-03 08:36:21 +00005625 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00005626 !mss && skb->len > ETH_DATA_LEN)
5627 base_flags |= TXD_FLAG_JMB_PKT;
5628
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005629 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
Michael Chan5a6f3072006-03-20 22:28:05 -08005630 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5631
5632 entry = NEXT_TX(entry);
5633
5634 /* Now loop through additional data fragments, and queue them. */
5635 if (skb_shinfo(skb)->nr_frags > 0) {
Michael Chan5a6f3072006-03-20 22:28:05 -08005636 last = skb_shinfo(skb)->nr_frags - 1;
5637 for (i = 0; i <= last; i++) {
5638 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5639
5640 len = frag->size;
Alexander Duyckf4188d82009-12-02 16:48:38 +00005641 mapping = pci_map_page(tp->pdev,
5642 frag->page,
5643 frag->page_offset,
5644 len, PCI_DMA_TODEVICE);
5645 if (pci_dma_mapping_error(tp->pdev, mapping))
5646 goto dma_error;
5647
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005648 tnapi->tx_buffers[entry].skb = NULL;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005649 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
Alexander Duyckf4188d82009-12-02 16:48:38 +00005650 mapping);
Michael Chan5a6f3072006-03-20 22:28:05 -08005651
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005652 tg3_set_txd(tnapi, entry, mapping, len,
Michael Chan5a6f3072006-03-20 22:28:05 -08005653 base_flags, (i == last) | (mss << 1));
5654
5655 entry = NEXT_TX(entry);
5656 }
5657 }
5658
5659 /* Packets are ready, update Tx producer idx local and on card. */
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005660 tw32_tx_mbox(tnapi->prodmbox, entry);
Michael Chan5a6f3072006-03-20 22:28:05 -08005661
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005662 tnapi->tx_prod = entry;
5663 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005664 netif_tx_stop_queue(txq);
Matt Carlsonf65aac12010-08-02 11:26:03 +00005665
5666 /* netif_tx_stop_queue() must be done before checking
5667 * checking tx index in tg3_tx_avail() below, because in
5668 * tg3_tx(), we update tx index before checking for
5669 * netif_tx_queue_stopped().
5670 */
5671 smp_mb();
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005672 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005673 netif_tx_wake_queue(txq);
Michael Chan5a6f3072006-03-20 22:28:05 -08005674 }
5675
5676out_unlock:
Eric Dumazetcdd0db02009-05-28 00:00:41 +00005677 mmiowb();
Michael Chan5a6f3072006-03-20 22:28:05 -08005678
5679 return NETDEV_TX_OK;
Alexander Duyckf4188d82009-12-02 16:48:38 +00005680
5681dma_error:
5682 last = i;
5683 entry = tnapi->tx_prod;
5684 tnapi->tx_buffers[entry].skb = NULL;
5685 pci_unmap_single(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005686 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
Alexander Duyckf4188d82009-12-02 16:48:38 +00005687 skb_headlen(skb),
5688 PCI_DMA_TODEVICE);
5689 for (i = 0; i <= last; i++) {
5690 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5691 entry = NEXT_TX(entry);
5692
5693 pci_unmap_page(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005694 dma_unmap_addr(&tnapi->tx_buffers[entry],
Alexander Duyckf4188d82009-12-02 16:48:38 +00005695 mapping),
5696 frag->size, PCI_DMA_TODEVICE);
5697 }
5698
5699 dev_kfree_skb(skb);
5700 return NETDEV_TX_OK;
Michael Chan5a6f3072006-03-20 22:28:05 -08005701}
5702
Stephen Hemminger613573252009-08-31 19:50:58 +00005703static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5704 struct net_device *);
Michael Chan52c0fd82006-06-29 20:15:54 -07005705
5706/* Use GSO to workaround a rare TSO bug that may be triggered when the
5707 * TSO header is greater than 80 bytes.
5708 */
5709static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5710{
5711 struct sk_buff *segs, *nskb;
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005712 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
Michael Chan52c0fd82006-06-29 20:15:54 -07005713
5714 /* Estimate the number of fragments in the worst case */
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005715 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
Michael Chan52c0fd82006-06-29 20:15:54 -07005716 netif_stop_queue(tp->dev);
Matt Carlsonf65aac12010-08-02 11:26:03 +00005717
5718 /* netif_tx_stop_queue() must be done before checking
5719 * checking tx index in tg3_tx_avail() below, because in
5720 * tg3_tx(), we update tx index before checking for
5721 * netif_tx_queue_stopped().
5722 */
5723 smp_mb();
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005724 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
Michael Chan7f62ad52007-02-20 23:25:40 -08005725 return NETDEV_TX_BUSY;
5726
5727 netif_wake_queue(tp->dev);
Michael Chan52c0fd82006-06-29 20:15:54 -07005728 }
5729
5730 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
Hirofumi Nakagawa801678c2008-04-29 01:03:09 -07005731 if (IS_ERR(segs))
Michael Chan52c0fd82006-06-29 20:15:54 -07005732 goto tg3_tso_bug_end;
5733
5734 do {
5735 nskb = segs;
5736 segs = segs->next;
5737 nskb->next = NULL;
5738 tg3_start_xmit_dma_bug(nskb, tp->dev);
5739 } while (segs);
5740
5741tg3_tso_bug_end:
5742 dev_kfree_skb(skb);
5743
5744 return NETDEV_TX_OK;
5745}
Michael Chan52c0fd82006-06-29 20:15:54 -07005746
Michael Chan5a6f3072006-03-20 22:28:05 -08005747/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5748 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5749 */
Stephen Hemminger613573252009-08-31 19:50:58 +00005750static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5751 struct net_device *dev)
Michael Chan5a6f3072006-03-20 22:28:05 -08005752{
5753 struct tg3 *tp = netdev_priv(dev);
Michael Chan5a6f3072006-03-20 22:28:05 -08005754 u32 len, entry, base_flags, mss;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005755 int would_hit_hwbug;
David S. Miller90079ce2008-09-11 04:52:51 -07005756 dma_addr_t mapping;
Matt Carlson24f4efd2009-11-13 13:03:35 +00005757 struct tg3_napi *tnapi;
5758 struct netdev_queue *txq;
Alexander Duyckf4188d82009-12-02 16:48:38 +00005759 unsigned int i, last;
5760
Matt Carlson24f4efd2009-11-13 13:03:35 +00005761 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5762 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
Matt Carlson19cfaec2009-12-03 08:36:20 +00005763 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
Matt Carlson24f4efd2009-11-13 13:03:35 +00005764 tnapi++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005765
Michael Chan00b70502006-06-17 21:58:45 -07005766 /* We are running in BH disabled context with netif_tx_lock
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005767 * and TX reclaim runs via tp->napi.poll inside of a software
David S. Millerf47c11e2005-06-24 20:18:35 -07005768 * interrupt. Furthermore, IRQ processing runs lockless so we have
5769 * no IRQ context deadlocks to worry about either. Rejoice!
Linus Torvalds1da177e2005-04-16 15:20:36 -07005770 */
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005771 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
Matt Carlson24f4efd2009-11-13 13:03:35 +00005772 if (!netif_tx_queue_stopped(txq)) {
5773 netif_tx_stop_queue(txq);
Stephen Hemminger1f064a82005-12-06 17:36:44 -08005774
5775 /* This is a hard error, log it. */
Matt Carlson5129c3a2010-04-05 10:19:23 +00005776 netdev_err(dev,
5777 "BUG! Tx Ring full when queue awake!\n");
Stephen Hemminger1f064a82005-12-06 17:36:44 -08005778 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005779 return NETDEV_TX_BUSY;
5780 }
5781
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005782 entry = tnapi->tx_prod;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005783 base_flags = 0;
Patrick McHardy84fa7932006-08-29 16:44:56 -07005784 if (skb->ip_summed == CHECKSUM_PARTIAL)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005785 base_flags |= TXD_FLAG_TCPUDP_CSUM;
Matt Carlson24f4efd2009-11-13 13:03:35 +00005786
Matt Carlsonbe98da62010-07-11 09:31:46 +00005787 mss = skb_shinfo(skb)->gso_size;
5788 if (mss) {
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07005789 struct iphdr *iph;
Matt Carlson34195c32010-07-11 09:31:42 +00005790 u32 tcp_opt_len, hdr_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005791
5792 if (skb_header_cloned(skb) &&
5793 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5794 dev_kfree_skb(skb);
5795 goto out_unlock;
5796 }
5797
Matt Carlson34195c32010-07-11 09:31:42 +00005798 iph = ip_hdr(skb);
Arnaldo Carvalho de Meloab6a5bb2007-03-18 17:43:48 -07005799 tcp_opt_len = tcp_optlen(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005800
Matt Carlson34195c32010-07-11 09:31:42 +00005801 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5802 hdr_len = skb_headlen(skb) - ETH_HLEN;
5803 } else {
5804 u32 ip_tcp_len;
5805
5806 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5807 hdr_len = ip_tcp_len + tcp_opt_len;
5808
5809 iph->check = 0;
5810 iph->tot_len = htons(mss + hdr_len);
5811 }
5812
Michael Chan52c0fd82006-06-29 20:15:54 -07005813 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
Michael Chan7f62ad52007-02-20 23:25:40 -08005814 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
Matt Carlsonde6f31e2010-04-12 06:58:30 +00005815 return tg3_tso_bug(tp, skb);
Michael Chan52c0fd82006-06-29 20:15:54 -07005816
Linus Torvalds1da177e2005-04-16 15:20:36 -07005817 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5818 TXD_FLAG_CPU_POST_DMA);
5819
Linus Torvalds1da177e2005-04-16 15:20:36 -07005820 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
Arnaldo Carvalho de Meloaa8223c2007-04-10 21:04:22 -07005821 tcp_hdr(skb)->check = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005822 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
Arnaldo Carvalho de Meloaa8223c2007-04-10 21:04:22 -07005823 } else
5824 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5825 iph->daddr, 0,
5826 IPPROTO_TCP,
5827 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005828
Matt Carlson615774f2009-11-13 13:03:39 +00005829 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5830 mss |= (hdr_len & 0xc) << 12;
5831 if (hdr_len & 0x10)
5832 base_flags |= 0x00000010;
5833 base_flags |= (hdr_len & 0x3e0) << 5;
5834 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
Matt Carlson92c6b8d2009-11-02 14:23:27 +00005835 mss |= hdr_len << 9;
5836 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5837 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07005838 if (tcp_opt_len || iph->ihl > 5) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005839 int tsflags;
5840
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07005841 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005842 mss |= (tsflags << 11);
5843 }
5844 } else {
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07005845 if (tcp_opt_len || iph->ihl > 5) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005846 int tsflags;
5847
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07005848 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005849 base_flags |= tsflags << 12;
5850 }
5851 }
5852 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005853#if TG3_VLAN_TAG_USED
5854 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5855 base_flags |= (TXD_FLAG_VLAN |
5856 (vlan_tx_tag_get(skb) << 16));
5857#endif
5858
Matt Carlsonb703df62009-12-03 08:36:21 +00005859 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
Matt Carlson615774f2009-11-13 13:03:39 +00005860 !mss && skb->len > ETH_DATA_LEN)
5861 base_flags |= TXD_FLAG_JMB_PKT;
5862
Alexander Duyckf4188d82009-12-02 16:48:38 +00005863 len = skb_headlen(skb);
5864
5865 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5866 if (pci_dma_mapping_error(tp->pdev, mapping)) {
David S. Miller90079ce2008-09-11 04:52:51 -07005867 dev_kfree_skb(skb);
5868 goto out_unlock;
5869 }
5870
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005871 tnapi->tx_buffers[entry].skb = skb;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005872 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005873
5874 would_hit_hwbug = 0;
5875
Matt Carlson92c6b8d2009-11-02 14:23:27 +00005876 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5877 would_hit_hwbug = 1;
5878
Matt Carlson0e1406d2009-11-02 12:33:33 +00005879 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5880 tg3_4g_overflow_test(mapping, len))
Matt Carlson41588ba2008-04-19 18:12:33 -07005881 would_hit_hwbug = 1;
Matt Carlson0e1406d2009-11-02 12:33:33 +00005882
5883 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5884 tg3_40bit_overflow_test(tp, mapping, len))
5885 would_hit_hwbug = 1;
5886
5887 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
Michael Chanc58ec932005-09-17 00:46:27 -07005888 would_hit_hwbug = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005889
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005890 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005891 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5892
5893 entry = NEXT_TX(entry);
5894
5895 /* Now loop through additional data fragments, and queue them. */
5896 if (skb_shinfo(skb)->nr_frags > 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005897 last = skb_shinfo(skb)->nr_frags - 1;
5898 for (i = 0; i <= last; i++) {
5899 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5900
5901 len = frag->size;
Alexander Duyckf4188d82009-12-02 16:48:38 +00005902 mapping = pci_map_page(tp->pdev,
5903 frag->page,
5904 frag->page_offset,
5905 len, PCI_DMA_TODEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005906
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005907 tnapi->tx_buffers[entry].skb = NULL;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005908 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
Alexander Duyckf4188d82009-12-02 16:48:38 +00005909 mapping);
5910 if (pci_dma_mapping_error(tp->pdev, mapping))
5911 goto dma_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005912
Matt Carlson92c6b8d2009-11-02 14:23:27 +00005913 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5914 len <= 8)
5915 would_hit_hwbug = 1;
5916
Matt Carlson0e1406d2009-11-02 12:33:33 +00005917 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5918 tg3_4g_overflow_test(mapping, len))
Michael Chanc58ec932005-09-17 00:46:27 -07005919 would_hit_hwbug = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005920
Matt Carlson0e1406d2009-11-02 12:33:33 +00005921 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5922 tg3_40bit_overflow_test(tp, mapping, len))
Michael Chan72f2afb2006-03-06 19:28:35 -08005923 would_hit_hwbug = 1;
5924
Linus Torvalds1da177e2005-04-16 15:20:36 -07005925 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005926 tg3_set_txd(tnapi, entry, mapping, len,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005927 base_flags, (i == last)|(mss << 1));
5928 else
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005929 tg3_set_txd(tnapi, entry, mapping, len,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005930 base_flags, (i == last));
5931
5932 entry = NEXT_TX(entry);
5933 }
5934 }
5935
5936 if (would_hit_hwbug) {
5937 u32 last_plus_one = entry;
5938 u32 start;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005939
Michael Chanc58ec932005-09-17 00:46:27 -07005940 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5941 start &= (TG3_TX_RING_SIZE - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005942
5943 /* If the workaround fails due to memory/mapping
5944 * failure, silently drop this packet.
5945 */
Matt Carlson24f4efd2009-11-13 13:03:35 +00005946 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
Michael Chanc58ec932005-09-17 00:46:27 -07005947 &start, base_flags, mss))
Linus Torvalds1da177e2005-04-16 15:20:36 -07005948 goto out_unlock;
5949
5950 entry = start;
5951 }
5952
5953 /* Packets are ready, update Tx producer idx local and on card. */
Matt Carlson24f4efd2009-11-13 13:03:35 +00005954 tw32_tx_mbox(tnapi->prodmbox, entry);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005955
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005956 tnapi->tx_prod = entry;
5957 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
Matt Carlson24f4efd2009-11-13 13:03:35 +00005958 netif_tx_stop_queue(txq);
Matt Carlsonf65aac12010-08-02 11:26:03 +00005959
5960 /* netif_tx_stop_queue() must be done before checking
5961 * checking tx index in tg3_tx_avail() below, because in
5962 * tg3_tx(), we update tx index before checking for
5963 * netif_tx_queue_stopped().
5964 */
5965 smp_mb();
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005966 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
Matt Carlson24f4efd2009-11-13 13:03:35 +00005967 netif_tx_wake_queue(txq);
Michael Chan51b91462005-09-01 17:41:28 -07005968 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005969
5970out_unlock:
Eric Dumazetcdd0db02009-05-28 00:00:41 +00005971 mmiowb();
Linus Torvalds1da177e2005-04-16 15:20:36 -07005972
5973 return NETDEV_TX_OK;
Alexander Duyckf4188d82009-12-02 16:48:38 +00005974
5975dma_error:
5976 last = i;
5977 entry = tnapi->tx_prod;
5978 tnapi->tx_buffers[entry].skb = NULL;
5979 pci_unmap_single(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005980 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
Alexander Duyckf4188d82009-12-02 16:48:38 +00005981 skb_headlen(skb),
5982 PCI_DMA_TODEVICE);
5983 for (i = 0; i <= last; i++) {
5984 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5985 entry = NEXT_TX(entry);
5986
5987 pci_unmap_page(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005988 dma_unmap_addr(&tnapi->tx_buffers[entry],
Alexander Duyckf4188d82009-12-02 16:48:38 +00005989 mapping),
5990 frag->size, PCI_DMA_TODEVICE);
5991 }
5992
5993 dev_kfree_skb(skb);
5994 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005995}
5996
5997static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5998 int new_mtu)
5999{
6000 dev->mtu = new_mtu;
6001
Michael Chanef7f5ec2005-07-25 12:32:25 -07006002 if (new_mtu > ETH_DATA_LEN) {
Michael Chana4e2b342005-10-26 15:46:52 -07006003 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
Michael Chanef7f5ec2005-07-25 12:32:25 -07006004 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6005 ethtool_op_set_tso(dev, 0);
Matt Carlson859a588792010-04-05 10:19:28 +00006006 } else {
Michael Chanef7f5ec2005-07-25 12:32:25 -07006007 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
Matt Carlson859a588792010-04-05 10:19:28 +00006008 }
Michael Chanef7f5ec2005-07-25 12:32:25 -07006009 } else {
Michael Chana4e2b342005-10-26 15:46:52 -07006010 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
Michael Chanef7f5ec2005-07-25 12:32:25 -07006011 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
Michael Chan0f893dc2005-07-25 12:30:38 -07006012 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
Michael Chanef7f5ec2005-07-25 12:32:25 -07006013 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006014}
6015
6016static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6017{
6018 struct tg3 *tp = netdev_priv(dev);
Michael Chanb9ec6c12006-07-25 16:37:27 -07006019 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006020
6021 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6022 return -EINVAL;
6023
6024 if (!netif_running(dev)) {
6025 /* We'll just catch it later when the
6026 * device is up'd.
6027 */
6028 tg3_set_mtu(dev, tp, new_mtu);
6029 return 0;
6030 }
6031
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07006032 tg3_phy_stop(tp);
6033
Linus Torvalds1da177e2005-04-16 15:20:36 -07006034 tg3_netif_stop(tp);
David S. Millerf47c11e2005-06-24 20:18:35 -07006035
6036 tg3_full_lock(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006037
Michael Chan944d9802005-05-29 14:57:48 -07006038 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006039
6040 tg3_set_mtu(dev, tp, new_mtu);
6041
Michael Chanb9ec6c12006-07-25 16:37:27 -07006042 err = tg3_restart_hw(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006043
Michael Chanb9ec6c12006-07-25 16:37:27 -07006044 if (!err)
6045 tg3_netif_start(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006046
David S. Millerf47c11e2005-06-24 20:18:35 -07006047 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006048
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07006049 if (!err)
6050 tg3_phy_start(tp);
6051
Michael Chanb9ec6c12006-07-25 16:37:27 -07006052 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006053}
6054
Matt Carlson21f581a2009-08-28 14:00:25 +00006055static void tg3_rx_prodring_free(struct tg3 *tp,
6056 struct tg3_rx_prodring_set *tpr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006057{
Linus Torvalds1da177e2005-04-16 15:20:36 -07006058 int i;
6059
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006060 if (tpr != &tp->prodring[0]) {
6061 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6062 i = (i + 1) % TG3_RX_RING_SIZE)
6063 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6064 tp->rx_pkt_map_sz);
6065
6066 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6067 for (i = tpr->rx_jmb_cons_idx;
6068 i != tpr->rx_jmb_prod_idx;
6069 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6070 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6071 TG3_RX_JMB_MAP_SZ);
6072 }
6073 }
6074
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006075 return;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006076 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006077
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006078 for (i = 0; i < TG3_RX_RING_SIZE; i++)
6079 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6080 tp->rx_pkt_map_sz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006081
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006082 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006083 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6084 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6085 TG3_RX_JMB_MAP_SZ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006086 }
6087}
6088
Matt Carlsonc6cdf432010-04-05 10:19:26 +00006089/* Initialize rx rings for packet processing.
Linus Torvalds1da177e2005-04-16 15:20:36 -07006090 *
6091 * The chip has been shut down and the driver detached from
6092 * the networking, so no interrupts or new tx packets will
6093 * end up in the driver. tp->{tx,}lock are held and thus
6094 * we may not sleep.
6095 */
Matt Carlson21f581a2009-08-28 14:00:25 +00006096static int tg3_rx_prodring_alloc(struct tg3 *tp,
6097 struct tg3_rx_prodring_set *tpr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006098{
Matt Carlson287be122009-08-28 13:58:46 +00006099 u32 i, rx_pkt_dma_sz;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006100
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006101 tpr->rx_std_cons_idx = 0;
6102 tpr->rx_std_prod_idx = 0;
6103 tpr->rx_jmb_cons_idx = 0;
6104 tpr->rx_jmb_prod_idx = 0;
6105
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006106 if (tpr != &tp->prodring[0]) {
6107 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6108 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6109 memset(&tpr->rx_jmb_buffers[0], 0,
6110 TG3_RX_JMB_BUFF_RING_SIZE);
6111 goto done;
6112 }
6113
Linus Torvalds1da177e2005-04-16 15:20:36 -07006114 /* Zero out all descriptors. */
Matt Carlson21f581a2009-08-28 14:00:25 +00006115 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006116
Matt Carlson287be122009-08-28 13:58:46 +00006117 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
Michael Chana4e2b342005-10-26 15:46:52 -07006118 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
Matt Carlson287be122009-08-28 13:58:46 +00006119 tp->dev->mtu > ETH_DATA_LEN)
6120 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6121 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
Michael Chan7e72aad2005-07-25 12:31:17 -07006122
Linus Torvalds1da177e2005-04-16 15:20:36 -07006123 /* Initialize invariants of the rings, we only set this
6124 * stuff once. This works because the card does not
6125 * write into the rx buffer posting rings.
6126 */
6127 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6128 struct tg3_rx_buffer_desc *rxd;
6129
Matt Carlson21f581a2009-08-28 14:00:25 +00006130 rxd = &tpr->rx_std[i];
Matt Carlson287be122009-08-28 13:58:46 +00006131 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006132 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6133 rxd->opaque = (RXD_OPAQUE_RING_STD |
6134 (i << RXD_OPAQUE_INDEX_SHIFT));
6135 }
6136
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006137 /* Now allocate fresh SKBs for each rx ring. */
6138 for (i = 0; i < tp->rx_pending; i++) {
Matt Carlson86b21e52009-11-13 13:03:45 +00006139 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
Matt Carlson5129c3a2010-04-05 10:19:23 +00006140 netdev_warn(tp->dev,
6141 "Using a smaller RX standard ring. Only "
6142 "%d out of %d buffers were allocated "
6143 "successfully\n", i, tp->rx_pending);
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006144 if (i == 0)
6145 goto initfail;
6146 tp->rx_pending = i;
6147 break;
6148 }
6149 }
6150
6151 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6152 goto done;
6153
Matt Carlson21f581a2009-08-28 14:00:25 +00006154 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006155
Matt Carlson0d86df82010-02-17 15:17:00 +00006156 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6157 goto done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006158
Matt Carlson0d86df82010-02-17 15:17:00 +00006159 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6160 struct tg3_rx_buffer_desc *rxd;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006161
Matt Carlson0d86df82010-02-17 15:17:00 +00006162 rxd = &tpr->rx_jmb[i].std;
6163 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6164 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6165 RXD_FLAG_JUMBO;
6166 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6167 (i << RXD_OPAQUE_INDEX_SHIFT));
6168 }
6169
6170 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6171 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
Matt Carlson5129c3a2010-04-05 10:19:23 +00006172 netdev_warn(tp->dev,
6173 "Using a smaller RX jumbo ring. Only %d "
6174 "out of %d buffers were allocated "
6175 "successfully\n", i, tp->rx_jumbo_pending);
Matt Carlson0d86df82010-02-17 15:17:00 +00006176 if (i == 0)
6177 goto initfail;
6178 tp->rx_jumbo_pending = i;
6179 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006180 }
6181 }
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006182
6183done:
Michael Chan32d8c572006-07-25 16:38:29 -07006184 return 0;
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006185
6186initfail:
Matt Carlson21f581a2009-08-28 14:00:25 +00006187 tg3_rx_prodring_free(tp, tpr);
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006188 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006189}
6190
Matt Carlson21f581a2009-08-28 14:00:25 +00006191static void tg3_rx_prodring_fini(struct tg3 *tp,
6192 struct tg3_rx_prodring_set *tpr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006193{
Matt Carlson21f581a2009-08-28 14:00:25 +00006194 kfree(tpr->rx_std_buffers);
6195 tpr->rx_std_buffers = NULL;
6196 kfree(tpr->rx_jmb_buffers);
6197 tpr->rx_jmb_buffers = NULL;
6198 if (tpr->rx_std) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07006199 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
Matt Carlson21f581a2009-08-28 14:00:25 +00006200 tpr->rx_std, tpr->rx_std_mapping);
6201 tpr->rx_std = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006202 }
Matt Carlson21f581a2009-08-28 14:00:25 +00006203 if (tpr->rx_jmb) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07006204 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
Matt Carlson21f581a2009-08-28 14:00:25 +00006205 tpr->rx_jmb, tpr->rx_jmb_mapping);
6206 tpr->rx_jmb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006207 }
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006208}
6209
Matt Carlson21f581a2009-08-28 14:00:25 +00006210static int tg3_rx_prodring_init(struct tg3 *tp,
6211 struct tg3_rx_prodring_set *tpr)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006212{
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006213 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
Matt Carlson21f581a2009-08-28 14:00:25 +00006214 if (!tpr->rx_std_buffers)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006215 return -ENOMEM;
6216
Matt Carlson21f581a2009-08-28 14:00:25 +00006217 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6218 &tpr->rx_std_mapping);
6219 if (!tpr->rx_std)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006220 goto err_out;
6221
6222 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006223 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
Matt Carlson21f581a2009-08-28 14:00:25 +00006224 GFP_KERNEL);
6225 if (!tpr->rx_jmb_buffers)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006226 goto err_out;
6227
Matt Carlson21f581a2009-08-28 14:00:25 +00006228 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6229 TG3_RX_JUMBO_RING_BYTES,
6230 &tpr->rx_jmb_mapping);
6231 if (!tpr->rx_jmb)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006232 goto err_out;
6233 }
6234
6235 return 0;
6236
6237err_out:
Matt Carlson21f581a2009-08-28 14:00:25 +00006238 tg3_rx_prodring_fini(tp, tpr);
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006239 return -ENOMEM;
6240}
6241
6242/* Free up pending packets in all rx/tx rings.
6243 *
6244 * The chip has been shut down and the driver detached from
6245 * the networking, so no interrupts or new tx packets will
6246 * end up in the driver. tp->{tx,}lock is not held and we are not
6247 * in an interrupt context and thus may sleep.
6248 */
6249static void tg3_free_rings(struct tg3 *tp)
6250{
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006251 int i, j;
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006252
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006253 for (j = 0; j < tp->irq_cnt; j++) {
6254 struct tg3_napi *tnapi = &tp->napi[j];
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006255
Matt Carlsonb28f6422010-06-05 17:24:32 +00006256 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6257
Matt Carlson0c1d0e22009-09-01 13:16:33 +00006258 if (!tnapi->tx_buffers)
6259 continue;
6260
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006261 for (i = 0; i < TG3_TX_RING_SIZE; ) {
Alexander Duyckf4188d82009-12-02 16:48:38 +00006262 struct ring_info *txp;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006263 struct sk_buff *skb;
Alexander Duyckf4188d82009-12-02 16:48:38 +00006264 unsigned int k;
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006265
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006266 txp = &tnapi->tx_buffers[i];
6267 skb = txp->skb;
6268
6269 if (skb == NULL) {
6270 i++;
6271 continue;
6272 }
6273
Alexander Duyckf4188d82009-12-02 16:48:38 +00006274 pci_unmap_single(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00006275 dma_unmap_addr(txp, mapping),
Alexander Duyckf4188d82009-12-02 16:48:38 +00006276 skb_headlen(skb),
6277 PCI_DMA_TODEVICE);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006278 txp->skb = NULL;
6279
Alexander Duyckf4188d82009-12-02 16:48:38 +00006280 i++;
6281
6282 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6283 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6284 pci_unmap_page(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00006285 dma_unmap_addr(txp, mapping),
Alexander Duyckf4188d82009-12-02 16:48:38 +00006286 skb_shinfo(skb)->frags[k].size,
6287 PCI_DMA_TODEVICE);
6288 i++;
6289 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006290
6291 dev_kfree_skb_any(skb);
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006292 }
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006293 }
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006294}
6295
6296/* Initialize tx/rx rings for packet processing.
6297 *
6298 * The chip has been shut down and the driver detached from
6299 * the networking, so no interrupts or new tx packets will
6300 * end up in the driver. tp->{tx,}lock are held and thus
6301 * we may not sleep.
6302 */
6303static int tg3_init_rings(struct tg3 *tp)
6304{
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006305 int i;
Matt Carlson72334482009-08-28 14:03:01 +00006306
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006307 /* Free up all the SKBs. */
6308 tg3_free_rings(tp);
6309
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006310 for (i = 0; i < tp->irq_cnt; i++) {
6311 struct tg3_napi *tnapi = &tp->napi[i];
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006312
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006313 tnapi->last_tag = 0;
6314 tnapi->last_irq_tag = 0;
6315 tnapi->hw_status->status = 0;
6316 tnapi->hw_status->status_tag = 0;
6317 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6318
6319 tnapi->tx_prod = 0;
6320 tnapi->tx_cons = 0;
Matt Carlson0c1d0e22009-09-01 13:16:33 +00006321 if (tnapi->tx_ring)
6322 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006323
6324 tnapi->rx_rcb_ptr = 0;
Matt Carlson0c1d0e22009-09-01 13:16:33 +00006325 if (tnapi->rx_rcb)
6326 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006327
Matt Carlsone4af1af2010-02-12 14:47:05 +00006328 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6329 tg3_free_rings(tp);
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006330 return -ENOMEM;
Matt Carlsone4af1af2010-02-12 14:47:05 +00006331 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006332 }
Matt Carlson72334482009-08-28 14:03:01 +00006333
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006334 return 0;
Matt Carlsoncf7a7292009-08-28 13:59:57 +00006335}
6336
6337/*
6338 * Must not be invoked with interrupt sources disabled and
6339 * the hardware shutdown down.
6340 */
6341static void tg3_free_consistent(struct tg3 *tp)
6342{
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006343 int i;
Matt Carlson898a56f2009-08-28 14:02:40 +00006344
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006345 for (i = 0; i < tp->irq_cnt; i++) {
6346 struct tg3_napi *tnapi = &tp->napi[i];
6347
6348 if (tnapi->tx_ring) {
6349 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6350 tnapi->tx_ring, tnapi->tx_desc_mapping);
6351 tnapi->tx_ring = NULL;
6352 }
6353
6354 kfree(tnapi->tx_buffers);
6355 tnapi->tx_buffers = NULL;
6356
6357 if (tnapi->rx_rcb) {
6358 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6359 tnapi->rx_rcb,
6360 tnapi->rx_rcb_mapping);
6361 tnapi->rx_rcb = NULL;
6362 }
6363
6364 if (tnapi->hw_status) {
6365 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6366 tnapi->hw_status,
6367 tnapi->status_mapping);
6368 tnapi->hw_status = NULL;
6369 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006370 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006371
Linus Torvalds1da177e2005-04-16 15:20:36 -07006372 if (tp->hw_stats) {
6373 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6374 tp->hw_stats, tp->stats_mapping);
6375 tp->hw_stats = NULL;
6376 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006377
Matt Carlsone4af1af2010-02-12 14:47:05 +00006378 for (i = 0; i < tp->irq_cnt; i++)
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006379 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006380}
6381
6382/*
6383 * Must not be invoked with interrupt sources disabled and
6384 * the hardware shutdown down. Can sleep.
6385 */
6386static int tg3_alloc_consistent(struct tg3 *tp)
6387{
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006388 int i;
Matt Carlson898a56f2009-08-28 14:02:40 +00006389
Matt Carlsone4af1af2010-02-12 14:47:05 +00006390 for (i = 0; i < tp->irq_cnt; i++) {
Matt Carlson2b2cdb62009-11-13 13:03:48 +00006391 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6392 goto err_out;
6393 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006394
Linus Torvalds1da177e2005-04-16 15:20:36 -07006395 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6396 sizeof(struct tg3_hw_stats),
6397 &tp->stats_mapping);
6398 if (!tp->hw_stats)
6399 goto err_out;
6400
Linus Torvalds1da177e2005-04-16 15:20:36 -07006401 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6402
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006403 for (i = 0; i < tp->irq_cnt; i++) {
6404 struct tg3_napi *tnapi = &tp->napi[i];
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00006405 struct tg3_hw_status *sblk;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006406
6407 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6408 TG3_HW_STATUS_SIZE,
6409 &tnapi->status_mapping);
6410 if (!tnapi->hw_status)
6411 goto err_out;
6412
6413 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00006414 sblk = tnapi->hw_status;
6415
Matt Carlson19cfaec2009-12-03 08:36:20 +00006416 /* If multivector TSS is enabled, vector 0 does not handle
6417 * tx interrupts. Don't allocate any resources for it.
6418 */
6419 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6420 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6421 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6422 TG3_TX_RING_SIZE,
6423 GFP_KERNEL);
6424 if (!tnapi->tx_buffers)
6425 goto err_out;
6426
6427 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6428 TG3_TX_RING_BYTES,
6429 &tnapi->tx_desc_mapping);
6430 if (!tnapi->tx_ring)
6431 goto err_out;
6432 }
6433
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00006434 /*
6435 * When RSS is enabled, the status block format changes
6436 * slightly. The "rx_jumbo_consumer", "reserved",
6437 * and "rx_mini_consumer" members get mapped to the
6438 * other three rx return ring producer indexes.
6439 */
6440 switch (i) {
6441 default:
6442 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6443 break;
6444 case 2:
6445 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6446 break;
6447 case 3:
6448 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6449 break;
6450 case 4:
6451 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6452 break;
6453 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006454
Matt Carlsone4af1af2010-02-12 14:47:05 +00006455 tnapi->prodring = &tp->prodring[i];
Matt Carlsonb196c7e2009-11-13 13:03:50 +00006456
Matt Carlson0c1d0e22009-09-01 13:16:33 +00006457 /*
6458 * If multivector RSS is enabled, vector 0 does not handle
6459 * rx or tx interrupts. Don't allocate any resources for it.
6460 */
6461 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6462 continue;
6463
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006464 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6465 TG3_RX_RCB_RING_BYTES(tp),
6466 &tnapi->rx_rcb_mapping);
6467 if (!tnapi->rx_rcb)
6468 goto err_out;
6469
6470 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006471 }
6472
Linus Torvalds1da177e2005-04-16 15:20:36 -07006473 return 0;
6474
6475err_out:
6476 tg3_free_consistent(tp);
6477 return -ENOMEM;
6478}
6479
6480#define MAX_WAIT_CNT 1000
6481
6482/* To stop a block, clear the enable bit and poll till it
6483 * clears. tp->lock is held.
6484 */
David S. Millerb3b7d6b2005-05-05 14:40:20 -07006485static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006486{
6487 unsigned int i;
6488 u32 val;
6489
6490 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6491 switch (ofs) {
6492 case RCVLSC_MODE:
6493 case DMAC_MODE:
6494 case MBFREE_MODE:
6495 case BUFMGR_MODE:
6496 case MEMARB_MODE:
6497 /* We can't enable/disable these bits of the
6498 * 5705/5750, just say success.
6499 */
6500 return 0;
6501
6502 default:
6503 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07006504 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006505 }
6506
6507 val = tr32(ofs);
6508 val &= ~enable_bit;
6509 tw32_f(ofs, val);
6510
6511 for (i = 0; i < MAX_WAIT_CNT; i++) {
6512 udelay(100);
6513 val = tr32(ofs);
6514 if ((val & enable_bit) == 0)
6515 break;
6516 }
6517
David S. Millerb3b7d6b2005-05-05 14:40:20 -07006518 if (i == MAX_WAIT_CNT && !silent) {
Matt Carlson2445e462010-04-05 10:19:21 +00006519 dev_err(&tp->pdev->dev,
6520 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6521 ofs, enable_bit);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006522 return -ENODEV;
6523 }
6524
6525 return 0;
6526}
6527
6528/* tp->lock is held. */
David S. Millerb3b7d6b2005-05-05 14:40:20 -07006529static int tg3_abort_hw(struct tg3 *tp, int silent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006530{
6531 int i, err;
6532
6533 tg3_disable_ints(tp);
6534
6535 tp->rx_mode &= ~RX_MODE_ENABLE;
6536 tw32_f(MAC_RX_MODE, tp->rx_mode);
6537 udelay(10);
6538
David S. Millerb3b7d6b2005-05-05 14:40:20 -07006539 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6540 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6541 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6542 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6543 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6544 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006545
David S. Millerb3b7d6b2005-05-05 14:40:20 -07006546 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6547 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6548 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6549 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6550 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6551 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6552 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006553
6554 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6555 tw32_f(MAC_MODE, tp->mac_mode);
6556 udelay(40);
6557
6558 tp->tx_mode &= ~TX_MODE_ENABLE;
6559 tw32_f(MAC_TX_MODE, tp->tx_mode);
6560
6561 for (i = 0; i < MAX_WAIT_CNT; i++) {
6562 udelay(100);
6563 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6564 break;
6565 }
6566 if (i >= MAX_WAIT_CNT) {
Matt Carlsonab96b242010-04-05 10:19:22 +00006567 dev_err(&tp->pdev->dev,
6568 "%s timed out, TX_MODE_ENABLE will not clear "
6569 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
Michael Chane6de8ad2005-05-05 14:42:41 -07006570 err |= -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006571 }
6572
Michael Chane6de8ad2005-05-05 14:42:41 -07006573 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
David S. Millerb3b7d6b2005-05-05 14:40:20 -07006574 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6575 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006576
6577 tw32(FTQ_RESET, 0xffffffff);
6578 tw32(FTQ_RESET, 0x00000000);
6579
David S. Millerb3b7d6b2005-05-05 14:40:20 -07006580 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6581 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006582
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006583 for (i = 0; i < tp->irq_cnt; i++) {
6584 struct tg3_napi *tnapi = &tp->napi[i];
6585 if (tnapi->hw_status)
6586 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6587 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006588 if (tp->hw_stats)
6589 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6590
Linus Torvalds1da177e2005-04-16 15:20:36 -07006591 return err;
6592}
6593
Matt Carlson0d3031d2007-10-10 18:02:43 -07006594static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6595{
6596 int i;
6597 u32 apedata;
6598
6599 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6600 if (apedata != APE_SEG_SIG_MAGIC)
6601 return;
6602
6603 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
Matt Carlson731fd792008-08-15 14:07:51 -07006604 if (!(apedata & APE_FW_STATUS_READY))
Matt Carlson0d3031d2007-10-10 18:02:43 -07006605 return;
6606
6607 /* Wait for up to 1 millisecond for APE to service previous event. */
6608 for (i = 0; i < 10; i++) {
6609 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6610 return;
6611
6612 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6613
6614 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6615 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6616 event | APE_EVENT_STATUS_EVENT_PENDING);
6617
6618 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6619
6620 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6621 break;
6622
6623 udelay(100);
6624 }
6625
6626 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6627 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6628}
6629
6630static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6631{
6632 u32 event;
6633 u32 apedata;
6634
6635 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6636 return;
6637
6638 switch (kind) {
Matt Carlson33f401a2010-04-05 10:19:27 +00006639 case RESET_KIND_INIT:
6640 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6641 APE_HOST_SEG_SIG_MAGIC);
6642 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6643 APE_HOST_SEG_LEN_MAGIC);
6644 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6645 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6646 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
Matt Carlson6867c842010-07-11 09:31:44 +00006647 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
Matt Carlson33f401a2010-04-05 10:19:27 +00006648 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6649 APE_HOST_BEHAV_NO_PHYLOCK);
Matt Carlson0d3031d2007-10-10 18:02:43 -07006650
Matt Carlson33f401a2010-04-05 10:19:27 +00006651 event = APE_EVENT_STATUS_STATE_START;
6652 break;
6653 case RESET_KIND_SHUTDOWN:
6654 /* With the interface we are currently using,
6655 * APE does not track driver state. Wiping
6656 * out the HOST SEGMENT SIGNATURE forces
6657 * the APE to assume OS absent status.
6658 */
6659 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
Matt Carlsonb2aee152008-11-03 16:51:11 -08006660
Matt Carlson33f401a2010-04-05 10:19:27 +00006661 event = APE_EVENT_STATUS_STATE_UNLOAD;
6662 break;
6663 case RESET_KIND_SUSPEND:
6664 event = APE_EVENT_STATUS_STATE_SUSPEND;
6665 break;
6666 default:
6667 return;
Matt Carlson0d3031d2007-10-10 18:02:43 -07006668 }
6669
6670 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6671
6672 tg3_ape_send_event(tp, event);
6673}
6674
Michael Chane6af3012005-04-21 17:12:05 -07006675/* tp->lock is held. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07006676static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6677{
David S. Millerf49639e2006-06-09 11:58:36 -07006678 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6679 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006680
6681 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6682 switch (kind) {
6683 case RESET_KIND_INIT:
6684 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6685 DRV_STATE_START);
6686 break;
6687
6688 case RESET_KIND_SHUTDOWN:
6689 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6690 DRV_STATE_UNLOAD);
6691 break;
6692
6693 case RESET_KIND_SUSPEND:
6694 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6695 DRV_STATE_SUSPEND);
6696 break;
6697
6698 default:
6699 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07006700 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006701 }
Matt Carlson0d3031d2007-10-10 18:02:43 -07006702
6703 if (kind == RESET_KIND_INIT ||
6704 kind == RESET_KIND_SUSPEND)
6705 tg3_ape_driver_state_change(tp, kind);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006706}
6707
6708/* tp->lock is held. */
6709static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6710{
6711 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6712 switch (kind) {
6713 case RESET_KIND_INIT:
6714 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6715 DRV_STATE_START_DONE);
6716 break;
6717
6718 case RESET_KIND_SHUTDOWN:
6719 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6720 DRV_STATE_UNLOAD_DONE);
6721 break;
6722
6723 default:
6724 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07006725 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006726 }
Matt Carlson0d3031d2007-10-10 18:02:43 -07006727
6728 if (kind == RESET_KIND_SHUTDOWN)
6729 tg3_ape_driver_state_change(tp, kind);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006730}
6731
6732/* tp->lock is held. */
6733static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6734{
6735 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6736 switch (kind) {
6737 case RESET_KIND_INIT:
6738 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6739 DRV_STATE_START);
6740 break;
6741
6742 case RESET_KIND_SHUTDOWN:
6743 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6744 DRV_STATE_UNLOAD);
6745 break;
6746
6747 case RESET_KIND_SUSPEND:
6748 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6749 DRV_STATE_SUSPEND);
6750 break;
6751
6752 default:
6753 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07006754 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006755 }
6756}
6757
Michael Chan7a6f4362006-09-27 16:03:31 -07006758static int tg3_poll_fw(struct tg3 *tp)
6759{
6760 int i;
6761 u32 val;
6762
Michael Chanb5d37722006-09-27 16:06:21 -07006763 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Gary Zambrano0ccead12006-11-14 16:34:00 -08006764 /* Wait up to 20ms for init done. */
6765 for (i = 0; i < 200; i++) {
Michael Chanb5d37722006-09-27 16:06:21 -07006766 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6767 return 0;
Gary Zambrano0ccead12006-11-14 16:34:00 -08006768 udelay(100);
Michael Chanb5d37722006-09-27 16:06:21 -07006769 }
6770 return -ENODEV;
6771 }
6772
Michael Chan7a6f4362006-09-27 16:03:31 -07006773 /* Wait for firmware initialization to complete. */
6774 for (i = 0; i < 100000; i++) {
6775 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6776 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6777 break;
6778 udelay(10);
6779 }
6780
6781 /* Chip might not be fitted with firmware. Some Sun onboard
6782 * parts are configured like that. So don't signal the timeout
6783 * of the above loop as an error, but do report the lack of
6784 * running firmware once.
6785 */
6786 if (i >= 100000 &&
6787 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6788 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6789
Joe Perches05dbe002010-02-17 19:44:19 +00006790 netdev_info(tp->dev, "No firmware running\n");
Michael Chan7a6f4362006-09-27 16:03:31 -07006791 }
6792
Matt Carlson6b10c162010-02-12 14:47:08 +00006793 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6794 /* The 57765 A0 needs a little more
6795 * time to do some important work.
6796 */
6797 mdelay(10);
6798 }
6799
Michael Chan7a6f4362006-09-27 16:03:31 -07006800 return 0;
6801}
6802
Michael Chanee6a99b2007-07-18 21:49:10 -07006803/* Save PCI command register before chip reset */
6804static void tg3_save_pci_state(struct tg3 *tp)
6805{
Matt Carlson8a6eac92007-10-21 16:17:55 -07006806 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
Michael Chanee6a99b2007-07-18 21:49:10 -07006807}
6808
6809/* Restore PCI state after chip reset */
6810static void tg3_restore_pci_state(struct tg3 *tp)
6811{
6812 u32 val;
6813
6814 /* Re-enable indirect register accesses. */
6815 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6816 tp->misc_host_ctrl);
6817
6818 /* Set MAX PCI retry to zero. */
6819 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6820 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6821 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6822 val |= PCISTATE_RETRY_SAME_DMA;
Matt Carlson0d3031d2007-10-10 18:02:43 -07006823 /* Allow reads and writes to the APE register and memory space. */
6824 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6825 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
Matt Carlsonf92d9dc12010-06-05 17:24:30 +00006826 PCISTATE_ALLOW_APE_SHMEM_WR |
6827 PCISTATE_ALLOW_APE_PSPACE_WR;
Michael Chanee6a99b2007-07-18 21:49:10 -07006828 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6829
Matt Carlson8a6eac92007-10-21 16:17:55 -07006830 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
Michael Chanee6a99b2007-07-18 21:49:10 -07006831
Matt Carlsonfcb389d2008-11-03 16:55:44 -08006832 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6833 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6834 pcie_set_readrq(tp->pdev, 4096);
6835 else {
6836 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6837 tp->pci_cacheline_sz);
6838 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6839 tp->pci_lat_timer);
6840 }
Michael Chan114342f2007-10-15 02:12:26 -07006841 }
Matt Carlson5f5c51e2007-11-12 21:19:37 -08006842
Michael Chanee6a99b2007-07-18 21:49:10 -07006843 /* Make sure PCI-X relaxed ordering bit is clear. */
Matt Carlson52f44902008-11-21 17:17:04 -08006844 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
Matt Carlson9974a352007-10-07 23:27:28 -07006845 u16 pcix_cmd;
6846
6847 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6848 &pcix_cmd);
6849 pcix_cmd &= ~PCI_X_CMD_ERO;
6850 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6851 pcix_cmd);
6852 }
Michael Chanee6a99b2007-07-18 21:49:10 -07006853
6854 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
Michael Chanee6a99b2007-07-18 21:49:10 -07006855
6856 /* Chip reset on 5780 will reset MSI enable bit,
6857 * so need to restore it.
6858 */
6859 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6860 u16 ctrl;
6861
6862 pci_read_config_word(tp->pdev,
6863 tp->msi_cap + PCI_MSI_FLAGS,
6864 &ctrl);
6865 pci_write_config_word(tp->pdev,
6866 tp->msi_cap + PCI_MSI_FLAGS,
6867 ctrl | PCI_MSI_FLAGS_ENABLE);
6868 val = tr32(MSGINT_MODE);
6869 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6870 }
6871 }
6872}
6873
Linus Torvalds1da177e2005-04-16 15:20:36 -07006874static void tg3_stop_fw(struct tg3 *);
6875
6876/* tp->lock is held. */
6877static int tg3_chip_reset(struct tg3 *tp)
6878{
6879 u32 val;
Michael Chan1ee582d2005-08-09 20:16:46 -07006880 void (*write_op)(struct tg3 *, u32, u32);
Matt Carlson4f125f42009-09-01 12:55:02 +00006881 int i, err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006882
David S. Millerf49639e2006-06-09 11:58:36 -07006883 tg3_nvram_lock(tp);
6884
Matt Carlson77b483f2008-08-15 14:07:24 -07006885 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6886
David S. Millerf49639e2006-06-09 11:58:36 -07006887 /* No matching tg3_nvram_unlock() after this because
6888 * chip reset below will undo the nvram lock.
6889 */
6890 tp->nvram_lock_cnt = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006891
Michael Chanee6a99b2007-07-18 21:49:10 -07006892 /* GRC_MISC_CFG core clock reset will clear the memory
6893 * enable bit in PCI register 4 and the MSI enable bit
6894 * on some chips, so we save relevant registers here.
6895 */
6896 tg3_save_pci_state(tp);
6897
Michael Chand9ab5ad2006-03-20 22:27:35 -08006898 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
Matt Carlson321d32a2008-11-21 17:22:19 -08006899 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
Michael Chand9ab5ad2006-03-20 22:27:35 -08006900 tw32(GRC_FASTBOOT_PC, 0);
6901
Linus Torvalds1da177e2005-04-16 15:20:36 -07006902 /*
6903 * We must avoid the readl() that normally takes place.
6904 * It locks machines, causes machine checks, and other
6905 * fun things. So, temporarily disable the 5701
6906 * hardware workaround, while we do the reset.
6907 */
Michael Chan1ee582d2005-08-09 20:16:46 -07006908 write_op = tp->write32;
6909 if (write_op == tg3_write_flush_reg32)
6910 tp->write32 = tg3_write32;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006911
Michael Chand18edcb2007-03-24 20:57:11 -07006912 /* Prevent the irq handler from reading or writing PCI registers
6913 * during chip reset when the memory enable bit in the PCI command
6914 * register may be cleared. The chip does not generate interrupt
6915 * at this time, but the irq handler may still be called due to irq
6916 * sharing or irqpoll.
6917 */
6918 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00006919 for (i = 0; i < tp->irq_cnt; i++) {
6920 struct tg3_napi *tnapi = &tp->napi[i];
6921 if (tnapi->hw_status) {
6922 tnapi->hw_status->status = 0;
6923 tnapi->hw_status->status_tag = 0;
6924 }
6925 tnapi->last_tag = 0;
6926 tnapi->last_irq_tag = 0;
Michael Chanb8fa2f32007-04-06 17:35:37 -07006927 }
Michael Chand18edcb2007-03-24 20:57:11 -07006928 smp_mb();
Matt Carlson4f125f42009-09-01 12:55:02 +00006929
6930 for (i = 0; i < tp->irq_cnt; i++)
6931 synchronize_irq(tp->napi[i].irq_vec);
Michael Chand18edcb2007-03-24 20:57:11 -07006932
Matt Carlson255ca312009-08-25 10:07:27 +00006933 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6934 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6935 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6936 }
6937
Linus Torvalds1da177e2005-04-16 15:20:36 -07006938 /* do the reset */
6939 val = GRC_MISC_CFG_CORECLK_RESET;
6940
6941 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
Matt Carlson88075d92010-08-02 11:25:58 +00006942 /* Force PCIe 1.0a mode */
6943 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6944 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
6945 tr32(TG3_PCIE_PHY_TSTCTL) ==
6946 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
6947 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
6948
Linus Torvalds1da177e2005-04-16 15:20:36 -07006949 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6950 tw32(GRC_MISC_CFG, (1 << 29));
6951 val |= (1 << 29);
6952 }
6953 }
6954
Michael Chanb5d37722006-09-27 16:06:21 -07006955 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6956 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6957 tw32(GRC_VCPU_EXT_CTRL,
6958 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6959 }
6960
Matt Carlsonf37500d2010-08-02 11:25:59 +00006961 /* Manage gphy power for all CPMU absent PCIe devices. */
6962 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6963 !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
Linus Torvalds1da177e2005-04-16 15:20:36 -07006964 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
Matt Carlsonf37500d2010-08-02 11:25:59 +00006965
Linus Torvalds1da177e2005-04-16 15:20:36 -07006966 tw32(GRC_MISC_CFG, val);
6967
Michael Chan1ee582d2005-08-09 20:16:46 -07006968 /* restore 5701 hardware bug workaround write method */
6969 tp->write32 = write_op;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006970
6971 /* Unfortunately, we have to delay before the PCI read back.
6972 * Some 575X chips even will not respond to a PCI cfg access
6973 * when the reset command is given to the chip.
6974 *
6975 * How do these hardware designers expect things to work
6976 * properly if the PCI write is posted for a long period
6977 * of time? It is always necessary to have some method by
6978 * which a register read back can occur to push the write
6979 * out which does the reset.
6980 *
6981 * For most tg3 variants the trick below was working.
6982 * Ho hum...
6983 */
6984 udelay(120);
6985
6986 /* Flush PCI posted writes. The normal MMIO registers
6987 * are inaccessible at this time so this is the only
6988 * way to make this reliably (actually, this is no longer
6989 * the case, see above). I tried to use indirect
6990 * register read/write but this upset some 5701 variants.
6991 */
6992 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6993
6994 udelay(120);
6995
Matt Carlson5e7dfd02008-11-21 17:18:16 -08006996 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
Matt Carlsone7126992009-08-25 10:08:16 +00006997 u16 val16;
6998
Linus Torvalds1da177e2005-04-16 15:20:36 -07006999 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7000 int i;
7001 u32 cfg_val;
7002
7003 /* Wait for link training to complete. */
7004 for (i = 0; i < 5000; i++)
7005 udelay(100);
7006
7007 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7008 pci_write_config_dword(tp->pdev, 0xc4,
7009 cfg_val | (1 << 15));
7010 }
Matt Carlson5e7dfd02008-11-21 17:18:16 -08007011
Matt Carlsone7126992009-08-25 10:08:16 +00007012 /* Clear the "no snoop" and "relaxed ordering" bits. */
7013 pci_read_config_word(tp->pdev,
7014 tp->pcie_cap + PCI_EXP_DEVCTL,
7015 &val16);
7016 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7017 PCI_EXP_DEVCTL_NOSNOOP_EN);
7018 /*
7019 * Older PCIe devices only support the 128 byte
7020 * MPS setting. Enforce the restriction.
Matt Carlson5e7dfd02008-11-21 17:18:16 -08007021 */
Matt Carlson6de34cb2010-08-02 11:25:55 +00007022 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
Matt Carlsone7126992009-08-25 10:08:16 +00007023 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
Matt Carlson5e7dfd02008-11-21 17:18:16 -08007024 pci_write_config_word(tp->pdev,
7025 tp->pcie_cap + PCI_EXP_DEVCTL,
Matt Carlsone7126992009-08-25 10:08:16 +00007026 val16);
Matt Carlson5e7dfd02008-11-21 17:18:16 -08007027
7028 pcie_set_readrq(tp->pdev, 4096);
7029
7030 /* Clear error status */
7031 pci_write_config_word(tp->pdev,
7032 tp->pcie_cap + PCI_EXP_DEVSTA,
7033 PCI_EXP_DEVSTA_CED |
7034 PCI_EXP_DEVSTA_NFED |
7035 PCI_EXP_DEVSTA_FED |
7036 PCI_EXP_DEVSTA_URD);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007037 }
7038
Michael Chanee6a99b2007-07-18 21:49:10 -07007039 tg3_restore_pci_state(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007040
Michael Chand18edcb2007-03-24 20:57:11 -07007041 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7042
Michael Chanee6a99b2007-07-18 21:49:10 -07007043 val = 0;
7044 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
Michael Chan4cf78e42005-07-25 12:29:19 -07007045 val = tr32(MEMARB_MODE);
Michael Chanee6a99b2007-07-18 21:49:10 -07007046 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007047
7048 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7049 tg3_stop_fw(tp);
7050 tw32(0x5000, 0x400);
7051 }
7052
7053 tw32(GRC_MODE, tp->grc_mode);
7054
7055 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
Andy Gospodarekab0049b2007-09-06 20:42:14 +01007056 val = tr32(0xc4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007057
7058 tw32(0xc4, val | (1 << 15));
7059 }
7060
7061 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7062 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7063 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7064 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7065 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7066 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7067 }
7068
Matt Carlsonf07e9af2010-08-02 11:26:07 +00007069 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07007070 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7071 tw32_f(MAC_MODE, tp->mac_mode);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00007072 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
Michael Chan747e8f82005-07-25 12:33:22 -07007073 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7074 tw32_f(MAC_MODE, tp->mac_mode);
Matt Carlson3bda1252008-08-15 14:08:22 -07007075 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7076 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7077 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7078 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7079 tw32_f(MAC_MODE, tp->mac_mode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007080 } else
7081 tw32_f(MAC_MODE, 0);
7082 udelay(40);
7083
Matt Carlson77b483f2008-08-15 14:07:24 -07007084 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7085
Michael Chan7a6f4362006-09-27 16:03:31 -07007086 err = tg3_poll_fw(tp);
7087 if (err)
7088 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007089
Matt Carlson0a9140c2009-08-28 12:27:50 +00007090 tg3_mdio_start(tp);
7091
Linus Torvalds1da177e2005-04-16 15:20:36 -07007092 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00007093 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7094 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
Matt Carlsonc885e822010-08-02 11:25:57 +00007095 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
Andy Gospodarekab0049b2007-09-06 20:42:14 +01007096 val = tr32(0x7c00);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007097
7098 tw32(0x7c00, val | (1 << 25));
7099 }
7100
7101 /* Reprobe ASF enable state. */
7102 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7103 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7104 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7105 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7106 u32 nic_cfg;
7107
7108 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7109 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7110 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
Matt Carlson4ba526c2008-08-15 14:10:04 -07007111 tp->last_event_jiffies = jiffies;
John W. Linvillecbf46852005-04-21 17:01:29 -07007112 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007113 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7114 }
7115 }
7116
7117 return 0;
7118}
7119
7120/* tp->lock is held. */
7121static void tg3_stop_fw(struct tg3 *tp)
7122{
Matt Carlson0d3031d2007-10-10 18:02:43 -07007123 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7124 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
Matt Carlson7c5026a2008-05-02 16:49:29 -07007125 /* Wait for RX cpu to ACK the previous event. */
7126 tg3_wait_for_event_ack(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007127
7128 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
Matt Carlson4ba526c2008-08-15 14:10:04 -07007129
7130 tg3_generate_fw_event(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007131
Matt Carlson7c5026a2008-05-02 16:49:29 -07007132 /* Wait for RX cpu to ACK this event. */
7133 tg3_wait_for_event_ack(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007134 }
7135}
7136
7137/* tp->lock is held. */
Michael Chan944d9802005-05-29 14:57:48 -07007138static int tg3_halt(struct tg3 *tp, int kind, int silent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007139{
7140 int err;
7141
7142 tg3_stop_fw(tp);
7143
Michael Chan944d9802005-05-29 14:57:48 -07007144 tg3_write_sig_pre_reset(tp, kind);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007145
David S. Millerb3b7d6b2005-05-05 14:40:20 -07007146 tg3_abort_hw(tp, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007147 err = tg3_chip_reset(tp);
7148
Matt Carlsondaba2a62009-04-20 06:58:52 +00007149 __tg3_set_mac_addr(tp, 0);
7150
Michael Chan944d9802005-05-29 14:57:48 -07007151 tg3_write_sig_legacy(tp, kind);
7152 tg3_write_sig_post_reset(tp, kind);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007153
7154 if (err)
7155 return err;
7156
7157 return 0;
7158}
7159
Linus Torvalds1da177e2005-04-16 15:20:36 -07007160#define RX_CPU_SCRATCH_BASE 0x30000
7161#define RX_CPU_SCRATCH_SIZE 0x04000
7162#define TX_CPU_SCRATCH_BASE 0x34000
7163#define TX_CPU_SCRATCH_SIZE 0x04000
7164
7165/* tp->lock is held. */
7166static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7167{
7168 int i;
7169
Eric Sesterhenn5d9428d2006-04-02 13:52:48 +02007170 BUG_ON(offset == TX_CPU_BASE &&
7171 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
Linus Torvalds1da177e2005-04-16 15:20:36 -07007172
Michael Chanb5d37722006-09-27 16:06:21 -07007173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7174 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7175
7176 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7177 return 0;
7178 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007179 if (offset == RX_CPU_BASE) {
7180 for (i = 0; i < 10000; i++) {
7181 tw32(offset + CPU_STATE, 0xffffffff);
7182 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7183 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7184 break;
7185 }
7186
7187 tw32(offset + CPU_STATE, 0xffffffff);
7188 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7189 udelay(10);
7190 } else {
7191 for (i = 0; i < 10000; i++) {
7192 tw32(offset + CPU_STATE, 0xffffffff);
7193 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7194 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7195 break;
7196 }
7197 }
7198
7199 if (i >= 10000) {
Joe Perches05dbe002010-02-17 19:44:19 +00007200 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7201 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
Linus Torvalds1da177e2005-04-16 15:20:36 -07007202 return -ENODEV;
7203 }
Michael Chanec41c7d2006-01-17 02:40:55 -08007204
7205 /* Clear firmware's nvram arbitration. */
7206 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7207 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007208 return 0;
7209}
7210
7211struct fw_info {
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007212 unsigned int fw_base;
7213 unsigned int fw_len;
7214 const __be32 *fw_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007215};
7216
7217/* tp->lock is held. */
7218static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7219 int cpu_scratch_size, struct fw_info *info)
7220{
Michael Chanec41c7d2006-01-17 02:40:55 -08007221 int err, lock_err, i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007222 void (*write_op)(struct tg3 *, u32, u32);
7223
7224 if (cpu_base == TX_CPU_BASE &&
7225 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
Matt Carlson5129c3a2010-04-05 10:19:23 +00007226 netdev_err(tp->dev,
7227 "%s: Trying to load TX cpu firmware which is 5705\n",
Joe Perches05dbe002010-02-17 19:44:19 +00007228 __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007229 return -EINVAL;
7230 }
7231
7232 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7233 write_op = tg3_write_mem;
7234 else
7235 write_op = tg3_write_indirect_reg32;
7236
Michael Chan1b628152005-05-29 14:59:49 -07007237 /* It is possible that bootcode is still loading at this point.
7238 * Get the nvram lock first before halting the cpu.
7239 */
Michael Chanec41c7d2006-01-17 02:40:55 -08007240 lock_err = tg3_nvram_lock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007241 err = tg3_halt_cpu(tp, cpu_base);
Michael Chanec41c7d2006-01-17 02:40:55 -08007242 if (!lock_err)
7243 tg3_nvram_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007244 if (err)
7245 goto out;
7246
7247 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7248 write_op(tp, cpu_scratch_base + i, 0);
7249 tw32(cpu_base + CPU_STATE, 0xffffffff);
7250 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007251 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007252 write_op(tp, (cpu_scratch_base +
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007253 (info->fw_base & 0xffff) +
Linus Torvalds1da177e2005-04-16 15:20:36 -07007254 (i * sizeof(u32))),
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007255 be32_to_cpu(info->fw_data[i]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07007256
7257 err = 0;
7258
7259out:
Linus Torvalds1da177e2005-04-16 15:20:36 -07007260 return err;
7261}
7262
7263/* tp->lock is held. */
7264static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7265{
7266 struct fw_info info;
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007267 const __be32 *fw_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007268 int err, i;
7269
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007270 fw_data = (void *)tp->fw->data;
7271
7272 /* Firmware blob starts with version numbers, followed by
7273 start address and length. We are setting complete length.
7274 length = end_address_of_bss - start_address_of_text.
7275 Remainder is the blob to be loaded contiguously
7276 from start address. */
7277
7278 info.fw_base = be32_to_cpu(fw_data[1]);
7279 info.fw_len = tp->fw->size - 12;
7280 info.fw_data = &fw_data[3];
Linus Torvalds1da177e2005-04-16 15:20:36 -07007281
7282 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7283 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7284 &info);
7285 if (err)
7286 return err;
7287
7288 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7289 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7290 &info);
7291 if (err)
7292 return err;
7293
7294 /* Now startup only the RX cpu. */
7295 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007296 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007297
7298 for (i = 0; i < 5; i++) {
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007299 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007300 break;
7301 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7302 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007303 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007304 udelay(1000);
7305 }
7306 if (i >= 5) {
Matt Carlson5129c3a2010-04-05 10:19:23 +00007307 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7308 "should be %08x\n", __func__,
Joe Perches05dbe002010-02-17 19:44:19 +00007309 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007310 return -ENODEV;
7311 }
7312 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7313 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7314
7315 return 0;
7316}
7317
Linus Torvalds1da177e2005-04-16 15:20:36 -07007318/* 5705 needs a special version of the TSO firmware. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07007319
7320/* tp->lock is held. */
7321static int tg3_load_tso_firmware(struct tg3 *tp)
7322{
7323 struct fw_info info;
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007324 const __be32 *fw_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007325 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7326 int err, i;
7327
7328 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7329 return 0;
7330
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007331 fw_data = (void *)tp->fw->data;
7332
7333 /* Firmware blob starts with version numbers, followed by
7334 start address and length. We are setting complete length.
7335 length = end_address_of_bss - start_address_of_text.
7336 Remainder is the blob to be loaded contiguously
7337 from start address. */
7338
7339 info.fw_base = be32_to_cpu(fw_data[1]);
7340 cpu_scratch_size = tp->fw_len;
7341 info.fw_len = tp->fw->size - 12;
7342 info.fw_data = &fw_data[3];
7343
Linus Torvalds1da177e2005-04-16 15:20:36 -07007344 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07007345 cpu_base = RX_CPU_BASE;
7346 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007347 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07007348 cpu_base = TX_CPU_BASE;
7349 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7350 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7351 }
7352
7353 err = tg3_load_firmware_cpu(tp, cpu_base,
7354 cpu_scratch_base, cpu_scratch_size,
7355 &info);
7356 if (err)
7357 return err;
7358
7359 /* Now startup the cpu. */
7360 tw32(cpu_base + CPU_STATE, 0xffffffff);
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007361 tw32_f(cpu_base + CPU_PC, info.fw_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007362
7363 for (i = 0; i < 5; i++) {
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007364 if (tr32(cpu_base + CPU_PC) == info.fw_base)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007365 break;
7366 tw32(cpu_base + CPU_STATE, 0xffffffff);
7367 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007368 tw32_f(cpu_base + CPU_PC, info.fw_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007369 udelay(1000);
7370 }
7371 if (i >= 5) {
Matt Carlson5129c3a2010-04-05 10:19:23 +00007372 netdev_err(tp->dev,
7373 "%s fails to set CPU PC, is %08x should be %08x\n",
Joe Perches05dbe002010-02-17 19:44:19 +00007374 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007375 return -ENODEV;
7376 }
7377 tw32(cpu_base + CPU_STATE, 0xffffffff);
7378 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7379 return 0;
7380}
7381
Linus Torvalds1da177e2005-04-16 15:20:36 -07007382
Linus Torvalds1da177e2005-04-16 15:20:36 -07007383static int tg3_set_mac_addr(struct net_device *dev, void *p)
7384{
7385 struct tg3 *tp = netdev_priv(dev);
7386 struct sockaddr *addr = p;
Michael Chan986e0ae2007-05-05 12:10:20 -07007387 int err = 0, skip_mac_1 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007388
Michael Chanf9804dd2005-09-27 12:13:10 -07007389 if (!is_valid_ether_addr(addr->sa_data))
7390 return -EINVAL;
7391
Linus Torvalds1da177e2005-04-16 15:20:36 -07007392 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7393
Michael Chane75f7c92006-03-20 21:33:26 -08007394 if (!netif_running(dev))
7395 return 0;
7396
Michael Chan58712ef2006-04-29 18:58:01 -07007397 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
Michael Chan986e0ae2007-05-05 12:10:20 -07007398 u32 addr0_high, addr0_low, addr1_high, addr1_low;
Michael Chan58712ef2006-04-29 18:58:01 -07007399
Michael Chan986e0ae2007-05-05 12:10:20 -07007400 addr0_high = tr32(MAC_ADDR_0_HIGH);
7401 addr0_low = tr32(MAC_ADDR_0_LOW);
7402 addr1_high = tr32(MAC_ADDR_1_HIGH);
7403 addr1_low = tr32(MAC_ADDR_1_LOW);
7404
7405 /* Skip MAC addr 1 if ASF is using it. */
7406 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7407 !(addr1_high == 0 && addr1_low == 0))
7408 skip_mac_1 = 1;
Michael Chan58712ef2006-04-29 18:58:01 -07007409 }
Michael Chan986e0ae2007-05-05 12:10:20 -07007410 spin_lock_bh(&tp->lock);
7411 __tg3_set_mac_addr(tp, skip_mac_1);
7412 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007413
Michael Chanb9ec6c12006-07-25 16:37:27 -07007414 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007415}
7416
7417/* tp->lock is held. */
7418static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7419 dma_addr_t mapping, u32 maxlen_flags,
7420 u32 nic_addr)
7421{
7422 tg3_write_mem(tp,
7423 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7424 ((u64) mapping >> 32));
7425 tg3_write_mem(tp,
7426 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7427 ((u64) mapping & 0xffffffff));
7428 tg3_write_mem(tp,
7429 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7430 maxlen_flags);
7431
7432 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7433 tg3_write_mem(tp,
7434 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7435 nic_addr);
7436}
7437
7438static void __tg3_set_rx_mode(struct net_device *);
Michael Chand244c892005-07-05 14:42:33 -07007439static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
David S. Miller15f98502005-05-18 22:49:26 -07007440{
Matt Carlsonb6080e12009-09-01 13:12:00 +00007441 int i;
7442
Matt Carlson19cfaec2009-12-03 08:36:20 +00007443 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
Matt Carlsonb6080e12009-09-01 13:12:00 +00007444 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7445 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7446 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
Matt Carlsonb6080e12009-09-01 13:12:00 +00007447 } else {
7448 tw32(HOSTCC_TXCOL_TICKS, 0);
7449 tw32(HOSTCC_TXMAX_FRAMES, 0);
7450 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
Matt Carlson19cfaec2009-12-03 08:36:20 +00007451 }
Matt Carlsonb6080e12009-09-01 13:12:00 +00007452
Matt Carlson20d73752010-07-11 09:31:41 +00007453 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
Matt Carlson19cfaec2009-12-03 08:36:20 +00007454 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7455 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7456 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7457 } else {
Matt Carlsonb6080e12009-09-01 13:12:00 +00007458 tw32(HOSTCC_RXCOL_TICKS, 0);
7459 tw32(HOSTCC_RXMAX_FRAMES, 0);
7460 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
David S. Miller15f98502005-05-18 22:49:26 -07007461 }
Matt Carlsonb6080e12009-09-01 13:12:00 +00007462
David S. Miller15f98502005-05-18 22:49:26 -07007463 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7464 u32 val = ec->stats_block_coalesce_usecs;
7465
Matt Carlsonb6080e12009-09-01 13:12:00 +00007466 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7467 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7468
David S. Miller15f98502005-05-18 22:49:26 -07007469 if (!netif_carrier_ok(tp->dev))
7470 val = 0;
7471
7472 tw32(HOSTCC_STAT_COAL_TICKS, val);
7473 }
Matt Carlsonb6080e12009-09-01 13:12:00 +00007474
7475 for (i = 0; i < tp->irq_cnt - 1; i++) {
7476 u32 reg;
7477
7478 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7479 tw32(reg, ec->rx_coalesce_usecs);
Matt Carlsonb6080e12009-09-01 13:12:00 +00007480 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7481 tw32(reg, ec->rx_max_coalesced_frames);
Matt Carlsonb6080e12009-09-01 13:12:00 +00007482 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7483 tw32(reg, ec->rx_max_coalesced_frames_irq);
Matt Carlson19cfaec2009-12-03 08:36:20 +00007484
7485 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7486 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7487 tw32(reg, ec->tx_coalesce_usecs);
7488 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7489 tw32(reg, ec->tx_max_coalesced_frames);
7490 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7491 tw32(reg, ec->tx_max_coalesced_frames_irq);
7492 }
Matt Carlsonb6080e12009-09-01 13:12:00 +00007493 }
7494
7495 for (; i < tp->irq_max - 1; i++) {
7496 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
Matt Carlsonb6080e12009-09-01 13:12:00 +00007497 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
Matt Carlsonb6080e12009-09-01 13:12:00 +00007498 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
Matt Carlson19cfaec2009-12-03 08:36:20 +00007499
7500 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7501 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7502 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7503 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7504 }
Matt Carlsonb6080e12009-09-01 13:12:00 +00007505 }
David S. Miller15f98502005-05-18 22:49:26 -07007506}
Linus Torvalds1da177e2005-04-16 15:20:36 -07007507
7508/* tp->lock is held. */
Matt Carlson2d31eca2009-09-01 12:53:31 +00007509static void tg3_rings_reset(struct tg3 *tp)
7510{
7511 int i;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007512 u32 stblk, txrcb, rxrcb, limit;
Matt Carlson2d31eca2009-09-01 12:53:31 +00007513 struct tg3_napi *tnapi = &tp->napi[0];
7514
7515 /* Disable all transmit rings but the first. */
7516 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7517 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
Matt Carlsonb703df62009-12-03 08:36:21 +00007518 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7519 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
Matt Carlson2d31eca2009-09-01 12:53:31 +00007520 else
7521 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7522
7523 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7524 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7525 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7526 BDINFO_FLAGS_DISABLED);
7527
7528
7529 /* Disable all receive return rings but the first. */
Matt Carlsona50d0792010-06-05 17:24:37 +00007530 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7531 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00007532 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7533 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
Matt Carlson2d31eca2009-09-01 12:53:31 +00007534 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
Matt Carlsonb703df62009-12-03 08:36:21 +00007535 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7536 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
Matt Carlson2d31eca2009-09-01 12:53:31 +00007537 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7538 else
7539 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7540
7541 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7542 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7543 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7544 BDINFO_FLAGS_DISABLED);
7545
7546 /* Disable interrupts */
7547 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7548
7549 /* Zero mailbox registers. */
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007550 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7551 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7552 tp->napi[i].tx_prod = 0;
7553 tp->napi[i].tx_cons = 0;
Matt Carlsonc2353a32010-01-20 16:58:08 +00007554 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7555 tw32_mailbox(tp->napi[i].prodmbox, 0);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007556 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7557 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7558 }
Matt Carlsonc2353a32010-01-20 16:58:08 +00007559 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7560 tw32_mailbox(tp->napi[0].prodmbox, 0);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007561 } else {
7562 tp->napi[0].tx_prod = 0;
7563 tp->napi[0].tx_cons = 0;
7564 tw32_mailbox(tp->napi[0].prodmbox, 0);
7565 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7566 }
Matt Carlson2d31eca2009-09-01 12:53:31 +00007567
7568 /* Make sure the NIC-based send BD rings are disabled. */
7569 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7570 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7571 for (i = 0; i < 16; i++)
7572 tw32_tx_mbox(mbox + i * 8, 0);
7573 }
7574
7575 txrcb = NIC_SRAM_SEND_RCB;
7576 rxrcb = NIC_SRAM_RCV_RET_RCB;
7577
7578 /* Clear status block in ram. */
7579 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7580
7581 /* Set status block DMA address */
7582 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7583 ((u64) tnapi->status_mapping >> 32));
7584 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7585 ((u64) tnapi->status_mapping & 0xffffffff));
7586
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007587 if (tnapi->tx_ring) {
7588 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7589 (TG3_TX_RING_SIZE <<
7590 BDINFO_FLAGS_MAXLEN_SHIFT),
7591 NIC_SRAM_TX_BUFFER_DESC);
7592 txrcb += TG3_BDINFO_SIZE;
7593 }
Matt Carlson2d31eca2009-09-01 12:53:31 +00007594
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007595 if (tnapi->rx_rcb) {
7596 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7597 (TG3_RX_RCB_RING_SIZE(tp) <<
7598 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7599 rxrcb += TG3_BDINFO_SIZE;
7600 }
7601
7602 stblk = HOSTCC_STATBLCK_RING1;
7603
7604 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7605 u64 mapping = (u64)tnapi->status_mapping;
7606 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7607 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7608
7609 /* Clear status block in ram. */
7610 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7611
Matt Carlson19cfaec2009-12-03 08:36:20 +00007612 if (tnapi->tx_ring) {
7613 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7614 (TG3_TX_RING_SIZE <<
7615 BDINFO_FLAGS_MAXLEN_SHIFT),
7616 NIC_SRAM_TX_BUFFER_DESC);
7617 txrcb += TG3_BDINFO_SIZE;
7618 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007619
7620 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7621 (TG3_RX_RCB_RING_SIZE(tp) <<
7622 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7623
7624 stblk += 8;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007625 rxrcb += TG3_BDINFO_SIZE;
7626 }
Matt Carlson2d31eca2009-09-01 12:53:31 +00007627}
7628
7629/* tp->lock is held. */
Gary Zambrano8e7a22e2006-04-29 18:59:13 -07007630static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007631{
7632 u32 val, rdmac_mode;
7633 int i, err, limit;
Matt Carlson21f581a2009-08-28 14:00:25 +00007634 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
Linus Torvalds1da177e2005-04-16 15:20:36 -07007635
7636 tg3_disable_ints(tp);
7637
7638 tg3_stop_fw(tp);
7639
7640 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7641
Matt Carlson859a588792010-04-05 10:19:28 +00007642 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
Michael Chane6de8ad2005-05-05 14:42:41 -07007643 tg3_abort_hw(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007644
Matt Carlson603f1172010-02-12 14:47:10 +00007645 if (reset_phy)
Michael Chand4d2c552006-03-20 17:47:20 -08007646 tg3_phy_reset(tp);
7647
Linus Torvalds1da177e2005-04-16 15:20:36 -07007648 err = tg3_chip_reset(tp);
7649 if (err)
7650 return err;
7651
7652 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7653
Matt Carlsonbcb37f62008-11-03 16:52:09 -08007654 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
Matt Carlsond30cdd22007-10-07 23:28:35 -07007655 val = tr32(TG3_CPMU_CTRL);
7656 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7657 tw32(TG3_CPMU_CTRL, val);
Matt Carlson9acb9612007-11-12 21:10:06 -08007658
7659 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7660 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7661 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7662 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7663
7664 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7665 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7666 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7667 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7668
7669 val = tr32(TG3_CPMU_HST_ACC);
7670 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7671 val |= CPMU_HST_ACC_MACCLK_6_25;
7672 tw32(TG3_CPMU_HST_ACC, val);
Matt Carlsond30cdd22007-10-07 23:28:35 -07007673 }
7674
Matt Carlson33466d92009-04-20 06:57:41 +00007675 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7676 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7677 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7678 PCIE_PWR_MGMT_L1_THRESH_4MS;
7679 tw32(PCIE_PWR_MGMT_THRESH, val);
Matt Carlson521e6b92009-08-25 10:06:01 +00007680
7681 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7682 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7683
7684 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
Matt Carlson33466d92009-04-20 06:57:41 +00007685
Matt Carlsonf40386c2009-11-02 14:24:02 +00007686 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7687 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
Matt Carlson255ca312009-08-25 10:07:27 +00007688 }
7689
Matt Carlson614b0592010-01-20 16:58:02 +00007690 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7691 u32 grc_mode = tr32(GRC_MODE);
7692
7693 /* Access the lower 1K of PL PCIE block registers. */
7694 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7695 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7696
7697 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7698 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7699 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7700
7701 tw32(GRC_MODE, grc_mode);
7702 }
7703
Matt Carlsoncea46462010-04-12 06:58:24 +00007704 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7705 u32 grc_mode = tr32(GRC_MODE);
7706
7707 /* Access the lower 1K of PL PCIE block registers. */
7708 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7709 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7710
7711 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7712 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7713 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7714
7715 tw32(GRC_MODE, grc_mode);
Matt Carlsona977dbe2010-04-12 06:58:26 +00007716
7717 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7718 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7719 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7720 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
Matt Carlsoncea46462010-04-12 06:58:24 +00007721 }
7722
Linus Torvalds1da177e2005-04-16 15:20:36 -07007723 /* This works around an issue with Athlon chipsets on
7724 * B3 tigon3 silicon. This bit has no effect on any
7725 * other revision. But do not set this on PCI Express
Matt Carlson795d01c2007-10-07 23:28:17 -07007726 * chips and don't even touch the clocks if the CPMU is present.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007727 */
Matt Carlson795d01c2007-10-07 23:28:17 -07007728 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7729 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7730 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7731 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7732 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007733
7734 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7735 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7736 val = tr32(TG3PCI_PCISTATE);
7737 val |= PCISTATE_RETRY_SAME_DMA;
7738 tw32(TG3PCI_PCISTATE, val);
7739 }
7740
Matt Carlson0d3031d2007-10-10 18:02:43 -07007741 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7742 /* Allow reads and writes to the
7743 * APE register and memory space.
7744 */
7745 val = tr32(TG3PCI_PCISTATE);
7746 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
Matt Carlsonf92d9dc12010-06-05 17:24:30 +00007747 PCISTATE_ALLOW_APE_SHMEM_WR |
7748 PCISTATE_ALLOW_APE_PSPACE_WR;
Matt Carlson0d3031d2007-10-10 18:02:43 -07007749 tw32(TG3PCI_PCISTATE, val);
7750 }
7751
Linus Torvalds1da177e2005-04-16 15:20:36 -07007752 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7753 /* Enable some hw fixes. */
7754 val = tr32(TG3PCI_MSI_DATA);
7755 val |= (1 << 26) | (1 << 28) | (1 << 29);
7756 tw32(TG3PCI_MSI_DATA, val);
7757 }
7758
7759 /* Descriptor ring init may make accesses to the
7760 * NIC SRAM area to setup the TX descriptors, so we
7761 * can only do this after the hardware has been
7762 * successfully reset.
7763 */
Michael Chan32d8c572006-07-25 16:38:29 -07007764 err = tg3_init_rings(tp);
7765 if (err)
7766 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007767
Matt Carlsonc885e822010-08-02 11:25:57 +00007768 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
Matt Carlsoncbf9ca62009-11-13 13:03:40 +00007769 val = tr32(TG3PCI_DMA_RW_CTRL) &
7770 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
Matt Carlson1a319022010-04-12 06:58:25 +00007771 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7772 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
Matt Carlsoncbf9ca62009-11-13 13:03:40 +00007773 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7774 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7775 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
Matt Carlsond30cdd22007-10-07 23:28:35 -07007776 /* This value is determined during the probe time DMA
7777 * engine test, tg3_test_dma.
7778 */
7779 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7780 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007781
7782 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7783 GRC_MODE_4X_NIC_SEND_RINGS |
7784 GRC_MODE_NO_TX_PHDR_CSUM |
7785 GRC_MODE_NO_RX_PHDR_CSUM);
7786 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
Michael Chand2d746f2006-04-06 21:45:39 -07007787
7788 /* Pseudo-header checksum is done by hardware logic and not
7789 * the offload processers, so make the chip do the pseudo-
7790 * header checksums on receive. For transmit it is more
7791 * convenient to do the pseudo-header checksum in software
7792 * as Linux does that on transmit for us in all cases.
7793 */
7794 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007795
7796 tw32(GRC_MODE,
7797 tp->grc_mode |
7798 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7799
7800 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7801 val = tr32(GRC_MISC_CFG);
7802 val &= ~0xff;
7803 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7804 tw32(GRC_MISC_CFG, val);
7805
7806 /* Initialize MBUF/DESC pool. */
John W. Linvillecbf46852005-04-21 17:01:29 -07007807 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07007808 /* Do nothing. */
7809 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7810 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7811 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7812 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7813 else
7814 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7815 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7816 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
Matt Carlson859a588792010-04-05 10:19:28 +00007817 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07007818 int fw_len;
7819
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08007820 fw_len = tp->fw_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007821 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7822 tw32(BUFMGR_MB_POOL_ADDR,
7823 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7824 tw32(BUFMGR_MB_POOL_SIZE,
7825 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7826 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007827
Michael Chan0f893dc2005-07-25 12:30:38 -07007828 if (tp->dev->mtu <= ETH_DATA_LEN) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07007829 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7830 tp->bufmgr_config.mbuf_read_dma_low_water);
7831 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7832 tp->bufmgr_config.mbuf_mac_rx_low_water);
7833 tw32(BUFMGR_MB_HIGH_WATER,
7834 tp->bufmgr_config.mbuf_high_water);
7835 } else {
7836 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7837 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7838 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7839 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7840 tw32(BUFMGR_MB_HIGH_WATER,
7841 tp->bufmgr_config.mbuf_high_water_jumbo);
7842 }
7843 tw32(BUFMGR_DMA_LOW_WATER,
7844 tp->bufmgr_config.dma_low_water);
7845 tw32(BUFMGR_DMA_HIGH_WATER,
7846 tp->bufmgr_config.dma_high_water);
7847
7848 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7849 for (i = 0; i < 2000; i++) {
7850 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7851 break;
7852 udelay(10);
7853 }
7854 if (i >= 2000) {
Joe Perches05dbe002010-02-17 19:44:19 +00007855 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007856 return -ENODEV;
7857 }
7858
7859 /* Setup replenish threshold. */
Michael Chanf92905d2006-06-29 20:14:29 -07007860 val = tp->rx_pending / 8;
7861 if (val == 0)
7862 val = 1;
7863 else if (val > tp->rx_std_max_post)
7864 val = tp->rx_std_max_post;
Michael Chanb5d37722006-09-27 16:06:21 -07007865 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7866 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7867 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7868
7869 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7870 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7871 }
Michael Chanf92905d2006-06-29 20:14:29 -07007872
7873 tw32(RCVBDI_STD_THRESH, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007874
7875 /* Initialize TG3_BDINFO's at:
7876 * RCVDBDI_STD_BD: standard eth size rx ring
7877 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7878 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7879 *
7880 * like so:
7881 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7882 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7883 * ring attribute flags
7884 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7885 *
7886 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7887 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7888 *
7889 * The size of each ring is fixed in the firmware, but the location is
7890 * configurable.
7891 */
7892 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
Matt Carlson21f581a2009-08-28 14:00:25 +00007893 ((u64) tpr->rx_std_mapping >> 32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07007894 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
Matt Carlson21f581a2009-08-28 14:00:25 +00007895 ((u64) tpr->rx_std_mapping & 0xffffffff));
Matt Carlsona50d0792010-06-05 17:24:37 +00007896 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7897 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
Matt Carlson87668d32009-11-13 13:03:34 +00007898 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7899 NIC_SRAM_RX_BUFFER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007900
Matt Carlsonfdb72b32009-08-28 13:57:12 +00007901 /* Disable the mini ring */
7902 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07007903 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7904 BDINFO_FLAGS_DISABLED);
7905
Matt Carlsonfdb72b32009-08-28 13:57:12 +00007906 /* Program the jumbo buffer descriptor ring control
7907 * blocks on those devices that have them.
7908 */
Matt Carlson8f666b02009-08-28 13:58:24 +00007909 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
Matt Carlsonfdb72b32009-08-28 13:57:12 +00007910 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07007911 /* Setup replenish threshold. */
7912 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7913
Michael Chan0f893dc2005-07-25 12:30:38 -07007914 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07007915 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
Matt Carlson21f581a2009-08-28 14:00:25 +00007916 ((u64) tpr->rx_jmb_mapping >> 32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07007917 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
Matt Carlson21f581a2009-08-28 14:00:25 +00007918 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
Linus Torvalds1da177e2005-04-16 15:20:36 -07007919 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
Matt Carlson79ed5ac2009-08-28 14:00:55 +00007920 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7921 BDINFO_FLAGS_USE_EXT_RECV);
Matt Carlsona50d0792010-06-05 17:24:37 +00007922 if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7923 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
Matt Carlson87668d32009-11-13 13:03:34 +00007924 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7925 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007926 } else {
7927 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7928 BDINFO_FLAGS_DISABLED);
7929 }
7930
Matt Carlsonc885e822010-08-02 11:25:57 +00007931 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00007932 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
Matt Carlson04380d42010-04-12 06:58:29 +00007933 (TG3_RX_STD_DMA_SZ << 2);
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00007934 else
Matt Carlson04380d42010-04-12 06:58:29 +00007935 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
Matt Carlsonfdb72b32009-08-28 13:57:12 +00007936 } else
7937 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7938
7939 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007940
Matt Carlson411da642009-11-13 13:03:46 +00007941 tpr->rx_std_prod_idx = tp->rx_pending;
Matt Carlson66711e62009-11-13 13:03:49 +00007942 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007943
Matt Carlson411da642009-11-13 13:03:46 +00007944 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
Matt Carlson21f581a2009-08-28 14:00:25 +00007945 tp->rx_jumbo_pending : 0;
Matt Carlson66711e62009-11-13 13:03:49 +00007946 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007947
Matt Carlsonc885e822010-08-02 11:25:57 +00007948 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00007949 tw32(STD_REPLENISH_LWM, 32);
7950 tw32(JMB_REPLENISH_LWM, 16);
7951 }
7952
Matt Carlson2d31eca2009-09-01 12:53:31 +00007953 tg3_rings_reset(tp);
7954
Linus Torvalds1da177e2005-04-16 15:20:36 -07007955 /* Initialize MAC address and backoff seed. */
Michael Chan986e0ae2007-05-05 12:10:20 -07007956 __tg3_set_mac_addr(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007957
7958 /* MTU + ethernet header + FCS + optional VLAN tag */
Matt Carlsonf7b493e2009-02-25 14:21:52 +00007959 tw32(MAC_RX_MTU_SIZE,
7960 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007961
7962 /* The slot time is changed by tg3_setup_phy if we
7963 * run at gigabit with half duplex.
7964 */
7965 tw32(MAC_TX_LENGTHS,
7966 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7967 (6 << TX_LENGTHS_IPG_SHIFT) |
7968 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7969
7970 /* Receive rules. */
7971 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7972 tw32(RCVLPC_CONFIG, 0x0181);
7973
7974 /* Calculate RDMAC_MODE setting early, we need it to determine
7975 * the RCVLPC_STATE_ENABLE mask.
7976 */
7977 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7978 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7979 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7980 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7981 RDMAC_MODE_LNGREAD_ENAB);
Michael Chan85e94ce2005-04-21 17:05:28 -07007982
Matt Carlsona50d0792010-06-05 17:24:37 +00007983 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7984 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
Matt Carlson0339e4e2010-02-12 14:47:09 +00007985 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7986
Matt Carlson57e69832008-05-25 23:48:31 -07007987 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
Matt Carlson321d32a2008-11-21 17:22:19 -08007988 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7989 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
Matt Carlsond30cdd22007-10-07 23:28:35 -07007990 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7991 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7992 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7993
Michael Chan85e94ce2005-04-21 17:05:28 -07007994 /* If statement applies to 5705 and 5750 PCI devices only */
7995 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7996 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7997 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07007998 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
Matt Carlsonc13e3712007-05-05 11:50:04 -07007999 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008000 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8001 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8002 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8003 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8004 }
8005 }
8006
Michael Chan85e94ce2005-04-21 17:05:28 -07008007 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8008 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8009
Linus Torvalds1da177e2005-04-16 15:20:36 -07008010 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
Matt Carlson027455a2008-12-21 20:19:30 -08008011 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8012
Matt Carlsone849cdc2009-11-13 13:03:38 +00008013 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8014 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
Matt Carlson027455a2008-12-21 20:19:30 -08008015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8016 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008017
8018 /* Receive/send statistics. */
Michael Chan16613942006-06-29 20:15:13 -07008019 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8020 val = tr32(RCVLPC_STATS_ENABLE);
8021 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8022 tw32(RCVLPC_STATS_ENABLE, val);
8023 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8024 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008025 val = tr32(RCVLPC_STATS_ENABLE);
8026 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8027 tw32(RCVLPC_STATS_ENABLE, val);
8028 } else {
8029 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8030 }
8031 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8032 tw32(SNDDATAI_STATSENAB, 0xffffff);
8033 tw32(SNDDATAI_STATSCTRL,
8034 (SNDDATAI_SCTRL_ENABLE |
8035 SNDDATAI_SCTRL_FASTUPD));
8036
8037 /* Setup host coalescing engine. */
8038 tw32(HOSTCC_MODE, 0);
8039 for (i = 0; i < 2000; i++) {
8040 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8041 break;
8042 udelay(10);
8043 }
8044
Michael Chand244c892005-07-05 14:42:33 -07008045 __tg3_set_coalesce(tp, &tp->coal);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008046
Linus Torvalds1da177e2005-04-16 15:20:36 -07008047 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8048 /* Status/statistics block address. See tg3_timer,
8049 * the tg3_periodic_fetch_stats call there, and
8050 * tg3_get_stats to see how this works for 5705/5750 chips.
8051 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07008052 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8053 ((u64) tp->stats_mapping >> 32));
8054 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8055 ((u64) tp->stats_mapping & 0xffffffff));
8056 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
Matt Carlson2d31eca2009-09-01 12:53:31 +00008057
Linus Torvalds1da177e2005-04-16 15:20:36 -07008058 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
Matt Carlson2d31eca2009-09-01 12:53:31 +00008059
8060 /* Clear statistics and status block memory areas */
8061 for (i = NIC_SRAM_STATS_BLK;
8062 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8063 i += sizeof(u32)) {
8064 tg3_write_mem(tp, i, 0);
8065 udelay(40);
8066 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008067 }
8068
8069 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8070
8071 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8072 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8073 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8074 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8075
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008076 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8077 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chanc94e3942005-09-27 12:12:42 -07008078 /* reset to prevent losing 1st rx packet intermittently */
8079 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8080 udelay(10);
8081 }
8082
Matt Carlson3bda1252008-08-15 14:08:22 -07008083 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8084 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8085 else
8086 tp->mac_mode = 0;
8087 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
Linus Torvalds1da177e2005-04-16 15:20:36 -07008088 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07008089 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008090 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07008091 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8092 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008093 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8094 udelay(40);
8095
Michael Chan314fba32005-04-21 17:07:04 -07008096 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
Michael Chan9d26e212006-12-07 00:21:14 -08008097 * If TG3_FLG2_IS_NIC is zero, we should read the
Michael Chan314fba32005-04-21 17:07:04 -07008098 * register to preserve the GPIO settings for LOMs. The GPIOs,
8099 * whether used as inputs or outputs, are set by boot code after
8100 * reset.
8101 */
Michael Chan9d26e212006-12-07 00:21:14 -08008102 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
Michael Chan314fba32005-04-21 17:07:04 -07008103 u32 gpio_mask;
8104
Michael Chan9d26e212006-12-07 00:21:14 -08008105 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8106 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8107 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
Michael Chan3e7d83b2005-04-21 17:10:36 -07008108
8109 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8110 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8111 GRC_LCLCTRL_GPIO_OUTPUT3;
8112
Michael Chanaf36e6b2006-03-23 01:28:06 -08008113 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8114 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8115
Gary Zambranoaaf84462007-05-05 11:51:45 -07008116 tp->grc_local_ctrl &= ~gpio_mask;
Michael Chan314fba32005-04-21 17:07:04 -07008117 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8118
8119 /* GPIO1 must be driven high for eeprom write protect */
Michael Chan9d26e212006-12-07 00:21:14 -08008120 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8121 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8122 GRC_LCLCTRL_GPIO_OUTPUT1);
Michael Chan314fba32005-04-21 17:07:04 -07008123 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008124 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8125 udelay(100);
8126
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008127 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8128 val = tr32(MSGINT_MODE);
8129 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8130 tw32(MSGINT_MODE, val);
8131 }
8132
Linus Torvalds1da177e2005-04-16 15:20:36 -07008133 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8134 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8135 udelay(40);
8136 }
8137
8138 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8139 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8140 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8141 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8142 WDMAC_MODE_LNGREAD_ENAB);
8143
Michael Chan85e94ce2005-04-21 17:05:28 -07008144 /* If statement applies to 5705 and 5750 PCI devices only */
8145 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8146 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8147 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
Matt Carlson29ea0952009-08-25 10:07:54 +00008148 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07008149 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8150 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8151 /* nothing */
8152 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8153 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8154 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8155 val |= WDMAC_MODE_RX_ACCEL;
8156 }
8157 }
8158
Michael Chand9ab5ad2006-03-20 22:27:35 -08008159 /* Enable host coalescing bug fix */
Matt Carlson321d32a2008-11-21 17:22:19 -08008160 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
Matt Carlsonf51f3562008-05-25 23:45:08 -07008161 val |= WDMAC_MODE_STATUS_TAG_FIX;
Michael Chand9ab5ad2006-03-20 22:27:35 -08008162
Matt Carlson788a0352009-11-02 14:26:03 +00008163 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8164 val |= WDMAC_MODE_BURST_ALL_DATA;
8165
Linus Torvalds1da177e2005-04-16 15:20:36 -07008166 tw32_f(WDMAC_MODE, val);
8167 udelay(40);
8168
Matt Carlson9974a352007-10-07 23:27:28 -07008169 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8170 u16 pcix_cmd;
8171
8172 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8173 &pcix_cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008174 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
Matt Carlson9974a352007-10-07 23:27:28 -07008175 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8176 pcix_cmd |= PCI_X_CMD_READ_2K;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008177 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
Matt Carlson9974a352007-10-07 23:27:28 -07008178 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8179 pcix_cmd |= PCI_X_CMD_READ_2K;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008180 }
Matt Carlson9974a352007-10-07 23:27:28 -07008181 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8182 pcix_cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008183 }
8184
8185 tw32_f(RDMAC_MODE, rdmac_mode);
8186 udelay(40);
8187
8188 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8189 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8190 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
Matt Carlson9936bcf2007-10-10 18:03:07 -07008191
8192 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8193 tw32(SNDDATAC_MODE,
8194 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8195 else
8196 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8197
Linus Torvalds1da177e2005-04-16 15:20:36 -07008198 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8199 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8200 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8201 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008202 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8203 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008204 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
Matt Carlson19cfaec2009-12-03 08:36:20 +00008205 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008206 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8207 tw32(SNDBDI_MODE, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008208 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8209
8210 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8211 err = tg3_load_5701_a0_firmware_fix(tp);
8212 if (err)
8213 return err;
8214 }
8215
Linus Torvalds1da177e2005-04-16 15:20:36 -07008216 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8217 err = tg3_load_tso_firmware(tp);
8218 if (err)
8219 return err;
8220 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008221
8222 tp->tx_mode = TX_MODE_ENABLE;
Matt Carlsonb1d05212010-06-05 17:24:31 +00008223 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8224 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8225 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008226 tw32_f(MAC_TX_MODE, tp->tx_mode);
8227 udelay(100);
8228
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008229 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8230 u32 reg = MAC_RSS_INDIR_TBL_0;
8231 u8 *ent = (u8 *)&val;
8232
8233 /* Setup the indirection table */
8234 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8235 int idx = i % sizeof(val);
8236
Matt Carlson5efeeea2010-07-11 09:31:40 +00008237 ent[idx] = i % (tp->irq_cnt - 1);
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008238 if (idx == sizeof(val) - 1) {
8239 tw32(reg, val);
8240 reg += 4;
8241 }
8242 }
8243
8244 /* Setup the "secret" hash key. */
8245 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8246 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8247 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8248 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8249 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8250 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8251 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8252 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8253 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8254 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8255 }
8256
Linus Torvalds1da177e2005-04-16 15:20:36 -07008257 tp->rx_mode = RX_MODE_ENABLE;
Matt Carlson321d32a2008-11-21 17:22:19 -08008258 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
Michael Chanaf36e6b2006-03-23 01:28:06 -08008259 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8260
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008261 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8262 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8263 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8264 RX_MODE_RSS_IPV6_HASH_EN |
8265 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8266 RX_MODE_RSS_IPV4_HASH_EN |
8267 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8268
Linus Torvalds1da177e2005-04-16 15:20:36 -07008269 tw32_f(MAC_RX_MODE, tp->rx_mode);
8270 udelay(10);
8271
Linus Torvalds1da177e2005-04-16 15:20:36 -07008272 tw32(MAC_LED_CTRL, tp->led_ctrl);
8273
8274 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008275 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008276 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8277 udelay(10);
8278 }
8279 tw32_f(MAC_RX_MODE, tp->rx_mode);
8280 udelay(10);
8281
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008282 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008283 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008284 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008285 /* Set drive transmission level to 1.2V */
8286 /* only if the signal pre-emphasis bit is not set */
8287 val = tr32(MAC_SERDES_CFG);
8288 val &= 0xfffff000;
8289 val |= 0x880;
8290 tw32(MAC_SERDES_CFG, val);
8291 }
8292 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8293 tw32(MAC_SERDES_CFG, 0x616000);
8294 }
8295
8296 /* Prevent chip from dropping frames when flow control
8297 * is enabled.
8298 */
Matt Carlson666bc832010-01-20 16:58:03 +00008299 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8300 val = 1;
8301 else
8302 val = 2;
8303 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008304
8305 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008306 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008307 /* Use hardware link auto-negotiation */
8308 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8309 }
8310
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008311 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
Michael Chand4d2c552006-03-20 17:47:20 -08008312 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8313 u32 tmp;
8314
8315 tmp = tr32(SERDES_RX_CTRL);
8316 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8317 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8318 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8319 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8320 }
8321
Matt Carlsondd477002008-05-25 23:45:58 -07008322 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
Matt Carlson800960682010-08-02 11:26:06 +00008323 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8324 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
Matt Carlsondd477002008-05-25 23:45:58 -07008325 tp->link_config.speed = tp->link_config.orig_speed;
8326 tp->link_config.duplex = tp->link_config.orig_duplex;
8327 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8328 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008329
Matt Carlsondd477002008-05-25 23:45:58 -07008330 err = tg3_setup_phy(tp, 0);
8331 if (err)
8332 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008333
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008334 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8335 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
Matt Carlsondd477002008-05-25 23:45:58 -07008336 u32 tmp;
8337
8338 /* Clear CRC stats. */
8339 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8340 tg3_writephy(tp, MII_TG3_TEST1,
8341 tmp | MII_TG3_TEST1_CRC_EN);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00008342 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
Matt Carlsondd477002008-05-25 23:45:58 -07008343 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008344 }
8345 }
8346
8347 __tg3_set_rx_mode(tp->dev);
8348
8349 /* Initialize receive rules. */
8350 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8351 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8352 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8353 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8354
Michael Chan4cf78e42005-07-25 12:29:19 -07008355 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
Michael Chana4e2b342005-10-26 15:46:52 -07008356 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07008357 limit = 8;
8358 else
8359 limit = 16;
8360 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8361 limit -= 4;
8362 switch (limit) {
8363 case 16:
8364 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8365 case 15:
8366 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8367 case 14:
8368 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8369 case 13:
8370 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8371 case 12:
8372 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8373 case 11:
8374 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8375 case 10:
8376 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8377 case 9:
8378 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8379 case 8:
8380 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8381 case 7:
8382 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8383 case 6:
8384 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8385 case 5:
8386 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8387 case 4:
8388 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8389 case 3:
8390 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8391 case 2:
8392 case 1:
8393
8394 default:
8395 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07008396 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008397
Matt Carlson9ce768e2007-10-11 19:49:11 -07008398 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8399 /* Write our heartbeat update interval to APE. */
8400 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8401 APE_HOST_HEARTBEAT_INT_DISABLE);
Matt Carlson0d3031d2007-10-10 18:02:43 -07008402
Linus Torvalds1da177e2005-04-16 15:20:36 -07008403 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8404
Linus Torvalds1da177e2005-04-16 15:20:36 -07008405 return 0;
8406}
8407
8408/* Called at device open time to get the chip ready for
8409 * packet processing. Invoked with tp->lock held.
8410 */
Gary Zambrano8e7a22e2006-04-29 18:59:13 -07008411static int tg3_init_hw(struct tg3 *tp, int reset_phy)
Linus Torvalds1da177e2005-04-16 15:20:36 -07008412{
Linus Torvalds1da177e2005-04-16 15:20:36 -07008413 tg3_switch_clocks(tp);
8414
8415 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8416
Matt Carlson2f751b62008-08-04 23:17:34 -07008417 return tg3_reset_hw(tp, reset_phy);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008418}
8419
8420#define TG3_STAT_ADD32(PSTAT, REG) \
8421do { u32 __val = tr32(REG); \
8422 (PSTAT)->low += __val; \
8423 if ((PSTAT)->low < __val) \
8424 (PSTAT)->high += 1; \
8425} while (0)
8426
8427static void tg3_periodic_fetch_stats(struct tg3 *tp)
8428{
8429 struct tg3_hw_stats *sp = tp->hw_stats;
8430
8431 if (!netif_carrier_ok(tp->dev))
8432 return;
8433
8434 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8435 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8436 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8437 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8438 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8439 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8440 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8441 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8442 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8443 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8444 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8445 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8446 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8447
8448 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8449 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8450 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8451 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8452 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8453 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8454 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8455 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8456 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8457 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8458 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8459 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8460 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8461 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
Michael Chan463d3052006-05-22 16:36:27 -07008462
8463 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8464 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8465 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008466}
8467
8468static void tg3_timer(unsigned long __opaque)
8469{
8470 struct tg3 *tp = (struct tg3 *) __opaque;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008471
Michael Chanf475f162006-03-27 23:20:14 -08008472 if (tp->irq_sync)
8473 goto restart_timer;
8474
David S. Millerf47c11e2005-06-24 20:18:35 -07008475 spin_lock(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008476
David S. Millerfac9b832005-05-18 22:46:34 -07008477 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8478 /* All of this garbage is because when using non-tagged
8479 * IRQ status the mailbox/status_block protocol the chip
8480 * uses with the cpu is race prone.
8481 */
Matt Carlson898a56f2009-08-28 14:02:40 +00008482 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
David S. Millerfac9b832005-05-18 22:46:34 -07008483 tw32(GRC_LOCAL_CTRL,
8484 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8485 } else {
8486 tw32(HOSTCC_MODE, tp->coalesce_mode |
Matt Carlsonfd2ce372009-09-01 12:51:13 +00008487 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
David S. Millerfac9b832005-05-18 22:46:34 -07008488 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008489
David S. Millerfac9b832005-05-18 22:46:34 -07008490 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8491 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
David S. Millerf47c11e2005-06-24 20:18:35 -07008492 spin_unlock(&tp->lock);
David S. Millerfac9b832005-05-18 22:46:34 -07008493 schedule_work(&tp->reset_task);
8494 return;
8495 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008496 }
8497
Linus Torvalds1da177e2005-04-16 15:20:36 -07008498 /* This part only runs once per second. */
8499 if (!--tp->timer_counter) {
David S. Millerfac9b832005-05-18 22:46:34 -07008500 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8501 tg3_periodic_fetch_stats(tp);
8502
Linus Torvalds1da177e2005-04-16 15:20:36 -07008503 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8504 u32 mac_stat;
8505 int phy_event;
8506
8507 mac_stat = tr32(MAC_STATUS);
8508
8509 phy_event = 0;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008510 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008511 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8512 phy_event = 1;
8513 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8514 phy_event = 1;
8515
8516 if (phy_event)
8517 tg3_setup_phy(tp, 0);
8518 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8519 u32 mac_stat = tr32(MAC_STATUS);
8520 int need_setup = 0;
8521
8522 if (netif_carrier_ok(tp->dev) &&
8523 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8524 need_setup = 1;
8525 }
Matt Carlsonbe98da62010-07-11 09:31:46 +00008526 if (!netif_carrier_ok(tp->dev) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07008527 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8528 MAC_STATUS_SIGNAL_DET))) {
8529 need_setup = 1;
8530 }
8531 if (need_setup) {
Michael Chan3d3ebe72006-09-27 15:59:15 -07008532 if (!tp->serdes_counter) {
8533 tw32_f(MAC_MODE,
8534 (tp->mac_mode &
8535 ~MAC_MODE_PORT_MODE_MASK));
8536 udelay(40);
8537 tw32_f(MAC_MODE, tp->mac_mode);
8538 udelay(40);
8539 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008540 tg3_setup_phy(tp, 0);
8541 }
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008542 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
Matt Carlson2138c002010-07-11 09:31:43 +00008543 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
Michael Chan747e8f82005-07-25 12:33:22 -07008544 tg3_serdes_parallel_detect(tp);
Matt Carlson57d8b882010-06-05 17:24:35 +00008545 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008546
8547 tp->timer_counter = tp->timer_multiplier;
8548 }
8549
Michael Chan130b8e42006-09-27 16:00:40 -07008550 /* Heartbeat is only sent once every 2 seconds.
8551 *
8552 * The heartbeat is to tell the ASF firmware that the host
8553 * driver is still alive. In the event that the OS crashes,
8554 * ASF needs to reset the hardware to free up the FIFO space
8555 * that may be filled with rx packets destined for the host.
8556 * If the FIFO is full, ASF will no longer function properly.
8557 *
8558 * Unintended resets have been reported on real time kernels
8559 * where the timer doesn't run on time. Netpoll will also have
8560 * same problem.
8561 *
8562 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8563 * to check the ring condition when the heartbeat is expiring
8564 * before doing the reset. This will prevent most unintended
8565 * resets.
8566 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07008567 if (!--tp->asf_counter) {
Matt Carlsonbc7959b2008-08-15 14:08:55 -07008568 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8569 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
Matt Carlson7c5026a2008-05-02 16:49:29 -07008570 tg3_wait_for_event_ack(tp);
8571
Michael Chanbbadf502006-04-06 21:46:34 -07008572 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
Michael Chan130b8e42006-09-27 16:00:40 -07008573 FWCMD_NICDRV_ALIVE3);
Michael Chanbbadf502006-04-06 21:46:34 -07008574 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
Matt Carlsonc6cdf432010-04-05 10:19:26 +00008575 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8576 TG3_FW_UPDATE_TIMEOUT_SEC);
Matt Carlson4ba526c2008-08-15 14:10:04 -07008577
8578 tg3_generate_fw_event(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008579 }
8580 tp->asf_counter = tp->asf_multiplier;
8581 }
8582
David S. Millerf47c11e2005-06-24 20:18:35 -07008583 spin_unlock(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008584
Michael Chanf475f162006-03-27 23:20:14 -08008585restart_timer:
Linus Torvalds1da177e2005-04-16 15:20:36 -07008586 tp->timer.expires = jiffies + tp->timer_offset;
8587 add_timer(&tp->timer);
8588}
8589
Matt Carlson4f125f42009-09-01 12:55:02 +00008590static int tg3_request_irq(struct tg3 *tp, int irq_num)
Michael Chanfcfa0a32006-03-20 22:28:41 -08008591{
David Howells7d12e782006-10-05 14:55:46 +01008592 irq_handler_t fn;
Michael Chanfcfa0a32006-03-20 22:28:41 -08008593 unsigned long flags;
Matt Carlson4f125f42009-09-01 12:55:02 +00008594 char *name;
8595 struct tg3_napi *tnapi = &tp->napi[irq_num];
8596
8597 if (tp->irq_cnt == 1)
8598 name = tp->dev->name;
8599 else {
8600 name = &tnapi->irq_lbl[0];
8601 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8602 name[IFNAMSIZ-1] = 0;
8603 }
Michael Chanfcfa0a32006-03-20 22:28:41 -08008604
Matt Carlson679563f2009-09-01 12:55:46 +00008605 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
Michael Chanfcfa0a32006-03-20 22:28:41 -08008606 fn = tg3_msi;
8607 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8608 fn = tg3_msi_1shot;
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07008609 flags = IRQF_SAMPLE_RANDOM;
Michael Chanfcfa0a32006-03-20 22:28:41 -08008610 } else {
8611 fn = tg3_interrupt;
8612 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8613 fn = tg3_interrupt_tagged;
Thomas Gleixner1fb9df52006-07-01 19:29:39 -07008614 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
Michael Chanfcfa0a32006-03-20 22:28:41 -08008615 }
Matt Carlson4f125f42009-09-01 12:55:02 +00008616
8617 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
Michael Chanfcfa0a32006-03-20 22:28:41 -08008618}
8619
Michael Chan79381092005-04-21 17:13:59 -07008620static int tg3_test_interrupt(struct tg3 *tp)
8621{
Matt Carlson09943a12009-08-28 14:01:57 +00008622 struct tg3_napi *tnapi = &tp->napi[0];
Michael Chan79381092005-04-21 17:13:59 -07008623 struct net_device *dev = tp->dev;
Michael Chanb16250e2006-09-27 16:10:14 -07008624 int err, i, intr_ok = 0;
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00008625 u32 val;
Michael Chan79381092005-04-21 17:13:59 -07008626
Michael Chand4bc3922005-05-29 14:59:20 -07008627 if (!netif_running(dev))
8628 return -ENODEV;
8629
Michael Chan79381092005-04-21 17:13:59 -07008630 tg3_disable_ints(tp);
8631
Matt Carlson4f125f42009-09-01 12:55:02 +00008632 free_irq(tnapi->irq_vec, tnapi);
Michael Chan79381092005-04-21 17:13:59 -07008633
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00008634 /*
8635 * Turn off MSI one shot mode. Otherwise this test has no
8636 * observable way to know whether the interrupt was delivered.
8637 */
Matt Carlsonc885e822010-08-02 11:25:57 +00008638 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00008639 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8640 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8641 tw32(MSGINT_MODE, val);
8642 }
8643
Matt Carlson4f125f42009-09-01 12:55:02 +00008644 err = request_irq(tnapi->irq_vec, tg3_test_isr,
Matt Carlson09943a12009-08-28 14:01:57 +00008645 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
Michael Chan79381092005-04-21 17:13:59 -07008646 if (err)
8647 return err;
8648
Matt Carlson898a56f2009-08-28 14:02:40 +00008649 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
Michael Chan79381092005-04-21 17:13:59 -07008650 tg3_enable_ints(tp);
8651
8652 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
Matt Carlsonfd2ce372009-09-01 12:51:13 +00008653 tnapi->coal_now);
Michael Chan79381092005-04-21 17:13:59 -07008654
8655 for (i = 0; i < 5; i++) {
Michael Chanb16250e2006-09-27 16:10:14 -07008656 u32 int_mbox, misc_host_ctrl;
8657
Matt Carlson898a56f2009-08-28 14:02:40 +00008658 int_mbox = tr32_mailbox(tnapi->int_mbox);
Michael Chanb16250e2006-09-27 16:10:14 -07008659 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8660
8661 if ((int_mbox != 0) ||
8662 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8663 intr_ok = 1;
Michael Chan79381092005-04-21 17:13:59 -07008664 break;
Michael Chanb16250e2006-09-27 16:10:14 -07008665 }
8666
Michael Chan79381092005-04-21 17:13:59 -07008667 msleep(10);
8668 }
8669
8670 tg3_disable_ints(tp);
8671
Matt Carlson4f125f42009-09-01 12:55:02 +00008672 free_irq(tnapi->irq_vec, tnapi);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04008673
Matt Carlson4f125f42009-09-01 12:55:02 +00008674 err = tg3_request_irq(tp, 0);
Michael Chan79381092005-04-21 17:13:59 -07008675
8676 if (err)
8677 return err;
8678
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00008679 if (intr_ok) {
8680 /* Reenable MSI one shot mode. */
Matt Carlsonc885e822010-08-02 11:25:57 +00008681 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00008682 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8683 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8684 tw32(MSGINT_MODE, val);
8685 }
Michael Chan79381092005-04-21 17:13:59 -07008686 return 0;
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00008687 }
Michael Chan79381092005-04-21 17:13:59 -07008688
8689 return -EIO;
8690}
8691
8692/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8693 * successfully restored
8694 */
8695static int tg3_test_msi(struct tg3 *tp)
8696{
Michael Chan79381092005-04-21 17:13:59 -07008697 int err;
8698 u16 pci_cmd;
8699
8700 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8701 return 0;
8702
8703 /* Turn off SERR reporting in case MSI terminates with Master
8704 * Abort.
8705 */
8706 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8707 pci_write_config_word(tp->pdev, PCI_COMMAND,
8708 pci_cmd & ~PCI_COMMAND_SERR);
8709
8710 err = tg3_test_interrupt(tp);
8711
8712 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8713
8714 if (!err)
8715 return 0;
8716
8717 /* other failures */
8718 if (err != -EIO)
8719 return err;
8720
8721 /* MSI test failed, go back to INTx mode */
Matt Carlson5129c3a2010-04-05 10:19:23 +00008722 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8723 "to INTx mode. Please report this failure to the PCI "
8724 "maintainer and include system chipset information\n");
Michael Chan79381092005-04-21 17:13:59 -07008725
Matt Carlson4f125f42009-09-01 12:55:02 +00008726 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
Matt Carlson09943a12009-08-28 14:01:57 +00008727
Michael Chan79381092005-04-21 17:13:59 -07008728 pci_disable_msi(tp->pdev);
8729
8730 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
Andre Detschdc8bf1b2010-04-26 07:27:07 +00008731 tp->napi[0].irq_vec = tp->pdev->irq;
Michael Chan79381092005-04-21 17:13:59 -07008732
Matt Carlson4f125f42009-09-01 12:55:02 +00008733 err = tg3_request_irq(tp, 0);
Michael Chan79381092005-04-21 17:13:59 -07008734 if (err)
8735 return err;
8736
8737 /* Need to reset the chip because the MSI cycle may have terminated
8738 * with Master Abort.
8739 */
David S. Millerf47c11e2005-06-24 20:18:35 -07008740 tg3_full_lock(tp, 1);
Michael Chan79381092005-04-21 17:13:59 -07008741
Michael Chan944d9802005-05-29 14:57:48 -07008742 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Gary Zambrano8e7a22e2006-04-29 18:59:13 -07008743 err = tg3_init_hw(tp, 1);
Michael Chan79381092005-04-21 17:13:59 -07008744
David S. Millerf47c11e2005-06-24 20:18:35 -07008745 tg3_full_unlock(tp);
Michael Chan79381092005-04-21 17:13:59 -07008746
8747 if (err)
Matt Carlson4f125f42009-09-01 12:55:02 +00008748 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
Michael Chan79381092005-04-21 17:13:59 -07008749
8750 return err;
8751}
8752
Matt Carlson9e9fd122009-01-19 16:57:45 -08008753static int tg3_request_firmware(struct tg3 *tp)
8754{
8755 const __be32 *fw_data;
8756
8757 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
Joe Perches05dbe002010-02-17 19:44:19 +00008758 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8759 tp->fw_needed);
Matt Carlson9e9fd122009-01-19 16:57:45 -08008760 return -ENOENT;
8761 }
8762
8763 fw_data = (void *)tp->fw->data;
8764
8765 /* Firmware blob starts with version numbers, followed by
8766 * start address and _full_ length including BSS sections
8767 * (which must be longer than the actual data, of course
8768 */
8769
8770 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8771 if (tp->fw_len < (tp->fw->size - 12)) {
Joe Perches05dbe002010-02-17 19:44:19 +00008772 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8773 tp->fw_len, tp->fw_needed);
Matt Carlson9e9fd122009-01-19 16:57:45 -08008774 release_firmware(tp->fw);
8775 tp->fw = NULL;
8776 return -EINVAL;
8777 }
8778
8779 /* We no longer need firmware; we have it. */
8780 tp->fw_needed = NULL;
8781 return 0;
8782}
8783
Matt Carlson679563f2009-09-01 12:55:46 +00008784static bool tg3_enable_msix(struct tg3 *tp)
8785{
8786 int i, rc, cpus = num_online_cpus();
8787 struct msix_entry msix_ent[tp->irq_max];
8788
8789 if (cpus == 1)
8790 /* Just fallback to the simpler MSI mode. */
8791 return false;
8792
8793 /*
8794 * We want as many rx rings enabled as there are cpus.
8795 * The first MSIX vector only deals with link interrupts, etc,
8796 * so we add one to the number of vectors we are requesting.
8797 */
8798 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8799
8800 for (i = 0; i < tp->irq_max; i++) {
8801 msix_ent[i].entry = i;
8802 msix_ent[i].vector = 0;
8803 }
8804
8805 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
Matt Carlson2430b032010-06-05 17:24:34 +00008806 if (rc < 0) {
8807 return false;
8808 } else if (rc != 0) {
Matt Carlson679563f2009-09-01 12:55:46 +00008809 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8810 return false;
Joe Perches05dbe002010-02-17 19:44:19 +00008811 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8812 tp->irq_cnt, rc);
Matt Carlson679563f2009-09-01 12:55:46 +00008813 tp->irq_cnt = rc;
8814 }
8815
8816 for (i = 0; i < tp->irq_max; i++)
8817 tp->napi[i].irq_vec = msix_ent[i].vector;
8818
Matt Carlson2430b032010-06-05 17:24:34 +00008819 tp->dev->real_num_tx_queues = 1;
8820 if (tp->irq_cnt > 1) {
8821 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8822
Matt Carlsona50d0792010-06-05 17:24:37 +00008823 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8824 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
Matt Carlson2430b032010-06-05 17:24:34 +00008825 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8826 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8827 }
8828 }
Matt Carlsonfe5f5782009-09-01 13:09:39 +00008829
Matt Carlson679563f2009-09-01 12:55:46 +00008830 return true;
8831}
8832
Matt Carlson07b01732009-08-28 14:01:15 +00008833static void tg3_ints_init(struct tg3 *tp)
8834{
Matt Carlson679563f2009-09-01 12:55:46 +00008835 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8836 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
Matt Carlson07b01732009-08-28 14:01:15 +00008837 /* All MSI supporting chips should support tagged
8838 * status. Assert that this is the case.
8839 */
Matt Carlson5129c3a2010-04-05 10:19:23 +00008840 netdev_warn(tp->dev,
8841 "MSI without TAGGED_STATUS? Not using MSI\n");
Matt Carlson679563f2009-09-01 12:55:46 +00008842 goto defcfg;
Matt Carlson07b01732009-08-28 14:01:15 +00008843 }
Matt Carlson4f125f42009-09-01 12:55:02 +00008844
Matt Carlson679563f2009-09-01 12:55:46 +00008845 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8846 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8847 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8848 pci_enable_msi(tp->pdev) == 0)
8849 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8850
8851 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8852 u32 msi_mode = tr32(MSGINT_MODE);
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008853 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8854 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
Matt Carlson679563f2009-09-01 12:55:46 +00008855 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8856 }
8857defcfg:
8858 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8859 tp->irq_cnt = 1;
8860 tp->napi[0].irq_vec = tp->pdev->irq;
Matt Carlsonfe5f5782009-09-01 13:09:39 +00008861 tp->dev->real_num_tx_queues = 1;
Matt Carlson679563f2009-09-01 12:55:46 +00008862 }
Matt Carlson07b01732009-08-28 14:01:15 +00008863}
8864
8865static void tg3_ints_fini(struct tg3 *tp)
8866{
Matt Carlson679563f2009-09-01 12:55:46 +00008867 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8868 pci_disable_msix(tp->pdev);
8869 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8870 pci_disable_msi(tp->pdev);
8871 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
Matt Carlson774ee752010-08-02 11:25:56 +00008872 tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
Matt Carlson07b01732009-08-28 14:01:15 +00008873}
8874
Linus Torvalds1da177e2005-04-16 15:20:36 -07008875static int tg3_open(struct net_device *dev)
8876{
8877 struct tg3 *tp = netdev_priv(dev);
Matt Carlson4f125f42009-09-01 12:55:02 +00008878 int i, err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008879
Matt Carlson9e9fd122009-01-19 16:57:45 -08008880 if (tp->fw_needed) {
8881 err = tg3_request_firmware(tp);
8882 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8883 if (err)
8884 return err;
8885 } else if (err) {
Joe Perches05dbe002010-02-17 19:44:19 +00008886 netdev_warn(tp->dev, "TSO capability disabled\n");
Matt Carlson9e9fd122009-01-19 16:57:45 -08008887 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8888 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
Joe Perches05dbe002010-02-17 19:44:19 +00008889 netdev_notice(tp->dev, "TSO capability restored\n");
Matt Carlson9e9fd122009-01-19 16:57:45 -08008890 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8891 }
8892 }
8893
Michael Chanc49a1562006-12-17 17:07:29 -08008894 netif_carrier_off(tp->dev);
8895
Michael Chanbc1c7562006-03-20 17:48:03 -08008896 err = tg3_set_power_state(tp, PCI_D0);
Matt Carlson2f751b62008-08-04 23:17:34 -07008897 if (err)
Michael Chanbc1c7562006-03-20 17:48:03 -08008898 return err;
Matt Carlson2f751b62008-08-04 23:17:34 -07008899
8900 tg3_full_lock(tp, 0);
Michael Chanbc1c7562006-03-20 17:48:03 -08008901
Linus Torvalds1da177e2005-04-16 15:20:36 -07008902 tg3_disable_ints(tp);
8903 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8904
David S. Millerf47c11e2005-06-24 20:18:35 -07008905 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008906
Matt Carlson679563f2009-09-01 12:55:46 +00008907 /*
8908 * Setup interrupts first so we know how
8909 * many NAPI resources to allocate
8910 */
8911 tg3_ints_init(tp);
8912
Linus Torvalds1da177e2005-04-16 15:20:36 -07008913 /* The placement of this call is tied
8914 * to the setup and use of Host TX descriptors.
8915 */
8916 err = tg3_alloc_consistent(tp);
8917 if (err)
Matt Carlson679563f2009-09-01 12:55:46 +00008918 goto err_out1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008919
Matt Carlsonfed97812009-09-01 13:10:19 +00008920 tg3_napi_enable(tp);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07008921
Matt Carlson4f125f42009-09-01 12:55:02 +00008922 for (i = 0; i < tp->irq_cnt; i++) {
8923 struct tg3_napi *tnapi = &tp->napi[i];
8924 err = tg3_request_irq(tp, i);
8925 if (err) {
8926 for (i--; i >= 0; i--)
8927 free_irq(tnapi->irq_vec, tnapi);
8928 break;
8929 }
8930 }
Matt Carlson07b01732009-08-28 14:01:15 +00008931
8932 if (err)
Matt Carlson679563f2009-09-01 12:55:46 +00008933 goto err_out2;
Matt Carlson07b01732009-08-28 14:01:15 +00008934
David S. Millerf47c11e2005-06-24 20:18:35 -07008935 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008936
Gary Zambrano8e7a22e2006-04-29 18:59:13 -07008937 err = tg3_init_hw(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008938 if (err) {
Michael Chan944d9802005-05-29 14:57:48 -07008939 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008940 tg3_free_rings(tp);
8941 } else {
David S. Millerfac9b832005-05-18 22:46:34 -07008942 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8943 tp->timer_offset = HZ;
8944 else
8945 tp->timer_offset = HZ / 10;
8946
8947 BUG_ON(tp->timer_offset > HZ);
8948 tp->timer_counter = tp->timer_multiplier =
8949 (HZ / tp->timer_offset);
8950 tp->asf_counter = tp->asf_multiplier =
Michael Chan28fbef72005-10-26 15:48:35 -07008951 ((HZ / tp->timer_offset) * 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008952
8953 init_timer(&tp->timer);
8954 tp->timer.expires = jiffies + tp->timer_offset;
8955 tp->timer.data = (unsigned long) tp;
8956 tp->timer.function = tg3_timer;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008957 }
8958
David S. Millerf47c11e2005-06-24 20:18:35 -07008959 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008960
Matt Carlson07b01732009-08-28 14:01:15 +00008961 if (err)
Matt Carlson679563f2009-09-01 12:55:46 +00008962 goto err_out3;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008963
Michael Chan79381092005-04-21 17:13:59 -07008964 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8965 err = tg3_test_msi(tp);
David S. Millerfac9b832005-05-18 22:46:34 -07008966
Michael Chan79381092005-04-21 17:13:59 -07008967 if (err) {
David S. Millerf47c11e2005-06-24 20:18:35 -07008968 tg3_full_lock(tp, 0);
Michael Chan944d9802005-05-29 14:57:48 -07008969 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Michael Chan79381092005-04-21 17:13:59 -07008970 tg3_free_rings(tp);
David S. Millerf47c11e2005-06-24 20:18:35 -07008971 tg3_full_unlock(tp);
Michael Chan79381092005-04-21 17:13:59 -07008972
Matt Carlson679563f2009-09-01 12:55:46 +00008973 goto err_out2;
Michael Chan79381092005-04-21 17:13:59 -07008974 }
Michael Chanfcfa0a32006-03-20 22:28:41 -08008975
Matt Carlsonc885e822010-08-02 11:25:57 +00008976 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8977 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00008978 u32 val = tr32(PCIE_TRANSACTION_CFG);
Michael Chanfcfa0a32006-03-20 22:28:41 -08008979
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00008980 tw32(PCIE_TRANSACTION_CFG,
8981 val | PCIE_TRANS_CFG_1SHOT_MSI);
Michael Chanfcfa0a32006-03-20 22:28:41 -08008982 }
Michael Chan79381092005-04-21 17:13:59 -07008983 }
8984
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07008985 tg3_phy_start(tp);
8986
David S. Millerf47c11e2005-06-24 20:18:35 -07008987 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008988
Michael Chan79381092005-04-21 17:13:59 -07008989 add_timer(&tp->timer);
8990 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008991 tg3_enable_ints(tp);
8992
David S. Millerf47c11e2005-06-24 20:18:35 -07008993 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008994
Matt Carlsonfe5f5782009-09-01 13:09:39 +00008995 netif_tx_start_all_queues(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008996
8997 return 0;
Matt Carlson07b01732009-08-28 14:01:15 +00008998
Matt Carlson679563f2009-09-01 12:55:46 +00008999err_out3:
Matt Carlson4f125f42009-09-01 12:55:02 +00009000 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9001 struct tg3_napi *tnapi = &tp->napi[i];
9002 free_irq(tnapi->irq_vec, tnapi);
9003 }
Matt Carlson07b01732009-08-28 14:01:15 +00009004
Matt Carlson679563f2009-09-01 12:55:46 +00009005err_out2:
Matt Carlsonfed97812009-09-01 13:10:19 +00009006 tg3_napi_disable(tp);
Matt Carlson07b01732009-08-28 14:01:15 +00009007 tg3_free_consistent(tp);
Matt Carlson679563f2009-09-01 12:55:46 +00009008
9009err_out1:
9010 tg3_ints_fini(tp);
Matt Carlson07b01732009-08-28 14:01:15 +00009011 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009012}
9013
Eric Dumazet511d2222010-07-07 20:44:24 +00009014static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9015 struct rtnl_link_stats64 *);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009016static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9017
9018static int tg3_close(struct net_device *dev)
9019{
Matt Carlson4f125f42009-09-01 12:55:02 +00009020 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009021 struct tg3 *tp = netdev_priv(dev);
9022
Matt Carlsonfed97812009-09-01 13:10:19 +00009023 tg3_napi_disable(tp);
Oleg Nesterov28e53bd2007-05-09 02:34:22 -07009024 cancel_work_sync(&tp->reset_task);
Michael Chan7faa0062006-02-02 17:29:28 -08009025
Matt Carlsonfe5f5782009-09-01 13:09:39 +00009026 netif_tx_stop_all_queues(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009027
9028 del_timer_sync(&tp->timer);
9029
Matt Carlson24bb4fb2009-10-05 17:55:29 +00009030 tg3_phy_stop(tp);
9031
David S. Millerf47c11e2005-06-24 20:18:35 -07009032 tg3_full_lock(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009033
9034 tg3_disable_ints(tp);
9035
Michael Chan944d9802005-05-29 14:57:48 -07009036 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009037 tg3_free_rings(tp);
Michael Chan5cf64b8a2007-05-05 12:11:21 -07009038 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009039
David S. Millerf47c11e2005-06-24 20:18:35 -07009040 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009041
Matt Carlson4f125f42009-09-01 12:55:02 +00009042 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9043 struct tg3_napi *tnapi = &tp->napi[i];
9044 free_irq(tnapi->irq_vec, tnapi);
9045 }
Matt Carlson07b01732009-08-28 14:01:15 +00009046
9047 tg3_ints_fini(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009048
Eric Dumazet511d2222010-07-07 20:44:24 +00009049 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9050
Linus Torvalds1da177e2005-04-16 15:20:36 -07009051 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9052 sizeof(tp->estats_prev));
9053
9054 tg3_free_consistent(tp);
9055
Michael Chanbc1c7562006-03-20 17:48:03 -08009056 tg3_set_power_state(tp, PCI_D3hot);
9057
9058 netif_carrier_off(tp->dev);
9059
Linus Torvalds1da177e2005-04-16 15:20:36 -07009060 return 0;
9061}
9062
Eric Dumazet511d2222010-07-07 20:44:24 +00009063static inline u64 get_stat64(tg3_stat64_t *val)
Stefan Buehler816f8b82008-08-15 14:10:54 -07009064{
9065 return ((u64)val->high << 32) | ((u64)val->low);
9066}
9067
Eric Dumazet511d2222010-07-07 20:44:24 +00009068static u64 calc_crc_errors(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009069{
9070 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9071
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009072 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07009073 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9074 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009075 u32 val;
9076
David S. Millerf47c11e2005-06-24 20:18:35 -07009077 spin_lock_bh(&tp->lock);
Michael Chan569a5df2007-02-13 12:18:15 -08009078 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9079 tg3_writephy(tp, MII_TG3_TEST1,
9080 val | MII_TG3_TEST1_CRC_EN);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00009081 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009082 } else
9083 val = 0;
David S. Millerf47c11e2005-06-24 20:18:35 -07009084 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009085
9086 tp->phy_crc_errors += val;
9087
9088 return tp->phy_crc_errors;
9089 }
9090
9091 return get_stat64(&hw_stats->rx_fcs_errors);
9092}
9093
9094#define ESTAT_ADD(member) \
9095 estats->member = old_estats->member + \
Eric Dumazet511d2222010-07-07 20:44:24 +00009096 get_stat64(&hw_stats->member)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009097
9098static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9099{
9100 struct tg3_ethtool_stats *estats = &tp->estats;
9101 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9102 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9103
9104 if (!hw_stats)
9105 return old_estats;
9106
9107 ESTAT_ADD(rx_octets);
9108 ESTAT_ADD(rx_fragments);
9109 ESTAT_ADD(rx_ucast_packets);
9110 ESTAT_ADD(rx_mcast_packets);
9111 ESTAT_ADD(rx_bcast_packets);
9112 ESTAT_ADD(rx_fcs_errors);
9113 ESTAT_ADD(rx_align_errors);
9114 ESTAT_ADD(rx_xon_pause_rcvd);
9115 ESTAT_ADD(rx_xoff_pause_rcvd);
9116 ESTAT_ADD(rx_mac_ctrl_rcvd);
9117 ESTAT_ADD(rx_xoff_entered);
9118 ESTAT_ADD(rx_frame_too_long_errors);
9119 ESTAT_ADD(rx_jabbers);
9120 ESTAT_ADD(rx_undersize_packets);
9121 ESTAT_ADD(rx_in_length_errors);
9122 ESTAT_ADD(rx_out_length_errors);
9123 ESTAT_ADD(rx_64_or_less_octet_packets);
9124 ESTAT_ADD(rx_65_to_127_octet_packets);
9125 ESTAT_ADD(rx_128_to_255_octet_packets);
9126 ESTAT_ADD(rx_256_to_511_octet_packets);
9127 ESTAT_ADD(rx_512_to_1023_octet_packets);
9128 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9129 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9130 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9131 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9132 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9133
9134 ESTAT_ADD(tx_octets);
9135 ESTAT_ADD(tx_collisions);
9136 ESTAT_ADD(tx_xon_sent);
9137 ESTAT_ADD(tx_xoff_sent);
9138 ESTAT_ADD(tx_flow_control);
9139 ESTAT_ADD(tx_mac_errors);
9140 ESTAT_ADD(tx_single_collisions);
9141 ESTAT_ADD(tx_mult_collisions);
9142 ESTAT_ADD(tx_deferred);
9143 ESTAT_ADD(tx_excessive_collisions);
9144 ESTAT_ADD(tx_late_collisions);
9145 ESTAT_ADD(tx_collide_2times);
9146 ESTAT_ADD(tx_collide_3times);
9147 ESTAT_ADD(tx_collide_4times);
9148 ESTAT_ADD(tx_collide_5times);
9149 ESTAT_ADD(tx_collide_6times);
9150 ESTAT_ADD(tx_collide_7times);
9151 ESTAT_ADD(tx_collide_8times);
9152 ESTAT_ADD(tx_collide_9times);
9153 ESTAT_ADD(tx_collide_10times);
9154 ESTAT_ADD(tx_collide_11times);
9155 ESTAT_ADD(tx_collide_12times);
9156 ESTAT_ADD(tx_collide_13times);
9157 ESTAT_ADD(tx_collide_14times);
9158 ESTAT_ADD(tx_collide_15times);
9159 ESTAT_ADD(tx_ucast_packets);
9160 ESTAT_ADD(tx_mcast_packets);
9161 ESTAT_ADD(tx_bcast_packets);
9162 ESTAT_ADD(tx_carrier_sense_errors);
9163 ESTAT_ADD(tx_discards);
9164 ESTAT_ADD(tx_errors);
9165
9166 ESTAT_ADD(dma_writeq_full);
9167 ESTAT_ADD(dma_write_prioq_full);
9168 ESTAT_ADD(rxbds_empty);
9169 ESTAT_ADD(rx_discards);
9170 ESTAT_ADD(rx_errors);
9171 ESTAT_ADD(rx_threshold_hit);
9172
9173 ESTAT_ADD(dma_readq_full);
9174 ESTAT_ADD(dma_read_prioq_full);
9175 ESTAT_ADD(tx_comp_queue_full);
9176
9177 ESTAT_ADD(ring_set_send_prod_index);
9178 ESTAT_ADD(ring_status_update);
9179 ESTAT_ADD(nic_irqs);
9180 ESTAT_ADD(nic_avoided_irqs);
9181 ESTAT_ADD(nic_tx_threshold_hit);
9182
9183 return estats;
9184}
9185
Eric Dumazet511d2222010-07-07 20:44:24 +00009186static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9187 struct rtnl_link_stats64 *stats)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009188{
9189 struct tg3 *tp = netdev_priv(dev);
Eric Dumazet511d2222010-07-07 20:44:24 +00009190 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009191 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9192
9193 if (!hw_stats)
9194 return old_stats;
9195
9196 stats->rx_packets = old_stats->rx_packets +
9197 get_stat64(&hw_stats->rx_ucast_packets) +
9198 get_stat64(&hw_stats->rx_mcast_packets) +
9199 get_stat64(&hw_stats->rx_bcast_packets);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009200
Linus Torvalds1da177e2005-04-16 15:20:36 -07009201 stats->tx_packets = old_stats->tx_packets +
9202 get_stat64(&hw_stats->tx_ucast_packets) +
9203 get_stat64(&hw_stats->tx_mcast_packets) +
9204 get_stat64(&hw_stats->tx_bcast_packets);
9205
9206 stats->rx_bytes = old_stats->rx_bytes +
9207 get_stat64(&hw_stats->rx_octets);
9208 stats->tx_bytes = old_stats->tx_bytes +
9209 get_stat64(&hw_stats->tx_octets);
9210
9211 stats->rx_errors = old_stats->rx_errors +
John W. Linville4f63b872005-09-12 14:43:18 -07009212 get_stat64(&hw_stats->rx_errors);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009213 stats->tx_errors = old_stats->tx_errors +
9214 get_stat64(&hw_stats->tx_errors) +
9215 get_stat64(&hw_stats->tx_mac_errors) +
9216 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9217 get_stat64(&hw_stats->tx_discards);
9218
9219 stats->multicast = old_stats->multicast +
9220 get_stat64(&hw_stats->rx_mcast_packets);
9221 stats->collisions = old_stats->collisions +
9222 get_stat64(&hw_stats->tx_collisions);
9223
9224 stats->rx_length_errors = old_stats->rx_length_errors +
9225 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9226 get_stat64(&hw_stats->rx_undersize_packets);
9227
9228 stats->rx_over_errors = old_stats->rx_over_errors +
9229 get_stat64(&hw_stats->rxbds_empty);
9230 stats->rx_frame_errors = old_stats->rx_frame_errors +
9231 get_stat64(&hw_stats->rx_align_errors);
9232 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9233 get_stat64(&hw_stats->tx_discards);
9234 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9235 get_stat64(&hw_stats->tx_carrier_sense_errors);
9236
9237 stats->rx_crc_errors = old_stats->rx_crc_errors +
9238 calc_crc_errors(tp);
9239
John W. Linville4f63b872005-09-12 14:43:18 -07009240 stats->rx_missed_errors = old_stats->rx_missed_errors +
9241 get_stat64(&hw_stats->rx_discards);
9242
Linus Torvalds1da177e2005-04-16 15:20:36 -07009243 return stats;
9244}
9245
9246static inline u32 calc_crc(unsigned char *buf, int len)
9247{
9248 u32 reg;
9249 u32 tmp;
9250 int j, k;
9251
9252 reg = 0xffffffff;
9253
9254 for (j = 0; j < len; j++) {
9255 reg ^= buf[j];
9256
9257 for (k = 0; k < 8; k++) {
9258 tmp = reg & 0x01;
9259
9260 reg >>= 1;
9261
Matt Carlson859a588792010-04-05 10:19:28 +00009262 if (tmp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009263 reg ^= 0xedb88320;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009264 }
9265 }
9266
9267 return ~reg;
9268}
9269
9270static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9271{
9272 /* accept or reject all multicast frames */
9273 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9274 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9275 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9276 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9277}
9278
9279static void __tg3_set_rx_mode(struct net_device *dev)
9280{
9281 struct tg3 *tp = netdev_priv(dev);
9282 u32 rx_mode;
9283
9284 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9285 RX_MODE_KEEP_VLAN_TAG);
9286
9287 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9288 * flag clear.
9289 */
9290#if TG3_VLAN_TAG_USED
9291 if (!tp->vlgrp &&
9292 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9293 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9294#else
9295 /* By definition, VLAN is disabled always in this
9296 * case.
9297 */
9298 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9299 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9300#endif
9301
9302 if (dev->flags & IFF_PROMISC) {
9303 /* Promiscuous mode. */
9304 rx_mode |= RX_MODE_PROMISC;
9305 } else if (dev->flags & IFF_ALLMULTI) {
9306 /* Accept all multicast. */
Matt Carlsonde6f31e2010-04-12 06:58:30 +00009307 tg3_set_multi(tp, 1);
Jiri Pirko4cd24ea2010-02-08 04:30:35 +00009308 } else if (netdev_mc_empty(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009309 /* Reject all multicast. */
Matt Carlsonde6f31e2010-04-12 06:58:30 +00009310 tg3_set_multi(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009311 } else {
9312 /* Accept one or more multicast(s). */
Jiri Pirko22bedad32010-04-01 21:22:57 +00009313 struct netdev_hw_addr *ha;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009314 u32 mc_filter[4] = { 0, };
9315 u32 regidx;
9316 u32 bit;
9317 u32 crc;
9318
Jiri Pirko22bedad32010-04-01 21:22:57 +00009319 netdev_for_each_mc_addr(ha, dev) {
9320 crc = calc_crc(ha->addr, ETH_ALEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009321 bit = ~crc & 0x7f;
9322 regidx = (bit & 0x60) >> 5;
9323 bit &= 0x1f;
9324 mc_filter[regidx] |= (1 << bit);
9325 }
9326
9327 tw32(MAC_HASH_REG_0, mc_filter[0]);
9328 tw32(MAC_HASH_REG_1, mc_filter[1]);
9329 tw32(MAC_HASH_REG_2, mc_filter[2]);
9330 tw32(MAC_HASH_REG_3, mc_filter[3]);
9331 }
9332
9333 if (rx_mode != tp->rx_mode) {
9334 tp->rx_mode = rx_mode;
9335 tw32_f(MAC_RX_MODE, rx_mode);
9336 udelay(10);
9337 }
9338}
9339
9340static void tg3_set_rx_mode(struct net_device *dev)
9341{
9342 struct tg3 *tp = netdev_priv(dev);
9343
Michael Chane75f7c92006-03-20 21:33:26 -08009344 if (!netif_running(dev))
9345 return;
9346
David S. Millerf47c11e2005-06-24 20:18:35 -07009347 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009348 __tg3_set_rx_mode(dev);
David S. Millerf47c11e2005-06-24 20:18:35 -07009349 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009350}
9351
9352#define TG3_REGDUMP_LEN (32 * 1024)
9353
9354static int tg3_get_regs_len(struct net_device *dev)
9355{
9356 return TG3_REGDUMP_LEN;
9357}
9358
9359static void tg3_get_regs(struct net_device *dev,
9360 struct ethtool_regs *regs, void *_p)
9361{
9362 u32 *p = _p;
9363 struct tg3 *tp = netdev_priv(dev);
9364 u8 *orig_p = _p;
9365 int i;
9366
9367 regs->version = 0;
9368
9369 memset(p, 0, TG3_REGDUMP_LEN);
9370
Matt Carlson800960682010-08-02 11:26:06 +00009371 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Michael Chanbc1c7562006-03-20 17:48:03 -08009372 return;
9373
David S. Millerf47c11e2005-06-24 20:18:35 -07009374 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009375
9376#define __GET_REG32(reg) (*(p)++ = tr32(reg))
Matt Carlsonbe98da62010-07-11 09:31:46 +00009377#define GET_REG32_LOOP(base, len) \
Linus Torvalds1da177e2005-04-16 15:20:36 -07009378do { p = (u32 *)(orig_p + (base)); \
9379 for (i = 0; i < len; i += 4) \
9380 __GET_REG32((base) + i); \
9381} while (0)
9382#define GET_REG32_1(reg) \
9383do { p = (u32 *)(orig_p + (reg)); \
9384 __GET_REG32((reg)); \
9385} while (0)
9386
9387 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9388 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9389 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9390 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9391 GET_REG32_1(SNDDATAC_MODE);
9392 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9393 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9394 GET_REG32_1(SNDBDC_MODE);
9395 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9396 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9397 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9398 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9399 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9400 GET_REG32_1(RCVDCC_MODE);
9401 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9402 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9403 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9404 GET_REG32_1(MBFREE_MODE);
9405 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9406 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9407 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9408 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9409 GET_REG32_LOOP(WDMAC_MODE, 0x08);
Chris Elmquist091465d2005-12-20 13:25:19 -08009410 GET_REG32_1(RX_CPU_MODE);
9411 GET_REG32_1(RX_CPU_STATE);
9412 GET_REG32_1(RX_CPU_PGMCTR);
9413 GET_REG32_1(RX_CPU_HWBKPT);
9414 GET_REG32_1(TX_CPU_MODE);
9415 GET_REG32_1(TX_CPU_STATE);
9416 GET_REG32_1(TX_CPU_PGMCTR);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009417 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9418 GET_REG32_LOOP(FTQ_RESET, 0x120);
9419 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9420 GET_REG32_1(DMAC_MODE);
9421 GET_REG32_LOOP(GRC_MODE, 0x4c);
9422 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9423 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9424
9425#undef __GET_REG32
9426#undef GET_REG32_LOOP
9427#undef GET_REG32_1
9428
David S. Millerf47c11e2005-06-24 20:18:35 -07009429 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009430}
9431
9432static int tg3_get_eeprom_len(struct net_device *dev)
9433{
9434 struct tg3 *tp = netdev_priv(dev);
9435
9436 return tp->nvram_size;
9437}
9438
Linus Torvalds1da177e2005-04-16 15:20:36 -07009439static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9440{
9441 struct tg3 *tp = netdev_priv(dev);
9442 int ret;
9443 u8 *pd;
Al Virob9fc7dc2007-12-17 22:59:57 -08009444 u32 i, offset, len, b_offset, b_count;
Matt Carlsona9dc5292009-02-25 14:25:30 +00009445 __be32 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009446
Matt Carlsondf259d82009-04-20 06:57:14 +00009447 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9448 return -EINVAL;
9449
Matt Carlson800960682010-08-02 11:26:06 +00009450 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Michael Chanbc1c7562006-03-20 17:48:03 -08009451 return -EAGAIN;
9452
Linus Torvalds1da177e2005-04-16 15:20:36 -07009453 offset = eeprom->offset;
9454 len = eeprom->len;
9455 eeprom->len = 0;
9456
9457 eeprom->magic = TG3_EEPROM_MAGIC;
9458
9459 if (offset & 3) {
9460 /* adjustments to start on required 4 byte boundary */
9461 b_offset = offset & 3;
9462 b_count = 4 - b_offset;
9463 if (b_count > len) {
9464 /* i.e. offset=1 len=2 */
9465 b_count = len;
9466 }
Matt Carlsona9dc5292009-02-25 14:25:30 +00009467 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009468 if (ret)
9469 return ret;
Matt Carlsonbe98da62010-07-11 09:31:46 +00009470 memcpy(data, ((char *)&val) + b_offset, b_count);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009471 len -= b_count;
9472 offset += b_count;
Matt Carlsonc6cdf432010-04-05 10:19:26 +00009473 eeprom->len += b_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009474 }
9475
9476 /* read bytes upto the last 4 byte boundary */
9477 pd = &data[eeprom->len];
9478 for (i = 0; i < (len - (len & 3)); i += 4) {
Matt Carlsona9dc5292009-02-25 14:25:30 +00009479 ret = tg3_nvram_read_be32(tp, offset + i, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009480 if (ret) {
9481 eeprom->len += i;
9482 return ret;
9483 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009484 memcpy(pd + i, &val, 4);
9485 }
9486 eeprom->len += i;
9487
9488 if (len & 3) {
9489 /* read last bytes not ending on 4 byte boundary */
9490 pd = &data[eeprom->len];
9491 b_count = len & 3;
9492 b_offset = offset + len - b_count;
Matt Carlsona9dc5292009-02-25 14:25:30 +00009493 ret = tg3_nvram_read_be32(tp, b_offset, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009494 if (ret)
9495 return ret;
Al Virob9fc7dc2007-12-17 22:59:57 -08009496 memcpy(pd, &val, b_count);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009497 eeprom->len += b_count;
9498 }
9499 return 0;
9500}
9501
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009502static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009503
9504static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9505{
9506 struct tg3 *tp = netdev_priv(dev);
9507 int ret;
Al Virob9fc7dc2007-12-17 22:59:57 -08009508 u32 offset, len, b_offset, odd_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009509 u8 *buf;
Matt Carlsona9dc5292009-02-25 14:25:30 +00009510 __be32 start, end;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009511
Matt Carlson800960682010-08-02 11:26:06 +00009512 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Michael Chanbc1c7562006-03-20 17:48:03 -08009513 return -EAGAIN;
9514
Matt Carlsondf259d82009-04-20 06:57:14 +00009515 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9516 eeprom->magic != TG3_EEPROM_MAGIC)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009517 return -EINVAL;
9518
9519 offset = eeprom->offset;
9520 len = eeprom->len;
9521
9522 if ((b_offset = (offset & 3))) {
9523 /* adjustments to start on required 4 byte boundary */
Matt Carlsona9dc5292009-02-25 14:25:30 +00009524 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009525 if (ret)
9526 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009527 len += b_offset;
9528 offset &= ~3;
Michael Chan1c8594b2005-04-21 17:12:46 -07009529 if (len < 4)
9530 len = 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009531 }
9532
9533 odd_len = 0;
Michael Chan1c8594b2005-04-21 17:12:46 -07009534 if (len & 3) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009535 /* adjustments to end on required 4 byte boundary */
9536 odd_len = 1;
9537 len = (len + 3) & ~3;
Matt Carlsona9dc5292009-02-25 14:25:30 +00009538 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009539 if (ret)
9540 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009541 }
9542
9543 buf = data;
9544 if (b_offset || odd_len) {
9545 buf = kmalloc(len, GFP_KERNEL);
Andy Gospodarekab0049b2007-09-06 20:42:14 +01009546 if (!buf)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009547 return -ENOMEM;
9548 if (b_offset)
9549 memcpy(buf, &start, 4);
9550 if (odd_len)
9551 memcpy(buf+len-4, &end, 4);
9552 memcpy(buf + b_offset, data, eeprom->len);
9553 }
9554
9555 ret = tg3_nvram_write_block(tp, offset, len, buf);
9556
9557 if (buf != data)
9558 kfree(buf);
9559
9560 return ret;
9561}
9562
9563static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9564{
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009565 struct tg3 *tp = netdev_priv(dev);
9566
9567 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00009568 struct phy_device *phydev;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009569 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009570 return -EAGAIN;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00009571 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9572 return phy_ethtool_gset(phydev, cmd);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009573 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009574
Linus Torvalds1da177e2005-04-16 15:20:36 -07009575 cmd->supported = (SUPPORTED_Autoneg);
9576
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009577 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
Linus Torvalds1da177e2005-04-16 15:20:36 -07009578 cmd->supported |= (SUPPORTED_1000baseT_Half |
9579 SUPPORTED_1000baseT_Full);
9580
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009581 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009582 cmd->supported |= (SUPPORTED_100baseT_Half |
9583 SUPPORTED_100baseT_Full |
9584 SUPPORTED_10baseT_Half |
9585 SUPPORTED_10baseT_Full |
Matt Carlson3bebab52007-11-12 21:22:40 -08009586 SUPPORTED_TP);
Karsten Keilef348142006-05-12 12:49:08 -07009587 cmd->port = PORT_TP;
9588 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009589 cmd->supported |= SUPPORTED_FIBRE;
Karsten Keilef348142006-05-12 12:49:08 -07009590 cmd->port = PORT_FIBRE;
9591 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009592
Linus Torvalds1da177e2005-04-16 15:20:36 -07009593 cmd->advertising = tp->link_config.advertising;
9594 if (netif_running(dev)) {
9595 cmd->speed = tp->link_config.active_speed;
9596 cmd->duplex = tp->link_config.active_duplex;
9597 }
Matt Carlson882e9792009-09-01 13:21:36 +00009598 cmd->phy_address = tp->phy_addr;
Matt Carlson7e5856b2009-02-25 14:23:01 +00009599 cmd->transceiver = XCVR_INTERNAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009600 cmd->autoneg = tp->link_config.autoneg;
9601 cmd->maxtxpkt = 0;
9602 cmd->maxrxpkt = 0;
9603 return 0;
9604}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009605
Linus Torvalds1da177e2005-04-16 15:20:36 -07009606static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9607{
9608 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009609
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009610 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00009611 struct phy_device *phydev;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009612 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009613 return -EAGAIN;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00009614 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9615 return phy_ethtool_sset(phydev, cmd);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009616 }
9617
Matt Carlson7e5856b2009-02-25 14:23:01 +00009618 if (cmd->autoneg != AUTONEG_ENABLE &&
9619 cmd->autoneg != AUTONEG_DISABLE)
Michael Chan37ff2382005-10-26 15:49:51 -07009620 return -EINVAL;
Matt Carlson7e5856b2009-02-25 14:23:01 +00009621
9622 if (cmd->autoneg == AUTONEG_DISABLE &&
9623 cmd->duplex != DUPLEX_FULL &&
9624 cmd->duplex != DUPLEX_HALF)
Michael Chan37ff2382005-10-26 15:49:51 -07009625 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009626
Matt Carlson7e5856b2009-02-25 14:23:01 +00009627 if (cmd->autoneg == AUTONEG_ENABLE) {
9628 u32 mask = ADVERTISED_Autoneg |
9629 ADVERTISED_Pause |
9630 ADVERTISED_Asym_Pause;
9631
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009632 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
Matt Carlson7e5856b2009-02-25 14:23:01 +00009633 mask |= ADVERTISED_1000baseT_Half |
9634 ADVERTISED_1000baseT_Full;
9635
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009636 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
Matt Carlson7e5856b2009-02-25 14:23:01 +00009637 mask |= ADVERTISED_100baseT_Half |
9638 ADVERTISED_100baseT_Full |
9639 ADVERTISED_10baseT_Half |
9640 ADVERTISED_10baseT_Full |
9641 ADVERTISED_TP;
9642 else
9643 mask |= ADVERTISED_FIBRE;
9644
9645 if (cmd->advertising & ~mask)
9646 return -EINVAL;
9647
9648 mask &= (ADVERTISED_1000baseT_Half |
9649 ADVERTISED_1000baseT_Full |
9650 ADVERTISED_100baseT_Half |
9651 ADVERTISED_100baseT_Full |
9652 ADVERTISED_10baseT_Half |
9653 ADVERTISED_10baseT_Full);
9654
9655 cmd->advertising &= mask;
9656 } else {
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009657 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
Matt Carlson7e5856b2009-02-25 14:23:01 +00009658 if (cmd->speed != SPEED_1000)
9659 return -EINVAL;
9660
9661 if (cmd->duplex != DUPLEX_FULL)
9662 return -EINVAL;
9663 } else {
9664 if (cmd->speed != SPEED_100 &&
9665 cmd->speed != SPEED_10)
9666 return -EINVAL;
9667 }
9668 }
9669
David S. Millerf47c11e2005-06-24 20:18:35 -07009670 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009671
9672 tp->link_config.autoneg = cmd->autoneg;
9673 if (cmd->autoneg == AUTONEG_ENABLE) {
Andy Gospodarek405d8e52007-10-08 01:08:47 -07009674 tp->link_config.advertising = (cmd->advertising |
9675 ADVERTISED_Autoneg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009676 tp->link_config.speed = SPEED_INVALID;
9677 tp->link_config.duplex = DUPLEX_INVALID;
9678 } else {
9679 tp->link_config.advertising = 0;
9680 tp->link_config.speed = cmd->speed;
9681 tp->link_config.duplex = cmd->duplex;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009682 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009683
Michael Chan24fcad62006-12-17 17:06:46 -08009684 tp->link_config.orig_speed = tp->link_config.speed;
9685 tp->link_config.orig_duplex = tp->link_config.duplex;
9686 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9687
Linus Torvalds1da177e2005-04-16 15:20:36 -07009688 if (netif_running(dev))
9689 tg3_setup_phy(tp, 1);
9690
David S. Millerf47c11e2005-06-24 20:18:35 -07009691 tg3_full_unlock(tp);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009692
Linus Torvalds1da177e2005-04-16 15:20:36 -07009693 return 0;
9694}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009695
Linus Torvalds1da177e2005-04-16 15:20:36 -07009696static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9697{
9698 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009699
Linus Torvalds1da177e2005-04-16 15:20:36 -07009700 strcpy(info->driver, DRV_MODULE_NAME);
9701 strcpy(info->version, DRV_MODULE_VERSION);
Michael Chanc4e65752006-03-20 22:29:32 -08009702 strcpy(info->fw_version, tp->fw_ver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009703 strcpy(info->bus_info, pci_name(tp->pdev));
9704}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009705
Linus Torvalds1da177e2005-04-16 15:20:36 -07009706static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9707{
9708 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009709
Rafael J. Wysocki12dac072008-07-30 16:37:33 -07009710 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9711 device_can_wakeup(&tp->pdev->dev))
Gary Zambranoa85feb82007-05-05 11:52:19 -07009712 wol->supported = WAKE_MAGIC;
9713 else
9714 wol->supported = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009715 wol->wolopts = 0;
Matt Carlson05ac4cb2008-11-03 16:53:46 -08009716 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9717 device_can_wakeup(&tp->pdev->dev))
Linus Torvalds1da177e2005-04-16 15:20:36 -07009718 wol->wolopts = WAKE_MAGIC;
9719 memset(&wol->sopass, 0, sizeof(wol->sopass));
9720}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009721
Linus Torvalds1da177e2005-04-16 15:20:36 -07009722static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9723{
9724 struct tg3 *tp = netdev_priv(dev);
Rafael J. Wysocki12dac072008-07-30 16:37:33 -07009725 struct device *dp = &tp->pdev->dev;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009726
Linus Torvalds1da177e2005-04-16 15:20:36 -07009727 if (wol->wolopts & ~WAKE_MAGIC)
9728 return -EINVAL;
9729 if ((wol->wolopts & WAKE_MAGIC) &&
Rafael J. Wysocki12dac072008-07-30 16:37:33 -07009730 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
Linus Torvalds1da177e2005-04-16 15:20:36 -07009731 return -EINVAL;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009732
David S. Millerf47c11e2005-06-24 20:18:35 -07009733 spin_lock_bh(&tp->lock);
Rafael J. Wysocki12dac072008-07-30 16:37:33 -07009734 if (wol->wolopts & WAKE_MAGIC) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009735 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
Rafael J. Wysocki12dac072008-07-30 16:37:33 -07009736 device_set_wakeup_enable(dp, true);
9737 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009738 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
Rafael J. Wysocki12dac072008-07-30 16:37:33 -07009739 device_set_wakeup_enable(dp, false);
9740 }
David S. Millerf47c11e2005-06-24 20:18:35 -07009741 spin_unlock_bh(&tp->lock);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009742
Linus Torvalds1da177e2005-04-16 15:20:36 -07009743 return 0;
9744}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009745
Linus Torvalds1da177e2005-04-16 15:20:36 -07009746static u32 tg3_get_msglevel(struct net_device *dev)
9747{
9748 struct tg3 *tp = netdev_priv(dev);
9749 return tp->msg_enable;
9750}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009751
Linus Torvalds1da177e2005-04-16 15:20:36 -07009752static void tg3_set_msglevel(struct net_device *dev, u32 value)
9753{
9754 struct tg3 *tp = netdev_priv(dev);
9755 tp->msg_enable = value;
9756}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009757
Linus Torvalds1da177e2005-04-16 15:20:36 -07009758static int tg3_set_tso(struct net_device *dev, u32 value)
9759{
9760 struct tg3 *tp = netdev_priv(dev);
9761
9762 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9763 if (value)
9764 return -EINVAL;
9765 return 0;
9766 }
Matt Carlson027455a2008-12-21 20:19:30 -08009767 if ((dev->features & NETIF_F_IPV6_CSUM) &&
Matt Carlsone849cdc2009-11-13 13:03:38 +00009768 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9769 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
Matt Carlson9936bcf2007-10-10 18:03:07 -07009770 if (value) {
Michael Chanb0026622006-07-03 19:42:14 -07009771 dev->features |= NETIF_F_TSO6;
Matt Carlsone849cdc2009-11-13 13:03:38 +00009772 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9773 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
Matt Carlson57e69832008-05-25 23:48:31 -07009774 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9775 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
Matt Carlson321d32a2008-11-21 17:22:19 -08009776 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
Matt Carlsone849cdc2009-11-13 13:03:38 +00009777 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
Matt Carlson9936bcf2007-10-10 18:03:07 -07009778 dev->features |= NETIF_F_TSO_ECN;
9779 } else
9780 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
Michael Chanb0026622006-07-03 19:42:14 -07009781 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009782 return ethtool_op_set_tso(dev, value);
9783}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009784
Linus Torvalds1da177e2005-04-16 15:20:36 -07009785static int tg3_nway_reset(struct net_device *dev)
9786{
9787 struct tg3 *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009788 int r;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009789
Linus Torvalds1da177e2005-04-16 15:20:36 -07009790 if (!netif_running(dev))
9791 return -EAGAIN;
9792
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009793 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Michael Chanc94e3942005-09-27 12:12:42 -07009794 return -EINVAL;
9795
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009796 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009797 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009798 return -EAGAIN;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00009799 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009800 } else {
9801 u32 bmcr;
9802
9803 spin_lock_bh(&tp->lock);
9804 r = -EINVAL;
9805 tg3_readphy(tp, MII_BMCR, &bmcr);
9806 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9807 ((bmcr & BMCR_ANENABLE) ||
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009808 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009809 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9810 BMCR_ANENABLE);
9811 r = 0;
9812 }
9813 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009814 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009815
Linus Torvalds1da177e2005-04-16 15:20:36 -07009816 return r;
9817}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009818
Linus Torvalds1da177e2005-04-16 15:20:36 -07009819static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9820{
9821 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009822
Linus Torvalds1da177e2005-04-16 15:20:36 -07009823 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9824 ering->rx_mini_max_pending = 0;
Michael Chan4f81c322006-03-20 21:33:42 -08009825 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9826 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9827 else
9828 ering->rx_jumbo_max_pending = 0;
9829
9830 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009831
9832 ering->rx_pending = tp->rx_pending;
9833 ering->rx_mini_pending = 0;
Michael Chan4f81c322006-03-20 21:33:42 -08009834 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9835 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9836 else
9837 ering->rx_jumbo_pending = 0;
9838
Matt Carlsonf3f3f272009-08-28 14:03:21 +00009839 ering->tx_pending = tp->napi[0].tx_pending;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009840}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009841
Linus Torvalds1da177e2005-04-16 15:20:36 -07009842static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9843{
9844 struct tg3 *tp = netdev_priv(dev);
Matt Carlson646c9ed2009-09-01 12:58:41 +00009845 int i, irq_sync = 0, err = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009846
Linus Torvalds1da177e2005-04-16 15:20:36 -07009847 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9848 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
Michael Chanbc3a9252006-10-18 20:55:18 -07009849 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9850 (ering->tx_pending <= MAX_SKB_FRAGS) ||
Michael Chan7f62ad52007-02-20 23:25:40 -08009851 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
Michael Chanbc3a9252006-10-18 20:55:18 -07009852 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
Linus Torvalds1da177e2005-04-16 15:20:36 -07009853 return -EINVAL;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009854
Michael Chanbbe832c2005-06-24 20:20:04 -07009855 if (netif_running(dev)) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009856 tg3_phy_stop(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009857 tg3_netif_stop(tp);
Michael Chanbbe832c2005-06-24 20:20:04 -07009858 irq_sync = 1;
9859 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009860
Michael Chanbbe832c2005-06-24 20:20:04 -07009861 tg3_full_lock(tp, irq_sync);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009862
Linus Torvalds1da177e2005-04-16 15:20:36 -07009863 tp->rx_pending = ering->rx_pending;
9864
9865 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9866 tp->rx_pending > 63)
9867 tp->rx_pending = 63;
9868 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
Matt Carlson646c9ed2009-09-01 12:58:41 +00009869
9870 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9871 tp->napi[i].tx_pending = ering->tx_pending;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009872
9873 if (netif_running(dev)) {
Michael Chan944d9802005-05-29 14:57:48 -07009874 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Michael Chanb9ec6c12006-07-25 16:37:27 -07009875 err = tg3_restart_hw(tp, 1);
9876 if (!err)
9877 tg3_netif_start(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009878 }
9879
David S. Millerf47c11e2005-06-24 20:18:35 -07009880 tg3_full_unlock(tp);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009881
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009882 if (irq_sync && !err)
9883 tg3_phy_start(tp);
9884
Michael Chanb9ec6c12006-07-25 16:37:27 -07009885 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009886}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009887
Linus Torvalds1da177e2005-04-16 15:20:36 -07009888static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9889{
9890 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009891
Linus Torvalds1da177e2005-04-16 15:20:36 -07009892 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
Matt Carlson8d018622007-12-20 20:05:44 -08009893
Steve Glendinninge18ce342008-12-16 02:00:00 -08009894 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
Matt Carlson8d018622007-12-20 20:05:44 -08009895 epause->rx_pause = 1;
9896 else
9897 epause->rx_pause = 0;
9898
Steve Glendinninge18ce342008-12-16 02:00:00 -08009899 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
Matt Carlson8d018622007-12-20 20:05:44 -08009900 epause->tx_pause = 1;
9901 else
9902 epause->tx_pause = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009903}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009904
Linus Torvalds1da177e2005-04-16 15:20:36 -07009905static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9906{
9907 struct tg3 *tp = netdev_priv(dev);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009908 int err = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009909
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009910 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
Matt Carlson27121682010-02-17 15:16:57 +00009911 u32 newadv;
9912 struct phy_device *phydev;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009913
Matt Carlson27121682010-02-17 15:16:57 +00009914 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009915
Matt Carlson27121682010-02-17 15:16:57 +00009916 if (!(phydev->supported & SUPPORTED_Pause) ||
9917 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9918 ((epause->rx_pause && !epause->tx_pause) ||
9919 (!epause->rx_pause && epause->tx_pause))))
9920 return -EINVAL;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009921
Matt Carlson27121682010-02-17 15:16:57 +00009922 tp->link_config.flowctrl = 0;
9923 if (epause->rx_pause) {
9924 tp->link_config.flowctrl |= FLOW_CTRL_RX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009925
Matt Carlson27121682010-02-17 15:16:57 +00009926 if (epause->tx_pause) {
Steve Glendinninge18ce342008-12-16 02:00:00 -08009927 tp->link_config.flowctrl |= FLOW_CTRL_TX;
Matt Carlson27121682010-02-17 15:16:57 +00009928 newadv = ADVERTISED_Pause;
9929 } else
9930 newadv = ADVERTISED_Pause |
9931 ADVERTISED_Asym_Pause;
9932 } else if (epause->tx_pause) {
9933 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9934 newadv = ADVERTISED_Asym_Pause;
9935 } else
9936 newadv = 0;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009937
Matt Carlson27121682010-02-17 15:16:57 +00009938 if (epause->autoneg)
9939 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9940 else
9941 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9942
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009943 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
Matt Carlson27121682010-02-17 15:16:57 +00009944 u32 oldadv = phydev->advertising &
9945 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9946 if (oldadv != newadv) {
9947 phydev->advertising &=
9948 ~(ADVERTISED_Pause |
9949 ADVERTISED_Asym_Pause);
9950 phydev->advertising |= newadv;
9951 if (phydev->autoneg) {
9952 /*
9953 * Always renegotiate the link to
9954 * inform our link partner of our
9955 * flow control settings, even if the
9956 * flow control is forced. Let
9957 * tg3_adjust_link() do the final
9958 * flow control setup.
9959 */
9960 return phy_start_aneg(phydev);
9961 }
9962 }
9963
9964 if (!epause->autoneg)
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009965 tg3_setup_flow_control(tp, 0, 0);
Matt Carlson27121682010-02-17 15:16:57 +00009966 } else {
9967 tp->link_config.orig_advertising &=
9968 ~(ADVERTISED_Pause |
9969 ADVERTISED_Asym_Pause);
9970 tp->link_config.orig_advertising |= newadv;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009971 }
9972 } else {
9973 int irq_sync = 0;
9974
9975 if (netif_running(dev)) {
9976 tg3_netif_stop(tp);
9977 irq_sync = 1;
9978 }
9979
9980 tg3_full_lock(tp, irq_sync);
9981
9982 if (epause->autoneg)
9983 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9984 else
9985 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9986 if (epause->rx_pause)
Steve Glendinninge18ce342008-12-16 02:00:00 -08009987 tp->link_config.flowctrl |= FLOW_CTRL_RX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009988 else
Steve Glendinninge18ce342008-12-16 02:00:00 -08009989 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009990 if (epause->tx_pause)
Steve Glendinninge18ce342008-12-16 02:00:00 -08009991 tp->link_config.flowctrl |= FLOW_CTRL_TX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009992 else
Steve Glendinninge18ce342008-12-16 02:00:00 -08009993 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009994
9995 if (netif_running(dev)) {
9996 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9997 err = tg3_restart_hw(tp, 1);
9998 if (!err)
9999 tg3_netif_start(tp);
10000 }
10001
10002 tg3_full_unlock(tp);
Michael Chanbbe832c2005-06-24 20:20:04 -070010003 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070010004
Michael Chanb9ec6c12006-07-25 16:37:27 -070010005 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010006}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010007
Linus Torvalds1da177e2005-04-16 15:20:36 -070010008static u32 tg3_get_rx_csum(struct net_device *dev)
10009{
10010 struct tg3 *tp = netdev_priv(dev);
10011 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10012}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010013
Linus Torvalds1da177e2005-04-16 15:20:36 -070010014static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10015{
10016 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010017
Linus Torvalds1da177e2005-04-16 15:20:36 -070010018 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10019 if (data != 0)
10020 return -EINVAL;
Matt Carlsonc6cdf432010-04-05 10:19:26 +000010021 return 0;
10022 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010023
David S. Millerf47c11e2005-06-24 20:18:35 -070010024 spin_lock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010025 if (data)
10026 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10027 else
10028 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
David S. Millerf47c11e2005-06-24 20:18:35 -070010029 spin_unlock_bh(&tp->lock);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010030
Linus Torvalds1da177e2005-04-16 15:20:36 -070010031 return 0;
10032}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010033
Linus Torvalds1da177e2005-04-16 15:20:36 -070010034static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10035{
10036 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010037
Linus Torvalds1da177e2005-04-16 15:20:36 -070010038 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10039 if (data != 0)
10040 return -EINVAL;
Matt Carlsonc6cdf432010-04-05 10:19:26 +000010041 return 0;
10042 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010043
Matt Carlson321d32a2008-11-21 17:22:19 -080010044 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
Michael Chan6460d942007-07-14 19:07:52 -070010045 ethtool_op_set_tx_ipv6_csum(dev, data);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010046 else
Michael Chan9c27dbd2006-03-20 22:28:27 -080010047 ethtool_op_set_tx_csum(dev, data);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010048
10049 return 0;
10050}
10051
Matt Carlsonde6f31e2010-04-12 06:58:30 +000010052static int tg3_get_sset_count(struct net_device *dev, int sset)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010053{
Jeff Garzikb9f2c042007-10-03 18:07:32 -070010054 switch (sset) {
10055 case ETH_SS_TEST:
10056 return TG3_NUM_TEST;
10057 case ETH_SS_STATS:
10058 return TG3_NUM_STATS;
10059 default:
10060 return -EOPNOTSUPP;
10061 }
Michael Chan4cafd3f2005-05-29 14:56:34 -070010062}
10063
Matt Carlsonde6f31e2010-04-12 06:58:30 +000010064static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010065{
10066 switch (stringset) {
10067 case ETH_SS_STATS:
10068 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10069 break;
Michael Chan4cafd3f2005-05-29 14:56:34 -070010070 case ETH_SS_TEST:
10071 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10072 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010073 default:
10074 WARN_ON(1); /* we need a WARN() */
10075 break;
10076 }
10077}
10078
Michael Chan4009a932005-09-05 17:52:54 -070010079static int tg3_phys_id(struct net_device *dev, u32 data)
10080{
10081 struct tg3 *tp = netdev_priv(dev);
10082 int i;
10083
10084 if (!netif_running(tp->dev))
10085 return -EAGAIN;
10086
10087 if (data == 0)
Stephen Hemminger759afc32008-02-23 19:51:59 -080010088 data = UINT_MAX / 2;
Michael Chan4009a932005-09-05 17:52:54 -070010089
10090 for (i = 0; i < (data * 2); i++) {
10091 if ((i % 2) == 0)
10092 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10093 LED_CTRL_1000MBPS_ON |
10094 LED_CTRL_100MBPS_ON |
10095 LED_CTRL_10MBPS_ON |
10096 LED_CTRL_TRAFFIC_OVERRIDE |
10097 LED_CTRL_TRAFFIC_BLINK |
10098 LED_CTRL_TRAFFIC_LED);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010099
Michael Chan4009a932005-09-05 17:52:54 -070010100 else
10101 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10102 LED_CTRL_TRAFFIC_OVERRIDE);
10103
10104 if (msleep_interruptible(500))
10105 break;
10106 }
10107 tw32(MAC_LED_CTRL, tp->led_ctrl);
10108 return 0;
10109}
10110
Matt Carlsonde6f31e2010-04-12 06:58:30 +000010111static void tg3_get_ethtool_stats(struct net_device *dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -070010112 struct ethtool_stats *estats, u64 *tmp_stats)
10113{
10114 struct tg3 *tp = netdev_priv(dev);
10115 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10116}
10117
Michael Chan566f86a2005-05-29 14:56:58 -070010118#define NVRAM_TEST_SIZE 0x100
Matt Carlsona5767de2007-11-12 21:10:58 -080010119#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10120#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10121#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
Michael Chanb16250e2006-09-27 16:10:14 -070010122#define NVRAM_SELFBOOT_HW_SIZE 0x20
10123#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
Michael Chan566f86a2005-05-29 14:56:58 -070010124
10125static int tg3_test_nvram(struct tg3 *tp)
10126{
Al Virob9fc7dc2007-12-17 22:59:57 -080010127 u32 csum, magic;
Matt Carlsona9dc5292009-02-25 14:25:30 +000010128 __be32 *buf;
Andy Gospodarekab0049b2007-09-06 20:42:14 +010010129 int i, j, k, err = 0, size;
Michael Chan566f86a2005-05-29 14:56:58 -070010130
Matt Carlsondf259d82009-04-20 06:57:14 +000010131 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10132 return 0;
10133
Matt Carlsone4f34112009-02-25 14:25:00 +000010134 if (tg3_nvram_read(tp, 0, &magic) != 0)
Michael Chan1b277772006-03-20 22:27:48 -080010135 return -EIO;
10136
Michael Chan1b277772006-03-20 22:27:48 -080010137 if (magic == TG3_EEPROM_MAGIC)
10138 size = NVRAM_TEST_SIZE;
Michael Chanb16250e2006-09-27 16:10:14 -070010139 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
Matt Carlsona5767de2007-11-12 21:10:58 -080010140 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10141 TG3_EEPROM_SB_FORMAT_1) {
10142 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10143 case TG3_EEPROM_SB_REVISION_0:
10144 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10145 break;
10146 case TG3_EEPROM_SB_REVISION_2:
10147 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10148 break;
10149 case TG3_EEPROM_SB_REVISION_3:
10150 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10151 break;
10152 default:
10153 return 0;
10154 }
10155 } else
Michael Chan1b277772006-03-20 22:27:48 -080010156 return 0;
Michael Chanb16250e2006-09-27 16:10:14 -070010157 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10158 size = NVRAM_SELFBOOT_HW_SIZE;
10159 else
Michael Chan1b277772006-03-20 22:27:48 -080010160 return -EIO;
10161
10162 buf = kmalloc(size, GFP_KERNEL);
Michael Chan566f86a2005-05-29 14:56:58 -070010163 if (buf == NULL)
10164 return -ENOMEM;
10165
Michael Chan1b277772006-03-20 22:27:48 -080010166 err = -EIO;
10167 for (i = 0, j = 0; i < size; i += 4, j++) {
Matt Carlsona9dc5292009-02-25 14:25:30 +000010168 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10169 if (err)
Michael Chan566f86a2005-05-29 14:56:58 -070010170 break;
Michael Chan566f86a2005-05-29 14:56:58 -070010171 }
Michael Chan1b277772006-03-20 22:27:48 -080010172 if (i < size)
Michael Chan566f86a2005-05-29 14:56:58 -070010173 goto out;
10174
Michael Chan1b277772006-03-20 22:27:48 -080010175 /* Selfboot format */
Matt Carlsona9dc5292009-02-25 14:25:30 +000010176 magic = be32_to_cpu(buf[0]);
Al Virob9fc7dc2007-12-17 22:59:57 -080010177 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
Michael Chanb16250e2006-09-27 16:10:14 -070010178 TG3_EEPROM_MAGIC_FW) {
Michael Chan1b277772006-03-20 22:27:48 -080010179 u8 *buf8 = (u8 *) buf, csum8 = 0;
10180
Al Virob9fc7dc2007-12-17 22:59:57 -080010181 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
Matt Carlsona5767de2007-11-12 21:10:58 -080010182 TG3_EEPROM_SB_REVISION_2) {
10183 /* For rev 2, the csum doesn't include the MBA. */
10184 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10185 csum8 += buf8[i];
10186 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10187 csum8 += buf8[i];
10188 } else {
10189 for (i = 0; i < size; i++)
10190 csum8 += buf8[i];
10191 }
Michael Chan1b277772006-03-20 22:27:48 -080010192
Adrian Bunkad96b482006-04-05 22:21:04 -070010193 if (csum8 == 0) {
10194 err = 0;
10195 goto out;
10196 }
10197
10198 err = -EIO;
10199 goto out;
Michael Chan1b277772006-03-20 22:27:48 -080010200 }
Michael Chan566f86a2005-05-29 14:56:58 -070010201
Al Virob9fc7dc2007-12-17 22:59:57 -080010202 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
Michael Chanb16250e2006-09-27 16:10:14 -070010203 TG3_EEPROM_MAGIC_HW) {
10204 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
Matt Carlsona9dc5292009-02-25 14:25:30 +000010205 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
Michael Chanb16250e2006-09-27 16:10:14 -070010206 u8 *buf8 = (u8 *) buf;
Michael Chanb16250e2006-09-27 16:10:14 -070010207
10208 /* Separate the parity bits and the data bytes. */
10209 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10210 if ((i == 0) || (i == 8)) {
10211 int l;
10212 u8 msk;
10213
10214 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10215 parity[k++] = buf8[i] & msk;
10216 i++;
Matt Carlson859a588792010-04-05 10:19:28 +000010217 } else if (i == 16) {
Michael Chanb16250e2006-09-27 16:10:14 -070010218 int l;
10219 u8 msk;
10220
10221 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10222 parity[k++] = buf8[i] & msk;
10223 i++;
10224
10225 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10226 parity[k++] = buf8[i] & msk;
10227 i++;
10228 }
10229 data[j++] = buf8[i];
10230 }
10231
10232 err = -EIO;
10233 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10234 u8 hw8 = hweight8(data[i]);
10235
10236 if ((hw8 & 0x1) && parity[i])
10237 goto out;
10238 else if (!(hw8 & 0x1) && !parity[i])
10239 goto out;
10240 }
10241 err = 0;
10242 goto out;
10243 }
10244
Michael Chan566f86a2005-05-29 14:56:58 -070010245 /* Bootstrap checksum at offset 0x10 */
10246 csum = calc_crc((unsigned char *) buf, 0x10);
Matt Carlsona9dc5292009-02-25 14:25:30 +000010247 if (csum != be32_to_cpu(buf[0x10/4]))
Michael Chan566f86a2005-05-29 14:56:58 -070010248 goto out;
10249
10250 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10251 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
Matt Carlsona9dc5292009-02-25 14:25:30 +000010252 if (csum != be32_to_cpu(buf[0xfc/4]))
10253 goto out;
Michael Chan566f86a2005-05-29 14:56:58 -070010254
10255 err = 0;
10256
10257out:
10258 kfree(buf);
10259 return err;
10260}
10261
Michael Chanca430072005-05-29 14:57:23 -070010262#define TG3_SERDES_TIMEOUT_SEC 2
10263#define TG3_COPPER_TIMEOUT_SEC 6
10264
10265static int tg3_test_link(struct tg3 *tp)
10266{
10267 int i, max;
10268
10269 if (!netif_running(tp->dev))
10270 return -ENODEV;
10271
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010272 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
Michael Chanca430072005-05-29 14:57:23 -070010273 max = TG3_SERDES_TIMEOUT_SEC;
10274 else
10275 max = TG3_COPPER_TIMEOUT_SEC;
10276
10277 for (i = 0; i < max; i++) {
10278 if (netif_carrier_ok(tp->dev))
10279 return 0;
10280
10281 if (msleep_interruptible(1000))
10282 break;
10283 }
10284
10285 return -EIO;
10286}
10287
Michael Chana71116d2005-05-29 14:58:11 -070010288/* Only test the commonly used registers */
David S. Miller30ca3e32006-03-20 23:02:36 -080010289static int tg3_test_registers(struct tg3 *tp)
Michael Chana71116d2005-05-29 14:58:11 -070010290{
Michael Chanb16250e2006-09-27 16:10:14 -070010291 int i, is_5705, is_5750;
Michael Chana71116d2005-05-29 14:58:11 -070010292 u32 offset, read_mask, write_mask, val, save_val, read_val;
10293 static struct {
10294 u16 offset;
10295 u16 flags;
10296#define TG3_FL_5705 0x1
10297#define TG3_FL_NOT_5705 0x2
10298#define TG3_FL_NOT_5788 0x4
Michael Chanb16250e2006-09-27 16:10:14 -070010299#define TG3_FL_NOT_5750 0x8
Michael Chana71116d2005-05-29 14:58:11 -070010300 u32 read_mask;
10301 u32 write_mask;
10302 } reg_tbl[] = {
10303 /* MAC Control Registers */
10304 { MAC_MODE, TG3_FL_NOT_5705,
10305 0x00000000, 0x00ef6f8c },
10306 { MAC_MODE, TG3_FL_5705,
10307 0x00000000, 0x01ef6b8c },
10308 { MAC_STATUS, TG3_FL_NOT_5705,
10309 0x03800107, 0x00000000 },
10310 { MAC_STATUS, TG3_FL_5705,
10311 0x03800100, 0x00000000 },
10312 { MAC_ADDR_0_HIGH, 0x0000,
10313 0x00000000, 0x0000ffff },
10314 { MAC_ADDR_0_LOW, 0x0000,
Matt Carlsonc6cdf432010-04-05 10:19:26 +000010315 0x00000000, 0xffffffff },
Michael Chana71116d2005-05-29 14:58:11 -070010316 { MAC_RX_MTU_SIZE, 0x0000,
10317 0x00000000, 0x0000ffff },
10318 { MAC_TX_MODE, 0x0000,
10319 0x00000000, 0x00000070 },
10320 { MAC_TX_LENGTHS, 0x0000,
10321 0x00000000, 0x00003fff },
10322 { MAC_RX_MODE, TG3_FL_NOT_5705,
10323 0x00000000, 0x000007fc },
10324 { MAC_RX_MODE, TG3_FL_5705,
10325 0x00000000, 0x000007dc },
10326 { MAC_HASH_REG_0, 0x0000,
10327 0x00000000, 0xffffffff },
10328 { MAC_HASH_REG_1, 0x0000,
10329 0x00000000, 0xffffffff },
10330 { MAC_HASH_REG_2, 0x0000,
10331 0x00000000, 0xffffffff },
10332 { MAC_HASH_REG_3, 0x0000,
10333 0x00000000, 0xffffffff },
10334
10335 /* Receive Data and Receive BD Initiator Control Registers. */
10336 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10337 0x00000000, 0xffffffff },
10338 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10339 0x00000000, 0xffffffff },
10340 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10341 0x00000000, 0x00000003 },
10342 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10343 0x00000000, 0xffffffff },
10344 { RCVDBDI_STD_BD+0, 0x0000,
10345 0x00000000, 0xffffffff },
10346 { RCVDBDI_STD_BD+4, 0x0000,
10347 0x00000000, 0xffffffff },
10348 { RCVDBDI_STD_BD+8, 0x0000,
10349 0x00000000, 0xffff0002 },
10350 { RCVDBDI_STD_BD+0xc, 0x0000,
10351 0x00000000, 0xffffffff },
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010352
Michael Chana71116d2005-05-29 14:58:11 -070010353 /* Receive BD Initiator Control Registers. */
10354 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10355 0x00000000, 0xffffffff },
10356 { RCVBDI_STD_THRESH, TG3_FL_5705,
10357 0x00000000, 0x000003ff },
10358 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10359 0x00000000, 0xffffffff },
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010360
Michael Chana71116d2005-05-29 14:58:11 -070010361 /* Host Coalescing Control Registers. */
10362 { HOSTCC_MODE, TG3_FL_NOT_5705,
10363 0x00000000, 0x00000004 },
10364 { HOSTCC_MODE, TG3_FL_5705,
10365 0x00000000, 0x000000f6 },
10366 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10367 0x00000000, 0xffffffff },
10368 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10369 0x00000000, 0x000003ff },
10370 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10371 0x00000000, 0xffffffff },
10372 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10373 0x00000000, 0x000003ff },
10374 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10375 0x00000000, 0xffffffff },
10376 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10377 0x00000000, 0x000000ff },
10378 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10379 0x00000000, 0xffffffff },
10380 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10381 0x00000000, 0x000000ff },
10382 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10383 0x00000000, 0xffffffff },
10384 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10385 0x00000000, 0xffffffff },
10386 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10387 0x00000000, 0xffffffff },
10388 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10389 0x00000000, 0x000000ff },
10390 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10391 0x00000000, 0xffffffff },
10392 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10393 0x00000000, 0x000000ff },
10394 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10395 0x00000000, 0xffffffff },
10396 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10397 0x00000000, 0xffffffff },
10398 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10399 0x00000000, 0xffffffff },
10400 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10401 0x00000000, 0xffffffff },
10402 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10403 0x00000000, 0xffffffff },
10404 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10405 0xffffffff, 0x00000000 },
10406 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10407 0xffffffff, 0x00000000 },
10408
10409 /* Buffer Manager Control Registers. */
Michael Chanb16250e2006-09-27 16:10:14 -070010410 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
Michael Chana71116d2005-05-29 14:58:11 -070010411 0x00000000, 0x007fff80 },
Michael Chanb16250e2006-09-27 16:10:14 -070010412 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
Michael Chana71116d2005-05-29 14:58:11 -070010413 0x00000000, 0x007fffff },
10414 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10415 0x00000000, 0x0000003f },
10416 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10417 0x00000000, 0x000001ff },
10418 { BUFMGR_MB_HIGH_WATER, 0x0000,
10419 0x00000000, 0x000001ff },
10420 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10421 0xffffffff, 0x00000000 },
10422 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10423 0xffffffff, 0x00000000 },
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010424
Michael Chana71116d2005-05-29 14:58:11 -070010425 /* Mailbox Registers */
10426 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10427 0x00000000, 0x000001ff },
10428 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10429 0x00000000, 0x000001ff },
10430 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10431 0x00000000, 0x000007ff },
10432 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10433 0x00000000, 0x000001ff },
10434
10435 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10436 };
10437
Michael Chanb16250e2006-09-27 16:10:14 -070010438 is_5705 = is_5750 = 0;
10439 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
Michael Chana71116d2005-05-29 14:58:11 -070010440 is_5705 = 1;
Michael Chanb16250e2006-09-27 16:10:14 -070010441 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10442 is_5750 = 1;
10443 }
Michael Chana71116d2005-05-29 14:58:11 -070010444
10445 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10446 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10447 continue;
10448
10449 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10450 continue;
10451
10452 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10453 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10454 continue;
10455
Michael Chanb16250e2006-09-27 16:10:14 -070010456 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10457 continue;
10458
Michael Chana71116d2005-05-29 14:58:11 -070010459 offset = (u32) reg_tbl[i].offset;
10460 read_mask = reg_tbl[i].read_mask;
10461 write_mask = reg_tbl[i].write_mask;
10462
10463 /* Save the original register content */
10464 save_val = tr32(offset);
10465
10466 /* Determine the read-only value. */
10467 read_val = save_val & read_mask;
10468
10469 /* Write zero to the register, then make sure the read-only bits
10470 * are not changed and the read/write bits are all zeros.
10471 */
10472 tw32(offset, 0);
10473
10474 val = tr32(offset);
10475
10476 /* Test the read-only and read/write bits. */
10477 if (((val & read_mask) != read_val) || (val & write_mask))
10478 goto out;
10479
10480 /* Write ones to all the bits defined by RdMask and WrMask, then
10481 * make sure the read-only bits are not changed and the
10482 * read/write bits are all ones.
10483 */
10484 tw32(offset, read_mask | write_mask);
10485
10486 val = tr32(offset);
10487
10488 /* Test the read-only bits. */
10489 if ((val & read_mask) != read_val)
10490 goto out;
10491
10492 /* Test the read/write bits. */
10493 if ((val & write_mask) != write_mask)
10494 goto out;
10495
10496 tw32(offset, save_val);
10497 }
10498
10499 return 0;
10500
10501out:
Michael Chan9f88f292006-12-07 00:22:54 -080010502 if (netif_msg_hw(tp))
Matt Carlson2445e462010-04-05 10:19:21 +000010503 netdev_err(tp->dev,
10504 "Register test failed at offset %x\n", offset);
Michael Chana71116d2005-05-29 14:58:11 -070010505 tw32(offset, save_val);
10506 return -EIO;
10507}
10508
Michael Chan7942e1d2005-05-29 14:58:36 -070010509static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10510{
Arjan van de Venf71e1302006-03-03 21:33:57 -050010511 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
Michael Chan7942e1d2005-05-29 14:58:36 -070010512 int i;
10513 u32 j;
10514
Alejandro Martinez Ruize9edda62007-10-15 03:37:43 +020010515 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
Michael Chan7942e1d2005-05-29 14:58:36 -070010516 for (j = 0; j < len; j += 4) {
10517 u32 val;
10518
10519 tg3_write_mem(tp, offset + j, test_pattern[i]);
10520 tg3_read_mem(tp, offset + j, &val);
10521 if (val != test_pattern[i])
10522 return -EIO;
10523 }
10524 }
10525 return 0;
10526}
10527
10528static int tg3_test_memory(struct tg3 *tp)
10529{
10530 static struct mem_entry {
10531 u32 offset;
10532 u32 len;
10533 } mem_tbl_570x[] = {
Michael Chan38690192005-12-19 16:27:28 -080010534 { 0x00000000, 0x00b50},
Michael Chan7942e1d2005-05-29 14:58:36 -070010535 { 0x00002000, 0x1c000},
10536 { 0xffffffff, 0x00000}
10537 }, mem_tbl_5705[] = {
10538 { 0x00000100, 0x0000c},
10539 { 0x00000200, 0x00008},
Michael Chan7942e1d2005-05-29 14:58:36 -070010540 { 0x00004000, 0x00800},
10541 { 0x00006000, 0x01000},
10542 { 0x00008000, 0x02000},
10543 { 0x00010000, 0x0e000},
10544 { 0xffffffff, 0x00000}
Michael Chan79f4d132006-03-20 22:28:57 -080010545 }, mem_tbl_5755[] = {
10546 { 0x00000200, 0x00008},
10547 { 0x00004000, 0x00800},
10548 { 0x00006000, 0x00800},
10549 { 0x00008000, 0x02000},
10550 { 0x00010000, 0x0c000},
10551 { 0xffffffff, 0x00000}
Michael Chanb16250e2006-09-27 16:10:14 -070010552 }, mem_tbl_5906[] = {
10553 { 0x00000200, 0x00008},
10554 { 0x00004000, 0x00400},
10555 { 0x00006000, 0x00400},
10556 { 0x00008000, 0x01000},
10557 { 0x00010000, 0x01000},
10558 { 0xffffffff, 0x00000}
Matt Carlson8b5a6c42010-01-20 16:58:06 +000010559 }, mem_tbl_5717[] = {
10560 { 0x00000200, 0x00008},
10561 { 0x00010000, 0x0a000},
10562 { 0x00020000, 0x13c00},
10563 { 0xffffffff, 0x00000}
10564 }, mem_tbl_57765[] = {
10565 { 0x00000200, 0x00008},
10566 { 0x00004000, 0x00800},
10567 { 0x00006000, 0x09800},
10568 { 0x00010000, 0x0a000},
10569 { 0xffffffff, 0x00000}
Michael Chan7942e1d2005-05-29 14:58:36 -070010570 };
10571 struct mem_entry *mem_tbl;
10572 int err = 0;
10573 int i;
10574
Matt Carlsona50d0792010-06-05 17:24:37 +000010575 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10576 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
Matt Carlson8b5a6c42010-01-20 16:58:06 +000010577 mem_tbl = mem_tbl_5717;
10578 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10579 mem_tbl = mem_tbl_57765;
10580 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
Matt Carlson321d32a2008-11-21 17:22:19 -080010581 mem_tbl = mem_tbl_5755;
10582 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10583 mem_tbl = mem_tbl_5906;
10584 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10585 mem_tbl = mem_tbl_5705;
10586 else
Michael Chan7942e1d2005-05-29 14:58:36 -070010587 mem_tbl = mem_tbl_570x;
10588
10589 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
Matt Carlsonbe98da62010-07-11 09:31:46 +000010590 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10591 if (err)
Michael Chan7942e1d2005-05-29 14:58:36 -070010592 break;
10593 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010594
Michael Chan7942e1d2005-05-29 14:58:36 -070010595 return err;
10596}
10597
Michael Chan9f40dea2005-09-05 17:53:06 -070010598#define TG3_MAC_LOOPBACK 0
10599#define TG3_PHY_LOOPBACK 1
10600
10601static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
Michael Chanc76949a2005-05-29 14:58:59 -070010602{
Michael Chan9f40dea2005-09-05 17:53:06 -070010603 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
Matt Carlsonfd2ce372009-09-01 12:51:13 +000010604 u32 desc_idx, coal_now;
Michael Chanc76949a2005-05-29 14:58:59 -070010605 struct sk_buff *skb, *rx_skb;
10606 u8 *tx_data;
10607 dma_addr_t map;
10608 int num_pkts, tx_len, rx_len, i, err;
10609 struct tg3_rx_buffer_desc *desc;
Matt Carlson898a56f2009-08-28 14:02:40 +000010610 struct tg3_napi *tnapi, *rnapi;
Matt Carlson21f581a2009-08-28 14:00:25 +000010611 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
Michael Chanc76949a2005-05-29 14:58:59 -070010612
Matt Carlsonc8873402010-02-12 14:47:11 +000010613 tnapi = &tp->napi[0];
10614 rnapi = &tp->napi[0];
Matt Carlson0c1d0e22009-09-01 13:16:33 +000010615 if (tp->irq_cnt > 1) {
Matt Carlson0c1d0e22009-09-01 13:16:33 +000010616 rnapi = &tp->napi[1];
Matt Carlsonc8873402010-02-12 14:47:11 +000010617 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10618 tnapi = &tp->napi[1];
Matt Carlson0c1d0e22009-09-01 13:16:33 +000010619 }
Matt Carlsonfd2ce372009-09-01 12:51:13 +000010620 coal_now = tnapi->coal_now | rnapi->coal_now;
Matt Carlson898a56f2009-08-28 14:02:40 +000010621
Michael Chan9f40dea2005-09-05 17:53:06 -070010622 if (loopback_mode == TG3_MAC_LOOPBACK) {
Michael Chanc94e3942005-09-27 12:12:42 -070010623 /* HW errata - mac loopback fails in some cases on 5780.
10624 * Normal traffic and PHY loopback are not affected by
10625 * errata.
10626 */
10627 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10628 return 0;
10629
Michael Chan9f40dea2005-09-05 17:53:06 -070010630 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
Matt Carlsone8f3f6c2007-07-11 19:47:55 -070010631 MAC_MODE_PORT_INT_LPBACK;
10632 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10633 mac_mode |= MAC_MODE_LINK_POLARITY;
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010634 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
Michael Chan3f7045c2006-09-27 16:02:29 -070010635 mac_mode |= MAC_MODE_PORT_MODE_MII;
10636 else
10637 mac_mode |= MAC_MODE_PORT_MODE_GMII;
Michael Chan9f40dea2005-09-05 17:53:06 -070010638 tw32(MAC_MODE, mac_mode);
10639 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
Michael Chan3f7045c2006-09-27 16:02:29 -070010640 u32 val;
10641
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010642 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Matt Carlson7f97a4b2009-08-25 10:10:03 +000010643 tg3_phy_fet_toggle_apd(tp, false);
Michael Chan5d64ad32006-12-07 00:19:40 -080010644 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10645 } else
10646 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
Michael Chan3f7045c2006-09-27 16:02:29 -070010647
Matt Carlson9ef8ca92007-07-11 19:48:29 -070010648 tg3_phy_toggle_automdix(tp, 0);
10649
Michael Chan3f7045c2006-09-27 16:02:29 -070010650 tg3_writephy(tp, MII_BMCR, val);
Michael Chanc94e3942005-09-27 12:12:42 -070010651 udelay(40);
Michael Chan5d64ad32006-12-07 00:19:40 -080010652
Matt Carlsone8f3f6c2007-07-11 19:47:55 -070010653 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010654 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Matt Carlson1061b7c2010-02-12 14:47:12 +000010655 tg3_writephy(tp, MII_TG3_FET_PTEST,
10656 MII_TG3_FET_PTEST_FRC_TX_LINK |
10657 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10658 /* The write needs to be flushed for the AC131 */
10659 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10660 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
Michael Chan5d64ad32006-12-07 00:19:40 -080010661 mac_mode |= MAC_MODE_PORT_MODE_MII;
10662 } else
10663 mac_mode |= MAC_MODE_PORT_MODE_GMII;
Michael Chanb16250e2006-09-27 16:10:14 -070010664
Michael Chanc94e3942005-09-27 12:12:42 -070010665 /* reset to prevent losing 1st rx packet intermittently */
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010666 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
Michael Chanc94e3942005-09-27 12:12:42 -070010667 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10668 udelay(10);
10669 tw32_f(MAC_RX_MODE, tp->rx_mode);
10670 }
Matt Carlsone8f3f6c2007-07-11 19:47:55 -070010671 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
Matt Carlson79eb6902010-02-17 15:17:03 +000010672 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10673 if (masked_phy_id == TG3_PHY_ID_BCM5401)
Matt Carlsone8f3f6c2007-07-11 19:47:55 -070010674 mac_mode &= ~MAC_MODE_LINK_POLARITY;
Matt Carlson79eb6902010-02-17 15:17:03 +000010675 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
Matt Carlsone8f3f6c2007-07-11 19:47:55 -070010676 mac_mode |= MAC_MODE_LINK_POLARITY;
Michael Chanff18ff02006-03-27 23:17:27 -080010677 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10678 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10679 }
Michael Chan9f40dea2005-09-05 17:53:06 -070010680 tw32(MAC_MODE, mac_mode);
Matt Carlson859a588792010-04-05 10:19:28 +000010681 } else {
Michael Chan9f40dea2005-09-05 17:53:06 -070010682 return -EINVAL;
Matt Carlson859a588792010-04-05 10:19:28 +000010683 }
Michael Chanc76949a2005-05-29 14:58:59 -070010684
10685 err = -EIO;
10686
Michael Chanc76949a2005-05-29 14:58:59 -070010687 tx_len = 1514;
David S. Millera20e9c62006-07-31 22:38:16 -070010688 skb = netdev_alloc_skb(tp->dev, tx_len);
Jesper Juhla50bb7b2006-05-09 23:14:35 -070010689 if (!skb)
10690 return -ENOMEM;
10691
Michael Chanc76949a2005-05-29 14:58:59 -070010692 tx_data = skb_put(skb, tx_len);
10693 memcpy(tx_data, tp->dev->dev_addr, 6);
10694 memset(tx_data + 6, 0x0, 8);
10695
10696 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10697
10698 for (i = 14; i < tx_len; i++)
10699 tx_data[i] = (u8) (i & 0xff);
10700
Alexander Duyckf4188d82009-12-02 16:48:38 +000010701 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10702 if (pci_dma_mapping_error(tp->pdev, map)) {
Matt Carlsona21771d2009-11-02 14:25:31 +000010703 dev_kfree_skb(skb);
10704 return -EIO;
10705 }
Michael Chanc76949a2005-05-29 14:58:59 -070010706
10707 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
Matt Carlsonfd2ce372009-09-01 12:51:13 +000010708 rnapi->coal_now);
Michael Chanc76949a2005-05-29 14:58:59 -070010709
10710 udelay(10);
10711
Matt Carlson898a56f2009-08-28 14:02:40 +000010712 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
Michael Chanc76949a2005-05-29 14:58:59 -070010713
Michael Chanc76949a2005-05-29 14:58:59 -070010714 num_pkts = 0;
10715
Alexander Duyckf4188d82009-12-02 16:48:38 +000010716 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
Michael Chanc76949a2005-05-29 14:58:59 -070010717
Matt Carlsonf3f3f272009-08-28 14:03:21 +000010718 tnapi->tx_prod++;
Michael Chanc76949a2005-05-29 14:58:59 -070010719 num_pkts++;
10720
Matt Carlsonf3f3f272009-08-28 14:03:21 +000010721 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10722 tr32_mailbox(tnapi->prodmbox);
Michael Chanc76949a2005-05-29 14:58:59 -070010723
10724 udelay(10);
10725
Matt Carlson303fc922009-11-02 14:27:34 +000010726 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10727 for (i = 0; i < 35; i++) {
Michael Chanc76949a2005-05-29 14:58:59 -070010728 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
Matt Carlsonfd2ce372009-09-01 12:51:13 +000010729 coal_now);
Michael Chanc76949a2005-05-29 14:58:59 -070010730
10731 udelay(10);
10732
Matt Carlson898a56f2009-08-28 14:02:40 +000010733 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10734 rx_idx = rnapi->hw_status->idx[0].rx_producer;
Matt Carlsonf3f3f272009-08-28 14:03:21 +000010735 if ((tx_idx == tnapi->tx_prod) &&
Michael Chanc76949a2005-05-29 14:58:59 -070010736 (rx_idx == (rx_start_idx + num_pkts)))
10737 break;
10738 }
10739
Alexander Duyckf4188d82009-12-02 16:48:38 +000010740 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
Michael Chanc76949a2005-05-29 14:58:59 -070010741 dev_kfree_skb(skb);
10742
Matt Carlsonf3f3f272009-08-28 14:03:21 +000010743 if (tx_idx != tnapi->tx_prod)
Michael Chanc76949a2005-05-29 14:58:59 -070010744 goto out;
10745
10746 if (rx_idx != rx_start_idx + num_pkts)
10747 goto out;
10748
Matt Carlson72334482009-08-28 14:03:01 +000010749 desc = &rnapi->rx_rcb[rx_start_idx];
Michael Chanc76949a2005-05-29 14:58:59 -070010750 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10751 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10752 if (opaque_key != RXD_OPAQUE_RING_STD)
10753 goto out;
10754
10755 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10756 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10757 goto out;
10758
10759 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10760 if (rx_len != tx_len)
10761 goto out;
10762
Matt Carlson21f581a2009-08-28 14:00:25 +000010763 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
Michael Chanc76949a2005-05-29 14:58:59 -070010764
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +000010765 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
Michael Chanc76949a2005-05-29 14:58:59 -070010766 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10767
10768 for (i = 14; i < tx_len; i++) {
10769 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10770 goto out;
10771 }
10772 err = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010773
Michael Chanc76949a2005-05-29 14:58:59 -070010774 /* tg3_free_rings will unmap and free the rx_skb */
10775out:
10776 return err;
10777}
10778
Michael Chan9f40dea2005-09-05 17:53:06 -070010779#define TG3_MAC_LOOPBACK_FAILED 1
10780#define TG3_PHY_LOOPBACK_FAILED 2
10781#define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10782 TG3_PHY_LOOPBACK_FAILED)
10783
10784static int tg3_test_loopback(struct tg3 *tp)
10785{
10786 int err = 0;
Matt Carlson9936bcf2007-10-10 18:03:07 -070010787 u32 cpmuctrl = 0;
Michael Chan9f40dea2005-09-05 17:53:06 -070010788
10789 if (!netif_running(tp->dev))
10790 return TG3_LOOPBACK_FAILED;
10791
Michael Chanb9ec6c12006-07-25 16:37:27 -070010792 err = tg3_reset_hw(tp, 1);
10793 if (err)
10794 return TG3_LOOPBACK_FAILED;
Michael Chan9f40dea2005-09-05 17:53:06 -070010795
Matt Carlson6833c042008-11-21 17:18:59 -080010796 /* Turn off gphy autopowerdown. */
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010797 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
Matt Carlson6833c042008-11-21 17:18:59 -080010798 tg3_phy_toggle_apd(tp, false);
10799
Matt Carlson321d32a2008-11-21 17:22:19 -080010800 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
Matt Carlson9936bcf2007-10-10 18:03:07 -070010801 int i;
10802 u32 status;
10803
10804 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10805
10806 /* Wait for up to 40 microseconds to acquire lock. */
10807 for (i = 0; i < 4; i++) {
10808 status = tr32(TG3_CPMU_MUTEX_GNT);
10809 if (status == CPMU_MUTEX_GNT_DRIVER)
10810 break;
10811 udelay(10);
10812 }
10813
10814 if (status != CPMU_MUTEX_GNT_DRIVER)
10815 return TG3_LOOPBACK_FAILED;
10816
Matt Carlsonb2a5c192008-04-03 21:44:44 -070010817 /* Turn off link-based power management. */
Matt Carlsone8750932007-11-12 21:11:51 -080010818 cpmuctrl = tr32(TG3_CPMU_CTRL);
Matt Carlson109115e2008-05-02 16:48:59 -070010819 tw32(TG3_CPMU_CTRL,
10820 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10821 CPMU_CTRL_LINK_AWARE_MODE));
Matt Carlson9936bcf2007-10-10 18:03:07 -070010822 }
10823
Michael Chan9f40dea2005-09-05 17:53:06 -070010824 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10825 err |= TG3_MAC_LOOPBACK_FAILED;
Matt Carlson9936bcf2007-10-10 18:03:07 -070010826
Matt Carlson321d32a2008-11-21 17:22:19 -080010827 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
Matt Carlson9936bcf2007-10-10 18:03:07 -070010828 tw32(TG3_CPMU_CTRL, cpmuctrl);
10829
10830 /* Release the mutex */
10831 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10832 }
10833
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010834 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
Matt Carlsondd477002008-05-25 23:45:58 -070010835 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
Michael Chan9f40dea2005-09-05 17:53:06 -070010836 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10837 err |= TG3_PHY_LOOPBACK_FAILED;
10838 }
10839
Matt Carlson6833c042008-11-21 17:18:59 -080010840 /* Re-enable gphy autopowerdown. */
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010841 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
Matt Carlson6833c042008-11-21 17:18:59 -080010842 tg3_phy_toggle_apd(tp, true);
10843
Michael Chan9f40dea2005-09-05 17:53:06 -070010844 return err;
10845}
10846
Michael Chan4cafd3f2005-05-29 14:56:34 -070010847static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10848 u64 *data)
10849{
Michael Chan566f86a2005-05-29 14:56:58 -070010850 struct tg3 *tp = netdev_priv(dev);
10851
Matt Carlson800960682010-08-02 11:26:06 +000010852 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Michael Chanbc1c7562006-03-20 17:48:03 -080010853 tg3_set_power_state(tp, PCI_D0);
10854
Michael Chan566f86a2005-05-29 14:56:58 -070010855 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10856
10857 if (tg3_test_nvram(tp) != 0) {
10858 etest->flags |= ETH_TEST_FL_FAILED;
10859 data[0] = 1;
10860 }
Michael Chanca430072005-05-29 14:57:23 -070010861 if (tg3_test_link(tp) != 0) {
10862 etest->flags |= ETH_TEST_FL_FAILED;
10863 data[1] = 1;
10864 }
Michael Chana71116d2005-05-29 14:58:11 -070010865 if (etest->flags & ETH_TEST_FL_OFFLINE) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010866 int err, err2 = 0, irq_sync = 0;
Michael Chana71116d2005-05-29 14:58:11 -070010867
Michael Chanbbe832c2005-06-24 20:20:04 -070010868 if (netif_running(dev)) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010869 tg3_phy_stop(tp);
Michael Chanbbe832c2005-06-24 20:20:04 -070010870 tg3_netif_stop(tp);
10871 irq_sync = 1;
10872 }
10873
10874 tg3_full_lock(tp, irq_sync);
Michael Chana71116d2005-05-29 14:58:11 -070010875
10876 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
Michael Chanec41c7d2006-01-17 02:40:55 -080010877 err = tg3_nvram_lock(tp);
Michael Chana71116d2005-05-29 14:58:11 -070010878 tg3_halt_cpu(tp, RX_CPU_BASE);
10879 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10880 tg3_halt_cpu(tp, TX_CPU_BASE);
Michael Chanec41c7d2006-01-17 02:40:55 -080010881 if (!err)
10882 tg3_nvram_unlock(tp);
Michael Chana71116d2005-05-29 14:58:11 -070010883
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010884 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
Michael Chand9ab5ad2006-03-20 22:27:35 -080010885 tg3_phy_reset(tp);
10886
Michael Chana71116d2005-05-29 14:58:11 -070010887 if (tg3_test_registers(tp) != 0) {
10888 etest->flags |= ETH_TEST_FL_FAILED;
10889 data[2] = 1;
10890 }
Michael Chan7942e1d2005-05-29 14:58:36 -070010891 if (tg3_test_memory(tp) != 0) {
10892 etest->flags |= ETH_TEST_FL_FAILED;
10893 data[3] = 1;
10894 }
Michael Chan9f40dea2005-09-05 17:53:06 -070010895 if ((data[4] = tg3_test_loopback(tp)) != 0)
Michael Chanc76949a2005-05-29 14:58:59 -070010896 etest->flags |= ETH_TEST_FL_FAILED;
Michael Chana71116d2005-05-29 14:58:11 -070010897
David S. Millerf47c11e2005-06-24 20:18:35 -070010898 tg3_full_unlock(tp);
10899
Michael Chand4bc3922005-05-29 14:59:20 -070010900 if (tg3_test_interrupt(tp) != 0) {
10901 etest->flags |= ETH_TEST_FL_FAILED;
10902 data[5] = 1;
10903 }
David S. Millerf47c11e2005-06-24 20:18:35 -070010904
10905 tg3_full_lock(tp, 0);
Michael Chand4bc3922005-05-29 14:59:20 -070010906
Michael Chana71116d2005-05-29 14:58:11 -070010907 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10908 if (netif_running(dev)) {
10909 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010910 err2 = tg3_restart_hw(tp, 1);
10911 if (!err2)
Michael Chanb9ec6c12006-07-25 16:37:27 -070010912 tg3_netif_start(tp);
Michael Chana71116d2005-05-29 14:58:11 -070010913 }
David S. Millerf47c11e2005-06-24 20:18:35 -070010914
10915 tg3_full_unlock(tp);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010916
10917 if (irq_sync && !err2)
10918 tg3_phy_start(tp);
Michael Chana71116d2005-05-29 14:58:11 -070010919 }
Matt Carlson800960682010-08-02 11:26:06 +000010920 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Michael Chanbc1c7562006-03-20 17:48:03 -080010921 tg3_set_power_state(tp, PCI_D3hot);
10922
Michael Chan4cafd3f2005-05-29 14:56:34 -070010923}
10924
Linus Torvalds1da177e2005-04-16 15:20:36 -070010925static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10926{
10927 struct mii_ioctl_data *data = if_mii(ifr);
10928 struct tg3 *tp = netdev_priv(dev);
10929 int err;
10930
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010931 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000010932 struct phy_device *phydev;
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010933 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010934 return -EAGAIN;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000010935 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Richard Cochran28b04112010-07-17 08:48:55 +000010936 return phy_mii_ioctl(phydev, ifr, cmd);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010937 }
10938
Matt Carlson33f401a2010-04-05 10:19:27 +000010939 switch (cmd) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070010940 case SIOCGMIIPHY:
Matt Carlson882e9792009-09-01 13:21:36 +000010941 data->phy_id = tp->phy_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010942
10943 /* fallthru */
10944 case SIOCGMIIREG: {
10945 u32 mii_regval;
10946
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010947 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010948 break; /* We have no PHY */
10949
Matt Carlson800960682010-08-02 11:26:06 +000010950 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Michael Chanbc1c7562006-03-20 17:48:03 -080010951 return -EAGAIN;
10952
David S. Millerf47c11e2005-06-24 20:18:35 -070010953 spin_lock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010954 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
David S. Millerf47c11e2005-06-24 20:18:35 -070010955 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010956
10957 data->val_out = mii_regval;
10958
10959 return err;
10960 }
10961
10962 case SIOCSMIIREG:
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010963 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010964 break; /* We have no PHY */
10965
Matt Carlson800960682010-08-02 11:26:06 +000010966 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Michael Chanbc1c7562006-03-20 17:48:03 -080010967 return -EAGAIN;
10968
David S. Millerf47c11e2005-06-24 20:18:35 -070010969 spin_lock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010970 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
David S. Millerf47c11e2005-06-24 20:18:35 -070010971 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010972
10973 return err;
10974
10975 default:
10976 /* do nothing */
10977 break;
10978 }
10979 return -EOPNOTSUPP;
10980}
10981
10982#if TG3_VLAN_TAG_USED
10983static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10984{
10985 struct tg3 *tp = netdev_priv(dev);
10986
Matt Carlson844b3ee2009-02-25 14:23:56 +000010987 if (!netif_running(dev)) {
10988 tp->vlgrp = grp;
10989 return;
10990 }
10991
10992 tg3_netif_stop(tp);
Michael Chan29315e82006-06-29 20:12:30 -070010993
David S. Millerf47c11e2005-06-24 20:18:35 -070010994 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010995
10996 tp->vlgrp = grp;
10997
10998 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10999 __tg3_set_rx_mode(dev);
11000
Matt Carlson844b3ee2009-02-25 14:23:56 +000011001 tg3_netif_start(tp);
Michael Chan46966542007-07-11 19:47:19 -070011002
11003 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011004}
Linus Torvalds1da177e2005-04-16 15:20:36 -070011005#endif
11006
David S. Miller15f98502005-05-18 22:49:26 -070011007static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11008{
11009 struct tg3 *tp = netdev_priv(dev);
11010
11011 memcpy(ec, &tp->coal, sizeof(*ec));
11012 return 0;
11013}
11014
Michael Chand244c892005-07-05 14:42:33 -070011015static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11016{
11017 struct tg3 *tp = netdev_priv(dev);
11018 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11019 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11020
11021 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11022 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11023 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11024 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11025 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11026 }
11027
11028 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11029 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11030 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11031 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11032 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11033 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11034 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11035 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11036 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11037 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11038 return -EINVAL;
11039
11040 /* No rx interrupts will be generated if both are zero */
11041 if ((ec->rx_coalesce_usecs == 0) &&
11042 (ec->rx_max_coalesced_frames == 0))
11043 return -EINVAL;
11044
11045 /* No tx interrupts will be generated if both are zero */
11046 if ((ec->tx_coalesce_usecs == 0) &&
11047 (ec->tx_max_coalesced_frames == 0))
11048 return -EINVAL;
11049
11050 /* Only copy relevant parameters, ignore all others. */
11051 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11052 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11053 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11054 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11055 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11056 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11057 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11058 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11059 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11060
11061 if (netif_running(dev)) {
11062 tg3_full_lock(tp, 0);
11063 __tg3_set_coalesce(tp, &tp->coal);
11064 tg3_full_unlock(tp);
11065 }
11066 return 0;
11067}
11068
Jeff Garzik7282d492006-09-13 14:30:00 -040011069static const struct ethtool_ops tg3_ethtool_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011070 .get_settings = tg3_get_settings,
11071 .set_settings = tg3_set_settings,
11072 .get_drvinfo = tg3_get_drvinfo,
11073 .get_regs_len = tg3_get_regs_len,
11074 .get_regs = tg3_get_regs,
11075 .get_wol = tg3_get_wol,
11076 .set_wol = tg3_set_wol,
11077 .get_msglevel = tg3_get_msglevel,
11078 .set_msglevel = tg3_set_msglevel,
11079 .nway_reset = tg3_nway_reset,
11080 .get_link = ethtool_op_get_link,
11081 .get_eeprom_len = tg3_get_eeprom_len,
11082 .get_eeprom = tg3_get_eeprom,
11083 .set_eeprom = tg3_set_eeprom,
11084 .get_ringparam = tg3_get_ringparam,
11085 .set_ringparam = tg3_set_ringparam,
11086 .get_pauseparam = tg3_get_pauseparam,
11087 .set_pauseparam = tg3_set_pauseparam,
11088 .get_rx_csum = tg3_get_rx_csum,
11089 .set_rx_csum = tg3_set_rx_csum,
Linus Torvalds1da177e2005-04-16 15:20:36 -070011090 .set_tx_csum = tg3_set_tx_csum,
Linus Torvalds1da177e2005-04-16 15:20:36 -070011091 .set_sg = ethtool_op_set_sg,
Linus Torvalds1da177e2005-04-16 15:20:36 -070011092 .set_tso = tg3_set_tso,
Michael Chan4cafd3f2005-05-29 14:56:34 -070011093 .self_test = tg3_self_test,
Linus Torvalds1da177e2005-04-16 15:20:36 -070011094 .get_strings = tg3_get_strings,
Michael Chan4009a932005-09-05 17:52:54 -070011095 .phys_id = tg3_phys_id,
Linus Torvalds1da177e2005-04-16 15:20:36 -070011096 .get_ethtool_stats = tg3_get_ethtool_stats,
David S. Miller15f98502005-05-18 22:49:26 -070011097 .get_coalesce = tg3_get_coalesce,
Michael Chand244c892005-07-05 14:42:33 -070011098 .set_coalesce = tg3_set_coalesce,
Jeff Garzikb9f2c042007-10-03 18:07:32 -070011099 .get_sset_count = tg3_get_sset_count,
Linus Torvalds1da177e2005-04-16 15:20:36 -070011100};
11101
11102static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11103{
Michael Chan1b277772006-03-20 22:27:48 -080011104 u32 cursize, val, magic;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011105
11106 tp->nvram_size = EEPROM_CHIP_SIZE;
11107
Matt Carlsone4f34112009-02-25 14:25:00 +000011108 if (tg3_nvram_read(tp, 0, &magic) != 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011109 return;
11110
Michael Chanb16250e2006-09-27 16:10:14 -070011111 if ((magic != TG3_EEPROM_MAGIC) &&
11112 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11113 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
Linus Torvalds1da177e2005-04-16 15:20:36 -070011114 return;
11115
11116 /*
11117 * Size the chip by reading offsets at increasing powers of two.
11118 * When we encounter our validation signature, we know the addressing
11119 * has wrapped around, and thus have our chip size.
11120 */
Michael Chan1b277772006-03-20 22:27:48 -080011121 cursize = 0x10;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011122
11123 while (cursize < tp->nvram_size) {
Matt Carlsone4f34112009-02-25 14:25:00 +000011124 if (tg3_nvram_read(tp, cursize, &val) != 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011125 return;
11126
Michael Chan18201802006-03-20 22:29:15 -080011127 if (val == magic)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011128 break;
11129
11130 cursize <<= 1;
11131 }
11132
11133 tp->nvram_size = cursize;
11134}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011135
Linus Torvalds1da177e2005-04-16 15:20:36 -070011136static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11137{
11138 u32 val;
11139
Matt Carlsondf259d82009-04-20 06:57:14 +000011140 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11141 tg3_nvram_read(tp, 0, &val) != 0)
Michael Chan1b277772006-03-20 22:27:48 -080011142 return;
11143
11144 /* Selfboot format */
Michael Chan18201802006-03-20 22:29:15 -080011145 if (val != TG3_EEPROM_MAGIC) {
Michael Chan1b277772006-03-20 22:27:48 -080011146 tg3_get_eeprom_size(tp);
11147 return;
11148 }
11149
Matt Carlson6d348f22009-02-25 14:25:52 +000011150 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011151 if (val != 0) {
Matt Carlson6d348f22009-02-25 14:25:52 +000011152 /* This is confusing. We want to operate on the
11153 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11154 * call will read from NVRAM and byteswap the data
11155 * according to the byteswapping settings for all
11156 * other register accesses. This ensures the data we
11157 * want will always reside in the lower 16-bits.
11158 * However, the data in NVRAM is in LE format, which
11159 * means the data from the NVRAM read will always be
11160 * opposite the endianness of the CPU. The 16-bit
11161 * byteswap then brings the data to CPU endianness.
11162 */
11163 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011164 return;
11165 }
11166 }
Matt Carlsonfd1122a2008-05-02 16:48:36 -070011167 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011168}
11169
11170static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11171{
11172 u32 nvcfg1;
11173
11174 nvcfg1 = tr32(NVRAM_CFG1);
11175 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11176 tp->tg3_flags2 |= TG3_FLG2_FLASH;
Matt Carlson8590a602009-08-28 12:29:16 +000011177 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011178 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11179 tw32(NVRAM_CFG1, nvcfg1);
11180 }
11181
Michael Chan4c987482005-09-05 17:52:38 -070011182 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
Michael Chana4e2b342005-10-26 15:46:52 -070011183 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011184 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
Matt Carlson8590a602009-08-28 12:29:16 +000011185 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11186 tp->nvram_jedecnum = JEDEC_ATMEL;
11187 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11188 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11189 break;
11190 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11191 tp->nvram_jedecnum = JEDEC_ATMEL;
11192 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11193 break;
11194 case FLASH_VENDOR_ATMEL_EEPROM:
11195 tp->nvram_jedecnum = JEDEC_ATMEL;
11196 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11197 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11198 break;
11199 case FLASH_VENDOR_ST:
11200 tp->nvram_jedecnum = JEDEC_ST;
11201 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11202 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11203 break;
11204 case FLASH_VENDOR_SAIFUN:
11205 tp->nvram_jedecnum = JEDEC_SAIFUN;
11206 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11207 break;
11208 case FLASH_VENDOR_SST_SMALL:
11209 case FLASH_VENDOR_SST_LARGE:
11210 tp->nvram_jedecnum = JEDEC_SST;
11211 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11212 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011213 }
Matt Carlson8590a602009-08-28 12:29:16 +000011214 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011215 tp->nvram_jedecnum = JEDEC_ATMEL;
11216 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11217 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11218 }
11219}
11220
Matt Carlsona1b950d2009-09-01 13:20:17 +000011221static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11222{
11223 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11224 case FLASH_5752PAGE_SIZE_256:
11225 tp->nvram_pagesize = 256;
11226 break;
11227 case FLASH_5752PAGE_SIZE_512:
11228 tp->nvram_pagesize = 512;
11229 break;
11230 case FLASH_5752PAGE_SIZE_1K:
11231 tp->nvram_pagesize = 1024;
11232 break;
11233 case FLASH_5752PAGE_SIZE_2K:
11234 tp->nvram_pagesize = 2048;
11235 break;
11236 case FLASH_5752PAGE_SIZE_4K:
11237 tp->nvram_pagesize = 4096;
11238 break;
11239 case FLASH_5752PAGE_SIZE_264:
11240 tp->nvram_pagesize = 264;
11241 break;
11242 case FLASH_5752PAGE_SIZE_528:
11243 tp->nvram_pagesize = 528;
11244 break;
11245 }
11246}
11247
Michael Chan361b4ac2005-04-21 17:11:21 -070011248static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11249{
11250 u32 nvcfg1;
11251
11252 nvcfg1 = tr32(NVRAM_CFG1);
11253
Michael Chane6af3012005-04-21 17:12:05 -070011254 /* NVRAM protection for TPM */
11255 if (nvcfg1 & (1 << 27))
Matt Carlsonf66a29b2009-11-13 13:03:36 +000011256 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
Michael Chane6af3012005-04-21 17:12:05 -070011257
Michael Chan361b4ac2005-04-21 17:11:21 -070011258 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
Matt Carlson8590a602009-08-28 12:29:16 +000011259 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11260 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11261 tp->nvram_jedecnum = JEDEC_ATMEL;
11262 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11263 break;
11264 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11265 tp->nvram_jedecnum = JEDEC_ATMEL;
11266 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11267 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11268 break;
11269 case FLASH_5752VENDOR_ST_M45PE10:
11270 case FLASH_5752VENDOR_ST_M45PE20:
11271 case FLASH_5752VENDOR_ST_M45PE40:
11272 tp->nvram_jedecnum = JEDEC_ST;
11273 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11274 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11275 break;
Michael Chan361b4ac2005-04-21 17:11:21 -070011276 }
11277
11278 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
Matt Carlsona1b950d2009-09-01 13:20:17 +000011279 tg3_nvram_get_pagesize(tp, nvcfg1);
Matt Carlson8590a602009-08-28 12:29:16 +000011280 } else {
Michael Chan361b4ac2005-04-21 17:11:21 -070011281 /* For eeprom, set pagesize to maximum eeprom size */
11282 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11283
11284 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11285 tw32(NVRAM_CFG1, nvcfg1);
11286 }
11287}
11288
Michael Chand3c7b882006-03-23 01:28:25 -080011289static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11290{
Matt Carlson989a9d22007-05-05 11:51:05 -070011291 u32 nvcfg1, protect = 0;
Michael Chand3c7b882006-03-23 01:28:25 -080011292
11293 nvcfg1 = tr32(NVRAM_CFG1);
11294
11295 /* NVRAM protection for TPM */
Matt Carlson989a9d22007-05-05 11:51:05 -070011296 if (nvcfg1 & (1 << 27)) {
Matt Carlsonf66a29b2009-11-13 13:03:36 +000011297 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
Matt Carlson989a9d22007-05-05 11:51:05 -070011298 protect = 1;
11299 }
Michael Chand3c7b882006-03-23 01:28:25 -080011300
Matt Carlson989a9d22007-05-05 11:51:05 -070011301 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11302 switch (nvcfg1) {
Matt Carlson8590a602009-08-28 12:29:16 +000011303 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11304 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11305 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11306 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11307 tp->nvram_jedecnum = JEDEC_ATMEL;
11308 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11309 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11310 tp->nvram_pagesize = 264;
11311 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11312 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11313 tp->nvram_size = (protect ? 0x3e200 :
11314 TG3_NVRAM_SIZE_512KB);
11315 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11316 tp->nvram_size = (protect ? 0x1f200 :
11317 TG3_NVRAM_SIZE_256KB);
11318 else
11319 tp->nvram_size = (protect ? 0x1f200 :
11320 TG3_NVRAM_SIZE_128KB);
11321 break;
11322 case FLASH_5752VENDOR_ST_M45PE10:
11323 case FLASH_5752VENDOR_ST_M45PE20:
11324 case FLASH_5752VENDOR_ST_M45PE40:
11325 tp->nvram_jedecnum = JEDEC_ST;
11326 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11327 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11328 tp->nvram_pagesize = 256;
11329 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11330 tp->nvram_size = (protect ?
11331 TG3_NVRAM_SIZE_64KB :
11332 TG3_NVRAM_SIZE_128KB);
11333 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11334 tp->nvram_size = (protect ?
11335 TG3_NVRAM_SIZE_64KB :
11336 TG3_NVRAM_SIZE_256KB);
11337 else
11338 tp->nvram_size = (protect ?
11339 TG3_NVRAM_SIZE_128KB :
11340 TG3_NVRAM_SIZE_512KB);
11341 break;
Michael Chand3c7b882006-03-23 01:28:25 -080011342 }
11343}
11344
Michael Chan1b277772006-03-20 22:27:48 -080011345static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11346{
11347 u32 nvcfg1;
11348
11349 nvcfg1 = tr32(NVRAM_CFG1);
11350
11351 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
Matt Carlson8590a602009-08-28 12:29:16 +000011352 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11353 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11354 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11355 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11356 tp->nvram_jedecnum = JEDEC_ATMEL;
11357 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11358 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
Michael Chan1b277772006-03-20 22:27:48 -080011359
Matt Carlson8590a602009-08-28 12:29:16 +000011360 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11361 tw32(NVRAM_CFG1, nvcfg1);
11362 break;
11363 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11364 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11365 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11366 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11367 tp->nvram_jedecnum = JEDEC_ATMEL;
11368 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11369 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11370 tp->nvram_pagesize = 264;
11371 break;
11372 case FLASH_5752VENDOR_ST_M45PE10:
11373 case FLASH_5752VENDOR_ST_M45PE20:
11374 case FLASH_5752VENDOR_ST_M45PE40:
11375 tp->nvram_jedecnum = JEDEC_ST;
11376 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11377 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11378 tp->nvram_pagesize = 256;
11379 break;
Michael Chan1b277772006-03-20 22:27:48 -080011380 }
11381}
11382
Matt Carlson6b91fa02007-10-10 18:01:09 -070011383static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11384{
11385 u32 nvcfg1, protect = 0;
11386
11387 nvcfg1 = tr32(NVRAM_CFG1);
11388
11389 /* NVRAM protection for TPM */
11390 if (nvcfg1 & (1 << 27)) {
Matt Carlsonf66a29b2009-11-13 13:03:36 +000011391 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
Matt Carlson6b91fa02007-10-10 18:01:09 -070011392 protect = 1;
11393 }
11394
11395 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11396 switch (nvcfg1) {
Matt Carlson8590a602009-08-28 12:29:16 +000011397 case FLASH_5761VENDOR_ATMEL_ADB021D:
11398 case FLASH_5761VENDOR_ATMEL_ADB041D:
11399 case FLASH_5761VENDOR_ATMEL_ADB081D:
11400 case FLASH_5761VENDOR_ATMEL_ADB161D:
11401 case FLASH_5761VENDOR_ATMEL_MDB021D:
11402 case FLASH_5761VENDOR_ATMEL_MDB041D:
11403 case FLASH_5761VENDOR_ATMEL_MDB081D:
11404 case FLASH_5761VENDOR_ATMEL_MDB161D:
11405 tp->nvram_jedecnum = JEDEC_ATMEL;
11406 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11407 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11408 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11409 tp->nvram_pagesize = 256;
11410 break;
11411 case FLASH_5761VENDOR_ST_A_M45PE20:
11412 case FLASH_5761VENDOR_ST_A_M45PE40:
11413 case FLASH_5761VENDOR_ST_A_M45PE80:
11414 case FLASH_5761VENDOR_ST_A_M45PE16:
11415 case FLASH_5761VENDOR_ST_M_M45PE20:
11416 case FLASH_5761VENDOR_ST_M_M45PE40:
11417 case FLASH_5761VENDOR_ST_M_M45PE80:
11418 case FLASH_5761VENDOR_ST_M_M45PE16:
11419 tp->nvram_jedecnum = JEDEC_ST;
11420 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11421 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11422 tp->nvram_pagesize = 256;
11423 break;
Matt Carlson6b91fa02007-10-10 18:01:09 -070011424 }
11425
11426 if (protect) {
11427 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11428 } else {
11429 switch (nvcfg1) {
Matt Carlson8590a602009-08-28 12:29:16 +000011430 case FLASH_5761VENDOR_ATMEL_ADB161D:
11431 case FLASH_5761VENDOR_ATMEL_MDB161D:
11432 case FLASH_5761VENDOR_ST_A_M45PE16:
11433 case FLASH_5761VENDOR_ST_M_M45PE16:
11434 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11435 break;
11436 case FLASH_5761VENDOR_ATMEL_ADB081D:
11437 case FLASH_5761VENDOR_ATMEL_MDB081D:
11438 case FLASH_5761VENDOR_ST_A_M45PE80:
11439 case FLASH_5761VENDOR_ST_M_M45PE80:
11440 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11441 break;
11442 case FLASH_5761VENDOR_ATMEL_ADB041D:
11443 case FLASH_5761VENDOR_ATMEL_MDB041D:
11444 case FLASH_5761VENDOR_ST_A_M45PE40:
11445 case FLASH_5761VENDOR_ST_M_M45PE40:
11446 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11447 break;
11448 case FLASH_5761VENDOR_ATMEL_ADB021D:
11449 case FLASH_5761VENDOR_ATMEL_MDB021D:
11450 case FLASH_5761VENDOR_ST_A_M45PE20:
11451 case FLASH_5761VENDOR_ST_M_M45PE20:
11452 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11453 break;
Matt Carlson6b91fa02007-10-10 18:01:09 -070011454 }
11455 }
11456}
11457
Michael Chanb5d37722006-09-27 16:06:21 -070011458static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11459{
11460 tp->nvram_jedecnum = JEDEC_ATMEL;
11461 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11462 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11463}
11464
Matt Carlson321d32a2008-11-21 17:22:19 -080011465static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11466{
11467 u32 nvcfg1;
11468
11469 nvcfg1 = tr32(NVRAM_CFG1);
11470
11471 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11472 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11473 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11474 tp->nvram_jedecnum = JEDEC_ATMEL;
11475 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11476 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11477
11478 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11479 tw32(NVRAM_CFG1, nvcfg1);
11480 return;
11481 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11482 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11483 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11484 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11485 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11486 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11487 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11488 tp->nvram_jedecnum = JEDEC_ATMEL;
11489 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11490 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11491
11492 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11493 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11494 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11495 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11496 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11497 break;
11498 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11499 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11500 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11501 break;
11502 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11503 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11504 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11505 break;
11506 }
11507 break;
11508 case FLASH_5752VENDOR_ST_M45PE10:
11509 case FLASH_5752VENDOR_ST_M45PE20:
11510 case FLASH_5752VENDOR_ST_M45PE40:
11511 tp->nvram_jedecnum = JEDEC_ST;
11512 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11513 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11514
11515 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11516 case FLASH_5752VENDOR_ST_M45PE10:
11517 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11518 break;
11519 case FLASH_5752VENDOR_ST_M45PE20:
11520 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11521 break;
11522 case FLASH_5752VENDOR_ST_M45PE40:
11523 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11524 break;
11525 }
11526 break;
11527 default:
Matt Carlsondf259d82009-04-20 06:57:14 +000011528 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
Matt Carlson321d32a2008-11-21 17:22:19 -080011529 return;
11530 }
11531
Matt Carlsona1b950d2009-09-01 13:20:17 +000011532 tg3_nvram_get_pagesize(tp, nvcfg1);
11533 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
Matt Carlson321d32a2008-11-21 17:22:19 -080011534 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
Matt Carlsona1b950d2009-09-01 13:20:17 +000011535}
11536
11537
11538static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11539{
11540 u32 nvcfg1;
11541
11542 nvcfg1 = tr32(NVRAM_CFG1);
11543
11544 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11545 case FLASH_5717VENDOR_ATMEL_EEPROM:
11546 case FLASH_5717VENDOR_MICRO_EEPROM:
11547 tp->nvram_jedecnum = JEDEC_ATMEL;
11548 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11549 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11550
11551 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11552 tw32(NVRAM_CFG1, nvcfg1);
11553 return;
11554 case FLASH_5717VENDOR_ATMEL_MDB011D:
11555 case FLASH_5717VENDOR_ATMEL_ADB011B:
11556 case FLASH_5717VENDOR_ATMEL_ADB011D:
11557 case FLASH_5717VENDOR_ATMEL_MDB021D:
11558 case FLASH_5717VENDOR_ATMEL_ADB021B:
11559 case FLASH_5717VENDOR_ATMEL_ADB021D:
11560 case FLASH_5717VENDOR_ATMEL_45USPT:
11561 tp->nvram_jedecnum = JEDEC_ATMEL;
11562 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11563 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11564
11565 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11566 case FLASH_5717VENDOR_ATMEL_MDB021D:
11567 case FLASH_5717VENDOR_ATMEL_ADB021B:
11568 case FLASH_5717VENDOR_ATMEL_ADB021D:
11569 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11570 break;
11571 default:
11572 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11573 break;
11574 }
Matt Carlson321d32a2008-11-21 17:22:19 -080011575 break;
Matt Carlsona1b950d2009-09-01 13:20:17 +000011576 case FLASH_5717VENDOR_ST_M_M25PE10:
11577 case FLASH_5717VENDOR_ST_A_M25PE10:
11578 case FLASH_5717VENDOR_ST_M_M45PE10:
11579 case FLASH_5717VENDOR_ST_A_M45PE10:
11580 case FLASH_5717VENDOR_ST_M_M25PE20:
11581 case FLASH_5717VENDOR_ST_A_M25PE20:
11582 case FLASH_5717VENDOR_ST_M_M45PE20:
11583 case FLASH_5717VENDOR_ST_A_M45PE20:
11584 case FLASH_5717VENDOR_ST_25USPT:
11585 case FLASH_5717VENDOR_ST_45USPT:
11586 tp->nvram_jedecnum = JEDEC_ST;
11587 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11588 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11589
11590 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11591 case FLASH_5717VENDOR_ST_M_M25PE20:
11592 case FLASH_5717VENDOR_ST_A_M25PE20:
11593 case FLASH_5717VENDOR_ST_M_M45PE20:
11594 case FLASH_5717VENDOR_ST_A_M45PE20:
11595 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11596 break;
11597 default:
11598 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11599 break;
11600 }
Matt Carlson321d32a2008-11-21 17:22:19 -080011601 break;
Matt Carlsona1b950d2009-09-01 13:20:17 +000011602 default:
11603 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11604 return;
Matt Carlson321d32a2008-11-21 17:22:19 -080011605 }
Matt Carlsona1b950d2009-09-01 13:20:17 +000011606
11607 tg3_nvram_get_pagesize(tp, nvcfg1);
11608 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11609 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
Matt Carlson321d32a2008-11-21 17:22:19 -080011610}
11611
Linus Torvalds1da177e2005-04-16 15:20:36 -070011612/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11613static void __devinit tg3_nvram_init(struct tg3 *tp)
11614{
Linus Torvalds1da177e2005-04-16 15:20:36 -070011615 tw32_f(GRC_EEPROM_ADDR,
11616 (EEPROM_ADDR_FSM_RESET |
11617 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11618 EEPROM_ADDR_CLKPERD_SHIFT)));
11619
Michael Chan9d57f012006-12-07 00:23:25 -080011620 msleep(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011621
11622 /* Enable seeprom accesses. */
11623 tw32_f(GRC_LOCAL_CTRL,
11624 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11625 udelay(100);
11626
11627 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11628 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11629 tp->tg3_flags |= TG3_FLAG_NVRAM;
11630
Michael Chanec41c7d2006-01-17 02:40:55 -080011631 if (tg3_nvram_lock(tp)) {
Matt Carlson5129c3a2010-04-05 10:19:23 +000011632 netdev_warn(tp->dev,
11633 "Cannot get nvram lock, %s failed\n",
Joe Perches05dbe002010-02-17 19:44:19 +000011634 __func__);
Michael Chanec41c7d2006-01-17 02:40:55 -080011635 return;
11636 }
Michael Chane6af3012005-04-21 17:12:05 -070011637 tg3_enable_nvram_access(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011638
Matt Carlson989a9d22007-05-05 11:51:05 -070011639 tp->nvram_size = 0;
11640
Michael Chan361b4ac2005-04-21 17:11:21 -070011641 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11642 tg3_get_5752_nvram_info(tp);
Michael Chand3c7b882006-03-23 01:28:25 -080011643 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11644 tg3_get_5755_nvram_info(tp);
Matt Carlsond30cdd22007-10-07 23:28:35 -070011645 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
Matt Carlson57e69832008-05-25 23:48:31 -070011646 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11647 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
Michael Chan1b277772006-03-20 22:27:48 -080011648 tg3_get_5787_nvram_info(tp);
Matt Carlson6b91fa02007-10-10 18:01:09 -070011649 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11650 tg3_get_5761_nvram_info(tp);
Michael Chanb5d37722006-09-27 16:06:21 -070011651 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11652 tg3_get_5906_nvram_info(tp);
Matt Carlsonb703df62009-12-03 08:36:21 +000011653 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11654 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
Matt Carlson321d32a2008-11-21 17:22:19 -080011655 tg3_get_57780_nvram_info(tp);
Matt Carlsona50d0792010-06-05 17:24:37 +000011656 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11657 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
Matt Carlsona1b950d2009-09-01 13:20:17 +000011658 tg3_get_5717_nvram_info(tp);
Michael Chan361b4ac2005-04-21 17:11:21 -070011659 else
11660 tg3_get_nvram_info(tp);
11661
Matt Carlson989a9d22007-05-05 11:51:05 -070011662 if (tp->nvram_size == 0)
11663 tg3_get_nvram_size(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011664
Michael Chane6af3012005-04-21 17:12:05 -070011665 tg3_disable_nvram_access(tp);
Michael Chan381291b2005-12-13 21:08:21 -080011666 tg3_nvram_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011667
11668 } else {
11669 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11670
11671 tg3_get_eeprom_size(tp);
11672 }
11673}
11674
Linus Torvalds1da177e2005-04-16 15:20:36 -070011675static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11676 u32 offset, u32 len, u8 *buf)
11677{
11678 int i, j, rc = 0;
11679 u32 val;
11680
11681 for (i = 0; i < len; i += 4) {
Al Virob9fc7dc2007-12-17 22:59:57 -080011682 u32 addr;
Matt Carlsona9dc5292009-02-25 14:25:30 +000011683 __be32 data;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011684
11685 addr = offset + i;
11686
11687 memcpy(&data, buf + i, 4);
11688
Matt Carlson62cedd12009-04-20 14:52:29 -070011689 /*
11690 * The SEEPROM interface expects the data to always be opposite
11691 * the native endian format. We accomplish this by reversing
11692 * all the operations that would have been performed on the
11693 * data from a call to tg3_nvram_read_be32().
11694 */
11695 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
Linus Torvalds1da177e2005-04-16 15:20:36 -070011696
11697 val = tr32(GRC_EEPROM_ADDR);
11698 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11699
11700 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11701 EEPROM_ADDR_READ);
11702 tw32(GRC_EEPROM_ADDR, val |
11703 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11704 (addr & EEPROM_ADDR_ADDR_MASK) |
11705 EEPROM_ADDR_START |
11706 EEPROM_ADDR_WRITE);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011707
Michael Chan9d57f012006-12-07 00:23:25 -080011708 for (j = 0; j < 1000; j++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011709 val = tr32(GRC_EEPROM_ADDR);
11710
11711 if (val & EEPROM_ADDR_COMPLETE)
11712 break;
Michael Chan9d57f012006-12-07 00:23:25 -080011713 msleep(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011714 }
11715 if (!(val & EEPROM_ADDR_COMPLETE)) {
11716 rc = -EBUSY;
11717 break;
11718 }
11719 }
11720
11721 return rc;
11722}
11723
11724/* offset and length are dword aligned */
11725static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11726 u8 *buf)
11727{
11728 int ret = 0;
11729 u32 pagesize = tp->nvram_pagesize;
11730 u32 pagemask = pagesize - 1;
11731 u32 nvram_cmd;
11732 u8 *tmp;
11733
11734 tmp = kmalloc(pagesize, GFP_KERNEL);
11735 if (tmp == NULL)
11736 return -ENOMEM;
11737
11738 while (len) {
11739 int j;
Michael Chane6af3012005-04-21 17:12:05 -070011740 u32 phy_addr, page_off, size;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011741
11742 phy_addr = offset & ~pagemask;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011743
Linus Torvalds1da177e2005-04-16 15:20:36 -070011744 for (j = 0; j < pagesize; j += 4) {
Matt Carlsona9dc5292009-02-25 14:25:30 +000011745 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11746 (__be32 *) (tmp + j));
11747 if (ret)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011748 break;
11749 }
11750 if (ret)
11751 break;
11752
Matt Carlsonc6cdf432010-04-05 10:19:26 +000011753 page_off = offset & pagemask;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011754 size = pagesize;
11755 if (len < size)
11756 size = len;
11757
11758 len -= size;
11759
11760 memcpy(tmp + page_off, buf, size);
11761
11762 offset = offset + (pagesize - page_off);
11763
Michael Chane6af3012005-04-21 17:12:05 -070011764 tg3_enable_nvram_access(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011765
11766 /*
11767 * Before we can erase the flash page, we need
11768 * to issue a special "write enable" command.
11769 */
11770 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11771
11772 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11773 break;
11774
11775 /* Erase the target page */
11776 tw32(NVRAM_ADDR, phy_addr);
11777
11778 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11779 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11780
Matt Carlsonc6cdf432010-04-05 10:19:26 +000011781 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
Linus Torvalds1da177e2005-04-16 15:20:36 -070011782 break;
11783
11784 /* Issue another write enable to start the write. */
11785 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11786
11787 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11788 break;
11789
11790 for (j = 0; j < pagesize; j += 4) {
Al Virob9fc7dc2007-12-17 22:59:57 -080011791 __be32 data;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011792
Al Virob9fc7dc2007-12-17 22:59:57 -080011793 data = *((__be32 *) (tmp + j));
Matt Carlsona9dc5292009-02-25 14:25:30 +000011794
Al Virob9fc7dc2007-12-17 22:59:57 -080011795 tw32(NVRAM_WRDATA, be32_to_cpu(data));
Linus Torvalds1da177e2005-04-16 15:20:36 -070011796
11797 tw32(NVRAM_ADDR, phy_addr + j);
11798
11799 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11800 NVRAM_CMD_WR;
11801
11802 if (j == 0)
11803 nvram_cmd |= NVRAM_CMD_FIRST;
11804 else if (j == (pagesize - 4))
11805 nvram_cmd |= NVRAM_CMD_LAST;
11806
11807 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11808 break;
11809 }
11810 if (ret)
11811 break;
11812 }
11813
11814 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11815 tg3_nvram_exec_cmd(tp, nvram_cmd);
11816
11817 kfree(tmp);
11818
11819 return ret;
11820}
11821
11822/* offset and length are dword aligned */
11823static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11824 u8 *buf)
11825{
11826 int i, ret = 0;
11827
11828 for (i = 0; i < len; i += 4, offset += 4) {
Al Virob9fc7dc2007-12-17 22:59:57 -080011829 u32 page_off, phy_addr, nvram_cmd;
11830 __be32 data;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011831
11832 memcpy(&data, buf + i, 4);
Al Virob9fc7dc2007-12-17 22:59:57 -080011833 tw32(NVRAM_WRDATA, be32_to_cpu(data));
Linus Torvalds1da177e2005-04-16 15:20:36 -070011834
Matt Carlsonc6cdf432010-04-05 10:19:26 +000011835 page_off = offset % tp->nvram_pagesize;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011836
Michael Chan18201802006-03-20 22:29:15 -080011837 phy_addr = tg3_nvram_phys_addr(tp, offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011838
11839 tw32(NVRAM_ADDR, phy_addr);
11840
11841 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11842
Matt Carlsonc6cdf432010-04-05 10:19:26 +000011843 if (page_off == 0 || i == 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011844 nvram_cmd |= NVRAM_CMD_FIRST;
Michael Chanf6d9a252006-04-29 19:00:24 -070011845 if (page_off == (tp->nvram_pagesize - 4))
Linus Torvalds1da177e2005-04-16 15:20:36 -070011846 nvram_cmd |= NVRAM_CMD_LAST;
11847
11848 if (i == (len - 4))
11849 nvram_cmd |= NVRAM_CMD_LAST;
11850
Matt Carlson321d32a2008-11-21 17:22:19 -080011851 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11852 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
Michael Chan4c987482005-09-05 17:52:38 -070011853 (tp->nvram_jedecnum == JEDEC_ST) &&
11854 (nvram_cmd & NVRAM_CMD_FIRST)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011855
11856 if ((ret = tg3_nvram_exec_cmd(tp,
11857 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11858 NVRAM_CMD_DONE)))
11859
11860 break;
11861 }
11862 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11863 /* We always do complete word writes to eeprom. */
11864 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11865 }
11866
11867 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11868 break;
11869 }
11870 return ret;
11871}
11872
11873/* offset and length are dword aligned */
11874static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11875{
11876 int ret;
11877
Linus Torvalds1da177e2005-04-16 15:20:36 -070011878 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
Michael Chan314fba32005-04-21 17:07:04 -070011879 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11880 ~GRC_LCLCTRL_GPIO_OUTPUT1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011881 udelay(40);
11882 }
11883
11884 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11885 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
Matt Carlson859a588792010-04-05 10:19:28 +000011886 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011887 u32 grc_mode;
11888
Michael Chanec41c7d2006-01-17 02:40:55 -080011889 ret = tg3_nvram_lock(tp);
11890 if (ret)
11891 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011892
Michael Chane6af3012005-04-21 17:12:05 -070011893 tg3_enable_nvram_access(tp);
11894 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
Matt Carlsonf66a29b2009-11-13 13:03:36 +000011895 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
Linus Torvalds1da177e2005-04-16 15:20:36 -070011896 tw32(NVRAM_WRITE1, 0x406);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011897
11898 grc_mode = tr32(GRC_MODE);
11899 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11900
11901 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11902 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11903
11904 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11905 buf);
Matt Carlson859a588792010-04-05 10:19:28 +000011906 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011907 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11908 buf);
11909 }
11910
11911 grc_mode = tr32(GRC_MODE);
11912 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11913
Michael Chane6af3012005-04-21 17:12:05 -070011914 tg3_disable_nvram_access(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011915 tg3_nvram_unlock(tp);
11916 }
11917
11918 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
Michael Chan314fba32005-04-21 17:07:04 -070011919 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011920 udelay(40);
11921 }
11922
11923 return ret;
11924}
11925
11926struct subsys_tbl_ent {
11927 u16 subsys_vendor, subsys_devid;
11928 u32 phy_id;
11929};
11930
Matt Carlson24daf2b2010-02-17 15:17:02 +000011931static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011932 /* Broadcom boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000011933 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000011934 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000011935 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000011936 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000011937 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000011938 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000011939 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11940 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11941 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000011942 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000011943 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000011944 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000011945 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11946 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11947 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000011948 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000011949 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000011950 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000011951 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000011952 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000011953 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000011954 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070011955
11956 /* 3com boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000011957 { TG3PCI_SUBVENDOR_ID_3COM,
Matt Carlson79eb6902010-02-17 15:17:03 +000011958 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000011959 { TG3PCI_SUBVENDOR_ID_3COM,
Matt Carlson79eb6902010-02-17 15:17:03 +000011960 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000011961 { TG3PCI_SUBVENDOR_ID_3COM,
11962 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11963 { TG3PCI_SUBVENDOR_ID_3COM,
Matt Carlson79eb6902010-02-17 15:17:03 +000011964 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000011965 { TG3PCI_SUBVENDOR_ID_3COM,
Matt Carlson79eb6902010-02-17 15:17:03 +000011966 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070011967
11968 /* DELL boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000011969 { TG3PCI_SUBVENDOR_ID_DELL,
Matt Carlson79eb6902010-02-17 15:17:03 +000011970 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000011971 { TG3PCI_SUBVENDOR_ID_DELL,
Matt Carlson79eb6902010-02-17 15:17:03 +000011972 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000011973 { TG3PCI_SUBVENDOR_ID_DELL,
Matt Carlson79eb6902010-02-17 15:17:03 +000011974 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000011975 { TG3PCI_SUBVENDOR_ID_DELL,
Matt Carlson79eb6902010-02-17 15:17:03 +000011976 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070011977
11978 /* Compaq boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000011979 { TG3PCI_SUBVENDOR_ID_COMPAQ,
Matt Carlson79eb6902010-02-17 15:17:03 +000011980 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000011981 { TG3PCI_SUBVENDOR_ID_COMPAQ,
Matt Carlson79eb6902010-02-17 15:17:03 +000011982 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000011983 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11984 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
11985 { TG3PCI_SUBVENDOR_ID_COMPAQ,
Matt Carlson79eb6902010-02-17 15:17:03 +000011986 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000011987 { TG3PCI_SUBVENDOR_ID_COMPAQ,
Matt Carlson79eb6902010-02-17 15:17:03 +000011988 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070011989
11990 /* IBM boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000011991 { TG3PCI_SUBVENDOR_ID_IBM,
11992 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070011993};
11994
Matt Carlson24daf2b2010-02-17 15:17:02 +000011995static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011996{
11997 int i;
11998
11999 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12000 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12001 tp->pdev->subsystem_vendor) &&
12002 (subsys_id_to_phy_id[i].subsys_devid ==
12003 tp->pdev->subsystem_device))
12004 return &subsys_id_to_phy_id[i];
12005 }
12006 return NULL;
12007}
12008
Michael Chan7d0c41e2005-04-21 17:06:20 -070012009static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012010{
Linus Torvalds1da177e2005-04-16 15:20:36 -070012011 u32 val;
Michael Chancaf636c72006-03-22 01:05:31 -080012012 u16 pmcsr;
12013
12014 /* On some early chips the SRAM cannot be accessed in D3hot state,
12015 * so need make sure we're in D0.
12016 */
12017 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12018 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12019 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12020 msleep(1);
Michael Chan7d0c41e2005-04-21 17:06:20 -070012021
12022 /* Make sure register accesses (indirect or otherwise)
12023 * will function correctly.
12024 */
12025 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12026 tp->misc_host_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012027
David S. Millerf49639e2006-06-09 11:58:36 -070012028 /* The memory arbiter has to be enabled in order for SRAM accesses
12029 * to succeed. Normally on powerup the tg3 chip firmware will make
12030 * sure it is enabled, but other entities such as system netboot
12031 * code might disable it.
12032 */
12033 val = tr32(MEMARB_MODE);
12034 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12035
Matt Carlson79eb6902010-02-17 15:17:03 +000012036 tp->phy_id = TG3_PHY_ID_INVALID;
Michael Chan7d0c41e2005-04-21 17:06:20 -070012037 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12038
Gary Zambranoa85feb82007-05-05 11:52:19 -070012039 /* Assume an onboard device and WOL capable by default. */
12040 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
David S. Miller72b845e2006-03-14 14:11:48 -080012041
Michael Chanb5d37722006-09-27 16:06:21 -070012042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chan9d26e212006-12-07 00:21:14 -080012043 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
Michael Chanb5d37722006-09-27 16:06:21 -070012044 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
Michael Chan9d26e212006-12-07 00:21:14 -080012045 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12046 }
Matt Carlson0527ba32007-10-10 18:03:30 -070012047 val = tr32(VCPU_CFGSHDW);
12048 if (val & VCPU_CFGSHDW_ASPM_DBNC)
Matt Carlson8ed5d972007-05-07 00:25:49 -070012049 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
Matt Carlson0527ba32007-10-10 18:03:30 -070012050 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
Matt Carlson20232762008-12-21 20:18:56 -080012051 (val & VCPU_CFGSHDW_WOL_MAGPKT))
Matt Carlson0527ba32007-10-10 18:03:30 -070012052 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
Matt Carlson05ac4cb2008-11-03 16:53:46 -080012053 goto done;
Michael Chanb5d37722006-09-27 16:06:21 -070012054 }
12055
Linus Torvalds1da177e2005-04-16 15:20:36 -070012056 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12057 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12058 u32 nic_cfg, led_cfg;
Matt Carlsona9daf362008-05-25 23:49:44 -070012059 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
Michael Chan7d0c41e2005-04-21 17:06:20 -070012060 int eeprom_phy_serdes = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012061
12062 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12063 tp->nic_sram_data_cfg = nic_cfg;
12064
12065 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12066 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12067 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12068 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12069 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12070 (ver > 0) && (ver < 0x100))
12071 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12072
Matt Carlsona9daf362008-05-25 23:49:44 -070012073 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12074 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12075
Linus Torvalds1da177e2005-04-16 15:20:36 -070012076 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12077 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12078 eeprom_phy_serdes = 1;
12079
12080 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12081 if (nic_phy_id != 0) {
12082 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12083 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12084
12085 eeprom_phy_id = (id1 >> 16) << 10;
12086 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12087 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12088 } else
12089 eeprom_phy_id = 0;
12090
Michael Chan7d0c41e2005-04-21 17:06:20 -070012091 tp->phy_id = eeprom_phy_id;
Michael Chan747e8f82005-07-25 12:33:22 -070012092 if (eeprom_phy_serdes) {
Matt Carlsona50d0792010-06-05 17:24:37 +000012093 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012094 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
Matt Carlsona50d0792010-06-05 17:24:37 +000012095 else
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012096 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
Michael Chan747e8f82005-07-25 12:33:22 -070012097 }
Michael Chan7d0c41e2005-04-21 17:06:20 -070012098
John W. Linvillecbf46852005-04-21 17:01:29 -070012099 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012100 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12101 SHASTA_EXT_LED_MODE_MASK);
John W. Linvillecbf46852005-04-21 17:01:29 -070012102 else
Linus Torvalds1da177e2005-04-16 15:20:36 -070012103 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12104
12105 switch (led_cfg) {
12106 default:
12107 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12108 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12109 break;
12110
12111 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12112 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12113 break;
12114
12115 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12116 tp->led_ctrl = LED_CTRL_MODE_MAC;
Michael Chan9ba27792005-06-06 15:16:20 -070012117
12118 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12119 * read on some older 5700/5701 bootcode.
12120 */
12121 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12122 ASIC_REV_5700 ||
12123 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12124 ASIC_REV_5701)
12125 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12126
Linus Torvalds1da177e2005-04-16 15:20:36 -070012127 break;
12128
12129 case SHASTA_EXT_LED_SHARED:
12130 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12131 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12132 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12133 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12134 LED_CTRL_MODE_PHY_2);
12135 break;
12136
12137 case SHASTA_EXT_LED_MAC:
12138 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12139 break;
12140
12141 case SHASTA_EXT_LED_COMBO:
12142 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12143 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12144 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12145 LED_CTRL_MODE_PHY_2);
12146 break;
12147
Stephen Hemminger855e1112008-04-16 16:37:28 -070012148 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070012149
12150 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12151 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12152 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12153 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12154
Matt Carlsonb2a5c192008-04-03 21:44:44 -070012155 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12156 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
Matt Carlson5f608912007-11-12 21:17:07 -080012157
Michael Chan9d26e212006-12-07 00:21:14 -080012158 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012159 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
Michael Chan9d26e212006-12-07 00:21:14 -080012160 if ((tp->pdev->subsystem_vendor ==
12161 PCI_VENDOR_ID_ARIMA) &&
12162 (tp->pdev->subsystem_device == 0x205a ||
12163 tp->pdev->subsystem_device == 0x2063))
12164 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12165 } else {
David S. Millerf49639e2006-06-09 11:58:36 -070012166 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
Michael Chan9d26e212006-12-07 00:21:14 -080012167 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12168 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070012169
12170 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12171 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
John W. Linvillecbf46852005-04-21 17:01:29 -070012172 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012173 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12174 }
Matt Carlsonb2b98d42008-11-03 16:52:32 -080012175
12176 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12177 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
Matt Carlson0d3031d2007-10-10 18:02:43 -070012178 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
Matt Carlsonb2b98d42008-11-03 16:52:32 -080012179
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012180 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
Gary Zambranoa85feb82007-05-05 11:52:19 -070012181 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12182 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012183
Rafael J. Wysocki12dac072008-07-30 16:37:33 -070012184 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
Matt Carlson05ac4cb2008-11-03 16:53:46 -080012185 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
Matt Carlson0527ba32007-10-10 18:03:30 -070012186 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12187
Linus Torvalds1da177e2005-04-16 15:20:36 -070012188 if (cfg2 & (1 << 17))
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012189 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012190
12191 /* serdes signal pre-emphasis in register 0x590 set by */
12192 /* bootcode if bit 18 is set */
12193 if (cfg2 & (1 << 18))
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012194 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
Matt Carlson8ed5d972007-05-07 00:25:49 -070012195
Matt Carlson321d32a2008-11-21 17:22:19 -080012196 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12197 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
Matt Carlson6833c042008-11-21 17:18:59 -080012198 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012199 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
Matt Carlson6833c042008-11-21 17:18:59 -080012200
Matt Carlson8c69b1e2010-08-02 11:26:00 +000012201 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12202 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12203 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
Matt Carlson8ed5d972007-05-07 00:25:49 -070012204 u32 cfg3;
12205
12206 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12207 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12208 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12209 }
Matt Carlsona9daf362008-05-25 23:49:44 -070012210
Matt Carlson14417062010-02-17 15:16:59 +000012211 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12212 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
Matt Carlsona9daf362008-05-25 23:49:44 -070012213 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12214 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12215 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12216 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012217 }
Matt Carlson05ac4cb2008-11-03 16:53:46 -080012218done:
12219 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12220 device_set_wakeup_enable(&tp->pdev->dev,
12221 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
Michael Chan7d0c41e2005-04-21 17:06:20 -070012222}
12223
Matt Carlsonb2a5c192008-04-03 21:44:44 -070012224static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12225{
12226 int i;
12227 u32 val;
12228
12229 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12230 tw32(OTP_CTRL, cmd);
12231
12232 /* Wait for up to 1 ms for command to execute. */
12233 for (i = 0; i < 100; i++) {
12234 val = tr32(OTP_STATUS);
12235 if (val & OTP_STATUS_CMD_DONE)
12236 break;
12237 udelay(10);
12238 }
12239
12240 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12241}
12242
12243/* Read the gphy configuration from the OTP region of the chip. The gphy
12244 * configuration is a 32-bit value that straddles the alignment boundary.
12245 * We do two 32-bit reads and then shift and merge the results.
12246 */
12247static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12248{
12249 u32 bhalf_otp, thalf_otp;
12250
12251 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12252
12253 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12254 return 0;
12255
12256 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12257
12258 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12259 return 0;
12260
12261 thalf_otp = tr32(OTP_READ_DATA);
12262
12263 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12264
12265 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12266 return 0;
12267
12268 bhalf_otp = tr32(OTP_READ_DATA);
12269
12270 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12271}
12272
Michael Chan7d0c41e2005-04-21 17:06:20 -070012273static int __devinit tg3_phy_probe(struct tg3 *tp)
12274{
12275 u32 hw_phy_id_1, hw_phy_id_2;
12276 u32 hw_phy_id, hw_phy_id_masked;
12277 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012278
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070012279 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12280 return tg3_phy_init(tp);
12281
Linus Torvalds1da177e2005-04-16 15:20:36 -070012282 /* Reading the PHY ID register can conflict with ASF
Nick Andrew877d0312009-01-26 11:06:57 +010012283 * firmware access to the PHY hardware.
Linus Torvalds1da177e2005-04-16 15:20:36 -070012284 */
12285 err = 0;
Matt Carlson0d3031d2007-10-10 18:02:43 -070012286 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12287 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
Matt Carlson79eb6902010-02-17 15:17:03 +000012288 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012289 } else {
12290 /* Now read the physical PHY_ID from the chip and verify
12291 * that it is sane. If it doesn't look good, we fall back
12292 * to either the hard-coded table based PHY_ID and failing
12293 * that the value found in the eeprom area.
12294 */
12295 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12296 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12297
12298 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12299 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12300 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12301
Matt Carlson79eb6902010-02-17 15:17:03 +000012302 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012303 }
12304
Matt Carlson79eb6902010-02-17 15:17:03 +000012305 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012306 tp->phy_id = hw_phy_id;
Matt Carlson79eb6902010-02-17 15:17:03 +000012307 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012308 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
Michael Chanda6b2d02005-08-19 12:54:29 -070012309 else
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012310 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012311 } else {
Matt Carlson79eb6902010-02-17 15:17:03 +000012312 if (tp->phy_id != TG3_PHY_ID_INVALID) {
Michael Chan7d0c41e2005-04-21 17:06:20 -070012313 /* Do nothing, phy ID already set up in
12314 * tg3_get_eeprom_hw_cfg().
12315 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070012316 } else {
12317 struct subsys_tbl_ent *p;
12318
12319 /* No eeprom signature? Try the hardcoded
12320 * subsys device table.
12321 */
Matt Carlson24daf2b2010-02-17 15:17:02 +000012322 p = tg3_lookup_by_subsys(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012323 if (!p)
12324 return -ENODEV;
12325
12326 tp->phy_id = p->phy_id;
12327 if (!tp->phy_id ||
Matt Carlson79eb6902010-02-17 15:17:03 +000012328 tp->phy_id == TG3_PHY_ID_BCM8002)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012329 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012330 }
12331 }
12332
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012333 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
Matt Carlson0d3031d2007-10-10 18:02:43 -070012334 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -070012335 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
Michael Chan3600d912006-12-07 00:21:48 -080012336 u32 bmsr, adv_reg, tg3_ctrl, mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012337
12338 tg3_readphy(tp, MII_BMSR, &bmsr);
12339 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12340 (bmsr & BMSR_LSTATUS))
12341 goto skip_phy_reset;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040012342
Linus Torvalds1da177e2005-04-16 15:20:36 -070012343 err = tg3_phy_reset(tp);
12344 if (err)
12345 return err;
12346
12347 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12348 ADVERTISE_100HALF | ADVERTISE_100FULL |
12349 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12350 tg3_ctrl = 0;
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012351 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012352 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12353 MII_TG3_CTRL_ADV_1000_FULL);
12354 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12355 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12356 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12357 MII_TG3_CTRL_ENABLE_AS_MASTER);
12358 }
12359
Michael Chan3600d912006-12-07 00:21:48 -080012360 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12361 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12362 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12363 if (!tg3_copper_is_advertising_all(tp, mask)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012364 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12365
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012366 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
Linus Torvalds1da177e2005-04-16 15:20:36 -070012367 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12368
12369 tg3_writephy(tp, MII_BMCR,
12370 BMCR_ANENABLE | BMCR_ANRESTART);
12371 }
12372 tg3_phy_set_wirespeed(tp);
12373
12374 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012375 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
Linus Torvalds1da177e2005-04-16 15:20:36 -070012376 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12377 }
12378
12379skip_phy_reset:
Matt Carlson79eb6902010-02-17 15:17:03 +000012380 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012381 err = tg3_init_5401phy_dsp(tp);
12382 if (err)
12383 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012384
Linus Torvalds1da177e2005-04-16 15:20:36 -070012385 err = tg3_init_5401phy_dsp(tp);
12386 }
12387
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012388 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012389 tp->link_config.advertising =
12390 (ADVERTISED_1000baseT_Half |
12391 ADVERTISED_1000baseT_Full |
12392 ADVERTISED_Autoneg |
12393 ADVERTISED_FIBRE);
Matt Carlsonf07e9af2010-08-02 11:26:07 +000012394 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012395 tp->link_config.advertising &=
12396 ~(ADVERTISED_1000baseT_Half |
12397 ADVERTISED_1000baseT_Full);
12398
12399 return err;
12400}
12401
Matt Carlson184b8902010-04-05 10:19:25 +000012402static void __devinit tg3_read_vpd(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012403{
Matt Carlson184b8902010-04-05 10:19:25 +000012404 u8 vpd_data[TG3_NVM_VPD_LEN];
Matt Carlson4181b2c2010-02-26 14:04:45 +000012405 unsigned int block_end, rosize, len;
Matt Carlson184b8902010-04-05 10:19:25 +000012406 int j, i = 0;
Michael Chan1b277772006-03-20 22:27:48 -080012407 u32 magic;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012408
Matt Carlsondf259d82009-04-20 06:57:14 +000012409 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12410 tg3_nvram_read(tp, 0x0, &magic))
David S. Millerf49639e2006-06-09 11:58:36 -070012411 goto out_not_found;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012412
Michael Chan18201802006-03-20 22:29:15 -080012413 if (magic == TG3_EEPROM_MAGIC) {
Matt Carlson141518c2009-12-03 08:36:22 +000012414 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
Michael Chan1b277772006-03-20 22:27:48 -080012415 u32 tmp;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012416
Matt Carlson6d348f22009-02-25 14:25:52 +000012417 /* The data is in little-endian format in NVRAM.
12418 * Use the big-endian read routines to preserve
12419 * the byte order as it exists in NVRAM.
12420 */
Matt Carlson141518c2009-12-03 08:36:22 +000012421 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
Michael Chan1b277772006-03-20 22:27:48 -080012422 goto out_not_found;
12423
Matt Carlson6d348f22009-02-25 14:25:52 +000012424 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
Michael Chan1b277772006-03-20 22:27:48 -080012425 }
12426 } else {
Matt Carlson94c982b2009-12-03 08:36:23 +000012427 ssize_t cnt;
Matt Carlson4181b2c2010-02-26 14:04:45 +000012428 unsigned int pos = 0;
Michael Chan1b277772006-03-20 22:27:48 -080012429
Matt Carlson94c982b2009-12-03 08:36:23 +000012430 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12431 cnt = pci_read_vpd(tp->pdev, pos,
12432 TG3_NVM_VPD_LEN - pos,
12433 &vpd_data[pos]);
12434 if (cnt == -ETIMEDOUT || -EINTR)
12435 cnt = 0;
12436 else if (cnt < 0)
David S. Millerf49639e2006-06-09 11:58:36 -070012437 goto out_not_found;
Michael Chan1b277772006-03-20 22:27:48 -080012438 }
Matt Carlson94c982b2009-12-03 08:36:23 +000012439 if (pos != TG3_NVM_VPD_LEN)
12440 goto out_not_found;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012441 }
12442
Matt Carlson4181b2c2010-02-26 14:04:45 +000012443 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12444 PCI_VPD_LRDT_RO_DATA);
12445 if (i < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012446 goto out_not_found;
Matt Carlson4181b2c2010-02-26 14:04:45 +000012447
12448 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12449 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12450 i += PCI_VPD_LRDT_TAG_SIZE;
12451
12452 if (block_end > TG3_NVM_VPD_LEN)
12453 goto out_not_found;
12454
Matt Carlson184b8902010-04-05 10:19:25 +000012455 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12456 PCI_VPD_RO_KEYWORD_MFR_ID);
12457 if (j > 0) {
12458 len = pci_vpd_info_field_size(&vpd_data[j]);
12459
12460 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12461 if (j + len > block_end || len != 4 ||
12462 memcmp(&vpd_data[j], "1028", 4))
12463 goto partno;
12464
12465 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12466 PCI_VPD_RO_KEYWORD_VENDOR0);
12467 if (j < 0)
12468 goto partno;
12469
12470 len = pci_vpd_info_field_size(&vpd_data[j]);
12471
12472 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12473 if (j + len > block_end)
12474 goto partno;
12475
12476 memcpy(tp->fw_ver, &vpd_data[j], len);
12477 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12478 }
12479
12480partno:
Matt Carlson4181b2c2010-02-26 14:04:45 +000012481 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12482 PCI_VPD_RO_KEYWORD_PARTNO);
12483 if (i < 0)
12484 goto out_not_found;
12485
12486 len = pci_vpd_info_field_size(&vpd_data[i]);
12487
12488 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12489 if (len > TG3_BPN_SIZE ||
12490 (len + i) > TG3_NVM_VPD_LEN)
12491 goto out_not_found;
12492
12493 memcpy(tp->board_part_number, &vpd_data[i], len);
12494
12495 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012496
12497out_not_found:
Michael Chanb5d37722006-09-27 16:06:21 -070012498 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12499 strcpy(tp->board_part_number, "BCM95906");
Matt Carlsondf259d82009-04-20 06:57:14 +000012500 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12501 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12502 strcpy(tp->board_part_number, "BCM57780");
12503 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12504 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12505 strcpy(tp->board_part_number, "BCM57760");
12506 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12507 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12508 strcpy(tp->board_part_number, "BCM57790");
Matt Carlson5e7ccf22009-08-25 10:08:42 +000012509 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12510 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12511 strcpy(tp->board_part_number, "BCM57788");
Matt Carlsonb474eca2010-02-17 15:16:58 +000012512 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12513 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12514 strcpy(tp->board_part_number, "BCM57761");
12515 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12516 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
Matt Carlsonb703df62009-12-03 08:36:21 +000012517 strcpy(tp->board_part_number, "BCM57765");
Matt Carlsonb474eca2010-02-17 15:16:58 +000012518 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12519 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12520 strcpy(tp->board_part_number, "BCM57781");
12521 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12522 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12523 strcpy(tp->board_part_number, "BCM57785");
12524 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12525 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12526 strcpy(tp->board_part_number, "BCM57791");
12527 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12528 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12529 strcpy(tp->board_part_number, "BCM57795");
Michael Chanb5d37722006-09-27 16:06:21 -070012530 else
12531 strcpy(tp->board_part_number, "none");
Linus Torvalds1da177e2005-04-16 15:20:36 -070012532}
12533
Matt Carlson9c8a6202007-10-21 16:16:08 -070012534static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12535{
12536 u32 val;
12537
Matt Carlsone4f34112009-02-25 14:25:00 +000012538 if (tg3_nvram_read(tp, offset, &val) ||
Matt Carlson9c8a6202007-10-21 16:16:08 -070012539 (val & 0xfc000000) != 0x0c000000 ||
Matt Carlsone4f34112009-02-25 14:25:00 +000012540 tg3_nvram_read(tp, offset + 4, &val) ||
Matt Carlson9c8a6202007-10-21 16:16:08 -070012541 val != 0)
12542 return 0;
12543
12544 return 1;
12545}
12546
Matt Carlsonacd9c112009-02-25 14:26:33 +000012547static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12548{
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000012549 u32 val, offset, start, ver_offset;
Matt Carlson75f99362010-04-05 10:19:24 +000012550 int i, dst_off;
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000012551 bool newver = false;
Matt Carlsonacd9c112009-02-25 14:26:33 +000012552
12553 if (tg3_nvram_read(tp, 0xc, &offset) ||
12554 tg3_nvram_read(tp, 0x4, &start))
12555 return;
12556
12557 offset = tg3_nvram_logical_addr(tp, offset);
12558
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000012559 if (tg3_nvram_read(tp, offset, &val))
Matt Carlsonacd9c112009-02-25 14:26:33 +000012560 return;
12561
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000012562 if ((val & 0xfc000000) == 0x0c000000) {
12563 if (tg3_nvram_read(tp, offset + 4, &val))
Matt Carlsonacd9c112009-02-25 14:26:33 +000012564 return;
12565
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000012566 if (val == 0)
12567 newver = true;
12568 }
12569
Matt Carlson75f99362010-04-05 10:19:24 +000012570 dst_off = strlen(tp->fw_ver);
12571
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000012572 if (newver) {
Matt Carlson75f99362010-04-05 10:19:24 +000012573 if (TG3_VER_SIZE - dst_off < 16 ||
12574 tg3_nvram_read(tp, offset + 8, &ver_offset))
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000012575 return;
12576
12577 offset = offset + ver_offset - start;
12578 for (i = 0; i < 16; i += 4) {
12579 __be32 v;
12580 if (tg3_nvram_read_be32(tp, offset + i, &v))
12581 return;
12582
Matt Carlson75f99362010-04-05 10:19:24 +000012583 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000012584 }
12585 } else {
12586 u32 major, minor;
12587
12588 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12589 return;
12590
12591 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12592 TG3_NVM_BCVER_MAJSFT;
12593 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
Matt Carlson75f99362010-04-05 10:19:24 +000012594 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12595 "v%d.%02d", major, minor);
Matt Carlsonacd9c112009-02-25 14:26:33 +000012596 }
12597}
12598
Matt Carlsona6f6cb12009-02-25 14:27:43 +000012599static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12600{
12601 u32 val, major, minor;
12602
12603 /* Use native endian representation */
12604 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12605 return;
12606
12607 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12608 TG3_NVM_HWSB_CFG1_MAJSFT;
12609 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12610 TG3_NVM_HWSB_CFG1_MINSFT;
12611
12612 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12613}
12614
Matt Carlsondfe00d72008-11-21 17:19:41 -080012615static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12616{
12617 u32 offset, major, minor, build;
12618
Matt Carlson75f99362010-04-05 10:19:24 +000012619 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
Matt Carlsondfe00d72008-11-21 17:19:41 -080012620
12621 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12622 return;
12623
12624 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12625 case TG3_EEPROM_SB_REVISION_0:
12626 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12627 break;
12628 case TG3_EEPROM_SB_REVISION_2:
12629 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12630 break;
12631 case TG3_EEPROM_SB_REVISION_3:
12632 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12633 break;
Matt Carlsona4153d42010-02-17 15:16:56 +000012634 case TG3_EEPROM_SB_REVISION_4:
12635 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12636 break;
12637 case TG3_EEPROM_SB_REVISION_5:
12638 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12639 break;
Matt Carlsondfe00d72008-11-21 17:19:41 -080012640 default:
12641 return;
12642 }
12643
Matt Carlsone4f34112009-02-25 14:25:00 +000012644 if (tg3_nvram_read(tp, offset, &val))
Matt Carlsondfe00d72008-11-21 17:19:41 -080012645 return;
12646
12647 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12648 TG3_EEPROM_SB_EDH_BLD_SHFT;
12649 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12650 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12651 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12652
12653 if (minor > 99 || build > 26)
12654 return;
12655
Matt Carlson75f99362010-04-05 10:19:24 +000012656 offset = strlen(tp->fw_ver);
12657 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12658 " v%d.%02d", major, minor);
Matt Carlsondfe00d72008-11-21 17:19:41 -080012659
12660 if (build > 0) {
Matt Carlson75f99362010-04-05 10:19:24 +000012661 offset = strlen(tp->fw_ver);
12662 if (offset < TG3_VER_SIZE - 1)
12663 tp->fw_ver[offset] = 'a' + build - 1;
Matt Carlsondfe00d72008-11-21 17:19:41 -080012664 }
12665}
12666
Matt Carlsonacd9c112009-02-25 14:26:33 +000012667static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
Michael Chanc4e65752006-03-20 22:29:32 -080012668{
12669 u32 val, offset, start;
Matt Carlsonacd9c112009-02-25 14:26:33 +000012670 int i, vlen;
Matt Carlson9c8a6202007-10-21 16:16:08 -070012671
12672 for (offset = TG3_NVM_DIR_START;
12673 offset < TG3_NVM_DIR_END;
12674 offset += TG3_NVM_DIRENT_SIZE) {
Matt Carlsone4f34112009-02-25 14:25:00 +000012675 if (tg3_nvram_read(tp, offset, &val))
Matt Carlson9c8a6202007-10-21 16:16:08 -070012676 return;
12677
12678 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12679 break;
12680 }
12681
12682 if (offset == TG3_NVM_DIR_END)
12683 return;
12684
12685 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12686 start = 0x08000000;
Matt Carlsone4f34112009-02-25 14:25:00 +000012687 else if (tg3_nvram_read(tp, offset - 4, &start))
Matt Carlson9c8a6202007-10-21 16:16:08 -070012688 return;
12689
Matt Carlsone4f34112009-02-25 14:25:00 +000012690 if (tg3_nvram_read(tp, offset + 4, &offset) ||
Matt Carlson9c8a6202007-10-21 16:16:08 -070012691 !tg3_fw_img_is_valid(tp, offset) ||
Matt Carlsone4f34112009-02-25 14:25:00 +000012692 tg3_nvram_read(tp, offset + 8, &val))
Matt Carlson9c8a6202007-10-21 16:16:08 -070012693 return;
12694
12695 offset += val - start;
12696
Matt Carlsonacd9c112009-02-25 14:26:33 +000012697 vlen = strlen(tp->fw_ver);
Matt Carlson9c8a6202007-10-21 16:16:08 -070012698
Matt Carlsonacd9c112009-02-25 14:26:33 +000012699 tp->fw_ver[vlen++] = ',';
12700 tp->fw_ver[vlen++] = ' ';
Matt Carlson9c8a6202007-10-21 16:16:08 -070012701
12702 for (i = 0; i < 4; i++) {
Matt Carlsona9dc5292009-02-25 14:25:30 +000012703 __be32 v;
12704 if (tg3_nvram_read_be32(tp, offset, &v))
Matt Carlson9c8a6202007-10-21 16:16:08 -070012705 return;
12706
Al Virob9fc7dc2007-12-17 22:59:57 -080012707 offset += sizeof(v);
Matt Carlson9c8a6202007-10-21 16:16:08 -070012708
Matt Carlsonacd9c112009-02-25 14:26:33 +000012709 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12710 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
Matt Carlson9c8a6202007-10-21 16:16:08 -070012711 break;
12712 }
12713
Matt Carlsonacd9c112009-02-25 14:26:33 +000012714 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12715 vlen += sizeof(v);
Matt Carlson9c8a6202007-10-21 16:16:08 -070012716 }
Matt Carlsonacd9c112009-02-25 14:26:33 +000012717}
12718
Matt Carlson7fd76442009-02-25 14:27:20 +000012719static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12720{
12721 int vlen;
12722 u32 apedata;
Matt Carlsonecc79642010-08-02 11:26:01 +000012723 char *fwtype;
Matt Carlson7fd76442009-02-25 14:27:20 +000012724
12725 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12726 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12727 return;
12728
12729 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12730 if (apedata != APE_SEG_SIG_MAGIC)
12731 return;
12732
12733 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12734 if (!(apedata & APE_FW_STATUS_READY))
12735 return;
12736
12737 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12738
Matt Carlsonecc79642010-08-02 11:26:01 +000012739 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
12740 fwtype = "NCSI";
12741 else
12742 fwtype = "DASH";
12743
Matt Carlson7fd76442009-02-25 14:27:20 +000012744 vlen = strlen(tp->fw_ver);
12745
Matt Carlsonecc79642010-08-02 11:26:01 +000012746 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12747 fwtype,
Matt Carlson7fd76442009-02-25 14:27:20 +000012748 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12749 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12750 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12751 (apedata & APE_FW_VERSION_BLDMSK));
12752}
12753
Matt Carlsonacd9c112009-02-25 14:26:33 +000012754static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12755{
12756 u32 val;
Matt Carlson75f99362010-04-05 10:19:24 +000012757 bool vpd_vers = false;
12758
12759 if (tp->fw_ver[0] != 0)
12760 vpd_vers = true;
Matt Carlsonacd9c112009-02-25 14:26:33 +000012761
Matt Carlsondf259d82009-04-20 06:57:14 +000012762 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
Matt Carlson75f99362010-04-05 10:19:24 +000012763 strcat(tp->fw_ver, "sb");
Matt Carlsondf259d82009-04-20 06:57:14 +000012764 return;
12765 }
12766
Matt Carlsonacd9c112009-02-25 14:26:33 +000012767 if (tg3_nvram_read(tp, 0, &val))
12768 return;
12769
12770 if (val == TG3_EEPROM_MAGIC)
12771 tg3_read_bc_ver(tp);
12772 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12773 tg3_read_sb_ver(tp, val);
Matt Carlsona6f6cb12009-02-25 14:27:43 +000012774 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12775 tg3_read_hwsb_ver(tp);
Matt Carlsonacd9c112009-02-25 14:26:33 +000012776 else
12777 return;
12778
12779 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
Matt Carlson75f99362010-04-05 10:19:24 +000012780 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12781 goto done;
Matt Carlsonacd9c112009-02-25 14:26:33 +000012782
12783 tg3_read_mgmtfw_ver(tp);
Matt Carlson9c8a6202007-10-21 16:16:08 -070012784
Matt Carlson75f99362010-04-05 10:19:24 +000012785done:
Matt Carlson9c8a6202007-10-21 16:16:08 -070012786 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
Michael Chanc4e65752006-03-20 22:29:32 -080012787}
12788
Michael Chan7544b092007-05-05 13:08:32 -070012789static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12790
Eric Dumazet7fe876a2010-07-08 06:14:55 +000012791static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
12792{
12793#if TG3_VLAN_TAG_USED
12794 dev->vlan_features |= flags;
12795#endif
12796}
12797
Linus Torvalds1da177e2005-04-16 15:20:36 -070012798static int __devinit tg3_get_invariants(struct tg3 *tp)
12799{
12800 static struct pci_device_id write_reorder_chipsets[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012801 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
Matt Carlsonc6cdf432010-04-05 10:19:26 +000012802 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
John W. Linvillec165b002006-07-08 13:28:53 -070012803 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
Matt Carlsonc6cdf432010-04-05 10:19:26 +000012804 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
Michael Chan399de502005-10-03 14:02:39 -070012805 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12806 PCI_DEVICE_ID_VIA_8385_0) },
Linus Torvalds1da177e2005-04-16 15:20:36 -070012807 { },
12808 };
12809 u32 misc_ctrl_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012810 u32 pci_state_reg, grc_misc_cfg;
12811 u32 val;
12812 u16 pci_cmd;
Matt Carlson5e7dfd02008-11-21 17:18:16 -080012813 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012814
Linus Torvalds1da177e2005-04-16 15:20:36 -070012815 /* Force memory write invalidate off. If we leave it on,
12816 * then on 5700_BX chips we have to enable a workaround.
12817 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12818 * to match the cacheline size. The Broadcom driver have this
12819 * workaround but turns MWI off all the times so never uses
12820 * it. This seems to suggest that the workaround is insufficient.
12821 */
12822 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12823 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12824 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12825
12826 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12827 * has the register indirect write enable bit set before
12828 * we try to access any of the MMIO registers. It is also
12829 * critical that the PCI-X hw workaround situation is decided
12830 * before that as well.
12831 */
12832 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12833 &misc_ctrl_reg);
12834
12835 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12836 MISC_HOST_CTRL_CHIPREV_SHIFT);
Matt Carlson795d01c2007-10-07 23:28:17 -070012837 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12838 u32 prod_id_asic_rev;
12839
Matt Carlson5001e2f2009-11-13 13:03:51 +000012840 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12841 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
Matt Carlsona50d0792010-06-05 17:24:37 +000012842 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
12843 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000012844 pci_read_config_dword(tp->pdev,
12845 TG3PCI_GEN2_PRODID_ASICREV,
12846 &prod_id_asic_rev);
Matt Carlsonb703df62009-12-03 08:36:21 +000012847 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12848 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12849 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12850 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12851 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12852 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12853 pci_read_config_dword(tp->pdev,
12854 TG3PCI_GEN15_PRODID_ASICREV,
12855 &prod_id_asic_rev);
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000012856 else
12857 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12858 &prod_id_asic_rev);
12859
Matt Carlson321d32a2008-11-21 17:22:19 -080012860 tp->pci_chip_rev_id = prod_id_asic_rev;
Matt Carlson795d01c2007-10-07 23:28:17 -070012861 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070012862
Michael Chanff645be2005-04-21 17:09:53 -070012863 /* Wrong chip ID in 5752 A0. This code can be removed later
12864 * as A0 is not in production.
12865 */
12866 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12867 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12868
Michael Chan68929142005-08-09 20:17:14 -070012869 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12870 * we need to disable memory and use config. cycles
12871 * only to access all registers. The 5702/03 chips
12872 * can mistakenly decode the special cycles from the
12873 * ICH chipsets as memory write cycles, causing corruption
12874 * of register and memory space. Only certain ICH bridges
12875 * will drive special cycles with non-zero data during the
12876 * address phase which can fall within the 5703's address
12877 * range. This is not an ICH bug as the PCI spec allows
12878 * non-zero address during special cycles. However, only
12879 * these ICH bridges are known to drive non-zero addresses
12880 * during special cycles.
12881 *
12882 * Since special cycles do not cross PCI bridges, we only
12883 * enable this workaround if the 5703 is on the secondary
12884 * bus of these ICH bridges.
12885 */
12886 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12887 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12888 static struct tg3_dev_id {
12889 u32 vendor;
12890 u32 device;
12891 u32 rev;
12892 } ich_chipsets[] = {
12893 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12894 PCI_ANY_ID },
12895 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12896 PCI_ANY_ID },
12897 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12898 0xa },
12899 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12900 PCI_ANY_ID },
12901 { },
12902 };
12903 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12904 struct pci_dev *bridge = NULL;
12905
12906 while (pci_id->vendor != 0) {
12907 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12908 bridge);
12909 if (!bridge) {
12910 pci_id++;
12911 continue;
12912 }
12913 if (pci_id->rev != PCI_ANY_ID) {
Auke Kok44c10132007-06-08 15:46:36 -070012914 if (bridge->revision > pci_id->rev)
Michael Chan68929142005-08-09 20:17:14 -070012915 continue;
12916 }
12917 if (bridge->subordinate &&
12918 (bridge->subordinate->number ==
12919 tp->pdev->bus->number)) {
12920
12921 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12922 pci_dev_put(bridge);
12923 break;
12924 }
12925 }
12926 }
12927
Matt Carlson41588ba2008-04-19 18:12:33 -070012928 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12929 static struct tg3_dev_id {
12930 u32 vendor;
12931 u32 device;
12932 } bridge_chipsets[] = {
12933 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12934 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12935 { },
12936 };
12937 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12938 struct pci_dev *bridge = NULL;
12939
12940 while (pci_id->vendor != 0) {
12941 bridge = pci_get_device(pci_id->vendor,
12942 pci_id->device,
12943 bridge);
12944 if (!bridge) {
12945 pci_id++;
12946 continue;
12947 }
12948 if (bridge->subordinate &&
12949 (bridge->subordinate->number <=
12950 tp->pdev->bus->number) &&
12951 (bridge->subordinate->subordinate >=
12952 tp->pdev->bus->number)) {
12953 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12954 pci_dev_put(bridge);
12955 break;
12956 }
12957 }
12958 }
12959
Michael Chan4a29cc22006-03-19 13:21:12 -080012960 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12961 * DMA addresses > 40-bit. This bridge may have other additional
12962 * 57xx devices behind it in some 4-port NIC designs for example.
12963 * Any tg3 device found behind the bridge will also need the 40-bit
12964 * DMA workaround.
12965 */
Michael Chana4e2b342005-10-26 15:46:52 -070012966 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12967 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12968 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
Michael Chan4a29cc22006-03-19 13:21:12 -080012969 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
Michael Chan4cf78e42005-07-25 12:29:19 -070012970 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
Matt Carlson859a588792010-04-05 10:19:28 +000012971 } else {
Michael Chan4a29cc22006-03-19 13:21:12 -080012972 struct pci_dev *bridge = NULL;
12973
12974 do {
12975 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12976 PCI_DEVICE_ID_SERVERWORKS_EPB,
12977 bridge);
12978 if (bridge && bridge->subordinate &&
12979 (bridge->subordinate->number <=
12980 tp->pdev->bus->number) &&
12981 (bridge->subordinate->subordinate >=
12982 tp->pdev->bus->number)) {
12983 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12984 pci_dev_put(bridge);
12985 break;
12986 }
12987 } while (bridge);
12988 }
Michael Chan4cf78e42005-07-25 12:29:19 -070012989
Linus Torvalds1da177e2005-04-16 15:20:36 -070012990 /* Initialize misc host control in PCI block. */
12991 tp->misc_host_ctrl |= (misc_ctrl_reg &
12992 MISC_HOST_CTRL_CHIPREV);
12993 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12994 tp->misc_host_ctrl);
12995
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000012996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12997 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
Michael Chan7544b092007-05-05 13:08:32 -070012999 tp->pdev_peer = tg3_find_peer(tp);
13000
Matt Carlsonc885e822010-08-02 11:25:57 +000013001 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13002 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13003 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13004 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13005
Matt Carlson321d32a2008-11-21 17:22:19 -080013006 /* Intentionally exclude ASIC_REV_5906 */
13007 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
Michael Chand9ab5ad2006-03-20 22:27:35 -080013008 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
Matt Carlsond30cdd22007-10-07 23:28:35 -070013009 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
Matt Carlson9936bcf2007-10-10 18:03:07 -070013010 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
Matt Carlson57e69832008-05-25 23:48:31 -070013011 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000013012 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
Matt Carlsonc885e822010-08-02 11:25:57 +000013013 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
Matt Carlson321d32a2008-11-21 17:22:19 -080013014 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13015
13016 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13017 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
Michael Chanb5d37722006-09-27 16:06:21 -070013018 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
Matt Carlson321d32a2008-11-21 17:22:19 -080013019 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
Michael Chana4e2b342005-10-26 15:46:52 -070013020 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
John W. Linville6708e5c2005-04-21 17:00:52 -070013021 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13022
John W. Linville1b440c562005-04-21 17:03:18 -070013023 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13024 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13025 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13026
Matt Carlson027455a2008-12-21 20:19:30 -080013027 /* 5700 B0 chips do not support checksumming correctly due
13028 * to hardware bugs.
13029 */
13030 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13031 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13032 else {
Eric Dumazet7fe876a2010-07-08 06:14:55 +000013033 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13034
Matt Carlson027455a2008-12-21 20:19:30 -080013035 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
Matt Carlson027455a2008-12-21 20:19:30 -080013036 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
Eric Dumazet7fe876a2010-07-08 06:14:55 +000013037 features |= NETIF_F_IPV6_CSUM;
13038 tp->dev->features |= features;
13039 vlan_features_add(tp->dev, features);
Matt Carlson027455a2008-12-21 20:19:30 -080013040 }
13041
Matt Carlson507399f2009-11-13 13:03:37 +000013042 /* Determine TSO capabilities */
Matt Carlsonc885e822010-08-02 11:25:57 +000013043 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
Matt Carlsone849cdc2009-11-13 13:03:38 +000013044 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13045 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13046 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
Matt Carlson507399f2009-11-13 13:03:37 +000013047 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13048 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13049 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13050 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13051 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13052 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13053 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13054 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13055 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13056 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13057 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13058 tp->fw_needed = FIRMWARE_TG3TSO5;
13059 else
13060 tp->fw_needed = FIRMWARE_TG3TSO;
13061 }
13062
13063 tp->irq_max = 1;
13064
Michael Chan5a6f3072006-03-20 22:28:05 -080013065 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
Michael Chan7544b092007-05-05 13:08:32 -070013066 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13067 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13068 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13069 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13070 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13071 tp->pdev_peer == tp->pdev))
13072 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13073
Matt Carlson321d32a2008-11-21 17:22:19 -080013074 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
Michael Chanb5d37722006-09-27 16:06:21 -070013075 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chanfcfa0a32006-03-20 22:28:41 -080013076 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
Michael Chan52c0fd82006-06-29 20:15:54 -070013077 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013078
Matt Carlsonc885e822010-08-02 11:25:57 +000013079 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
Matt Carlson507399f2009-11-13 13:03:37 +000013080 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13081 tp->irq_max = TG3_IRQ_MAX_VECS;
13082 }
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000013083 }
Matt Carlson0e1406d2009-11-02 12:33:33 +000013084
Matt Carlson615774f2009-11-13 13:03:39 +000013085 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
Matt Carlsona50d0792010-06-05 17:24:37 +000013086 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
Matt Carlson615774f2009-11-13 13:03:39 +000013087 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13088 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13089 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13090 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13091 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
Matt Carlson0e1406d2009-11-02 12:33:33 +000013092 }
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000013093
Matt Carlsonc885e822010-08-02 11:25:57 +000013094 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
Matt Carlsonb703df62009-12-03 08:36:21 +000013095 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13096
Matt Carlsonf51f3562008-05-25 23:45:08 -070013097 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
Matt Carlsonc6cdf432010-04-05 10:19:26 +000013098 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13099 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
Matt Carlson8f666b02009-08-28 13:58:24 +000013100 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
Michael Chan0f893dc2005-07-25 12:30:38 -070013101
Matt Carlson52f44902008-11-21 17:17:04 -080013102 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13103 &pci_state_reg);
13104
Matt Carlson5e7dfd02008-11-21 17:18:16 -080013105 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13106 if (tp->pcie_cap != 0) {
13107 u16 lnkctl;
13108
Linus Torvalds1da177e2005-04-16 15:20:36 -070013109 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
Matt Carlson5f5c51e2007-11-12 21:19:37 -080013110
13111 pcie_set_readrq(tp->pdev, 4096);
13112
Matt Carlson5e7dfd02008-11-21 17:18:16 -080013113 pci_read_config_word(tp->pdev,
13114 tp->pcie_cap + PCI_EXP_LNKCTL,
13115 &lnkctl);
13116 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13117 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
Michael Chanc7835a72006-11-15 21:14:42 -080013118 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
Matt Carlson5e7dfd02008-11-21 17:18:16 -080013119 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
Matt Carlson321d32a2008-11-21 17:22:19 -080013120 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
Matt Carlson9cf74eb2009-04-20 06:58:27 +000013121 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13122 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
Matt Carlson5e7dfd02008-11-21 17:18:16 -080013123 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
Matt Carlson614b0592010-01-20 16:58:02 +000013124 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13125 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
Michael Chanc7835a72006-11-15 21:14:42 -080013126 }
Matt Carlson52f44902008-11-21 17:17:04 -080013127 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
Matt Carlsonfcb389d2008-11-03 16:55:44 -080013128 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
Matt Carlson52f44902008-11-21 17:17:04 -080013129 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13130 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13131 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13132 if (!tp->pcix_cap) {
Matt Carlson2445e462010-04-05 10:19:21 +000013133 dev_err(&tp->pdev->dev,
13134 "Cannot find PCI-X capability, aborting\n");
Matt Carlson52f44902008-11-21 17:17:04 -080013135 return -EIO;
13136 }
13137
13138 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13139 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13140 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013141
Michael Chan399de502005-10-03 14:02:39 -070013142 /* If we have an AMD 762 or VIA K8T800 chipset, write
13143 * reordering to the mailbox registers done by the host
13144 * controller can cause major troubles. We read back from
13145 * every mailbox register write to force the writes to be
13146 * posted to the chip in order.
13147 */
13148 if (pci_dev_present(write_reorder_chipsets) &&
13149 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13150 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13151
Matt Carlson69fc4052008-12-21 20:19:57 -080013152 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13153 &tp->pci_cacheline_sz);
13154 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13155 &tp->pci_lat_timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013156 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13157 tp->pci_lat_timer < 64) {
13158 tp->pci_lat_timer = 64;
Matt Carlson69fc4052008-12-21 20:19:57 -080013159 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13160 tp->pci_lat_timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013161 }
13162
Matt Carlson52f44902008-11-21 17:17:04 -080013163 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13164 /* 5700 BX chips need to have their TX producer index
13165 * mailboxes written twice to workaround a bug.
13166 */
13167 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
Matt Carlson9974a352007-10-07 23:27:28 -070013168
Matt Carlson52f44902008-11-21 17:17:04 -080013169 /* If we are in PCI-X mode, enable register write workaround.
Linus Torvalds1da177e2005-04-16 15:20:36 -070013170 *
13171 * The workaround is to use indirect register accesses
13172 * for all chip writes not to mailbox registers.
13173 */
Matt Carlson52f44902008-11-21 17:17:04 -080013174 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070013175 u32 pm_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013176
13177 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13178
13179 /* The chip can have it's power management PCI config
13180 * space registers clobbered due to this bug.
13181 * So explicitly force the chip into D0 here.
13182 */
Matt Carlson9974a352007-10-07 23:27:28 -070013183 pci_read_config_dword(tp->pdev,
13184 tp->pm_cap + PCI_PM_CTRL,
Linus Torvalds1da177e2005-04-16 15:20:36 -070013185 &pm_reg);
13186 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13187 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
Matt Carlson9974a352007-10-07 23:27:28 -070013188 pci_write_config_dword(tp->pdev,
13189 tp->pm_cap + PCI_PM_CTRL,
Linus Torvalds1da177e2005-04-16 15:20:36 -070013190 pm_reg);
13191
13192 /* Also, force SERR#/PERR# in PCI command. */
13193 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13194 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13195 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13196 }
13197 }
13198
Linus Torvalds1da177e2005-04-16 15:20:36 -070013199 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13200 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13201 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13202 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13203
13204 /* Chip-specific fixup from Broadcom driver */
13205 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13206 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13207 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13208 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13209 }
13210
Michael Chan1ee582d2005-08-09 20:16:46 -070013211 /* Default fast path register access methods */
Michael Chan20094932005-08-09 20:16:32 -070013212 tp->read32 = tg3_read32;
Michael Chan1ee582d2005-08-09 20:16:46 -070013213 tp->write32 = tg3_write32;
Michael Chan09ee9292005-08-09 20:17:00 -070013214 tp->read32_mbox = tg3_read32;
Michael Chan20094932005-08-09 20:16:32 -070013215 tp->write32_mbox = tg3_write32;
Michael Chan1ee582d2005-08-09 20:16:46 -070013216 tp->write32_tx_mbox = tg3_write32;
13217 tp->write32_rx_mbox = tg3_write32;
13218
13219 /* Various workaround register access methods */
13220 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13221 tp->write32 = tg3_write_indirect_reg32;
Matt Carlson98efd8a2007-05-05 12:47:25 -070013222 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13223 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13224 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13225 /*
13226 * Back to back register writes can cause problems on these
13227 * chips, the workaround is to read back all reg writes
13228 * except those to mailbox regs.
13229 *
13230 * See tg3_write_indirect_reg32().
13231 */
Michael Chan1ee582d2005-08-09 20:16:46 -070013232 tp->write32 = tg3_write_flush_reg32;
Matt Carlson98efd8a2007-05-05 12:47:25 -070013233 }
13234
Michael Chan1ee582d2005-08-09 20:16:46 -070013235 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13236 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13237 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13238 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13239 tp->write32_rx_mbox = tg3_write_flush_reg32;
13240 }
Michael Chan20094932005-08-09 20:16:32 -070013241
Michael Chan68929142005-08-09 20:17:14 -070013242 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13243 tp->read32 = tg3_read_indirect_reg32;
13244 tp->write32 = tg3_write_indirect_reg32;
13245 tp->read32_mbox = tg3_read_indirect_mbox;
13246 tp->write32_mbox = tg3_write_indirect_mbox;
13247 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13248 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13249
13250 iounmap(tp->regs);
Peter Hagervall22abe312005-09-16 17:01:03 -070013251 tp->regs = NULL;
Michael Chan68929142005-08-09 20:17:14 -070013252
13253 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13254 pci_cmd &= ~PCI_COMMAND_MEMORY;
13255 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13256 }
Michael Chanb5d37722006-09-27 16:06:21 -070013257 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13258 tp->read32_mbox = tg3_read32_mbox_5906;
13259 tp->write32_mbox = tg3_write32_mbox_5906;
13260 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13261 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13262 }
Michael Chan68929142005-08-09 20:17:14 -070013263
Michael Chanbbadf502006-04-06 21:46:34 -070013264 if (tp->write32 == tg3_write_indirect_reg32 ||
13265 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13266 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
David S. Millerf49639e2006-06-09 11:58:36 -070013267 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
Michael Chanbbadf502006-04-06 21:46:34 -070013268 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13269
Michael Chan7d0c41e2005-04-21 17:06:20 -070013270 /* Get eeprom hw config before calling tg3_set_power_state().
Michael Chan9d26e212006-12-07 00:21:14 -080013271 * In particular, the TG3_FLG2_IS_NIC flag must be
Michael Chan7d0c41e2005-04-21 17:06:20 -070013272 * determined before calling tg3_set_power_state() so that
13273 * we know whether or not to switch out of Vaux power.
13274 * When the flag is set, it means that GPIO1 is used for eeprom
13275 * write protect and also implies that it is a LOM where GPIOs
13276 * are not used to switch power.
Jeff Garzik6aa20a22006-09-13 13:24:59 -040013277 */
Michael Chan7d0c41e2005-04-21 17:06:20 -070013278 tg3_get_eeprom_hw_cfg(tp);
13279
Matt Carlson0d3031d2007-10-10 18:02:43 -070013280 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13281 /* Allow reads and writes to the
13282 * APE register and memory space.
13283 */
13284 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
Matt Carlsonf92d9dc12010-06-05 17:24:30 +000013285 PCISTATE_ALLOW_APE_SHMEM_WR |
13286 PCISTATE_ALLOW_APE_PSPACE_WR;
Matt Carlson0d3031d2007-10-10 18:02:43 -070013287 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13288 pci_state_reg);
13289 }
13290
Matt Carlson9936bcf2007-10-10 18:03:07 -070013291 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
Matt Carlson57e69832008-05-25 23:48:31 -070013292 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
Matt Carlson321d32a2008-11-21 17:22:19 -080013293 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000013294 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
Matt Carlsonc885e822010-08-02 11:25:57 +000013295 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
Matt Carlsond30cdd22007-10-07 23:28:35 -070013296 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13297
Michael Chan314fba32005-04-21 17:07:04 -070013298 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13299 * GPIO1 driven high will bring 5700's external PHY out of reset.
13300 * It is also used as eeprom write protect on LOMs.
13301 */
13302 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13303 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13304 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13305 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13306 GRC_LCLCTRL_GPIO_OUTPUT1);
Michael Chan3e7d83b2005-04-21 17:10:36 -070013307 /* Unused GPIO3 must be driven as output on 5752 because there
13308 * are no pull-up resistors on unused GPIO pins.
13309 */
13310 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13311 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
Michael Chan314fba32005-04-21 17:07:04 -070013312
Matt Carlson321d32a2008-11-21 17:22:19 -080013313 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
Matt Carlsoncb4ed1f2010-01-20 16:58:09 +000013314 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13315 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
Michael Chanaf36e6b2006-03-23 01:28:06 -080013316 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13317
Matt Carlson8d519ab2009-04-20 06:58:01 +000013318 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13319 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
Matt Carlson5f0c4a32008-06-09 15:41:12 -070013320 /* Turn off the debug UART. */
13321 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13322 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13323 /* Keep VMain power. */
13324 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13325 GRC_LCLCTRL_GPIO_OUTPUT0;
13326 }
13327
Linus Torvalds1da177e2005-04-16 15:20:36 -070013328 /* Force the chip into D0. */
Michael Chanbc1c7562006-03-20 17:48:03 -080013329 err = tg3_set_power_state(tp, PCI_D0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013330 if (err) {
Matt Carlson2445e462010-04-05 10:19:21 +000013331 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070013332 return err;
13333 }
13334
Linus Torvalds1da177e2005-04-16 15:20:36 -070013335 /* Derive initial jumbo mode from MTU assigned in
13336 * ether_setup() via the alloc_etherdev() call
13337 */
Michael Chan0f893dc2005-07-25 12:30:38 -070013338 if (tp->dev->mtu > ETH_DATA_LEN &&
Michael Chana4e2b342005-10-26 15:46:52 -070013339 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
Michael Chan0f893dc2005-07-25 12:30:38 -070013340 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013341
13342 /* Determine WakeOnLan speed to use. */
13343 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13344 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13345 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13346 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13347 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13348 } else {
13349 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13350 }
13351
Matt Carlson7f97a4b2009-08-25 10:10:03 +000013352 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013353 tp->phy_flags |= TG3_PHYFLG_IS_FET;
Matt Carlson7f97a4b2009-08-25 10:10:03 +000013354
Linus Torvalds1da177e2005-04-16 15:20:36 -070013355 /* A few boards don't want Ethernet@WireSpeed phy feature */
13356 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13357 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13358 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
Michael Chan747e8f82005-07-25 12:33:22 -070013359 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013360 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13361 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13362 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013363
13364 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13365 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013366 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013367 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013368 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013369
Matt Carlson321d32a2008-11-21 17:22:19 -080013370 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013371 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
Matt Carlson321d32a2008-11-21 17:22:19 -080013372 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000013373 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
Matt Carlsonc885e822010-08-02 11:25:57 +000013374 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
Michael Chanc424cb22006-04-29 18:56:34 -070013375 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
Matt Carlsond30cdd22007-10-07 23:28:35 -070013376 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
Matt Carlson9936bcf2007-10-10 18:03:07 -070013377 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13378 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
Michael Chand4011ad2007-02-13 12:17:25 -080013379 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13380 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013381 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
Michael Chanc1d2a192007-01-08 19:57:20 -080013382 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013383 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
Matt Carlson321d32a2008-11-21 17:22:19 -080013384 } else
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013385 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
Michael Chanc424cb22006-04-29 18:56:34 -070013386 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013387
Matt Carlsonb2a5c192008-04-03 21:44:44 -070013388 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13389 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13390 tp->phy_otp = tg3_read_otp_phycfg(tp);
13391 if (tp->phy_otp == 0)
13392 tp->phy_otp = TG3_OTP_DEFAULT;
13393 }
13394
Matt Carlsonf51f3562008-05-25 23:45:08 -070013395 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
Matt Carlson8ef21422008-05-02 16:47:53 -070013396 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13397 else
13398 tp->mi_mode = MAC_MI_MODE_BASE;
13399
Linus Torvalds1da177e2005-04-16 15:20:36 -070013400 tp->coalesce_mode = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013401 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13402 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13403 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13404
Matt Carlson321d32a2008-11-21 17:22:19 -080013405 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13406 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
Matt Carlson57e69832008-05-25 23:48:31 -070013407 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13408
Matt Carlson158d7ab2008-05-29 01:37:54 -070013409 err = tg3_mdio_init(tp);
13410 if (err)
13411 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013412
Matt Carlson55dffe72010-01-12 10:11:39 +000013413 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
Matt Carlson2138c002010-07-11 09:31:43 +000013414 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
Matt Carlson55dffe72010-01-12 10:11:39 +000013415 return -ENOTSUPP;
13416
Linus Torvalds1da177e2005-04-16 15:20:36 -070013417 /* Initialize data/descriptor byte/word swapping. */
13418 val = tr32(GRC_MODE);
13419 val &= GRC_MODE_HOST_STACKUP;
13420 tw32(GRC_MODE, val | tp->grc_mode);
13421
13422 tg3_switch_clocks(tp);
13423
13424 /* Clear this out for sanity. */
13425 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13426
13427 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13428 &pci_state_reg);
13429 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13430 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13431 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13432
13433 if (chiprevid == CHIPREV_ID_5701_A0 ||
13434 chiprevid == CHIPREV_ID_5701_B0 ||
13435 chiprevid == CHIPREV_ID_5701_B2 ||
13436 chiprevid == CHIPREV_ID_5701_B5) {
13437 void __iomem *sram_base;
13438
13439 /* Write some dummy words into the SRAM status block
13440 * area, see if it reads back correctly. If the return
13441 * value is bad, force enable the PCIX workaround.
13442 */
13443 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13444
13445 writel(0x00000000, sram_base);
13446 writel(0x00000000, sram_base + 4);
13447 writel(0xffffffff, sram_base + 4);
13448 if (readl(sram_base) != 0x00000000)
13449 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13450 }
13451 }
13452
13453 udelay(50);
13454 tg3_nvram_init(tp);
13455
13456 grc_misc_cfg = tr32(GRC_MISC_CFG);
13457 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13458
Linus Torvalds1da177e2005-04-16 15:20:36 -070013459 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13460 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13461 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13462 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13463
David S. Millerfac9b832005-05-18 22:46:34 -070013464 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13465 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13466 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13467 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13468 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13469 HOSTCC_MODE_CLRTICK_TXBD);
13470
13471 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13472 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13473 tp->misc_host_ctrl);
13474 }
13475
Matt Carlson3bda1252008-08-15 14:08:22 -070013476 /* Preserve the APE MAC_MODE bits */
13477 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13478 tp->mac_mode = tr32(MAC_MODE) |
13479 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13480 else
13481 tp->mac_mode = TG3_DEF_MAC_MODE;
13482
Linus Torvalds1da177e2005-04-16 15:20:36 -070013483 /* these are limited to 10/100 only */
13484 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13485 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13486 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13487 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13488 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13489 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13490 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13491 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13492 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
Michael Chan676917d2006-12-07 00:20:22 -080013493 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13494 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
Matt Carlson321d32a2008-11-21 17:22:19 -080013495 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
Matt Carlsond1101142010-02-17 15:16:55 +000013496 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13497 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013498 (tp->phy_flags & TG3_PHYFLG_IS_FET))
13499 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013500
13501 err = tg3_phy_probe(tp);
13502 if (err) {
Matt Carlson2445e462010-04-05 10:19:21 +000013503 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013504 /* ... but do not return immediately ... */
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070013505 tg3_mdio_fini(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013506 }
13507
Matt Carlson184b8902010-04-05 10:19:25 +000013508 tg3_read_vpd(tp);
Michael Chanc4e65752006-03-20 22:29:32 -080013509 tg3_read_fw_ver(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013510
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013511 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13512 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013513 } else {
13514 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013515 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013516 else
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013517 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013518 }
13519
13520 /* 5700 {AX,BX} chips have a broken status block link
13521 * change bit implementation, so we must use the
13522 * status register in those cases.
13523 */
13524 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13525 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13526 else
13527 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13528
13529 /* The led_ctrl is set during tg3_phy_probe, here we might
13530 * have to force the link status polling mechanism based
13531 * upon subsystem IDs.
13532 */
13533 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
Michael Chan007a880d2007-05-31 14:49:51 -070013534 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013535 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13536 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13537 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013538 }
13539
13540 /* For all SERDES we poll the MAC status register. */
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013541 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Linus Torvalds1da177e2005-04-16 15:20:36 -070013542 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13543 else
13544 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13545
Matt Carlson9dc7a112010-04-12 06:58:28 +000013546 tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
Matt Carlsond2757fc2010-04-12 06:58:27 +000013547 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013548 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
Matt Carlsond2757fc2010-04-12 06:58:27 +000013549 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
Matt Carlson9dc7a112010-04-12 06:58:28 +000013550 tp->rx_offset -= NET_IP_ALIGN;
Matt Carlsond2757fc2010-04-12 06:58:27 +000013551#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
Matt Carlson9dc7a112010-04-12 06:58:28 +000013552 tp->rx_copy_thresh = ~(u16)0;
Matt Carlsond2757fc2010-04-12 06:58:27 +000013553#endif
13554 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013555
Michael Chanf92905d2006-06-29 20:14:29 -070013556 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13557
13558 /* Increment the rx prod index on the rx std ring by at most
13559 * 8 for these chips to workaround hw errata.
13560 */
13561 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13562 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13563 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13564 tp->rx_std_max_post = 8;
13565
Matt Carlson8ed5d972007-05-07 00:25:49 -070013566 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13567 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13568 PCIE_PWR_MGMT_L1_THRESH_MSK;
13569
Linus Torvalds1da177e2005-04-16 15:20:36 -070013570 return err;
13571}
13572
David S. Miller49b6e95f2007-03-29 01:38:42 -070013573#ifdef CONFIG_SPARC
Linus Torvalds1da177e2005-04-16 15:20:36 -070013574static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13575{
13576 struct net_device *dev = tp->dev;
13577 struct pci_dev *pdev = tp->pdev;
David S. Miller49b6e95f2007-03-29 01:38:42 -070013578 struct device_node *dp = pci_device_to_OF_node(pdev);
David S. Miller374d4ca2007-03-29 01:57:57 -070013579 const unsigned char *addr;
David S. Miller49b6e95f2007-03-29 01:38:42 -070013580 int len;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013581
David S. Miller49b6e95f2007-03-29 01:38:42 -070013582 addr = of_get_property(dp, "local-mac-address", &len);
13583 if (addr && len == 6) {
13584 memcpy(dev->dev_addr, addr, 6);
13585 memcpy(dev->perm_addr, dev->dev_addr, 6);
13586 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013587 }
13588 return -ENODEV;
13589}
13590
13591static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13592{
13593 struct net_device *dev = tp->dev;
13594
13595 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
John W. Linville2ff43692005-09-12 14:44:20 -070013596 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013597 return 0;
13598}
13599#endif
13600
13601static int __devinit tg3_get_device_address(struct tg3 *tp)
13602{
13603 struct net_device *dev = tp->dev;
13604 u32 hi, lo, mac_offset;
Michael Chan008652b2006-03-27 23:14:53 -080013605 int addr_ok = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013606
David S. Miller49b6e95f2007-03-29 01:38:42 -070013607#ifdef CONFIG_SPARC
Linus Torvalds1da177e2005-04-16 15:20:36 -070013608 if (!tg3_get_macaddr_sparc(tp))
13609 return 0;
13610#endif
13611
13612 mac_offset = 0x7c;
David S. Millerf49639e2006-06-09 11:58:36 -070013613 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
Michael Chana4e2b342005-10-26 15:46:52 -070013614 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070013615 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13616 mac_offset = 0xcc;
13617 if (tg3_nvram_lock(tp))
13618 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13619 else
13620 tg3_nvram_unlock(tp);
Matt Carlsona50d0792010-06-05 17:24:37 +000013621 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13622 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13623 if (PCI_FUNC(tp->pdev->devfn) & 1)
Matt Carlsona1b950d2009-09-01 13:20:17 +000013624 mac_offset = 0xcc;
Matt Carlsona50d0792010-06-05 17:24:37 +000013625 if (PCI_FUNC(tp->pdev->devfn) > 1)
13626 mac_offset += 0x18c;
Matt Carlsona1b950d2009-09-01 13:20:17 +000013627 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
Michael Chanb5d37722006-09-27 16:06:21 -070013628 mac_offset = 0x10;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013629
13630 /* First try to get it from MAC address mailbox. */
13631 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13632 if ((hi >> 16) == 0x484b) {
13633 dev->dev_addr[0] = (hi >> 8) & 0xff;
13634 dev->dev_addr[1] = (hi >> 0) & 0xff;
13635
13636 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13637 dev->dev_addr[2] = (lo >> 24) & 0xff;
13638 dev->dev_addr[3] = (lo >> 16) & 0xff;
13639 dev->dev_addr[4] = (lo >> 8) & 0xff;
13640 dev->dev_addr[5] = (lo >> 0) & 0xff;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013641
Michael Chan008652b2006-03-27 23:14:53 -080013642 /* Some old bootcode may report a 0 MAC address in SRAM */
13643 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13644 }
13645 if (!addr_ok) {
13646 /* Next, try NVRAM. */
Matt Carlsondf259d82009-04-20 06:57:14 +000013647 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13648 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
Matt Carlson6d348f22009-02-25 14:25:52 +000013649 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
Matt Carlson62cedd12009-04-20 14:52:29 -070013650 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13651 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
Michael Chan008652b2006-03-27 23:14:53 -080013652 }
13653 /* Finally just fetch it out of the MAC control regs. */
13654 else {
13655 hi = tr32(MAC_ADDR_0_HIGH);
13656 lo = tr32(MAC_ADDR_0_LOW);
13657
13658 dev->dev_addr[5] = lo & 0xff;
13659 dev->dev_addr[4] = (lo >> 8) & 0xff;
13660 dev->dev_addr[3] = (lo >> 16) & 0xff;
13661 dev->dev_addr[2] = (lo >> 24) & 0xff;
13662 dev->dev_addr[1] = hi & 0xff;
13663 dev->dev_addr[0] = (hi >> 8) & 0xff;
13664 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013665 }
13666
13667 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
David S. Miller7582a332008-03-20 15:53:15 -070013668#ifdef CONFIG_SPARC
Linus Torvalds1da177e2005-04-16 15:20:36 -070013669 if (!tg3_get_default_macaddr_sparc(tp))
13670 return 0;
13671#endif
13672 return -EINVAL;
13673 }
John W. Linville2ff43692005-09-12 14:44:20 -070013674 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013675 return 0;
13676}
13677
David S. Miller59e6b432005-05-18 22:50:10 -070013678#define BOUNDARY_SINGLE_CACHELINE 1
13679#define BOUNDARY_MULTI_CACHELINE 2
13680
13681static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13682{
13683 int cacheline_size;
13684 u8 byte;
13685 int goal;
13686
13687 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13688 if (byte == 0)
13689 cacheline_size = 1024;
13690 else
13691 cacheline_size = (int) byte * 4;
13692
13693 /* On 5703 and later chips, the boundary bits have no
13694 * effect.
13695 */
13696 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13697 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13698 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13699 goto out;
13700
13701#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13702 goal = BOUNDARY_MULTI_CACHELINE;
13703#else
13704#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13705 goal = BOUNDARY_SINGLE_CACHELINE;
13706#else
13707 goal = 0;
13708#endif
13709#endif
13710
Matt Carlsonc885e822010-08-02 11:25:57 +000013711 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
Matt Carlsoncbf9ca62009-11-13 13:03:40 +000013712 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13713 goto out;
13714 }
13715
David S. Miller59e6b432005-05-18 22:50:10 -070013716 if (!goal)
13717 goto out;
13718
13719 /* PCI controllers on most RISC systems tend to disconnect
13720 * when a device tries to burst across a cache-line boundary.
13721 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13722 *
13723 * Unfortunately, for PCI-E there are only limited
13724 * write-side controls for this, and thus for reads
13725 * we will still get the disconnects. We'll also waste
13726 * these PCI cycles for both read and write for chips
13727 * other than 5700 and 5701 which do not implement the
13728 * boundary bits.
13729 */
13730 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13731 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13732 switch (cacheline_size) {
13733 case 16:
13734 case 32:
13735 case 64:
13736 case 128:
13737 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13738 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13739 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13740 } else {
13741 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13742 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13743 }
13744 break;
13745
13746 case 256:
13747 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13748 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13749 break;
13750
13751 default:
13752 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13753 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13754 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -070013755 }
David S. Miller59e6b432005-05-18 22:50:10 -070013756 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13757 switch (cacheline_size) {
13758 case 16:
13759 case 32:
13760 case 64:
13761 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13762 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13763 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13764 break;
13765 }
13766 /* fallthrough */
13767 case 128:
13768 default:
13769 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13770 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13771 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -070013772 }
David S. Miller59e6b432005-05-18 22:50:10 -070013773 } else {
13774 switch (cacheline_size) {
13775 case 16:
13776 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13777 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13778 DMA_RWCTRL_WRITE_BNDRY_16);
13779 break;
13780 }
13781 /* fallthrough */
13782 case 32:
13783 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13784 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13785 DMA_RWCTRL_WRITE_BNDRY_32);
13786 break;
13787 }
13788 /* fallthrough */
13789 case 64:
13790 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13791 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13792 DMA_RWCTRL_WRITE_BNDRY_64);
13793 break;
13794 }
13795 /* fallthrough */
13796 case 128:
13797 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13798 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13799 DMA_RWCTRL_WRITE_BNDRY_128);
13800 break;
13801 }
13802 /* fallthrough */
13803 case 256:
13804 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13805 DMA_RWCTRL_WRITE_BNDRY_256);
13806 break;
13807 case 512:
13808 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13809 DMA_RWCTRL_WRITE_BNDRY_512);
13810 break;
13811 case 1024:
13812 default:
13813 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13814 DMA_RWCTRL_WRITE_BNDRY_1024);
13815 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -070013816 }
David S. Miller59e6b432005-05-18 22:50:10 -070013817 }
13818
13819out:
13820 return val;
13821}
13822
Linus Torvalds1da177e2005-04-16 15:20:36 -070013823static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13824{
13825 struct tg3_internal_buffer_desc test_desc;
13826 u32 sram_dma_descs;
13827 int i, ret;
13828
13829 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13830
13831 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13832 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13833 tw32(RDMAC_STATUS, 0);
13834 tw32(WDMAC_STATUS, 0);
13835
13836 tw32(BUFMGR_MODE, 0);
13837 tw32(FTQ_RESET, 0);
13838
13839 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13840 test_desc.addr_lo = buf_dma & 0xffffffff;
13841 test_desc.nic_mbuf = 0x00002100;
13842 test_desc.len = size;
13843
13844 /*
13845 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13846 * the *second* time the tg3 driver was getting loaded after an
13847 * initial scan.
13848 *
13849 * Broadcom tells me:
13850 * ...the DMA engine is connected to the GRC block and a DMA
13851 * reset may affect the GRC block in some unpredictable way...
13852 * The behavior of resets to individual blocks has not been tested.
13853 *
13854 * Broadcom noted the GRC reset will also reset all sub-components.
13855 */
13856 if (to_device) {
13857 test_desc.cqid_sqid = (13 << 8) | 2;
13858
13859 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13860 udelay(40);
13861 } else {
13862 test_desc.cqid_sqid = (16 << 8) | 7;
13863
13864 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13865 udelay(40);
13866 }
13867 test_desc.flags = 0x00000005;
13868
13869 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13870 u32 val;
13871
13872 val = *(((u32 *)&test_desc) + i);
13873 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13874 sram_dma_descs + (i * sizeof(u32)));
13875 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13876 }
13877 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13878
Matt Carlson859a588792010-04-05 10:19:28 +000013879 if (to_device)
Linus Torvalds1da177e2005-04-16 15:20:36 -070013880 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
Matt Carlson859a588792010-04-05 10:19:28 +000013881 else
Linus Torvalds1da177e2005-04-16 15:20:36 -070013882 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013883
13884 ret = -ENODEV;
13885 for (i = 0; i < 40; i++) {
13886 u32 val;
13887
13888 if (to_device)
13889 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13890 else
13891 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13892 if ((val & 0xffff) == sram_dma_descs) {
13893 ret = 0;
13894 break;
13895 }
13896
13897 udelay(100);
13898 }
13899
13900 return ret;
13901}
13902
David S. Millerded73402005-05-23 13:59:47 -070013903#define TEST_BUFFER_SIZE 0x2000
Linus Torvalds1da177e2005-04-16 15:20:36 -070013904
13905static int __devinit tg3_test_dma(struct tg3 *tp)
13906{
13907 dma_addr_t buf_dma;
David S. Miller59e6b432005-05-18 22:50:10 -070013908 u32 *buf, saved_dma_rwctrl;
Matt Carlsoncbf9ca62009-11-13 13:03:40 +000013909 int ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013910
13911 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13912 if (!buf) {
13913 ret = -ENOMEM;
13914 goto out_nofree;
13915 }
13916
13917 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13918 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13919
David S. Miller59e6b432005-05-18 22:50:10 -070013920 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013921
Matt Carlsonc885e822010-08-02 11:25:57 +000013922 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
Matt Carlsoncbf9ca62009-11-13 13:03:40 +000013923 goto out;
13924
Linus Torvalds1da177e2005-04-16 15:20:36 -070013925 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13926 /* DMA read watermark not used on PCIE */
13927 tp->dma_rwctrl |= 0x00180000;
13928 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
Michael Chan85e94ce2005-04-21 17:05:28 -070013929 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13930 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
Linus Torvalds1da177e2005-04-16 15:20:36 -070013931 tp->dma_rwctrl |= 0x003f0000;
13932 else
13933 tp->dma_rwctrl |= 0x003f000f;
13934 } else {
13935 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13936 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13937 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
Michael Chan49afdeb2007-02-13 12:17:03 -080013938 u32 read_water = 0x7;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013939
Michael Chan4a29cc22006-03-19 13:21:12 -080013940 /* If the 5704 is behind the EPB bridge, we can
13941 * do the less restrictive ONE_DMA workaround for
13942 * better performance.
13943 */
13944 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13945 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13946 tp->dma_rwctrl |= 0x8000;
13947 else if (ccval == 0x6 || ccval == 0x7)
Linus Torvalds1da177e2005-04-16 15:20:36 -070013948 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13949
Michael Chan49afdeb2007-02-13 12:17:03 -080013950 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13951 read_water = 4;
David S. Miller59e6b432005-05-18 22:50:10 -070013952 /* Set bit 23 to enable PCIX hw bug fix */
Michael Chan49afdeb2007-02-13 12:17:03 -080013953 tp->dma_rwctrl |=
13954 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13955 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13956 (1 << 23);
Michael Chan4cf78e42005-07-25 12:29:19 -070013957 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13958 /* 5780 always in PCIX mode */
13959 tp->dma_rwctrl |= 0x00144000;
Michael Chana4e2b342005-10-26 15:46:52 -070013960 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13961 /* 5714 always in PCIX mode */
13962 tp->dma_rwctrl |= 0x00148000;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013963 } else {
13964 tp->dma_rwctrl |= 0x001b000f;
13965 }
13966 }
13967
13968 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13969 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13970 tp->dma_rwctrl &= 0xfffffff0;
13971
13972 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13973 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13974 /* Remove this if it causes problems for some boards. */
13975 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13976
13977 /* On 5700/5701 chips, we need to set this bit.
13978 * Otherwise the chip will issue cacheline transactions
13979 * to streamable DMA memory with not all the byte
13980 * enables turned on. This is an error on several
13981 * RISC PCI controllers, in particular sparc64.
13982 *
13983 * On 5703/5704 chips, this bit has been reassigned
13984 * a different meaning. In particular, it is used
13985 * on those chips to enable a PCI-X workaround.
13986 */
13987 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13988 }
13989
13990 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13991
13992#if 0
13993 /* Unneeded, already done by tg3_get_invariants. */
13994 tg3_switch_clocks(tp);
13995#endif
13996
Linus Torvalds1da177e2005-04-16 15:20:36 -070013997 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13998 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13999 goto out;
14000
David S. Miller59e6b432005-05-18 22:50:10 -070014001 /* It is best to perform DMA test with maximum write burst size
14002 * to expose the 5700/5701 write DMA bug.
14003 */
14004 saved_dma_rwctrl = tp->dma_rwctrl;
14005 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14006 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14007
Linus Torvalds1da177e2005-04-16 15:20:36 -070014008 while (1) {
14009 u32 *p = buf, i;
14010
14011 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14012 p[i] = i;
14013
14014 /* Send the buffer to the chip. */
14015 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14016 if (ret) {
Matt Carlson2445e462010-04-05 10:19:21 +000014017 dev_err(&tp->pdev->dev,
14018 "%s: Buffer write failed. err = %d\n",
14019 __func__, ret);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014020 break;
14021 }
14022
14023#if 0
14024 /* validate data reached card RAM correctly. */
14025 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14026 u32 val;
14027 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14028 if (le32_to_cpu(val) != p[i]) {
Matt Carlson2445e462010-04-05 10:19:21 +000014029 dev_err(&tp->pdev->dev,
14030 "%s: Buffer corrupted on device! "
14031 "(%d != %d)\n", __func__, val, i);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014032 /* ret = -ENODEV here? */
14033 }
14034 p[i] = 0;
14035 }
14036#endif
14037 /* Now read it back. */
14038 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14039 if (ret) {
Matt Carlson5129c3a2010-04-05 10:19:23 +000014040 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14041 "err = %d\n", __func__, ret);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014042 break;
14043 }
14044
14045 /* Verify it. */
14046 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14047 if (p[i] == i)
14048 continue;
14049
David S. Miller59e6b432005-05-18 22:50:10 -070014050 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14051 DMA_RWCTRL_WRITE_BNDRY_16) {
14052 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014053 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14054 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14055 break;
14056 } else {
Matt Carlson2445e462010-04-05 10:19:21 +000014057 dev_err(&tp->pdev->dev,
14058 "%s: Buffer corrupted on read back! "
14059 "(%d != %d)\n", __func__, p[i], i);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014060 ret = -ENODEV;
14061 goto out;
14062 }
14063 }
14064
14065 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14066 /* Success. */
14067 ret = 0;
14068 break;
14069 }
14070 }
David S. Miller59e6b432005-05-18 22:50:10 -070014071 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14072 DMA_RWCTRL_WRITE_BNDRY_16) {
Michael Chan6d1cfba2005-06-08 14:13:14 -070014073 static struct pci_device_id dma_wait_state_chipsets[] = {
14074 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14075 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14076 { },
14077 };
14078
David S. Miller59e6b432005-05-18 22:50:10 -070014079 /* DMA test passed without adjusting DMA boundary,
Michael Chan6d1cfba2005-06-08 14:13:14 -070014080 * now look for chipsets that are known to expose the
14081 * DMA bug without failing the test.
David S. Miller59e6b432005-05-18 22:50:10 -070014082 */
Michael Chan6d1cfba2005-06-08 14:13:14 -070014083 if (pci_dev_present(dma_wait_state_chipsets)) {
14084 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14085 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
Matt Carlson859a588792010-04-05 10:19:28 +000014086 } else {
Michael Chan6d1cfba2005-06-08 14:13:14 -070014087 /* Safe to use the calculated DMA boundary. */
14088 tp->dma_rwctrl = saved_dma_rwctrl;
Matt Carlson859a588792010-04-05 10:19:28 +000014089 }
Michael Chan6d1cfba2005-06-08 14:13:14 -070014090
David S. Miller59e6b432005-05-18 22:50:10 -070014091 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14092 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014093
14094out:
14095 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14096out_nofree:
14097 return ret;
14098}
14099
14100static void __devinit tg3_init_link_config(struct tg3 *tp)
14101{
14102 tp->link_config.advertising =
14103 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14104 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14105 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14106 ADVERTISED_Autoneg | ADVERTISED_MII);
14107 tp->link_config.speed = SPEED_INVALID;
14108 tp->link_config.duplex = DUPLEX_INVALID;
14109 tp->link_config.autoneg = AUTONEG_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014110 tp->link_config.active_speed = SPEED_INVALID;
14111 tp->link_config.active_duplex = DUPLEX_INVALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014112 tp->link_config.orig_speed = SPEED_INVALID;
14113 tp->link_config.orig_duplex = DUPLEX_INVALID;
14114 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14115}
14116
14117static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14118{
Matt Carlsonc885e822010-08-02 11:25:57 +000014119 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
Matt Carlson666bc832010-01-20 16:58:03 +000014120 tp->bufmgr_config.mbuf_read_dma_low_water =
14121 DEFAULT_MB_RDMA_LOW_WATER_5705;
14122 tp->bufmgr_config.mbuf_mac_rx_low_water =
14123 DEFAULT_MB_MACRX_LOW_WATER_57765;
14124 tp->bufmgr_config.mbuf_high_water =
14125 DEFAULT_MB_HIGH_WATER_57765;
14126
14127 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14128 DEFAULT_MB_RDMA_LOW_WATER_5705;
14129 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14130 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14131 tp->bufmgr_config.mbuf_high_water_jumbo =
14132 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14133 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
Michael Chanfdfec1722005-07-25 12:31:48 -070014134 tp->bufmgr_config.mbuf_read_dma_low_water =
14135 DEFAULT_MB_RDMA_LOW_WATER_5705;
14136 tp->bufmgr_config.mbuf_mac_rx_low_water =
14137 DEFAULT_MB_MACRX_LOW_WATER_5705;
14138 tp->bufmgr_config.mbuf_high_water =
14139 DEFAULT_MB_HIGH_WATER_5705;
Michael Chanb5d37722006-09-27 16:06:21 -070014140 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14141 tp->bufmgr_config.mbuf_mac_rx_low_water =
14142 DEFAULT_MB_MACRX_LOW_WATER_5906;
14143 tp->bufmgr_config.mbuf_high_water =
14144 DEFAULT_MB_HIGH_WATER_5906;
14145 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014146
Michael Chanfdfec1722005-07-25 12:31:48 -070014147 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14148 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14149 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14150 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14151 tp->bufmgr_config.mbuf_high_water_jumbo =
14152 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14153 } else {
14154 tp->bufmgr_config.mbuf_read_dma_low_water =
14155 DEFAULT_MB_RDMA_LOW_WATER;
14156 tp->bufmgr_config.mbuf_mac_rx_low_water =
14157 DEFAULT_MB_MACRX_LOW_WATER;
14158 tp->bufmgr_config.mbuf_high_water =
14159 DEFAULT_MB_HIGH_WATER;
14160
14161 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14162 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14163 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14164 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14165 tp->bufmgr_config.mbuf_high_water_jumbo =
14166 DEFAULT_MB_HIGH_WATER_JUMBO;
14167 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014168
14169 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14170 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14171}
14172
14173static char * __devinit tg3_phy_string(struct tg3 *tp)
14174{
Matt Carlson79eb6902010-02-17 15:17:03 +000014175 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14176 case TG3_PHY_ID_BCM5400: return "5400";
14177 case TG3_PHY_ID_BCM5401: return "5401";
14178 case TG3_PHY_ID_BCM5411: return "5411";
14179 case TG3_PHY_ID_BCM5701: return "5701";
14180 case TG3_PHY_ID_BCM5703: return "5703";
14181 case TG3_PHY_ID_BCM5704: return "5704";
14182 case TG3_PHY_ID_BCM5705: return "5705";
14183 case TG3_PHY_ID_BCM5750: return "5750";
14184 case TG3_PHY_ID_BCM5752: return "5752";
14185 case TG3_PHY_ID_BCM5714: return "5714";
14186 case TG3_PHY_ID_BCM5780: return "5780";
14187 case TG3_PHY_ID_BCM5755: return "5755";
14188 case TG3_PHY_ID_BCM5787: return "5787";
14189 case TG3_PHY_ID_BCM5784: return "5784";
14190 case TG3_PHY_ID_BCM5756: return "5722/5756";
14191 case TG3_PHY_ID_BCM5906: return "5906";
14192 case TG3_PHY_ID_BCM5761: return "5761";
14193 case TG3_PHY_ID_BCM5718C: return "5718C";
14194 case TG3_PHY_ID_BCM5718S: return "5718S";
14195 case TG3_PHY_ID_BCM57765: return "57765";
Matt Carlson302b5002010-06-05 17:24:38 +000014196 case TG3_PHY_ID_BCM5719C: return "5719C";
Matt Carlson79eb6902010-02-17 15:17:03 +000014197 case TG3_PHY_ID_BCM8002: return "8002/serdes";
Linus Torvalds1da177e2005-04-16 15:20:36 -070014198 case 0: return "serdes";
14199 default: return "unknown";
Stephen Hemminger855e1112008-04-16 16:37:28 -070014200 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014201}
14202
Michael Chanf9804dd2005-09-27 12:13:10 -070014203static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14204{
14205 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14206 strcpy(str, "PCI Express");
14207 return str;
14208 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14209 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14210
14211 strcpy(str, "PCIX:");
14212
14213 if ((clock_ctrl == 7) ||
14214 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14215 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14216 strcat(str, "133MHz");
14217 else if (clock_ctrl == 0)
14218 strcat(str, "33MHz");
14219 else if (clock_ctrl == 2)
14220 strcat(str, "50MHz");
14221 else if (clock_ctrl == 4)
14222 strcat(str, "66MHz");
14223 else if (clock_ctrl == 6)
14224 strcat(str, "100MHz");
Michael Chanf9804dd2005-09-27 12:13:10 -070014225 } else {
14226 strcpy(str, "PCI:");
14227 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14228 strcat(str, "66MHz");
14229 else
14230 strcat(str, "33MHz");
14231 }
14232 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14233 strcat(str, ":32-bit");
14234 else
14235 strcat(str, ":64-bit");
14236 return str;
14237}
14238
Michael Chan8c2dc7e2005-12-19 16:26:02 -080014239static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -070014240{
14241 struct pci_dev *peer;
14242 unsigned int func, devnr = tp->pdev->devfn & ~7;
14243
14244 for (func = 0; func < 8; func++) {
14245 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14246 if (peer && peer != tp->pdev)
14247 break;
14248 pci_dev_put(peer);
14249 }
Michael Chan16fe9d72005-12-13 21:09:54 -080014250 /* 5704 can be configured in single-port mode, set peer to
14251 * tp->pdev in that case.
14252 */
14253 if (!peer) {
14254 peer = tp->pdev;
14255 return peer;
14256 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014257
14258 /*
14259 * We don't need to keep the refcount elevated; there's no way
14260 * to remove one half of this device without removing the other
14261 */
14262 pci_dev_put(peer);
14263
14264 return peer;
14265}
14266
David S. Miller15f98502005-05-18 22:49:26 -070014267static void __devinit tg3_init_coal(struct tg3 *tp)
14268{
14269 struct ethtool_coalesce *ec = &tp->coal;
14270
14271 memset(ec, 0, sizeof(*ec));
14272 ec->cmd = ETHTOOL_GCOALESCE;
14273 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14274 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14275 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14276 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14277 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14278 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14279 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14280 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14281 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14282
14283 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14284 HOSTCC_MODE_CLRTICK_TXBD)) {
14285 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14286 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14287 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14288 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14289 }
Michael Chand244c892005-07-05 14:42:33 -070014290
14291 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14292 ec->rx_coalesce_usecs_irq = 0;
14293 ec->tx_coalesce_usecs_irq = 0;
14294 ec->stats_block_coalesce_usecs = 0;
14295 }
David S. Miller15f98502005-05-18 22:49:26 -070014296}
14297
Stephen Hemminger7c7d64b2008-11-19 22:25:36 -080014298static const struct net_device_ops tg3_netdev_ops = {
14299 .ndo_open = tg3_open,
14300 .ndo_stop = tg3_close,
Stephen Hemminger00829822008-11-20 20:14:53 -080014301 .ndo_start_xmit = tg3_start_xmit,
Eric Dumazet511d2222010-07-07 20:44:24 +000014302 .ndo_get_stats64 = tg3_get_stats64,
Stephen Hemminger00829822008-11-20 20:14:53 -080014303 .ndo_validate_addr = eth_validate_addr,
14304 .ndo_set_multicast_list = tg3_set_rx_mode,
14305 .ndo_set_mac_address = tg3_set_mac_addr,
14306 .ndo_do_ioctl = tg3_ioctl,
14307 .ndo_tx_timeout = tg3_tx_timeout,
14308 .ndo_change_mtu = tg3_change_mtu,
14309#if TG3_VLAN_TAG_USED
14310 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14311#endif
14312#ifdef CONFIG_NET_POLL_CONTROLLER
14313 .ndo_poll_controller = tg3_poll_controller,
14314#endif
14315};
14316
14317static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14318 .ndo_open = tg3_open,
14319 .ndo_stop = tg3_close,
14320 .ndo_start_xmit = tg3_start_xmit_dma_bug,
Eric Dumazet511d2222010-07-07 20:44:24 +000014321 .ndo_get_stats64 = tg3_get_stats64,
Stephen Hemminger7c7d64b2008-11-19 22:25:36 -080014322 .ndo_validate_addr = eth_validate_addr,
14323 .ndo_set_multicast_list = tg3_set_rx_mode,
14324 .ndo_set_mac_address = tg3_set_mac_addr,
14325 .ndo_do_ioctl = tg3_ioctl,
14326 .ndo_tx_timeout = tg3_tx_timeout,
14327 .ndo_change_mtu = tg3_change_mtu,
14328#if TG3_VLAN_TAG_USED
14329 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14330#endif
14331#ifdef CONFIG_NET_POLL_CONTROLLER
14332 .ndo_poll_controller = tg3_poll_controller,
14333#endif
14334};
14335
Linus Torvalds1da177e2005-04-16 15:20:36 -070014336static int __devinit tg3_init_one(struct pci_dev *pdev,
14337 const struct pci_device_id *ent)
14338{
Linus Torvalds1da177e2005-04-16 15:20:36 -070014339 struct net_device *dev;
14340 struct tg3 *tp;
Matt Carlson646c9ed2009-09-01 12:58:41 +000014341 int i, err, pm_cap;
14342 u32 sndmbx, rcvmbx, intmbx;
Michael Chanf9804dd2005-09-27 12:13:10 -070014343 char str[40];
Michael Chan72f2afb2006-03-06 19:28:35 -080014344 u64 dma_mask, persist_dma_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014345
Joe Perches05dbe002010-02-17 19:44:19 +000014346 printk_once(KERN_INFO "%s\n", version);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014347
14348 err = pci_enable_device(pdev);
14349 if (err) {
Matt Carlson2445e462010-04-05 10:19:21 +000014350 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070014351 return err;
14352 }
14353
Linus Torvalds1da177e2005-04-16 15:20:36 -070014354 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14355 if (err) {
Matt Carlson2445e462010-04-05 10:19:21 +000014356 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070014357 goto err_out_disable_pdev;
14358 }
14359
14360 pci_set_master(pdev);
14361
14362 /* Find power-management capability. */
14363 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14364 if (pm_cap == 0) {
Matt Carlson2445e462010-04-05 10:19:21 +000014365 dev_err(&pdev->dev,
14366 "Cannot find Power Management capability, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070014367 err = -EIO;
14368 goto err_out_free_res;
14369 }
14370
Matt Carlsonfe5f5782009-09-01 13:09:39 +000014371 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014372 if (!dev) {
Matt Carlson2445e462010-04-05 10:19:21 +000014373 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070014374 err = -ENOMEM;
14375 goto err_out_free_res;
14376 }
14377
Linus Torvalds1da177e2005-04-16 15:20:36 -070014378 SET_NETDEV_DEV(dev, &pdev->dev);
14379
Linus Torvalds1da177e2005-04-16 15:20:36 -070014380#if TG3_VLAN_TAG_USED
14381 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014382#endif
14383
14384 tp = netdev_priv(dev);
14385 tp->pdev = pdev;
14386 tp->dev = dev;
14387 tp->pm_cap = pm_cap;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014388 tp->rx_mode = TG3_DEF_RX_MODE;
14389 tp->tx_mode = TG3_DEF_TX_MODE;
Matt Carlson8ef21422008-05-02 16:47:53 -070014390
Linus Torvalds1da177e2005-04-16 15:20:36 -070014391 if (tg3_debug > 0)
14392 tp->msg_enable = tg3_debug;
14393 else
14394 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14395
14396 /* The word/byte swap controls here control register access byte
14397 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14398 * setting below.
14399 */
14400 tp->misc_host_ctrl =
14401 MISC_HOST_CTRL_MASK_PCI_INT |
14402 MISC_HOST_CTRL_WORD_SWAP |
14403 MISC_HOST_CTRL_INDIR_ACCESS |
14404 MISC_HOST_CTRL_PCISTATE_RW;
14405
14406 /* The NONFRM (non-frame) byte/word swap controls take effect
14407 * on descriptor entries, anything which isn't packet data.
14408 *
14409 * The StrongARM chips on the board (one for tx, one for rx)
14410 * are running in big-endian mode.
14411 */
14412 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14413 GRC_MODE_WSWAP_NONFRM_DATA);
14414#ifdef __BIG_ENDIAN
14415 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14416#endif
14417 spin_lock_init(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014418 spin_lock_init(&tp->indirect_lock);
David Howellsc4028952006-11-22 14:57:56 +000014419 INIT_WORK(&tp->reset_task, tg3_reset_task);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014420
Matt Carlsond5fe4882008-11-21 17:20:32 -080014421 tp->regs = pci_ioremap_bar(pdev, BAR_0);
Andy Gospodarekab0049b2007-09-06 20:42:14 +010014422 if (!tp->regs) {
Matt Carlsonab96b242010-04-05 10:19:22 +000014423 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070014424 err = -ENOMEM;
14425 goto err_out_free_dev;
14426 }
14427
14428 tg3_init_link_config(tp);
14429
Linus Torvalds1da177e2005-04-16 15:20:36 -070014430 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14431 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014432
Linus Torvalds1da177e2005-04-16 15:20:36 -070014433 dev->ethtool_ops = &tg3_ethtool_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014434 dev->watchdog_timeo = TG3_TX_TIMEOUT;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014435 dev->irq = pdev->irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014436
14437 err = tg3_get_invariants(tp);
14438 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000014439 dev_err(&pdev->dev,
14440 "Problem fetching invariants of chip, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070014441 goto err_out_iounmap;
14442 }
14443
Matt Carlson615774f2009-11-13 13:03:39 +000014444 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
Matt Carlsona50d0792010-06-05 17:24:37 +000014445 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 &&
14446 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
Stephen Hemminger00829822008-11-20 20:14:53 -080014447 dev->netdev_ops = &tg3_netdev_ops;
14448 else
14449 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14450
14451
Michael Chan4a29cc22006-03-19 13:21:12 -080014452 /* The EPB bridge inside 5714, 5715, and 5780 and any
14453 * device behind the EPB cannot support DMA addresses > 40-bit.
Michael Chan72f2afb2006-03-06 19:28:35 -080014454 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14455 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14456 * do DMA address check in tg3_start_xmit().
14457 */
Michael Chan4a29cc22006-03-19 13:21:12 -080014458 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
Yang Hongyang284901a2009-04-06 19:01:15 -070014459 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
Michael Chan4a29cc22006-03-19 13:21:12 -080014460 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
Yang Hongyang50cf1562009-04-06 19:01:14 -070014461 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
Michael Chan72f2afb2006-03-06 19:28:35 -080014462#ifdef CONFIG_HIGHMEM
Yang Hongyang6a355282009-04-06 19:01:13 -070014463 dma_mask = DMA_BIT_MASK(64);
Michael Chan72f2afb2006-03-06 19:28:35 -080014464#endif
Michael Chan4a29cc22006-03-19 13:21:12 -080014465 } else
Yang Hongyang6a355282009-04-06 19:01:13 -070014466 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
Michael Chan72f2afb2006-03-06 19:28:35 -080014467
14468 /* Configure DMA attributes. */
Yang Hongyang284901a2009-04-06 19:01:15 -070014469 if (dma_mask > DMA_BIT_MASK(32)) {
Michael Chan72f2afb2006-03-06 19:28:35 -080014470 err = pci_set_dma_mask(pdev, dma_mask);
14471 if (!err) {
14472 dev->features |= NETIF_F_HIGHDMA;
14473 err = pci_set_consistent_dma_mask(pdev,
14474 persist_dma_mask);
14475 if (err < 0) {
Matt Carlsonab96b242010-04-05 10:19:22 +000014476 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14477 "DMA for consistent allocations\n");
Michael Chan72f2afb2006-03-06 19:28:35 -080014478 goto err_out_iounmap;
14479 }
14480 }
14481 }
Yang Hongyang284901a2009-04-06 19:01:15 -070014482 if (err || dma_mask == DMA_BIT_MASK(32)) {
14483 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Michael Chan72f2afb2006-03-06 19:28:35 -080014484 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000014485 dev_err(&pdev->dev,
14486 "No usable DMA configuration, aborting\n");
Michael Chan72f2afb2006-03-06 19:28:35 -080014487 goto err_out_iounmap;
14488 }
14489 }
14490
Michael Chanfdfec1722005-07-25 12:31:48 -070014491 tg3_init_bufmgr_config(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014492
Matt Carlson507399f2009-11-13 13:03:37 +000014493 /* Selectively allow TSO based on operating conditions */
14494 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14495 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14496 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14497 else {
14498 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14499 tp->fw_needed = NULL;
14500 }
14501
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -080014502 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
Matt Carlson9e9fd122009-01-19 16:57:45 -080014503 tp->fw_needed = FIRMWARE_TG3;
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -080014504
Michael Chan4e3a7aa2006-03-20 17:47:44 -080014505 /* TSO is on by default on chips that support hardware TSO.
14506 * Firmware TSO on older chips gives lower performance, so it
14507 * is off by default, but can be enabled using ethtool.
14508 */
Matt Carlsone849cdc2009-11-13 13:03:38 +000014509 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
Eric Dumazet7fe876a2010-07-08 06:14:55 +000014510 (dev->features & NETIF_F_IP_CSUM)) {
Matt Carlsone849cdc2009-11-13 13:03:38 +000014511 dev->features |= NETIF_F_TSO;
Eric Dumazet7fe876a2010-07-08 06:14:55 +000014512 vlan_features_add(dev, NETIF_F_TSO);
14513 }
Matt Carlsone849cdc2009-11-13 13:03:38 +000014514 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14515 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
Eric Dumazet7fe876a2010-07-08 06:14:55 +000014516 if (dev->features & NETIF_F_IPV6_CSUM) {
Michael Chanb0026622006-07-03 19:42:14 -070014517 dev->features |= NETIF_F_TSO6;
Eric Dumazet7fe876a2010-07-08 06:14:55 +000014518 vlan_features_add(dev, NETIF_F_TSO6);
14519 }
Matt Carlsone849cdc2009-11-13 13:03:38 +000014520 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14521 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
Matt Carlson57e69832008-05-25 23:48:31 -070014522 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14523 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
Matt Carlson321d32a2008-11-21 17:22:19 -080014524 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
Eric Dumazet7fe876a2010-07-08 06:14:55 +000014525 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
Matt Carlson9936bcf2007-10-10 18:03:07 -070014526 dev->features |= NETIF_F_TSO_ECN;
Eric Dumazet7fe876a2010-07-08 06:14:55 +000014527 vlan_features_add(dev, NETIF_F_TSO_ECN);
14528 }
Michael Chanb0026622006-07-03 19:42:14 -070014529 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014530
Linus Torvalds1da177e2005-04-16 15:20:36 -070014531 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14532 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14533 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14534 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14535 tp->rx_pending = 63;
14536 }
14537
Linus Torvalds1da177e2005-04-16 15:20:36 -070014538 err = tg3_get_device_address(tp);
14539 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000014540 dev_err(&pdev->dev,
14541 "Could not obtain valid ethernet address, aborting\n");
Matt Carlson026a6c22009-12-03 08:36:24 +000014542 goto err_out_iounmap;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014543 }
14544
Matt Carlson0d3031d2007-10-10 18:02:43 -070014545 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
Matt Carlson63532392008-11-03 16:49:57 -080014546 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
Al Viro79ea13c2008-01-24 02:06:46 -080014547 if (!tp->aperegs) {
Matt Carlsonab96b242010-04-05 10:19:22 +000014548 dev_err(&pdev->dev,
14549 "Cannot map APE registers, aborting\n");
Matt Carlson0d3031d2007-10-10 18:02:43 -070014550 err = -ENOMEM;
Matt Carlson026a6c22009-12-03 08:36:24 +000014551 goto err_out_iounmap;
Matt Carlson0d3031d2007-10-10 18:02:43 -070014552 }
14553
14554 tg3_ape_lock_init(tp);
Matt Carlson7fd76442009-02-25 14:27:20 +000014555
14556 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14557 tg3_read_dash_ver(tp);
Matt Carlson0d3031d2007-10-10 18:02:43 -070014558 }
14559
Matt Carlsonc88864d2007-11-12 21:07:01 -080014560 /*
14561 * Reset chip in case UNDI or EFI driver did not shutdown
14562 * DMA self test will enable WDMAC and we'll see (spurious)
14563 * pending DMA on the PCI bus at that point.
14564 */
14565 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14566 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14567 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14568 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14569 }
14570
14571 err = tg3_test_dma(tp);
14572 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000014573 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
Matt Carlsonc88864d2007-11-12 21:07:01 -080014574 goto err_out_apeunmap;
14575 }
14576
Matt Carlsonc88864d2007-11-12 21:07:01 -080014577 /* flow control autonegotiation is default behavior */
14578 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
Steve Glendinninge18ce342008-12-16 02:00:00 -080014579 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
Matt Carlsonc88864d2007-11-12 21:07:01 -080014580
Matt Carlson78f90dc2009-11-13 13:03:42 +000014581 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14582 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14583 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14584 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14585 struct tg3_napi *tnapi = &tp->napi[i];
14586
14587 tnapi->tp = tp;
14588 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14589
14590 tnapi->int_mbox = intmbx;
14591 if (i < 4)
14592 intmbx += 0x8;
14593 else
14594 intmbx += 0x4;
14595
14596 tnapi->consmbox = rcvmbx;
14597 tnapi->prodmbox = sndmbx;
14598
14599 if (i) {
14600 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14601 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14602 } else {
14603 tnapi->coal_now = HOSTCC_MODE_NOW;
14604 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14605 }
14606
14607 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14608 break;
14609
14610 /*
14611 * If we support MSIX, we'll be using RSS. If we're using
14612 * RSS, the first vector only handles link interrupts and the
14613 * remaining vectors handle rx and tx interrupts. Reuse the
14614 * mailbox values for the next iteration. The values we setup
14615 * above are still useful for the single vectored mode.
14616 */
14617 if (!i)
14618 continue;
14619
14620 rcvmbx += 0x8;
14621
14622 if (sndmbx & 0x4)
14623 sndmbx -= 0x4;
14624 else
14625 sndmbx += 0xc;
14626 }
14627
Matt Carlsonc88864d2007-11-12 21:07:01 -080014628 tg3_init_coal(tp);
14629
Michael Chanc49a1562006-12-17 17:07:29 -080014630 pci_set_drvdata(pdev, dev);
14631
Linus Torvalds1da177e2005-04-16 15:20:36 -070014632 err = register_netdev(dev);
14633 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000014634 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
Matt Carlson0d3031d2007-10-10 18:02:43 -070014635 goto err_out_apeunmap;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014636 }
14637
Joe Perches05dbe002010-02-17 19:44:19 +000014638 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14639 tp->board_part_number,
14640 tp->pci_chip_rev_id,
14641 tg3_bus_string(tp, str),
14642 dev->dev_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014643
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014644 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000014645 struct phy_device *phydev;
14646 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlson5129c3a2010-04-05 10:19:23 +000014647 netdev_info(dev,
14648 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
Joe Perches05dbe002010-02-17 19:44:19 +000014649 phydev->drv->name, dev_name(&phydev->dev));
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014650 } else {
14651 char *ethtype;
14652
14653 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14654 ethtype = "10/100Base-TX";
14655 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14656 ethtype = "1000Base-SX";
14657 else
14658 ethtype = "10/100/1000Base-T";
14659
Matt Carlson5129c3a2010-04-05 10:19:23 +000014660 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014661 "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14662 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14663 }
Matt Carlsondf59c942008-11-03 16:52:56 -080014664
Joe Perches05dbe002010-02-17 19:44:19 +000014665 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14666 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14667 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014668 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
Joe Perches05dbe002010-02-17 19:44:19 +000014669 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14670 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14671 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14672 tp->dma_rwctrl,
14673 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14674 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014675
14676 return 0;
14677
Matt Carlson0d3031d2007-10-10 18:02:43 -070014678err_out_apeunmap:
14679 if (tp->aperegs) {
14680 iounmap(tp->aperegs);
14681 tp->aperegs = NULL;
14682 }
14683
Linus Torvalds1da177e2005-04-16 15:20:36 -070014684err_out_iounmap:
Michael Chan68929142005-08-09 20:17:14 -070014685 if (tp->regs) {
14686 iounmap(tp->regs);
Peter Hagervall22abe312005-09-16 17:01:03 -070014687 tp->regs = NULL;
Michael Chan68929142005-08-09 20:17:14 -070014688 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014689
14690err_out_free_dev:
14691 free_netdev(dev);
14692
14693err_out_free_res:
14694 pci_release_regions(pdev);
14695
14696err_out_disable_pdev:
14697 pci_disable_device(pdev);
14698 pci_set_drvdata(pdev, NULL);
14699 return err;
14700}
14701
14702static void __devexit tg3_remove_one(struct pci_dev *pdev)
14703{
14704 struct net_device *dev = pci_get_drvdata(pdev);
14705
14706 if (dev) {
14707 struct tg3 *tp = netdev_priv(dev);
14708
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -080014709 if (tp->fw)
14710 release_firmware(tp->fw);
14711
Michael Chan7faa0062006-02-02 17:29:28 -080014712 flush_scheduled_work();
Matt Carlson158d7ab2008-05-29 01:37:54 -070014713
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070014714 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14715 tg3_phy_fini(tp);
Matt Carlson158d7ab2008-05-29 01:37:54 -070014716 tg3_mdio_fini(tp);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070014717 }
Matt Carlson158d7ab2008-05-29 01:37:54 -070014718
Linus Torvalds1da177e2005-04-16 15:20:36 -070014719 unregister_netdev(dev);
Matt Carlson0d3031d2007-10-10 18:02:43 -070014720 if (tp->aperegs) {
14721 iounmap(tp->aperegs);
14722 tp->aperegs = NULL;
14723 }
Michael Chan68929142005-08-09 20:17:14 -070014724 if (tp->regs) {
14725 iounmap(tp->regs);
Peter Hagervall22abe312005-09-16 17:01:03 -070014726 tp->regs = NULL;
Michael Chan68929142005-08-09 20:17:14 -070014727 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014728 free_netdev(dev);
14729 pci_release_regions(pdev);
14730 pci_disable_device(pdev);
14731 pci_set_drvdata(pdev, NULL);
14732 }
14733}
14734
14735static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14736{
14737 struct net_device *dev = pci_get_drvdata(pdev);
14738 struct tg3 *tp = netdev_priv(dev);
Rafael J. Wysocki12dac072008-07-30 16:37:33 -070014739 pci_power_t target_state;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014740 int err;
14741
Michael Chan3e0c95f2007-08-03 20:56:54 -070014742 /* PCI register 4 needs to be saved whether netif_running() or not.
14743 * MSI address and data need to be saved if using MSI and
14744 * netif_running().
14745 */
14746 pci_save_state(pdev);
14747
Linus Torvalds1da177e2005-04-16 15:20:36 -070014748 if (!netif_running(dev))
14749 return 0;
14750
Michael Chan7faa0062006-02-02 17:29:28 -080014751 flush_scheduled_work();
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070014752 tg3_phy_stop(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014753 tg3_netif_stop(tp);
14754
14755 del_timer_sync(&tp->timer);
14756
David S. Millerf47c11e2005-06-24 20:18:35 -070014757 tg3_full_lock(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014758 tg3_disable_ints(tp);
David S. Millerf47c11e2005-06-24 20:18:35 -070014759 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014760
14761 netif_device_detach(dev);
14762
David S. Millerf47c11e2005-06-24 20:18:35 -070014763 tg3_full_lock(tp, 0);
Michael Chan944d9802005-05-29 14:57:48 -070014764 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Michael Chan6a9eba12005-12-13 21:08:58 -080014765 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
David S. Millerf47c11e2005-06-24 20:18:35 -070014766 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014767
Rafael J. Wysocki12dac072008-07-30 16:37:33 -070014768 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14769
14770 err = tg3_set_power_state(tp, target_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014771 if (err) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070014772 int err2;
14773
David S. Millerf47c11e2005-06-24 20:18:35 -070014774 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014775
Michael Chan6a9eba12005-12-13 21:08:58 -080014776 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070014777 err2 = tg3_restart_hw(tp, 1);
14778 if (err2)
Michael Chanb9ec6c12006-07-25 16:37:27 -070014779 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014780
14781 tp->timer.expires = jiffies + tp->timer_offset;
14782 add_timer(&tp->timer);
14783
14784 netif_device_attach(dev);
14785 tg3_netif_start(tp);
14786
Michael Chanb9ec6c12006-07-25 16:37:27 -070014787out:
David S. Millerf47c11e2005-06-24 20:18:35 -070014788 tg3_full_unlock(tp);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070014789
14790 if (!err2)
14791 tg3_phy_start(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014792 }
14793
14794 return err;
14795}
14796
14797static int tg3_resume(struct pci_dev *pdev)
14798{
14799 struct net_device *dev = pci_get_drvdata(pdev);
14800 struct tg3 *tp = netdev_priv(dev);
14801 int err;
14802
Michael Chan3e0c95f2007-08-03 20:56:54 -070014803 pci_restore_state(tp->pdev);
14804
Linus Torvalds1da177e2005-04-16 15:20:36 -070014805 if (!netif_running(dev))
14806 return 0;
14807
Michael Chanbc1c7562006-03-20 17:48:03 -080014808 err = tg3_set_power_state(tp, PCI_D0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014809 if (err)
14810 return err;
14811
14812 netif_device_attach(dev);
14813
David S. Millerf47c11e2005-06-24 20:18:35 -070014814 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014815
Michael Chan6a9eba12005-12-13 21:08:58 -080014816 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
Michael Chanb9ec6c12006-07-25 16:37:27 -070014817 err = tg3_restart_hw(tp, 1);
14818 if (err)
14819 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014820
14821 tp->timer.expires = jiffies + tp->timer_offset;
14822 add_timer(&tp->timer);
14823
Linus Torvalds1da177e2005-04-16 15:20:36 -070014824 tg3_netif_start(tp);
14825
Michael Chanb9ec6c12006-07-25 16:37:27 -070014826out:
David S. Millerf47c11e2005-06-24 20:18:35 -070014827 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014828
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070014829 if (!err)
14830 tg3_phy_start(tp);
14831
Michael Chanb9ec6c12006-07-25 16:37:27 -070014832 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014833}
14834
14835static struct pci_driver tg3_driver = {
14836 .name = DRV_MODULE_NAME,
14837 .id_table = tg3_pci_tbl,
14838 .probe = tg3_init_one,
14839 .remove = __devexit_p(tg3_remove_one),
14840 .suspend = tg3_suspend,
14841 .resume = tg3_resume
14842};
14843
14844static int __init tg3_init(void)
14845{
Jeff Garzik29917622006-08-19 17:48:59 -040014846 return pci_register_driver(&tg3_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014847}
14848
14849static void __exit tg3_cleanup(void)
14850{
14851 pci_unregister_driver(&tg3_driver);
14852}
14853
14854module_init(tg3_init);
14855module_exit(tg3_cleanup);