Greg Rose | 50d9c84 | 2010-01-09 02:23:11 +0000 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel 82599 Virtual Function driver |
Greg Rose | 5c47a2b | 2012-01-06 02:53:30 +0000 | [diff] [blame] | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
Greg Rose | 50d9c84 | 2010-01-09 02:23:11 +0000 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | #ifndef _IXGBEVF_DEFINES_H_ |
| 29 | #define _IXGBEVF_DEFINES_H_ |
| 30 | |
| 31 | /* Device IDs */ |
| 32 | #define IXGBE_DEV_ID_82599_VF 0x10ED |
Greg Rose | 2316aa2 | 2010-12-02 07:12:26 +0000 | [diff] [blame] | 33 | #define IXGBE_DEV_ID_X540_VF 0x1515 |
Greg Rose | 50d9c84 | 2010-01-09 02:23:11 +0000 | [diff] [blame] | 34 | |
| 35 | #define IXGBE_VF_IRQ_CLEAR_MASK 7 |
| 36 | #define IXGBE_VF_MAX_TX_QUEUES 1 |
| 37 | #define IXGBE_VF_MAX_RX_QUEUES 1 |
Greg Rose | 50d9c84 | 2010-01-09 02:23:11 +0000 | [diff] [blame] | 38 | |
| 39 | /* Link speed */ |
| 40 | typedef u32 ixgbe_link_speed; |
| 41 | #define IXGBE_LINK_SPEED_1GB_FULL 0x0020 |
| 42 | #define IXGBE_LINK_SPEED_10GB_FULL 0x0080 |
Greg Rose | 31a1b37 | 2012-04-10 01:56:37 +0000 | [diff] [blame] | 43 | #define IXGBE_LINK_SPEED_100_FULL 0x0008 |
Greg Rose | 50d9c84 | 2010-01-09 02:23:11 +0000 | [diff] [blame] | 44 | |
Greg Rose | 3203df0 | 2010-04-27 11:31:45 +0000 | [diff] [blame] | 45 | #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ |
| 46 | #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ |
| 47 | #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ |
| 48 | #define IXGBE_LINKS_UP 0x40000000 |
| 49 | #define IXGBE_LINKS_SPEED_82599 0x30000000 |
| 50 | #define IXGBE_LINKS_SPEED_10G_82599 0x30000000 |
| 51 | #define IXGBE_LINKS_SPEED_1G_82599 0x20000000 |
Greg Rose | 31a1b37 | 2012-04-10 01:56:37 +0000 | [diff] [blame] | 52 | #define IXGBE_LINKS_SPEED_100_82599 0x10000000 |
Greg Rose | 50d9c84 | 2010-01-09 02:23:11 +0000 | [diff] [blame] | 53 | |
| 54 | /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ |
| 55 | #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 |
| 56 | #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 |
| 57 | #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 |
| 58 | |
| 59 | /* Interrupt Vector Allocation Registers */ |
| 60 | #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ |
| 61 | |
| 62 | #define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ |
| 63 | |
| 64 | /* Receive Config masks */ |
| 65 | #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ |
| 66 | #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ |
| 67 | #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ |
| 68 | #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ |
Greg Rose | 69bfbec | 2011-01-26 01:06:12 +0000 | [diff] [blame] | 69 | #define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */ |
| 70 | #define IXGBE_RXDCTL_RLPML_EN 0x00008000 |
Greg Rose | 50d9c84 | 2010-01-09 02:23:11 +0000 | [diff] [blame] | 71 | |
| 72 | /* DCA Control */ |
| 73 | #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ |
| 74 | |
| 75 | /* PSRTYPE bit definitions */ |
| 76 | #define IXGBE_PSRTYPE_TCPHDR 0x00000010 |
| 77 | #define IXGBE_PSRTYPE_UDPHDR 0x00000020 |
| 78 | #define IXGBE_PSRTYPE_IPV4HDR 0x00000100 |
| 79 | #define IXGBE_PSRTYPE_IPV6HDR 0x00000200 |
| 80 | #define IXGBE_PSRTYPE_L2HDR 0x00001000 |
| 81 | |
| 82 | /* SRRCTL bit definitions */ |
| 83 | #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ |
| 84 | #define IXGBE_SRRCTL_RDMTS_SHIFT 22 |
| 85 | #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 |
| 86 | #define IXGBE_SRRCTL_DROP_EN 0x10000000 |
| 87 | #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F |
| 88 | #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 |
| 89 | #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 |
| 90 | #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 |
| 91 | #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 |
| 92 | #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 |
| 93 | #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 |
| 94 | #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 |
| 95 | |
| 96 | /* Receive Descriptor bit definitions */ |
| 97 | #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ |
| 98 | #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ |
| 99 | #define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ |
| 100 | #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ |
| 101 | #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ |
| 102 | #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 |
| 103 | #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ |
| 104 | #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ |
| 105 | #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ |
| 106 | #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ |
| 107 | #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ |
| 108 | #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ |
| 109 | #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ |
| 110 | #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ |
| 111 | #define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ |
| 112 | #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ |
| 113 | #define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ |
| 114 | #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ |
| 115 | #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ |
| 116 | #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ |
| 117 | #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ |
| 118 | #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ |
| 119 | #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ |
| 120 | #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ |
| 121 | #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ |
| 122 | #define IXGBE_RXDADV_ERR_MASK 0xFFF00000 /* RDESC.ERRORS mask */ |
| 123 | #define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ |
| 124 | #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ |
| 125 | #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ |
| 126 | #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ |
| 127 | #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ |
| 128 | #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ |
| 129 | #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ |
| 130 | #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ |
| 131 | #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ |
| 132 | #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ |
| 133 | #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ |
| 134 | #define IXGBE_RXD_PRI_SHIFT 13 |
| 135 | #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ |
| 136 | #define IXGBE_RXD_CFI_SHIFT 12 |
| 137 | |
| 138 | #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ |
| 139 | #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ |
| 140 | #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ |
| 141 | #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ |
| 142 | #define IXGBE_RXDADV_STAT_MASK 0x000FFFFF /* Stat/NEXTP: bit 0-19 */ |
| 143 | #define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ |
| 144 | #define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ |
| 145 | #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ |
| 146 | #define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ |
| 147 | #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ |
| 148 | #define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ |
| 149 | |
| 150 | #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F |
| 151 | #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 |
| 152 | #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 |
| 153 | #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 |
| 154 | #define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 |
| 155 | #define IXGBE_RXDADV_RSCCNT_SHIFT 17 |
| 156 | #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 |
| 157 | #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 |
| 158 | #define IXGBE_RXDADV_SPH 0x8000 |
| 159 | |
| 160 | #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ |
| 161 | IXGBE_RXD_ERR_CE | \ |
| 162 | IXGBE_RXD_ERR_LE | \ |
| 163 | IXGBE_RXD_ERR_PE | \ |
| 164 | IXGBE_RXD_ERR_OSE | \ |
| 165 | IXGBE_RXD_ERR_USE) |
| 166 | |
| 167 | #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ |
| 168 | IXGBE_RXDADV_ERR_CE | \ |
| 169 | IXGBE_RXDADV_ERR_LE | \ |
| 170 | IXGBE_RXDADV_ERR_PE | \ |
| 171 | IXGBE_RXDADV_ERR_OSE | \ |
| 172 | IXGBE_RXDADV_ERR_USE) |
| 173 | |
| 174 | #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ |
| 175 | #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ |
| 176 | #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ |
| 177 | #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ |
| 178 | #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ |
| 179 | #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ |
| 180 | #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ |
| 181 | #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ |
| 182 | #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ |
| 183 | |
| 184 | /* Transmit Descriptor - Advanced */ |
| 185 | union ixgbe_adv_tx_desc { |
| 186 | struct { |
| 187 | __le64 buffer_addr; /* Address of descriptor's data buf */ |
| 188 | __le32 cmd_type_len; |
| 189 | __le32 olinfo_status; |
| 190 | } read; |
| 191 | struct { |
| 192 | __le64 rsvd; /* Reserved */ |
| 193 | __le32 nxtseq_seed; |
| 194 | __le32 status; |
| 195 | } wb; |
| 196 | }; |
| 197 | |
| 198 | /* Receive Descriptor - Advanced */ |
| 199 | union ixgbe_adv_rx_desc { |
| 200 | struct { |
| 201 | __le64 pkt_addr; /* Packet buffer address */ |
| 202 | __le64 hdr_addr; /* Header buffer address */ |
| 203 | } read; |
| 204 | struct { |
| 205 | struct { |
| 206 | union { |
| 207 | __le32 data; |
| 208 | struct { |
| 209 | __le16 pkt_info; /* RSS, Pkt type */ |
| 210 | __le16 hdr_info; /* Splithdr, hdrlen */ |
| 211 | } hs_rss; |
| 212 | } lo_dword; |
| 213 | union { |
| 214 | __le32 rss; /* RSS Hash */ |
| 215 | struct { |
| 216 | __le16 ip_id; /* IP id */ |
| 217 | __le16 csum; /* Packet Checksum */ |
| 218 | } csum_ip; |
| 219 | } hi_dword; |
| 220 | } lower; |
| 221 | struct { |
| 222 | __le32 status_error; /* ext status/error */ |
| 223 | __le16 length; /* Packet length */ |
| 224 | __le16 vlan; /* VLAN tag */ |
| 225 | } upper; |
| 226 | } wb; /* writeback */ |
| 227 | }; |
| 228 | |
| 229 | /* Context descriptors */ |
| 230 | struct ixgbe_adv_tx_context_desc { |
| 231 | __le32 vlan_macip_lens; |
| 232 | __le32 seqnum_seed; |
| 233 | __le32 type_tucmd_mlhl; |
| 234 | __le32 mss_l4len_idx; |
| 235 | }; |
| 236 | |
| 237 | /* Adv Transmit Descriptor Config Masks */ |
| 238 | #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ |
| 239 | #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ |
| 240 | #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ |
| 241 | #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ |
| 242 | #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ |
| 243 | #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ |
| 244 | #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ |
| 245 | #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ |
| 246 | #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ |
| 247 | #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ |
| 248 | #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ |
| 249 | #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ |
| 250 | #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ |
| 251 | #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ |
| 252 | #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ |
| 253 | #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ |
Alexander Duyck | 70a10e2 | 2012-05-11 08:33:21 +0000 | [diff] [blame] | 254 | #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ |
Greg Rose | 50d9c84 | 2010-01-09 02:23:11 +0000 | [diff] [blame] | 255 | #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ |
| 256 | #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ |
| 257 | IXGBE_ADVTXD_POPTS_SHIFT) |
| 258 | #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ |
| 259 | IXGBE_ADVTXD_POPTS_SHIFT) |
| 260 | #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ |
| 261 | #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ |
| 262 | #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ |
| 263 | #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ |
| 264 | #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ |
| 265 | |
| 266 | /* Interrupt register bitmasks */ |
| 267 | |
Greg Rose | 50d9c84 | 2010-01-09 02:23:11 +0000 | [diff] [blame] | 268 | #define IXGBE_EITR_CNT_WDIS 0x80000000 |
Alexander Duyck | 5f3600e | 2012-05-11 08:32:55 +0000 | [diff] [blame] | 269 | #define IXGBE_MAX_EITR 0x00000FF8 |
| 270 | #define IXGBE_MIN_EITR 8 |
Greg Rose | 50d9c84 | 2010-01-09 02:23:11 +0000 | [diff] [blame] | 271 | |
| 272 | /* Error Codes */ |
| 273 | #define IXGBE_ERR_INVALID_MAC_ADDR -1 |
| 274 | #define IXGBE_ERR_RESET_FAILED -2 |
Alexander Duyck | 3118678 | 2012-07-20 08:09:58 +0000 | [diff] [blame^] | 275 | #define IXGBE_ERR_INVALID_ARGUMENT -3 |
Greg Rose | 50d9c84 | 2010-01-09 02:23:11 +0000 | [diff] [blame] | 276 | |
| 277 | #endif /* _IXGBEVF_DEFINES_H_ */ |