Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2009 Jerome Glisse. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 20 | * |
| 21 | * The above copyright notice and this permission notice (including the |
| 22 | * next paragraph) shall be included in all copies or substantial portions |
| 23 | * of the Software. |
| 24 | * |
| 25 | */ |
| 26 | /* |
| 27 | * Authors: |
| 28 | * Jerome Glisse <glisse@freedesktop.org> |
| 29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> |
| 30 | * Dave Airlie |
| 31 | */ |
| 32 | #include <linux/list.h> |
| 33 | #include <drm/drmP.h> |
| 34 | #include "radeon_drm.h" |
| 35 | #include "radeon.h" |
| 36 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 37 | |
| 38 | int radeon_ttm_init(struct radeon_device *rdev); |
| 39 | void radeon_ttm_fini(struct radeon_device *rdev); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 40 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 41 | |
| 42 | /* |
| 43 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all |
| 44 | * function are calling it. |
| 45 | */ |
| 46 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 47 | static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 48 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 49 | struct radeon_bo *bo; |
| 50 | |
| 51 | bo = container_of(tbo, struct radeon_bo, tbo); |
| 52 | mutex_lock(&bo->rdev->gem.mutex); |
| 53 | list_del_init(&bo->list); |
| 54 | mutex_unlock(&bo->rdev->gem.mutex); |
| 55 | radeon_bo_clear_surface_reg(bo); |
| 56 | kfree(bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 57 | } |
| 58 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 59 | static inline u32 radeon_ttm_flags_from_domain(u32 domain) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 60 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 61 | u32 flags = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 62 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 63 | if (domain & RADEON_GEM_DOMAIN_VRAM) { |
Michel Dänzer | 664f865 | 2009-07-28 12:30:57 +0200 | [diff] [blame] | 64 | flags |= TTM_PL_FLAG_VRAM | TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 65 | } |
| 66 | if (domain & RADEON_GEM_DOMAIN_GTT) { |
Jerome Glisse | 985fe84 | 2009-07-29 18:55:53 +0200 | [diff] [blame] | 67 | flags |= TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 68 | } |
| 69 | if (domain & RADEON_GEM_DOMAIN_CPU) { |
Michel Dänzer | 664f865 | 2009-07-28 12:30:57 +0200 | [diff] [blame] | 70 | flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 71 | } |
| 72 | if (!flags) { |
Michel Dänzer | 664f865 | 2009-07-28 12:30:57 +0200 | [diff] [blame] | 73 | flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 74 | } |
| 75 | return flags; |
| 76 | } |
| 77 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 78 | int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj, |
| 79 | unsigned long size, bool kernel, u32 domain, |
| 80 | struct radeon_bo **bo_ptr) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 81 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 82 | struct radeon_bo *bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 83 | enum ttm_bo_type type; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 84 | u32 flags; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 85 | int r; |
| 86 | |
| 87 | if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { |
| 88 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; |
| 89 | } |
| 90 | if (kernel) { |
| 91 | type = ttm_bo_type_kernel; |
| 92 | } else { |
| 93 | type = ttm_bo_type_device; |
| 94 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 95 | *bo_ptr = NULL; |
| 96 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); |
| 97 | if (bo == NULL) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 98 | return -ENOMEM; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 99 | bo->rdev = rdev; |
| 100 | bo->gobj = gobj; |
| 101 | bo->surface_reg = -1; |
| 102 | INIT_LIST_HEAD(&bo->list); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 103 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 104 | flags = radeon_ttm_flags_from_domain(domain); |
| 105 | retry: |
| 106 | r = ttm_buffer_object_init(&rdev->mman.bdev, &bo->tbo, size, type, |
| 107 | flags, 0, 0, true, NULL, size, |
| 108 | &radeon_ttm_bo_destroy); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 109 | if (unlikely(r != 0)) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 110 | if (r == -ERESTART) |
| 111 | goto retry; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 112 | /* ttm call radeon_ttm_object_object_destroy if error happen */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 113 | dev_err(rdev->dev, "object_init failed for (%ld, 0x%08X)\n", |
| 114 | size, flags); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 115 | return r; |
| 116 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 117 | *bo_ptr = bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 118 | if (gobj) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 119 | mutex_lock(&bo->rdev->gem.mutex); |
| 120 | list_add_tail(&bo->list, &rdev->gem.objects); |
| 121 | mutex_unlock(&bo->rdev->gem.mutex); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 122 | } |
| 123 | return 0; |
| 124 | } |
| 125 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 126 | int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 127 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 128 | bool is_iomem; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 129 | int r; |
| 130 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 131 | if (bo->kptr) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 132 | if (ptr) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 133 | *ptr = bo->kptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 134 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 135 | return 0; |
| 136 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 137 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 138 | if (r) { |
| 139 | return r; |
| 140 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 141 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 142 | if (ptr) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 143 | *ptr = bo->kptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 144 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 145 | radeon_bo_check_tiling(bo, 0, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 146 | return 0; |
| 147 | } |
| 148 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 149 | void radeon_bo_kunmap(struct radeon_bo *bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 150 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 151 | if (bo->kptr == NULL) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 152 | return; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 153 | bo->kptr = NULL; |
| 154 | radeon_bo_check_tiling(bo, 0, 0); |
| 155 | ttm_bo_kunmap(&bo->kmap); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 156 | } |
| 157 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 158 | void radeon_bo_unref(struct radeon_bo **bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 159 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 160 | struct ttm_buffer_object *tbo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 161 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 162 | if ((*bo) == NULL) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 163 | return; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 164 | tbo = &((*bo)->tbo); |
| 165 | ttm_bo_unref(&tbo); |
| 166 | if (tbo == NULL) |
| 167 | *bo = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 168 | } |
| 169 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 170 | int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 171 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 172 | u32 flags; |
| 173 | u32 tmp; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 174 | int r; |
| 175 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 176 | flags = radeon_ttm_flags_from_domain(domain); |
| 177 | if (bo->pin_count) { |
| 178 | bo->pin_count++; |
| 179 | if (gpu_addr) |
| 180 | *gpu_addr = radeon_bo_gpu_offset(bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 181 | return 0; |
| 182 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 183 | tmp = bo->tbo.mem.placement; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 184 | ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 185 | bo->tbo.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT | |
| 186 | TTM_PL_MASK_CACHING; |
| 187 | retry: |
| 188 | r = ttm_buffer_object_validate(&bo->tbo, bo->tbo.proposed_placement, |
| 189 | true, false); |
| 190 | if (likely(r == 0)) { |
| 191 | bo->pin_count = 1; |
| 192 | if (gpu_addr != NULL) |
| 193 | *gpu_addr = radeon_bo_gpu_offset(bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 194 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 195 | if (unlikely(r != 0)) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 196 | if (r == -ERESTART) |
| 197 | goto retry; |
| 198 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 199 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 200 | return r; |
| 201 | } |
| 202 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 203 | int radeon_bo_unpin(struct radeon_bo *bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 204 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 205 | int r; |
| 206 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 207 | if (!bo->pin_count) { |
| 208 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); |
| 209 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 210 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 211 | bo->pin_count--; |
| 212 | if (bo->pin_count) |
| 213 | return 0; |
| 214 | bo->tbo.proposed_placement = bo->tbo.mem.placement & |
| 215 | ~TTM_PL_FLAG_NO_EVICT; |
| 216 | retry: |
| 217 | r = ttm_buffer_object_validate(&bo->tbo, bo->tbo.proposed_placement, |
| 218 | true, false); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 219 | if (unlikely(r != 0)) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 220 | if (r == -ERESTART) |
| 221 | goto retry; |
| 222 | dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 223 | return r; |
| 224 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 225 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 226 | } |
| 227 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 228 | int radeon_bo_evict_vram(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 229 | { |
| 230 | if (rdev->flags & RADEON_IS_IGP) { |
| 231 | /* Useless to evict on IGP chips */ |
| 232 | return 0; |
| 233 | } |
| 234 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); |
| 235 | } |
| 236 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 237 | void radeon_bo_force_delete(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 238 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 239 | struct radeon_bo *bo, *n; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 240 | struct drm_gem_object *gobj; |
| 241 | |
| 242 | if (list_empty(&rdev->gem.objects)) { |
| 243 | return; |
| 244 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 245 | dev_err(rdev->dev, "Userspace still has active objects !\n"); |
| 246 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 247 | mutex_lock(&rdev->ddev->struct_mutex); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 248 | gobj = bo->gobj; |
| 249 | dev_err(rdev->dev, "%p %p %lu %lu force free\n", |
| 250 | gobj, bo, (unsigned long)gobj->size, |
| 251 | *((unsigned long *)&gobj->refcount)); |
| 252 | mutex_lock(&bo->rdev->gem.mutex); |
| 253 | list_del_init(&bo->list); |
| 254 | mutex_unlock(&bo->rdev->gem.mutex); |
| 255 | radeon_bo_unref(&bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 256 | gobj->driver_private = NULL; |
| 257 | drm_gem_object_unreference(gobj); |
| 258 | mutex_unlock(&rdev->ddev->struct_mutex); |
| 259 | } |
| 260 | } |
| 261 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 262 | int radeon_bo_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 263 | { |
Jerome Glisse | a4d6827 | 2009-09-11 13:00:43 +0200 | [diff] [blame] | 264 | /* Add an MTRR for the VRAM */ |
| 265 | rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, |
| 266 | MTRR_TYPE_WRCOMB, 1); |
| 267 | DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", |
| 268 | rdev->mc.mc_vram_size >> 20, |
| 269 | (unsigned long long)rdev->mc.aper_size >> 20); |
| 270 | DRM_INFO("RAM width %dbits %cDR\n", |
| 271 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 272 | return radeon_ttm_init(rdev); |
| 273 | } |
| 274 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 275 | void radeon_bo_fini(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 276 | { |
| 277 | radeon_ttm_fini(rdev); |
| 278 | } |
| 279 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 280 | void radeon_bo_list_add_object(struct radeon_bo_list *lobj, |
| 281 | struct list_head *head) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 282 | { |
| 283 | if (lobj->wdomain) { |
| 284 | list_add(&lobj->list, head); |
| 285 | } else { |
| 286 | list_add_tail(&lobj->list, head); |
| 287 | } |
| 288 | } |
| 289 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 290 | int radeon_bo_list_reserve(struct list_head *head) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 291 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 292 | struct radeon_bo_list *lobj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 293 | int r; |
| 294 | |
Dave Airlie | 9d8401f | 2009-10-08 09:28:19 +1000 | [diff] [blame] | 295 | list_for_each_entry(lobj, head, list){ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 296 | r = radeon_bo_reserve(lobj->bo, false); |
| 297 | if (unlikely(r != 0)) |
| 298 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 299 | } |
| 300 | return 0; |
| 301 | } |
| 302 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 303 | void radeon_bo_list_unreserve(struct list_head *head) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 304 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 305 | struct radeon_bo_list *lobj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 306 | |
Dave Airlie | 9d8401f | 2009-10-08 09:28:19 +1000 | [diff] [blame] | 307 | list_for_each_entry(lobj, head, list) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 308 | /* only unreserve object we successfully reserved */ |
| 309 | if (radeon_bo_is_reserved(lobj->bo)) |
| 310 | radeon_bo_unreserve(lobj->bo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 311 | } |
| 312 | } |
| 313 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 314 | int radeon_bo_list_validate(struct list_head *head, void *fence) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 315 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 316 | struct radeon_bo_list *lobj; |
| 317 | struct radeon_bo *bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 318 | struct radeon_fence *old_fence = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 319 | int r; |
| 320 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 321 | r = radeon_bo_list_reserve(head); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 322 | if (unlikely(r != 0)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 323 | return r; |
| 324 | } |
Dave Airlie | 9d8401f | 2009-10-08 09:28:19 +1000 | [diff] [blame] | 325 | list_for_each_entry(lobj, head, list) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 326 | bo = lobj->bo; |
| 327 | if (!bo->pin_count) { |
Michel Dänzer | 664f865 | 2009-07-28 12:30:57 +0200 | [diff] [blame] | 328 | if (lobj->wdomain) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 329 | bo->tbo.proposed_placement = |
| 330 | radeon_ttm_flags_from_domain(lobj->wdomain); |
Michel Dänzer | 664f865 | 2009-07-28 12:30:57 +0200 | [diff] [blame] | 331 | } else { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 332 | bo->tbo.proposed_placement = |
| 333 | radeon_ttm_flags_from_domain(lobj->rdomain); |
Michel Dänzer | 664f865 | 2009-07-28 12:30:57 +0200 | [diff] [blame] | 334 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 335 | retry: |
| 336 | r = ttm_buffer_object_validate(&bo->tbo, |
| 337 | bo->tbo.proposed_placement, |
| 338 | true, false); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 339 | if (unlikely(r)) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 340 | if (r == -ERESTART) |
| 341 | goto retry; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 342 | return r; |
| 343 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 344 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 345 | lobj->gpu_offset = radeon_bo_gpu_offset(bo); |
| 346 | lobj->tiling_flags = bo->tiling_flags; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 347 | if (fence) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 348 | old_fence = (struct radeon_fence *)bo->tbo.sync_obj; |
| 349 | bo->tbo.sync_obj = radeon_fence_ref(fence); |
| 350 | bo->tbo.sync_obj_arg = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 351 | } |
| 352 | if (old_fence) { |
| 353 | radeon_fence_unref(&old_fence); |
| 354 | } |
| 355 | } |
| 356 | return 0; |
| 357 | } |
| 358 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 359 | void radeon_bo_list_unvalidate(struct list_head *head, void *fence) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 360 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 361 | struct radeon_bo_list *lobj; |
| 362 | struct radeon_fence *old_fence; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 363 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 364 | if (fence) |
| 365 | list_for_each_entry(lobj, head, list) { |
| 366 | old_fence = to_radeon_fence(lobj->bo->tbo.sync_obj); |
| 367 | if (old_fence == fence) { |
| 368 | lobj->bo->tbo.sync_obj = NULL; |
| 369 | radeon_fence_unref(&old_fence); |
| 370 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 371 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 372 | radeon_bo_list_unreserve(head); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 373 | } |
| 374 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 375 | int radeon_bo_fbdev_mmap(struct radeon_bo *bo, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 376 | struct vm_area_struct *vma) |
| 377 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 378 | return ttm_fbdev_mmap(vma, &bo->tbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 379 | } |
| 380 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 381 | static int radeon_bo_get_surface_reg(struct radeon_bo *bo) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 382 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 383 | struct radeon_device *rdev = bo->rdev; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 384 | struct radeon_surface_reg *reg; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 385 | struct radeon_bo *old_object; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 386 | int steal; |
| 387 | int i; |
| 388 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 389 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
| 390 | |
| 391 | if (!bo->tiling_flags) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 392 | return 0; |
| 393 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 394 | if (bo->surface_reg >= 0) { |
| 395 | reg = &rdev->surface_regs[bo->surface_reg]; |
| 396 | i = bo->surface_reg; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 397 | goto out; |
| 398 | } |
| 399 | |
| 400 | steal = -1; |
| 401 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
| 402 | |
| 403 | reg = &rdev->surface_regs[i]; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 404 | if (!reg->bo) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 405 | break; |
| 406 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 407 | old_object = reg->bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 408 | if (old_object->pin_count == 0) |
| 409 | steal = i; |
| 410 | } |
| 411 | |
| 412 | /* if we are all out */ |
| 413 | if (i == RADEON_GEM_MAX_SURFACES) { |
| 414 | if (steal == -1) |
| 415 | return -ENOMEM; |
| 416 | /* find someone with a surface reg and nuke their BO */ |
| 417 | reg = &rdev->surface_regs[steal]; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 418 | old_object = reg->bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 419 | /* blow away the mapping */ |
| 420 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 421 | ttm_bo_unmap_virtual(&old_object->tbo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 422 | old_object->surface_reg = -1; |
| 423 | i = steal; |
| 424 | } |
| 425 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 426 | bo->surface_reg = i; |
| 427 | reg->bo = bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 428 | |
| 429 | out: |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 430 | radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, |
| 431 | bo->tbo.mem.mm_node->start << PAGE_SHIFT, |
| 432 | bo->tbo.num_pages << PAGE_SHIFT); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 433 | return 0; |
| 434 | } |
| 435 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 436 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 437 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 438 | struct radeon_device *rdev = bo->rdev; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 439 | struct radeon_surface_reg *reg; |
| 440 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 441 | if (bo->surface_reg == -1) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 442 | return; |
| 443 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 444 | reg = &rdev->surface_regs[bo->surface_reg]; |
| 445 | radeon_clear_surface_reg(rdev, bo->surface_reg); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 446 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 447 | reg->bo = NULL; |
| 448 | bo->surface_reg = -1; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 449 | } |
| 450 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 451 | int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
| 452 | uint32_t tiling_flags, uint32_t pitch) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 453 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 454 | int r; |
| 455 | |
| 456 | r = radeon_bo_reserve(bo, false); |
| 457 | if (unlikely(r != 0)) |
| 458 | return r; |
| 459 | bo->tiling_flags = tiling_flags; |
| 460 | bo->pitch = pitch; |
| 461 | radeon_bo_unreserve(bo); |
| 462 | return 0; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 463 | } |
| 464 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 465 | void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
| 466 | uint32_t *tiling_flags, |
| 467 | uint32_t *pitch) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 468 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 469 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 470 | if (tiling_flags) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 471 | *tiling_flags = bo->tiling_flags; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 472 | if (pitch) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 473 | *pitch = bo->pitch; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 474 | } |
| 475 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 476 | int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
| 477 | bool force_drop) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 478 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 479 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
| 480 | |
| 481 | if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 482 | return 0; |
| 483 | |
| 484 | if (force_drop) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 485 | radeon_bo_clear_surface_reg(bo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 486 | return 0; |
| 487 | } |
| 488 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 489 | if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 490 | if (!has_moved) |
| 491 | return 0; |
| 492 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 493 | if (bo->surface_reg >= 0) |
| 494 | radeon_bo_clear_surface_reg(bo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 495 | return 0; |
| 496 | } |
| 497 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 498 | if ((bo->surface_reg >= 0) && !has_moved) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 499 | return 0; |
| 500 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 501 | return radeon_bo_get_surface_reg(bo); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 502 | } |
| 503 | |
| 504 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 505 | struct ttm_mem_reg *mem) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 506 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 507 | struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); |
| 508 | radeon_bo_check_tiling(rbo, 0, 1); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 509 | } |
| 510 | |
| 511 | void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) |
| 512 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 513 | struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); |
| 514 | radeon_bo_check_tiling(rbo, 0, 0); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 515 | } |