blob: bec4943848257f08a4683c66f72354dca7622d3c [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <linux/list.h>
33#include <drm/drmP.h>
34#include "radeon_drm.h"
35#include "radeon.h"
36
Jerome Glisse771fe6b2009-06-05 14:42:42 +020037
38int radeon_ttm_init(struct radeon_device *rdev);
39void radeon_ttm_fini(struct radeon_device *rdev);
Jerome Glisse4c788672009-11-20 14:29:23 +010040static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020041
42/*
43 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
44 * function are calling it.
45 */
46
Jerome Glisse4c788672009-11-20 14:29:23 +010047static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020048{
Jerome Glisse4c788672009-11-20 14:29:23 +010049 struct radeon_bo *bo;
50
51 bo = container_of(tbo, struct radeon_bo, tbo);
52 mutex_lock(&bo->rdev->gem.mutex);
53 list_del_init(&bo->list);
54 mutex_unlock(&bo->rdev->gem.mutex);
55 radeon_bo_clear_surface_reg(bo);
56 kfree(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020057}
58
Jerome Glisse4c788672009-11-20 14:29:23 +010059static inline u32 radeon_ttm_flags_from_domain(u32 domain)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020060{
Jerome Glisse4c788672009-11-20 14:29:23 +010061 u32 flags = 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020062
Jerome Glisse771fe6b2009-06-05 14:42:42 +020063 if (domain & RADEON_GEM_DOMAIN_VRAM) {
Michel Dänzer664f8652009-07-28 12:30:57 +020064 flags |= TTM_PL_FLAG_VRAM | TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020065 }
66 if (domain & RADEON_GEM_DOMAIN_GTT) {
Jerome Glisse985fe842009-07-29 18:55:53 +020067 flags |= TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020068 }
69 if (domain & RADEON_GEM_DOMAIN_CPU) {
Michel Dänzer664f8652009-07-28 12:30:57 +020070 flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020071 }
72 if (!flags) {
Michel Dänzer664f8652009-07-28 12:30:57 +020073 flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020074 }
75 return flags;
76}
77
Jerome Glisse4c788672009-11-20 14:29:23 +010078int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
79 unsigned long size, bool kernel, u32 domain,
80 struct radeon_bo **bo_ptr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020081{
Jerome Glisse4c788672009-11-20 14:29:23 +010082 struct radeon_bo *bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020083 enum ttm_bo_type type;
Jerome Glisse4c788672009-11-20 14:29:23 +010084 u32 flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020085 int r;
86
87 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
88 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
89 }
90 if (kernel) {
91 type = ttm_bo_type_kernel;
92 } else {
93 type = ttm_bo_type_device;
94 }
Jerome Glisse4c788672009-11-20 14:29:23 +010095 *bo_ptr = NULL;
96 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
97 if (bo == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020098 return -ENOMEM;
Jerome Glisse4c788672009-11-20 14:29:23 +010099 bo->rdev = rdev;
100 bo->gobj = gobj;
101 bo->surface_reg = -1;
102 INIT_LIST_HEAD(&bo->list);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200103
Jerome Glisse4c788672009-11-20 14:29:23 +0100104 flags = radeon_ttm_flags_from_domain(domain);
105retry:
106 r = ttm_buffer_object_init(&rdev->mman.bdev, &bo->tbo, size, type,
107 flags, 0, 0, true, NULL, size,
108 &radeon_ttm_bo_destroy);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200109 if (unlikely(r != 0)) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100110 if (r == -ERESTART)
111 goto retry;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200112 /* ttm call radeon_ttm_object_object_destroy if error happen */
Jerome Glisse4c788672009-11-20 14:29:23 +0100113 dev_err(rdev->dev, "object_init failed for (%ld, 0x%08X)\n",
114 size, flags);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200115 return r;
116 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100117 *bo_ptr = bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200118 if (gobj) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100119 mutex_lock(&bo->rdev->gem.mutex);
120 list_add_tail(&bo->list, &rdev->gem.objects);
121 mutex_unlock(&bo->rdev->gem.mutex);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200122 }
123 return 0;
124}
125
Jerome Glisse4c788672009-11-20 14:29:23 +0100126int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200127{
Jerome Glisse4c788672009-11-20 14:29:23 +0100128 bool is_iomem;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200129 int r;
130
Jerome Glisse4c788672009-11-20 14:29:23 +0100131 if (bo->kptr) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200132 if (ptr) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100133 *ptr = bo->kptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200134 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200135 return 0;
136 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100137 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200138 if (r) {
139 return r;
140 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100141 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200142 if (ptr) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100143 *ptr = bo->kptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200144 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100145 radeon_bo_check_tiling(bo, 0, 0);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200146 return 0;
147}
148
Jerome Glisse4c788672009-11-20 14:29:23 +0100149void radeon_bo_kunmap(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200150{
Jerome Glisse4c788672009-11-20 14:29:23 +0100151 if (bo->kptr == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200152 return;
Jerome Glisse4c788672009-11-20 14:29:23 +0100153 bo->kptr = NULL;
154 radeon_bo_check_tiling(bo, 0, 0);
155 ttm_bo_kunmap(&bo->kmap);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200156}
157
Jerome Glisse4c788672009-11-20 14:29:23 +0100158void radeon_bo_unref(struct radeon_bo **bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200159{
Jerome Glisse4c788672009-11-20 14:29:23 +0100160 struct ttm_buffer_object *tbo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200161
Jerome Glisse4c788672009-11-20 14:29:23 +0100162 if ((*bo) == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200163 return;
Jerome Glisse4c788672009-11-20 14:29:23 +0100164 tbo = &((*bo)->tbo);
165 ttm_bo_unref(&tbo);
166 if (tbo == NULL)
167 *bo = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200168}
169
Jerome Glisse4c788672009-11-20 14:29:23 +0100170int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200171{
Jerome Glisse4c788672009-11-20 14:29:23 +0100172 u32 flags;
173 u32 tmp;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200174 int r;
175
Jerome Glisse4c788672009-11-20 14:29:23 +0100176 flags = radeon_ttm_flags_from_domain(domain);
177 if (bo->pin_count) {
178 bo->pin_count++;
179 if (gpu_addr)
180 *gpu_addr = radeon_bo_gpu_offset(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200181 return 0;
182 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100183 tmp = bo->tbo.mem.placement;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200184 ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM);
Jerome Glisse4c788672009-11-20 14:29:23 +0100185 bo->tbo.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT |
186 TTM_PL_MASK_CACHING;
187retry:
188 r = ttm_buffer_object_validate(&bo->tbo, bo->tbo.proposed_placement,
189 true, false);
190 if (likely(r == 0)) {
191 bo->pin_count = 1;
192 if (gpu_addr != NULL)
193 *gpu_addr = radeon_bo_gpu_offset(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200194 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200195 if (unlikely(r != 0)) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100196 if (r == -ERESTART)
197 goto retry;
198 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200199 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200200 return r;
201}
202
Jerome Glisse4c788672009-11-20 14:29:23 +0100203int radeon_bo_unpin(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200204{
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200205 int r;
206
Jerome Glisse4c788672009-11-20 14:29:23 +0100207 if (!bo->pin_count) {
208 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
209 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200210 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100211 bo->pin_count--;
212 if (bo->pin_count)
213 return 0;
214 bo->tbo.proposed_placement = bo->tbo.mem.placement &
215 ~TTM_PL_FLAG_NO_EVICT;
216retry:
217 r = ttm_buffer_object_validate(&bo->tbo, bo->tbo.proposed_placement,
218 true, false);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200219 if (unlikely(r != 0)) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100220 if (r == -ERESTART)
221 goto retry;
222 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200223 return r;
224 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100225 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200226}
227
Jerome Glisse4c788672009-11-20 14:29:23 +0100228int radeon_bo_evict_vram(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200229{
230 if (rdev->flags & RADEON_IS_IGP) {
231 /* Useless to evict on IGP chips */
232 return 0;
233 }
234 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
235}
236
Jerome Glisse4c788672009-11-20 14:29:23 +0100237void radeon_bo_force_delete(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200238{
Jerome Glisse4c788672009-11-20 14:29:23 +0100239 struct radeon_bo *bo, *n;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200240 struct drm_gem_object *gobj;
241
242 if (list_empty(&rdev->gem.objects)) {
243 return;
244 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100245 dev_err(rdev->dev, "Userspace still has active objects !\n");
246 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200247 mutex_lock(&rdev->ddev->struct_mutex);
Jerome Glisse4c788672009-11-20 14:29:23 +0100248 gobj = bo->gobj;
249 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
250 gobj, bo, (unsigned long)gobj->size,
251 *((unsigned long *)&gobj->refcount));
252 mutex_lock(&bo->rdev->gem.mutex);
253 list_del_init(&bo->list);
254 mutex_unlock(&bo->rdev->gem.mutex);
255 radeon_bo_unref(&bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200256 gobj->driver_private = NULL;
257 drm_gem_object_unreference(gobj);
258 mutex_unlock(&rdev->ddev->struct_mutex);
259 }
260}
261
Jerome Glisse4c788672009-11-20 14:29:23 +0100262int radeon_bo_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200263{
Jerome Glissea4d68272009-09-11 13:00:43 +0200264 /* Add an MTRR for the VRAM */
265 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
266 MTRR_TYPE_WRCOMB, 1);
267 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
268 rdev->mc.mc_vram_size >> 20,
269 (unsigned long long)rdev->mc.aper_size >> 20);
270 DRM_INFO("RAM width %dbits %cDR\n",
271 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200272 return radeon_ttm_init(rdev);
273}
274
Jerome Glisse4c788672009-11-20 14:29:23 +0100275void radeon_bo_fini(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200276{
277 radeon_ttm_fini(rdev);
278}
279
Jerome Glisse4c788672009-11-20 14:29:23 +0100280void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
281 struct list_head *head)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200282{
283 if (lobj->wdomain) {
284 list_add(&lobj->list, head);
285 } else {
286 list_add_tail(&lobj->list, head);
287 }
288}
289
Jerome Glisse4c788672009-11-20 14:29:23 +0100290int radeon_bo_list_reserve(struct list_head *head)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200291{
Jerome Glisse4c788672009-11-20 14:29:23 +0100292 struct radeon_bo_list *lobj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200293 int r;
294
Dave Airlie9d8401f2009-10-08 09:28:19 +1000295 list_for_each_entry(lobj, head, list){
Jerome Glisse4c788672009-11-20 14:29:23 +0100296 r = radeon_bo_reserve(lobj->bo, false);
297 if (unlikely(r != 0))
298 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200299 }
300 return 0;
301}
302
Jerome Glisse4c788672009-11-20 14:29:23 +0100303void radeon_bo_list_unreserve(struct list_head *head)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200304{
Jerome Glisse4c788672009-11-20 14:29:23 +0100305 struct radeon_bo_list *lobj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200306
Dave Airlie9d8401f2009-10-08 09:28:19 +1000307 list_for_each_entry(lobj, head, list) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100308 /* only unreserve object we successfully reserved */
309 if (radeon_bo_is_reserved(lobj->bo))
310 radeon_bo_unreserve(lobj->bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200311 }
312}
313
Jerome Glisse4c788672009-11-20 14:29:23 +0100314int radeon_bo_list_validate(struct list_head *head, void *fence)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200315{
Jerome Glisse4c788672009-11-20 14:29:23 +0100316 struct radeon_bo_list *lobj;
317 struct radeon_bo *bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200318 struct radeon_fence *old_fence = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200319 int r;
320
Jerome Glisse4c788672009-11-20 14:29:23 +0100321 r = radeon_bo_list_reserve(head);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200322 if (unlikely(r != 0)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200323 return r;
324 }
Dave Airlie9d8401f2009-10-08 09:28:19 +1000325 list_for_each_entry(lobj, head, list) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100326 bo = lobj->bo;
327 if (!bo->pin_count) {
Michel Dänzer664f8652009-07-28 12:30:57 +0200328 if (lobj->wdomain) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100329 bo->tbo.proposed_placement =
330 radeon_ttm_flags_from_domain(lobj->wdomain);
Michel Dänzer664f8652009-07-28 12:30:57 +0200331 } else {
Jerome Glisse4c788672009-11-20 14:29:23 +0100332 bo->tbo.proposed_placement =
333 radeon_ttm_flags_from_domain(lobj->rdomain);
Michel Dänzer664f8652009-07-28 12:30:57 +0200334 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100335retry:
336 r = ttm_buffer_object_validate(&bo->tbo,
337 bo->tbo.proposed_placement,
338 true, false);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200339 if (unlikely(r)) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100340 if (r == -ERESTART)
341 goto retry;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200342 return r;
343 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200344 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100345 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
346 lobj->tiling_flags = bo->tiling_flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200347 if (fence) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100348 old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
349 bo->tbo.sync_obj = radeon_fence_ref(fence);
350 bo->tbo.sync_obj_arg = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200351 }
352 if (old_fence) {
353 radeon_fence_unref(&old_fence);
354 }
355 }
356 return 0;
357}
358
Jerome Glisse4c788672009-11-20 14:29:23 +0100359void radeon_bo_list_unvalidate(struct list_head *head, void *fence)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200360{
Jerome Glisse4c788672009-11-20 14:29:23 +0100361 struct radeon_bo_list *lobj;
362 struct radeon_fence *old_fence;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200363
Jerome Glisse4c788672009-11-20 14:29:23 +0100364 if (fence)
365 list_for_each_entry(lobj, head, list) {
366 old_fence = to_radeon_fence(lobj->bo->tbo.sync_obj);
367 if (old_fence == fence) {
368 lobj->bo->tbo.sync_obj = NULL;
369 radeon_fence_unref(&old_fence);
370 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200371 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100372 radeon_bo_list_unreserve(head);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200373}
374
Jerome Glisse4c788672009-11-20 14:29:23 +0100375int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200376 struct vm_area_struct *vma)
377{
Jerome Glisse4c788672009-11-20 14:29:23 +0100378 return ttm_fbdev_mmap(vma, &bo->tbo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200379}
380
Jerome Glisse4c788672009-11-20 14:29:23 +0100381static int radeon_bo_get_surface_reg(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200382{
Jerome Glisse4c788672009-11-20 14:29:23 +0100383 struct radeon_device *rdev = bo->rdev;
Dave Airliee024e112009-06-24 09:48:08 +1000384 struct radeon_surface_reg *reg;
Jerome Glisse4c788672009-11-20 14:29:23 +0100385 struct radeon_bo *old_object;
Dave Airliee024e112009-06-24 09:48:08 +1000386 int steal;
387 int i;
388
Jerome Glisse4c788672009-11-20 14:29:23 +0100389 BUG_ON(!atomic_read(&bo->tbo.reserved));
390
391 if (!bo->tiling_flags)
Dave Airliee024e112009-06-24 09:48:08 +1000392 return 0;
393
Jerome Glisse4c788672009-11-20 14:29:23 +0100394 if (bo->surface_reg >= 0) {
395 reg = &rdev->surface_regs[bo->surface_reg];
396 i = bo->surface_reg;
Dave Airliee024e112009-06-24 09:48:08 +1000397 goto out;
398 }
399
400 steal = -1;
401 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
402
403 reg = &rdev->surface_regs[i];
Jerome Glisse4c788672009-11-20 14:29:23 +0100404 if (!reg->bo)
Dave Airliee024e112009-06-24 09:48:08 +1000405 break;
406
Jerome Glisse4c788672009-11-20 14:29:23 +0100407 old_object = reg->bo;
Dave Airliee024e112009-06-24 09:48:08 +1000408 if (old_object->pin_count == 0)
409 steal = i;
410 }
411
412 /* if we are all out */
413 if (i == RADEON_GEM_MAX_SURFACES) {
414 if (steal == -1)
415 return -ENOMEM;
416 /* find someone with a surface reg and nuke their BO */
417 reg = &rdev->surface_regs[steal];
Jerome Glisse4c788672009-11-20 14:29:23 +0100418 old_object = reg->bo;
Dave Airliee024e112009-06-24 09:48:08 +1000419 /* blow away the mapping */
420 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
Jerome Glisse4c788672009-11-20 14:29:23 +0100421 ttm_bo_unmap_virtual(&old_object->tbo);
Dave Airliee024e112009-06-24 09:48:08 +1000422 old_object->surface_reg = -1;
423 i = steal;
424 }
425
Jerome Glisse4c788672009-11-20 14:29:23 +0100426 bo->surface_reg = i;
427 reg->bo = bo;
Dave Airliee024e112009-06-24 09:48:08 +1000428
429out:
Jerome Glisse4c788672009-11-20 14:29:23 +0100430 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
431 bo->tbo.mem.mm_node->start << PAGE_SHIFT,
432 bo->tbo.num_pages << PAGE_SHIFT);
Dave Airliee024e112009-06-24 09:48:08 +1000433 return 0;
434}
435
Jerome Glisse4c788672009-11-20 14:29:23 +0100436static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
Dave Airliee024e112009-06-24 09:48:08 +1000437{
Jerome Glisse4c788672009-11-20 14:29:23 +0100438 struct radeon_device *rdev = bo->rdev;
Dave Airliee024e112009-06-24 09:48:08 +1000439 struct radeon_surface_reg *reg;
440
Jerome Glisse4c788672009-11-20 14:29:23 +0100441 if (bo->surface_reg == -1)
Dave Airliee024e112009-06-24 09:48:08 +1000442 return;
443
Jerome Glisse4c788672009-11-20 14:29:23 +0100444 reg = &rdev->surface_regs[bo->surface_reg];
445 radeon_clear_surface_reg(rdev, bo->surface_reg);
Dave Airliee024e112009-06-24 09:48:08 +1000446
Jerome Glisse4c788672009-11-20 14:29:23 +0100447 reg->bo = NULL;
448 bo->surface_reg = -1;
Dave Airliee024e112009-06-24 09:48:08 +1000449}
450
Jerome Glisse4c788672009-11-20 14:29:23 +0100451int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
452 uint32_t tiling_flags, uint32_t pitch)
Dave Airliee024e112009-06-24 09:48:08 +1000453{
Jerome Glisse4c788672009-11-20 14:29:23 +0100454 int r;
455
456 r = radeon_bo_reserve(bo, false);
457 if (unlikely(r != 0))
458 return r;
459 bo->tiling_flags = tiling_flags;
460 bo->pitch = pitch;
461 radeon_bo_unreserve(bo);
462 return 0;
Dave Airliee024e112009-06-24 09:48:08 +1000463}
464
Jerome Glisse4c788672009-11-20 14:29:23 +0100465void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
466 uint32_t *tiling_flags,
467 uint32_t *pitch)
Dave Airliee024e112009-06-24 09:48:08 +1000468{
Jerome Glisse4c788672009-11-20 14:29:23 +0100469 BUG_ON(!atomic_read(&bo->tbo.reserved));
Dave Airliee024e112009-06-24 09:48:08 +1000470 if (tiling_flags)
Jerome Glisse4c788672009-11-20 14:29:23 +0100471 *tiling_flags = bo->tiling_flags;
Dave Airliee024e112009-06-24 09:48:08 +1000472 if (pitch)
Jerome Glisse4c788672009-11-20 14:29:23 +0100473 *pitch = bo->pitch;
Dave Airliee024e112009-06-24 09:48:08 +1000474}
475
Jerome Glisse4c788672009-11-20 14:29:23 +0100476int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
477 bool force_drop)
Dave Airliee024e112009-06-24 09:48:08 +1000478{
Jerome Glisse4c788672009-11-20 14:29:23 +0100479 BUG_ON(!atomic_read(&bo->tbo.reserved));
480
481 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
Dave Airliee024e112009-06-24 09:48:08 +1000482 return 0;
483
484 if (force_drop) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100485 radeon_bo_clear_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000486 return 0;
487 }
488
Jerome Glisse4c788672009-11-20 14:29:23 +0100489 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
Dave Airliee024e112009-06-24 09:48:08 +1000490 if (!has_moved)
491 return 0;
492
Jerome Glisse4c788672009-11-20 14:29:23 +0100493 if (bo->surface_reg >= 0)
494 radeon_bo_clear_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000495 return 0;
496 }
497
Jerome Glisse4c788672009-11-20 14:29:23 +0100498 if ((bo->surface_reg >= 0) && !has_moved)
Dave Airliee024e112009-06-24 09:48:08 +1000499 return 0;
500
Jerome Glisse4c788672009-11-20 14:29:23 +0100501 return radeon_bo_get_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000502}
503
504void radeon_bo_move_notify(struct ttm_buffer_object *bo,
Jerome Glisse4c788672009-11-20 14:29:23 +0100505 struct ttm_mem_reg *mem)
Dave Airliee024e112009-06-24 09:48:08 +1000506{
Jerome Glisse4c788672009-11-20 14:29:23 +0100507 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
508 radeon_bo_check_tiling(rbo, 0, 1);
Dave Airliee024e112009-06-24 09:48:08 +1000509}
510
511void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
512{
Jerome Glisse4c788672009-11-20 14:29:23 +0100513 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
514 radeon_bo_check_tiling(rbo, 0, 0);
Dave Airliee024e112009-06-24 09:48:08 +1000515}