blob: 26bdf2ca59d759cd581a6a301660c88f0a0364f1 [file] [log] [blame]
Dave Airlie414ed532005-08-16 20:43:16 +10001/* r300_cmdbuf.c -- Command buffer emission for R300 -*- linux-c -*-
2 *
3 * Copyright (C) The Weather Channel, Inc. 2002.
4 * Copyright (C) 2004 Nicolai Haehnle.
5 * All Rights Reserved.
6 *
7 * The Weather Channel (TM) funded Tungsten Graphics to develop the
8 * initial release of the Radeon 8500 driver under the XFree86 license.
9 * This notice must be preserved.
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the next
19 * paragraph) shall be included in all copies or substantial portions of the
20 * Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
26 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
27 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 *
30 * Authors:
31 * Nicolai Haehnle <prefect_@gmx.net>
32 */
33
34#include "drmP.h"
35#include "drm.h"
36#include "radeon_drm.h"
37#include "radeon_drv.h"
38#include "r300_reg.h"
39
Dave Airlie414ed532005-08-16 20:43:16 +100040#define R300_SIMULTANEOUS_CLIPRECTS 4
41
42/* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects
43 */
44static const int r300_cliprect_cntl[4] = {
45 0xAAAA,
46 0xEEEE,
47 0xFEFE,
48 0xFFFE
49};
50
Dave Airlie414ed532005-08-16 20:43:16 +100051/**
52 * Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command
53 * buffer, starting with index n.
54 */
Dave Airlied985c102006-01-02 21:32:48 +110055static int r300_emit_cliprects(drm_radeon_private_t *dev_priv,
56 drm_radeon_kcmd_buffer_t *cmdbuf, int n)
Dave Airlie414ed532005-08-16 20:43:16 +100057{
58 drm_clip_rect_t box;
59 int nr;
60 int i;
61 RING_LOCALS;
62
63 nr = cmdbuf->nbox - n;
64 if (nr > R300_SIMULTANEOUS_CLIPRECTS)
65 nr = R300_SIMULTANEOUS_CLIPRECTS;
66
67 DRM_DEBUG("%i cliprects\n", nr);
68
69 if (nr) {
Dave Airlieb5e89ed2005-09-25 14:28:13 +100070 BEGIN_RING(6 + nr * 2);
71 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1));
Dave Airlie414ed532005-08-16 20:43:16 +100072
Dave Airlieb5e89ed2005-09-25 14:28:13 +100073 for (i = 0; i < nr; ++i) {
74 if (DRM_COPY_FROM_USER_UNCHECKED
75 (&box, &cmdbuf->boxes[n + i], sizeof(box))) {
Dave Airlie414ed532005-08-16 20:43:16 +100076 DRM_ERROR("copy cliprect faulted\n");
77 return DRM_ERR(EFAULT);
78 }
79
Dave Airlieb5e89ed2005-09-25 14:28:13 +100080 box.x1 =
81 (box.x1 +
82 R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
83 box.y1 =
84 (box.y1 +
85 R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
86 box.x2 =
87 (box.x2 +
88 R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
89 box.y2 =
90 (box.y2 +
91 R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
Dave Airlie414ed532005-08-16 20:43:16 +100092
93 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
Dave Airlieb5e89ed2005-09-25 14:28:13 +100094 (box.y1 << R300_CLIPRECT_Y_SHIFT));
Dave Airlie414ed532005-08-16 20:43:16 +100095 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
Dave Airlieb5e89ed2005-09-25 14:28:13 +100096 (box.y2 << R300_CLIPRECT_Y_SHIFT));
Dave Airlie414ed532005-08-16 20:43:16 +100097 }
98
Dave Airlieb5e89ed2005-09-25 14:28:13 +100099 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr - 1]);
Dave Airlie414ed532005-08-16 20:43:16 +1000100
101 /* TODO/SECURITY: Force scissors to a safe value, otherwise the
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000102 * client might be able to trample over memory.
103 * The impact should be very limited, but I'd rather be safe than
104 * sorry.
105 */
106 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1));
107 OUT_RING(0);
108 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK);
Dave Airlie414ed532005-08-16 20:43:16 +1000109 ADVANCE_RING();
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000110 } else {
Dave Airlie414ed532005-08-16 20:43:16 +1000111 /* Why we allow zero cliprect rendering:
112 * There are some commands in a command buffer that must be submitted
113 * even when there are no cliprects, e.g. DMA buffer discard
114 * or state setting (though state setting could be avoided by
115 * simulating a loss of context).
116 *
117 * Now since the cmdbuf interface is so chaotic right now (and is
118 * bound to remain that way for a bit until things settle down),
119 * it is basically impossible to filter out the commands that are
120 * necessary and those that aren't.
121 *
122 * So I choose the safe way and don't do any filtering at all;
123 * instead, I simply set up the engine so that all rendering
124 * can't produce any fragments.
125 */
126 BEGIN_RING(2);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000127 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, 0);
Dave Airlie414ed532005-08-16 20:43:16 +1000128 ADVANCE_RING();
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000129 }
Dave Airlie414ed532005-08-16 20:43:16 +1000130
131 return 0;
132}
133
Dave Airlieb3a83632005-09-30 18:37:36 +1000134static u8 r300_reg_flags[0x10000 >> 2];
Dave Airlie414ed532005-08-16 20:43:16 +1000135
136void r300_init_reg_flags(void)
137{
138 int i;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000139 memset(r300_reg_flags, 0, 0x10000 >> 2);
140#define ADD_RANGE_MARK(reg, count,mark) \
Dave Airlie414ed532005-08-16 20:43:16 +1000141 for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\
142 r300_reg_flags[i]|=(mark);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000143
144#define MARK_SAFE 1
145#define MARK_CHECK_OFFSET 2
146
147#define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE)
Dave Airlie414ed532005-08-16 20:43:16 +1000148
149 /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */
150 ADD_RANGE(R300_SE_VPORT_XSCALE, 6);
151 ADD_RANGE(0x2080, 1);
152 ADD_RANGE(R300_SE_VTE_CNTL, 2);
153 ADD_RANGE(0x2134, 2);
154 ADD_RANGE(0x2140, 1);
155 ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2);
156 ADD_RANGE(0x21DC, 1);
157 ADD_RANGE(0x221C, 1);
158 ADD_RANGE(0x2220, 4);
159 ADD_RANGE(0x2288, 1);
160 ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2);
161 ADD_RANGE(R300_VAP_PVS_CNTL_1, 3);
162 ADD_RANGE(R300_GB_ENABLE, 1);
163 ADD_RANGE(R300_GB_MSPOS0, 5);
Dave Airlie4e5e2e22006-02-18 15:51:35 +1100164 ADD_RANGE(R300_TX_CNTL, 1);
Dave Airlie414ed532005-08-16 20:43:16 +1000165 ADD_RANGE(R300_TX_ENABLE, 1);
166 ADD_RANGE(0x4200, 4);
167 ADD_RANGE(0x4214, 1);
168 ADD_RANGE(R300_RE_POINTSIZE, 1);
169 ADD_RANGE(0x4230, 3);
170 ADD_RANGE(R300_RE_LINE_CNT, 1);
171 ADD_RANGE(0x4238, 1);
172 ADD_RANGE(0x4260, 3);
173 ADD_RANGE(0x4274, 4);
174 ADD_RANGE(0x4288, 5);
175 ADD_RANGE(0x42A0, 1);
176 ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4);
177 ADD_RANGE(0x42B4, 1);
178 ADD_RANGE(R300_RE_CULL_CNTL, 1);
179 ADD_RANGE(0x42C0, 2);
180 ADD_RANGE(R300_RS_CNTL_0, 2);
181 ADD_RANGE(R300_RS_INTERP_0, 8);
182 ADD_RANGE(R300_RS_ROUTE_0, 8);
183 ADD_RANGE(0x43A4, 2);
184 ADD_RANGE(0x43E8, 1);
185 ADD_RANGE(R300_PFS_CNTL_0, 3);
186 ADD_RANGE(R300_PFS_NODE_0, 4);
187 ADD_RANGE(R300_PFS_TEXI_0, 64);
188 ADD_RANGE(0x46A4, 5);
189 ADD_RANGE(R300_PFS_INSTR0_0, 64);
190 ADD_RANGE(R300_PFS_INSTR1_0, 64);
191 ADD_RANGE(R300_PFS_INSTR2_0, 64);
192 ADD_RANGE(R300_PFS_INSTR3_0, 64);
193 ADD_RANGE(0x4BC0, 1);
194 ADD_RANGE(0x4BC8, 3);
195 ADD_RANGE(R300_PP_ALPHA_TEST, 2);
196 ADD_RANGE(0x4BD8, 1);
197 ADD_RANGE(R300_PFS_PARAM_0_X, 64);
198 ADD_RANGE(0x4E00, 1);
199 ADD_RANGE(R300_RB3D_CBLEND, 2);
200 ADD_RANGE(R300_RB3D_COLORMASK, 1);
201 ADD_RANGE(0x4E10, 3);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000202 ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */
Dave Airlie414ed532005-08-16 20:43:16 +1000203 ADD_RANGE(R300_RB3D_COLORPITCH0, 1);
204 ADD_RANGE(0x4E50, 9);
205 ADD_RANGE(0x4E88, 1);
206 ADD_RANGE(0x4EA0, 2);
207 ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
208 ADD_RANGE(0x4F10, 4);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000209 ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
210 ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
Dave Airlie414ed532005-08-16 20:43:16 +1000211 ADD_RANGE(0x4F28, 1);
212 ADD_RANGE(0x4F30, 2);
213 ADD_RANGE(0x4F44, 1);
214 ADD_RANGE(0x4F54, 1);
215
216 ADD_RANGE(R300_TX_FILTER_0, 16);
Dave Airlie45f17102006-03-19 19:12:10 +1100217 ADD_RANGE(R300_TX_FILTER1_0, 16);
Dave Airlie414ed532005-08-16 20:43:16 +1000218 ADD_RANGE(R300_TX_SIZE_0, 16);
219 ADD_RANGE(R300_TX_FORMAT_0, 16);
Dave Airlied985c102006-01-02 21:32:48 +1100220 ADD_RANGE(R300_TX_PITCH_0, 16);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000221 /* Texture offset is dangerous and needs more checking */
Dave Airlie414ed532005-08-16 20:43:16 +1000222 ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET);
Dave Airlie45f17102006-03-19 19:12:10 +1100223 ADD_RANGE(R300_TX_CHROMA_KEY_0, 16);
Dave Airlie414ed532005-08-16 20:43:16 +1000224 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
225
226 /* Sporadic registers used as primitives are emitted */
227 ADD_RANGE(0x4f18, 1);
228 ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
229 ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
230 ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
231
232}
233
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000234static __inline__ int r300_check_range(unsigned reg, int count)
Dave Airlie414ed532005-08-16 20:43:16 +1000235{
236 int i;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000237 if (reg & ~0xffff)
238 return -1;
239 for (i = (reg >> 2); i < (reg >> 2) + count; i++)
240 if (r300_reg_flags[i] != MARK_SAFE)
241 return 1;
Dave Airlie414ed532005-08-16 20:43:16 +1000242 return 0;
243}
244
Dave Airlied5ea7022006-03-19 19:37:55 +1100245/*
246 * we expect offsets passed to the framebuffer to be either within video
247 * memory or within AGP space
248 */
Dave Airlied985c102006-01-02 21:32:48 +1100249static __inline__ int r300_check_offset(drm_radeon_private_t *dev_priv,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000250 u32 offset)
Dave Airlie414ed532005-08-16 20:43:16 +1000251{
252 /* we realy want to check against end of video aperture
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000253 but this value is not being kept.
254 This code is correct for now (does the same thing as the
255 code that sets MC_FB_LOCATION) in radeon_cp.c */
Dave Airlied5ea7022006-03-19 19:37:55 +1100256 if (offset >= dev_priv->fb_location &&
257 offset < (dev_priv->fb_location + dev_priv->fb_size))
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000258 return 0;
Dave Airlied5ea7022006-03-19 19:37:55 +1100259 if (offset >= dev_priv->gart_vm_start &&
260 offset < (dev_priv->gart_vm_start + dev_priv->gart_size))
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000261 return 0;
Dave Airlie414ed532005-08-16 20:43:16 +1000262 return 1;
263}
264
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000265static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t *
266 dev_priv,
Dave Airlieb3a83632005-09-30 18:37:36 +1000267 drm_radeon_kcmd_buffer_t
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000268 * cmdbuf,
269 drm_r300_cmd_header_t
270 header)
Dave Airlie414ed532005-08-16 20:43:16 +1000271{
272 int reg;
273 int sz;
274 int i;
275 int values[64];
276 RING_LOCALS;
277
278 sz = header.packet0.count;
279 reg = (header.packet0.reghi << 8) | header.packet0.reglo;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000280
281 if ((sz > 64) || (sz < 0)) {
282 DRM_ERROR
283 ("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n",
284 reg, sz);
Dave Airlie414ed532005-08-16 20:43:16 +1000285 return DRM_ERR(EINVAL);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000286 }
287 for (i = 0; i < sz; i++) {
Dave Airlieb3a83632005-09-30 18:37:36 +1000288 values[i] = ((int *)cmdbuf->buf)[i];
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000289 switch (r300_reg_flags[(reg >> 2) + i]) {
Dave Airlie414ed532005-08-16 20:43:16 +1000290 case MARK_SAFE:
291 break;
292 case MARK_CHECK_OFFSET:
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000293 if (r300_check_offset(dev_priv, (u32) values[i])) {
294 DRM_ERROR
295 ("Offset failed range check (reg=%04x sz=%d)\n",
296 reg, sz);
Dave Airlie414ed532005-08-16 20:43:16 +1000297 return DRM_ERR(EINVAL);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000298 }
Dave Airlie414ed532005-08-16 20:43:16 +1000299 break;
300 default:
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000301 DRM_ERROR("Register %04x failed check as flag=%02x\n",
302 reg + i * 4, r300_reg_flags[(reg >> 2) + i]);
Dave Airlie414ed532005-08-16 20:43:16 +1000303 return DRM_ERR(EINVAL);
Dave Airlie414ed532005-08-16 20:43:16 +1000304 }
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000305 }
306
307 BEGIN_RING(1 + sz);
308 OUT_RING(CP_PACKET0(reg, sz - 1));
309 OUT_RING_TABLE(values, sz);
Dave Airlie414ed532005-08-16 20:43:16 +1000310 ADVANCE_RING();
311
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000312 cmdbuf->buf += sz * 4;
313 cmdbuf->bufsz -= sz * 4;
Dave Airlie414ed532005-08-16 20:43:16 +1000314
315 return 0;
316}
317
318/**
319 * Emits a packet0 setting arbitrary registers.
320 * Called by r300_do_cp_cmdbuf.
321 *
322 * Note that checks are performed on contents and addresses of the registers
323 */
Dave Airlied985c102006-01-02 21:32:48 +1100324static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv,
325 drm_radeon_kcmd_buffer_t *cmdbuf,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000326 drm_r300_cmd_header_t header)
Dave Airlie414ed532005-08-16 20:43:16 +1000327{
328 int reg;
329 int sz;
330 RING_LOCALS;
331
332 sz = header.packet0.count;
333 reg = (header.packet0.reghi << 8) | header.packet0.reglo;
334
335 if (!sz)
336 return 0;
337
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000338 if (sz * 4 > cmdbuf->bufsz)
Dave Airlie414ed532005-08-16 20:43:16 +1000339 return DRM_ERR(EINVAL);
Dave Airlie414ed532005-08-16 20:43:16 +1000340
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000341 if (reg + sz * 4 >= 0x10000) {
342 DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg,
343 sz);
344 return DRM_ERR(EINVAL);
345 }
346
347 if (r300_check_range(reg, sz)) {
Dave Airlie414ed532005-08-16 20:43:16 +1000348 /* go and check everything */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000349 return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf,
350 header);
351 }
Dave Airlie414ed532005-08-16 20:43:16 +1000352 /* the rest of the data is safe to emit, whatever the values the user passed */
353
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000354 BEGIN_RING(1 + sz);
355 OUT_RING(CP_PACKET0(reg, sz - 1));
Dave Airlieb3a83632005-09-30 18:37:36 +1000356 OUT_RING_TABLE((int *)cmdbuf->buf, sz);
Dave Airlie414ed532005-08-16 20:43:16 +1000357 ADVANCE_RING();
358
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000359 cmdbuf->buf += sz * 4;
360 cmdbuf->bufsz -= sz * 4;
Dave Airlie414ed532005-08-16 20:43:16 +1000361
362 return 0;
363}
364
Dave Airlie414ed532005-08-16 20:43:16 +1000365/**
366 * Uploads user-supplied vertex program instructions or parameters onto
367 * the graphics card.
368 * Called by r300_do_cp_cmdbuf.
369 */
Dave Airlied985c102006-01-02 21:32:48 +1100370static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv,
371 drm_radeon_kcmd_buffer_t *cmdbuf,
Dave Airlie414ed532005-08-16 20:43:16 +1000372 drm_r300_cmd_header_t header)
373{
374 int sz;
375 int addr;
376 RING_LOCALS;
377
378 sz = header.vpu.count;
379 addr = (header.vpu.adrhi << 8) | header.vpu.adrlo;
380
381 if (!sz)
382 return 0;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000383 if (sz * 16 > cmdbuf->bufsz)
Dave Airlie414ed532005-08-16 20:43:16 +1000384 return DRM_ERR(EINVAL);
385
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000386 BEGIN_RING(5 + sz * 4);
Dave Airlie414ed532005-08-16 20:43:16 +1000387 /* Wait for VAP to come to senses.. */
388 /* there is no need to emit it multiple times, (only once before VAP is programmed,
389 but this optimization is for later */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000390 OUT_RING_REG(R300_VAP_PVS_WAITIDLE, 0);
391 OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
392 OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1));
Dave Airlieb3a83632005-09-30 18:37:36 +1000393 OUT_RING_TABLE((int *)cmdbuf->buf, sz * 4);
Dave Airlie414ed532005-08-16 20:43:16 +1000394
395 ADVANCE_RING();
396
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000397 cmdbuf->buf += sz * 16;
398 cmdbuf->bufsz -= sz * 16;
Dave Airlie414ed532005-08-16 20:43:16 +1000399
400 return 0;
401}
402
Dave Airlie414ed532005-08-16 20:43:16 +1000403/**
404 * Emit a clear packet from userspace.
405 * Called by r300_emit_packet3.
406 */
Dave Airlied985c102006-01-02 21:32:48 +1100407static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv,
408 drm_radeon_kcmd_buffer_t *cmdbuf)
Dave Airlie414ed532005-08-16 20:43:16 +1000409{
410 RING_LOCALS;
411
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000412 if (8 * 4 > cmdbuf->bufsz)
Dave Airlie414ed532005-08-16 20:43:16 +1000413 return DRM_ERR(EINVAL);
414
415 BEGIN_RING(10);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000416 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
417 OUT_RING(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
418 (1 << R300_PRIM_NUM_VERTICES_SHIFT));
Dave Airlieb3a83632005-09-30 18:37:36 +1000419 OUT_RING_TABLE((int *)cmdbuf->buf, 8);
Dave Airlie414ed532005-08-16 20:43:16 +1000420 ADVANCE_RING();
421
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000422 cmdbuf->buf += 8 * 4;
423 cmdbuf->bufsz -= 8 * 4;
Dave Airlie414ed532005-08-16 20:43:16 +1000424
425 return 0;
426}
427
Dave Airlied985c102006-01-02 21:32:48 +1100428static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv,
429 drm_radeon_kcmd_buffer_t *cmdbuf,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000430 u32 header)
Dave Airlie414ed532005-08-16 20:43:16 +1000431{
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000432 int count, i, k;
433#define MAX_ARRAY_PACKET 64
Dave Airlie414ed532005-08-16 20:43:16 +1000434 u32 payload[MAX_ARRAY_PACKET];
435 u32 narrays;
436 RING_LOCALS;
437
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000438 count = (header >> 16) & 0x3fff;
439
440 if ((count + 1) > MAX_ARRAY_PACKET) {
441 DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
442 count);
Dave Airlie414ed532005-08-16 20:43:16 +1000443 return DRM_ERR(EINVAL);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000444 }
445 memset(payload, 0, MAX_ARRAY_PACKET * 4);
446 memcpy(payload, cmdbuf->buf + 4, (count + 1) * 4);
447
Dave Airlie414ed532005-08-16 20:43:16 +1000448 /* carefully check packet contents */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000449
450 narrays = payload[0];
451 k = 0;
452 i = 1;
453 while ((k < narrays) && (i < (count + 1))) {
454 i++; /* skip attribute field */
455 if (r300_check_offset(dev_priv, payload[i])) {
456 DRM_ERROR
457 ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
458 k, i);
Dave Airlie414ed532005-08-16 20:43:16 +1000459 return DRM_ERR(EINVAL);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000460 }
Dave Airlie414ed532005-08-16 20:43:16 +1000461 k++;
462 i++;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000463 if (k == narrays)
464 break;
Dave Airlie414ed532005-08-16 20:43:16 +1000465 /* have one more to process, they come in pairs */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000466 if (r300_check_offset(dev_priv, payload[i])) {
467 DRM_ERROR
468 ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
469 k, i);
Dave Airlie414ed532005-08-16 20:43:16 +1000470 return DRM_ERR(EINVAL);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000471 }
Dave Airlie414ed532005-08-16 20:43:16 +1000472 k++;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000473 i++;
474 }
Dave Airlie414ed532005-08-16 20:43:16 +1000475 /* do the counts match what we expect ? */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000476 if ((k != narrays) || (i != (count + 1))) {
477 DRM_ERROR
478 ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
479 k, i, narrays, count + 1);
Dave Airlie414ed532005-08-16 20:43:16 +1000480 return DRM_ERR(EINVAL);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000481 }
Dave Airlie414ed532005-08-16 20:43:16 +1000482
483 /* all clear, output packet */
484
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000485 BEGIN_RING(count + 2);
Dave Airlie414ed532005-08-16 20:43:16 +1000486 OUT_RING(header);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000487 OUT_RING_TABLE(payload, count + 1);
Dave Airlie414ed532005-08-16 20:43:16 +1000488 ADVANCE_RING();
489
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000490 cmdbuf->buf += (count + 2) * 4;
491 cmdbuf->bufsz -= (count + 2) * 4;
Dave Airlie414ed532005-08-16 20:43:16 +1000492
493 return 0;
494}
Dave Airlied5ea7022006-03-19 19:37:55 +1100495
Dave Airlie4e5e2e22006-02-18 15:51:35 +1100496static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv,
497 drm_radeon_kcmd_buffer_t *cmdbuf)
498{
499 u32 *cmd = (u32 *) cmdbuf->buf;
500 int count, ret;
501 RING_LOCALS;
502
503 count=(cmd[0]>>16) & 0x3fff;
504
505 if (cmd[0] & 0x8000) {
506 u32 offset;
507
508 if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
509 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
510 offset = cmd[2] << 10;
511 ret = r300_check_offset(dev_priv, offset);
Dave Airlie73d72cf2006-02-18 16:30:54 +1100512 if (ret) {
Dave Airlie4e5e2e22006-02-18 15:51:35 +1100513 DRM_ERROR("Invalid bitblt first offset is %08X\n", offset);
514 return DRM_ERR(EINVAL);
515 }
516 }
517
518 if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
519 (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
520 offset = cmd[3] << 10;
521 ret = r300_check_offset(dev_priv, offset);
Dave Airlie73d72cf2006-02-18 16:30:54 +1100522 if (ret) {
Dave Airlie4e5e2e22006-02-18 15:51:35 +1100523 DRM_ERROR("Invalid bitblt second offset is %08X\n", offset);
524 return DRM_ERR(EINVAL);
525 }
526
527 }
528 }
529
530 BEGIN_RING(count+2);
531 OUT_RING(cmd[0]);
532 OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
533 ADVANCE_RING();
534
535 cmdbuf->buf += (count+2)*4;
536 cmdbuf->bufsz -= (count+2)*4;
537
538 return 0;
539}
Dave Airlie414ed532005-08-16 20:43:16 +1000540
Dave Airlied985c102006-01-02 21:32:48 +1100541static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv,
542 drm_radeon_kcmd_buffer_t *cmdbuf)
Dave Airlie414ed532005-08-16 20:43:16 +1000543{
544 u32 header;
545 int count;
546 RING_LOCALS;
547
548 if (4 > cmdbuf->bufsz)
549 return DRM_ERR(EINVAL);
550
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000551 /* Fixme !! This simply emits a packet without much checking.
Dave Airlie414ed532005-08-16 20:43:16 +1000552 We need to be smarter. */
553
554 /* obtain first word - actual packet3 header */
Dave Airlieb3a83632005-09-30 18:37:36 +1000555 header = *(u32 *) cmdbuf->buf;
Dave Airlie414ed532005-08-16 20:43:16 +1000556
557 /* Is it packet 3 ? */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000558 if ((header >> 30) != 0x3) {
Dave Airlie414ed532005-08-16 20:43:16 +1000559 DRM_ERROR("Not a packet3 header (0x%08x)\n", header);
560 return DRM_ERR(EINVAL);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000561 }
Dave Airlie414ed532005-08-16 20:43:16 +1000562
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000563 count = (header >> 16) & 0x3fff;
Dave Airlie414ed532005-08-16 20:43:16 +1000564
565 /* Check again now that we know how much data to expect */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000566 if ((count + 2) * 4 > cmdbuf->bufsz) {
567 DRM_ERROR
568 ("Expected packet3 of length %d but have only %d bytes left\n",
569 (count + 2) * 4, cmdbuf->bufsz);
Dave Airlie414ed532005-08-16 20:43:16 +1000570 return DRM_ERR(EINVAL);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000571 }
Dave Airlie414ed532005-08-16 20:43:16 +1000572
573 /* Is it a packet type we know about ? */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000574 switch (header & 0xff00) {
575 case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */
Dave Airlie414ed532005-08-16 20:43:16 +1000576 return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header);
577
Dave Airlie4e5e2e22006-02-18 15:51:35 +1100578 case RADEON_CNTL_BITBLT_MULTI:
579 return r300_emit_bitblt_multi(dev_priv, cmdbuf);
580
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000581 case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */
582 case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */
583 case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */
584 case RADEON_CP_INDX_BUFFER: /* DRAW_INDX_2 without INDX_BUFFER seems to lock up the gpu */
Dave Airlie414ed532005-08-16 20:43:16 +1000585 case RADEON_WAIT_FOR_IDLE:
586 case RADEON_CP_NOP:
587 /* these packets are safe */
588 break;
589 default:
590 DRM_ERROR("Unknown packet3 header (0x%08x)\n", header);
591 return DRM_ERR(EINVAL);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000592 }
Dave Airlie414ed532005-08-16 20:43:16 +1000593
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000594 BEGIN_RING(count + 2);
Dave Airlie414ed532005-08-16 20:43:16 +1000595 OUT_RING(header);
Dave Airlieb3a83632005-09-30 18:37:36 +1000596 OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
Dave Airlie414ed532005-08-16 20:43:16 +1000597 ADVANCE_RING();
598
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000599 cmdbuf->buf += (count + 2) * 4;
600 cmdbuf->bufsz -= (count + 2) * 4;
Dave Airlie414ed532005-08-16 20:43:16 +1000601
602 return 0;
603}
604
Dave Airlie414ed532005-08-16 20:43:16 +1000605/**
606 * Emit a rendering packet3 from userspace.
607 * Called by r300_do_cp_cmdbuf.
608 */
Dave Airlied985c102006-01-02 21:32:48 +1100609static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv,
610 drm_radeon_kcmd_buffer_t *cmdbuf,
Dave Airlie414ed532005-08-16 20:43:16 +1000611 drm_r300_cmd_header_t header)
612{
613 int n;
614 int ret;
Dave Airlieb3a83632005-09-30 18:37:36 +1000615 char *orig_buf = cmdbuf->buf;
Dave Airlie414ed532005-08-16 20:43:16 +1000616 int orig_bufsz = cmdbuf->bufsz;
617
618 /* This is a do-while-loop so that we run the interior at least once,
619 * even if cmdbuf->nbox is 0. Compare r300_emit_cliprects for rationale.
620 */
621 n = 0;
622 do {
623 if (cmdbuf->nbox > R300_SIMULTANEOUS_CLIPRECTS) {
624 ret = r300_emit_cliprects(dev_priv, cmdbuf, n);
625 if (ret)
626 return ret;
627
628 cmdbuf->buf = orig_buf;
629 cmdbuf->bufsz = orig_bufsz;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000630 }
Dave Airlie414ed532005-08-16 20:43:16 +1000631
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000632 switch (header.packet3.packet) {
Dave Airlie414ed532005-08-16 20:43:16 +1000633 case R300_CMD_PACKET3_CLEAR:
634 DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n");
635 ret = r300_emit_clear(dev_priv, cmdbuf);
636 if (ret) {
637 DRM_ERROR("r300_emit_clear failed\n");
638 return ret;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000639 }
Dave Airlie414ed532005-08-16 20:43:16 +1000640 break;
641
642 case R300_CMD_PACKET3_RAW:
643 DRM_DEBUG("R300_CMD_PACKET3_RAW\n");
644 ret = r300_emit_raw_packet3(dev_priv, cmdbuf);
645 if (ret) {
646 DRM_ERROR("r300_emit_raw_packet3 failed\n");
647 return ret;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000648 }
Dave Airlie414ed532005-08-16 20:43:16 +1000649 break;
650
651 default:
652 DRM_ERROR("bad packet3 type %i at %p\n",
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000653 header.packet3.packet,
654 cmdbuf->buf - sizeof(header));
Dave Airlie414ed532005-08-16 20:43:16 +1000655 return DRM_ERR(EINVAL);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000656 }
Dave Airlie414ed532005-08-16 20:43:16 +1000657
658 n += R300_SIMULTANEOUS_CLIPRECTS;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000659 } while (n < cmdbuf->nbox);
Dave Airlie414ed532005-08-16 20:43:16 +1000660
661 return 0;
662}
663
664/* Some of the R300 chips seem to be extremely touchy about the two registers
665 * that are configured in r300_pacify.
666 * Among the worst offenders seems to be the R300 ND (0x4E44): When userspace
667 * sends a command buffer that contains only state setting commands and a
668 * vertex program/parameter upload sequence, this will eventually lead to a
669 * lockup, unless the sequence is bracketed by calls to r300_pacify.
670 * So we should take great care to *always* call r300_pacify before
671 * *anything* 3D related, and again afterwards. This is what the
672 * call bracket in r300_do_cp_cmdbuf is for.
673 */
674
675/**
676 * Emit the sequence to pacify R300.
677 */
Dave Airlied985c102006-01-02 21:32:48 +1100678static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
Dave Airlie414ed532005-08-16 20:43:16 +1000679{
680 RING_LOCALS;
681
682 BEGIN_RING(6);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000683 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
684 OUT_RING(0xa);
685 OUT_RING(CP_PACKET0(0x4f18, 0));
686 OUT_RING(0x3);
687 OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
688 OUT_RING(0x0);
Dave Airlie414ed532005-08-16 20:43:16 +1000689 ADVANCE_RING();
690}
691
Dave Airlie414ed532005-08-16 20:43:16 +1000692/**
693 * Called by r300_do_cp_cmdbuf to update the internal buffer age and state.
694 * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must
695 * be careful about how this function is called.
696 */
697static void r300_discard_buffer(drm_device_t * dev, drm_buf_t * buf)
698{
699 drm_radeon_private_t *dev_priv = dev->dev_private;
700 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
701
702 buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
703 buf->pending = 1;
704 buf->used = 0;
705}
706
Dave Airlieee4621f2006-03-19 19:45:26 +1100707static int r300_scratch(drm_radeon_private_t *dev_priv,
708 drm_radeon_kcmd_buffer_t *cmdbuf,
709 drm_r300_cmd_header_t header)
710{
711 u32 *ref_age_base;
712 u32 i, buf_idx, h_pending;
713 RING_LOCALS;
714
715 if (cmdbuf->bufsz <
716 (sizeof(u64) + header.scratch.n_bufs * sizeof(buf_idx))) {
717 return DRM_ERR(EINVAL);
718 }
719
720 if (header.scratch.reg >= 5) {
721 return DRM_ERR(EINVAL);
722 }
723
724 dev_priv->scratch_ages[header.scratch.reg]++;
725
Dave Airliecaa98c42006-04-23 18:14:00 +1000726 ref_age_base = (u32 *)(unsigned long)*((uint64_t *)cmdbuf->buf);
Dave Airlieee4621f2006-03-19 19:45:26 +1100727
728 cmdbuf->buf += sizeof(u64);
729 cmdbuf->bufsz -= sizeof(u64);
730
731 for (i=0; i < header.scratch.n_bufs; i++) {
732 buf_idx = *(u32 *)cmdbuf->buf;
733 buf_idx *= 2; /* 8 bytes per buf */
734
735 if (DRM_COPY_TO_USER(ref_age_base + buf_idx, &dev_priv->scratch_ages[header.scratch.reg], sizeof(u32))) {
736 return DRM_ERR(EINVAL);
737 }
738
739 if (DRM_COPY_FROM_USER(&h_pending, ref_age_base + buf_idx + 1, sizeof(u32))) {
740 return DRM_ERR(EINVAL);
741 }
742
743 if (h_pending == 0) {
744 return DRM_ERR(EINVAL);
745 }
746
747 h_pending--;
748
749 if (DRM_COPY_TO_USER(ref_age_base + buf_idx + 1, &h_pending, sizeof(u32))) {
750 return DRM_ERR(EINVAL);
751 }
752
753 cmdbuf->buf += sizeof(buf_idx);
754 cmdbuf->bufsz -= sizeof(buf_idx);
755 }
756
757 BEGIN_RING(2);
758 OUT_RING(CP_PACKET0(RADEON_SCRATCH_REG0 + header.scratch.reg * 4, 0));
759 OUT_RING(dev_priv->scratch_ages[header.scratch.reg]);
760 ADVANCE_RING();
761
762 return 0;
763}
764
Dave Airlie414ed532005-08-16 20:43:16 +1000765/**
766 * Parses and validates a user-supplied command buffer and emits appropriate
767 * commands on the DMA ring buffer.
768 * Called by the ioctl handler function radeon_cp_cmdbuf.
769 */
Dave Airlied985c102006-01-02 21:32:48 +1100770int r300_do_cp_cmdbuf(drm_device_t *dev,
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000771 DRMFILE filp,
Dave Airlied985c102006-01-02 21:32:48 +1100772 drm_file_t *filp_priv,
773 drm_radeon_kcmd_buffer_t *cmdbuf)
Dave Airlie414ed532005-08-16 20:43:16 +1000774{
775 drm_radeon_private_t *dev_priv = dev->dev_private;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000776 drm_device_dma_t *dma = dev->dma;
777 drm_buf_t *buf = NULL;
Dave Airlie414ed532005-08-16 20:43:16 +1000778 int emit_dispatch_age = 0;
779 int ret = 0;
780
781 DRM_DEBUG("\n");
782
783 /* See the comment above r300_emit_begin3d for why this call must be here,
784 * and what the cleanup gotos are for. */
785 r300_pacify(dev_priv);
786
787 if (cmdbuf->nbox <= R300_SIMULTANEOUS_CLIPRECTS) {
788 ret = r300_emit_cliprects(dev_priv, cmdbuf, 0);
789 if (ret)
790 goto cleanup;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000791 }
Dave Airlie414ed532005-08-16 20:43:16 +1000792
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000793 while (cmdbuf->bufsz >= sizeof(drm_r300_cmd_header_t)) {
Dave Airlie414ed532005-08-16 20:43:16 +1000794 int idx;
795 drm_r300_cmd_header_t header;
796
797 header.u = *(unsigned int *)cmdbuf->buf;
798
799 cmdbuf->buf += sizeof(header);
800 cmdbuf->bufsz -= sizeof(header);
801
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000802 switch (header.header.cmd_type) {
803 case R300_CMD_PACKET0:
Dave Airlie414ed532005-08-16 20:43:16 +1000804 DRM_DEBUG("R300_CMD_PACKET0\n");
805 ret = r300_emit_packet0(dev_priv, cmdbuf, header);
806 if (ret) {
807 DRM_ERROR("r300_emit_packet0 failed\n");
808 goto cleanup;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000809 }
Dave Airlie414ed532005-08-16 20:43:16 +1000810 break;
811
812 case R300_CMD_VPU:
813 DRM_DEBUG("R300_CMD_VPU\n");
814 ret = r300_emit_vpu(dev_priv, cmdbuf, header);
815 if (ret) {
816 DRM_ERROR("r300_emit_vpu failed\n");
817 goto cleanup;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000818 }
Dave Airlie414ed532005-08-16 20:43:16 +1000819 break;
820
821 case R300_CMD_PACKET3:
822 DRM_DEBUG("R300_CMD_PACKET3\n");
823 ret = r300_emit_packet3(dev_priv, cmdbuf, header);
824 if (ret) {
825 DRM_ERROR("r300_emit_packet3 failed\n");
826 goto cleanup;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000827 }
Dave Airlie414ed532005-08-16 20:43:16 +1000828 break;
829
830 case R300_CMD_END3D:
831 DRM_DEBUG("R300_CMD_END3D\n");
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000832 /* TODO:
833 Ideally userspace driver should not need to issue this call,
834 i.e. the drm driver should issue it automatically and prevent
835 lockups.
Dave Airlie414ed532005-08-16 20:43:16 +1000836
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000837 In practice, we do not understand why this call is needed and what
838 it does (except for some vague guesses that it has to do with cache
839 coherence) and so the user space driver does it.
840
841 Once we are sure which uses prevent lockups the code could be moved
842 into the kernel and the userspace driver will not
843 need to use this command.
844
845 Note that issuing this command does not hurt anything
846 except, possibly, performance */
Dave Airlie414ed532005-08-16 20:43:16 +1000847 r300_pacify(dev_priv);
848 break;
849
850 case R300_CMD_CP_DELAY:
851 /* simple enough, we can do it here */
852 DRM_DEBUG("R300_CMD_CP_DELAY\n");
853 {
854 int i;
855 RING_LOCALS;
856
857 BEGIN_RING(header.delay.count);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000858 for (i = 0; i < header.delay.count; i++)
Dave Airlie414ed532005-08-16 20:43:16 +1000859 OUT_RING(RADEON_CP_PACKET2);
860 ADVANCE_RING();
861 }
862 break;
863
864 case R300_CMD_DMA_DISCARD:
865 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000866 idx = header.dma.buf_idx;
867 if (idx < 0 || idx >= dma->buf_count) {
868 DRM_ERROR("buffer index %d (of %d max)\n",
869 idx, dma->buf_count - 1);
Dave Airlie414ed532005-08-16 20:43:16 +1000870 ret = DRM_ERR(EINVAL);
Dave Airlie414ed532005-08-16 20:43:16 +1000871 goto cleanup;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000872 }
873
874 buf = dma->buflist[idx];
875 if (buf->filp != filp || buf->pending) {
876 DRM_ERROR("bad buffer %p %p %d\n",
877 buf->filp, filp, buf->pending);
878 ret = DRM_ERR(EINVAL);
879 goto cleanup;
880 }
Dave Airlie414ed532005-08-16 20:43:16 +1000881
882 emit_dispatch_age = 1;
883 r300_discard_buffer(dev, buf);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000884 break;
Dave Airlie414ed532005-08-16 20:43:16 +1000885
886 case R300_CMD_WAIT:
887 /* simple enough, we can do it here */
888 DRM_DEBUG("R300_CMD_WAIT\n");
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000889 if (header.wait.flags == 0)
890 break; /* nothing to do */
Dave Airlie414ed532005-08-16 20:43:16 +1000891
892 {
893 RING_LOCALS;
894
895 BEGIN_RING(2);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000896 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
897 OUT_RING((header.wait.flags & 0xf) << 14);
Dave Airlie414ed532005-08-16 20:43:16 +1000898 ADVANCE_RING();
899 }
900 break;
901
Dave Airlieee4621f2006-03-19 19:45:26 +1100902 case R300_CMD_SCRATCH:
903 DRM_DEBUG("R300_CMD_SCRATCH\n");
904 ret = r300_scratch(dev_priv, cmdbuf, header);
905 if (ret) {
906 DRM_ERROR("r300_scratch failed\n");
907 goto cleanup;
908 }
909 break;
910
Dave Airlie414ed532005-08-16 20:43:16 +1000911 default:
912 DRM_ERROR("bad cmd_type %i at %p\n",
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000913 header.header.cmd_type,
Dave Airlie414ed532005-08-16 20:43:16 +1000914 cmdbuf->buf - sizeof(header));
915 ret = DRM_ERR(EINVAL);
916 goto cleanup;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000917 }
Dave Airlie414ed532005-08-16 20:43:16 +1000918 }
919
920 DRM_DEBUG("END\n");
921
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000922 cleanup:
Dave Airlie414ed532005-08-16 20:43:16 +1000923 r300_pacify(dev_priv);
924
925 /* We emit the vertex buffer age here, outside the pacifier "brackets"
926 * for two reasons:
927 * (1) This may coalesce multiple age emissions into a single one and
928 * (2) more importantly, some chips lock up hard when scratch registers
929 * are written inside the pacifier bracket.
930 */
931 if (emit_dispatch_age) {
932 RING_LOCALS;
933
934 /* Emit the vertex buffer age */
935 BEGIN_RING(2);
936 RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch);
937 ADVANCE_RING();
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000938 }
Dave Airlie414ed532005-08-16 20:43:16 +1000939
940 COMMIT_RING();
941
942 return ret;
943}