Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 2 | * ata_piix.c - Intel PATA/SATA controllers |
| 3 | * |
| 4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
| 5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
| 6 | * on emails. |
| 7 | * |
| 8 | * |
| 9 | * Copyright 2003-2005 Red Hat Inc |
| 10 | * Copyright 2003-2005 Jeff Garzik |
| 11 | * |
| 12 | * |
| 13 | * Copyright header from piix.c: |
| 14 | * |
| 15 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer |
| 16 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> |
| 17 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> |
| 18 | * |
| 19 | * |
| 20 | * This program is free software; you can redistribute it and/or modify |
| 21 | * it under the terms of the GNU General Public License as published by |
| 22 | * the Free Software Foundation; either version 2, or (at your option) |
| 23 | * any later version. |
| 24 | * |
| 25 | * This program is distributed in the hope that it will be useful, |
| 26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 28 | * GNU General Public License for more details. |
| 29 | * |
| 30 | * You should have received a copy of the GNU General Public License |
| 31 | * along with this program; see the file COPYING. If not, write to |
| 32 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 33 | * |
| 34 | * |
| 35 | * libata documentation is available via 'make {ps|pdf}docs', |
| 36 | * as Documentation/DocBook/libata.* |
| 37 | * |
| 38 | * Hardware documentation available at http://developer.intel.com/ |
| 39 | * |
Alan Cox | d96212e | 2005-12-08 19:19:50 +0000 | [diff] [blame] | 40 | * Documentation |
| 41 | * Publically available from Intel web site. Errata documentation |
| 42 | * is also publically available. As an aide to anyone hacking on this |
| 43 | * driver the list of errata that are relevant is below.going back to |
| 44 | * PIIX4. Older device documentation is now a bit tricky to find. |
| 45 | * |
| 46 | * The chipsets all follow very much the same design. The orginal Triton |
| 47 | * series chipsets do _not_ support independant device timings, but this |
| 48 | * is fixed in Triton II. With the odd mobile exception the chips then |
| 49 | * change little except in gaining more modes until SATA arrives. This |
| 50 | * driver supports only the chips with independant timing (that is those |
| 51 | * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix |
| 52 | * for the early chip drivers. |
| 53 | * |
| 54 | * Errata of note: |
| 55 | * |
| 56 | * Unfixable |
| 57 | * PIIX4 errata #9 - Only on ultra obscure hw |
| 58 | * ICH3 errata #13 - Not observed to affect real hw |
| 59 | * by Intel |
| 60 | * |
| 61 | * Things we must deal with |
| 62 | * PIIX4 errata #10 - BM IDE hang with non UDMA |
| 63 | * (must stop/start dma to recover) |
| 64 | * 440MX errata #15 - As PIIX4 errata #10 |
| 65 | * PIIX4 errata #15 - Must not read control registers |
| 66 | * during a PIO transfer |
| 67 | * 440MX errata #13 - As PIIX4 errata #15 |
| 68 | * ICH2 errata #21 - DMA mode 0 doesn't work right |
| 69 | * ICH0/1 errata #55 - As ICH2 errata #21 |
| 70 | * ICH2 spec c #9 - Extra operations needed to handle |
| 71 | * drive hotswap [NOT YET SUPPORTED] |
| 72 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary |
| 73 | * and must be dword aligned |
| 74 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 |
| 75 | * |
| 76 | * Should have been BIOS fixed: |
| 77 | * 450NX: errata #19 - DMA hangs on old 450NX |
| 78 | * 450NX: errata #20 - DMA hangs on old 450NX |
| 79 | * 450NX: errata #25 - Corruption with DMA on old 450NX |
| 80 | * ICH3 errata #15 - IDE deadlock under high load |
| 81 | * (BIOS must set dev 31 fn 0 bit 23) |
| 82 | * ICH3 errata #18 - Don't use native mode |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | */ |
| 84 | |
| 85 | #include <linux/kernel.h> |
| 86 | #include <linux/module.h> |
| 87 | #include <linux/pci.h> |
| 88 | #include <linux/init.h> |
| 89 | #include <linux/blkdev.h> |
| 90 | #include <linux/delay.h> |
Jeff Garzik | 6248e64 | 2005-10-30 06:42:18 -0500 | [diff] [blame] | 91 | #include <linux/device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | #include <scsi/scsi_host.h> |
| 93 | #include <linux/libata.h> |
| 94 | |
| 95 | #define DRV_NAME "ata_piix" |
Jeff Garzik | 7bdd720 | 2005-11-16 11:06:59 -0500 | [diff] [blame] | 96 | #define DRV_VERSION "1.05" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 97 | |
| 98 | enum { |
| 99 | PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ |
| 100 | ICH5_PMR = 0x90, /* port mapping register */ |
| 101 | ICH5_PCS = 0x92, /* port control and status */ |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 102 | PIIX_SCC = 0x0A, /* sub-class code register */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | |
Tejun Heo | 219e621 | 2006-03-05 14:28:51 +0900 | [diff] [blame] | 104 | PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */ |
Tejun Heo | d435804 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 105 | PIIX_FLAG_SCR = (1 << 26), /* SCR available */ |
Tejun Heo | ff0fc14 | 2005-12-18 17:17:07 +0900 | [diff] [blame] | 106 | PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */ |
| 107 | PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ |
| 108 | PIIX_FLAG_COMBINED = (1 << 29), /* combined mode possible */ |
| 109 | /* ICH6/7 use different scheme for map value */ |
| 110 | PIIX_FLAG_COMBINED_ICH6 = PIIX_FLAG_COMBINED | (1 << 30), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | |
| 112 | /* combined mode. if set, PATA is channel 0. |
| 113 | * if clear, PATA is channel 1. |
| 114 | */ |
Hannes Reinecke | 6a690df | 2005-06-28 17:30:38 -0700 | [diff] [blame] | 115 | PIIX_PORT_ENABLED = (1 << 0), |
| 116 | PIIX_PORT_PRESENT = (1 << 4), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 117 | |
| 118 | PIIX_80C_PRI = (1 << 5) | (1 << 4), |
| 119 | PIIX_80C_SEC = (1 << 7) | (1 << 6), |
| 120 | |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 121 | /* controller IDs */ |
| 122 | piix4_pata = 0, |
| 123 | ich5_pata = 1, |
| 124 | ich5_sata = 2, |
| 125 | esb_sata = 3, |
| 126 | ich6_sata = 4, |
| 127 | ich6_sata_ahci = 5, |
| 128 | ich6m_sata_ahci = 6, |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 129 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 130 | /* constants for mapping table */ |
| 131 | P0 = 0, /* port 0 */ |
| 132 | P1 = 1, /* port 1 */ |
| 133 | P2 = 2, /* port 2 */ |
| 134 | P3 = 3, /* port 3 */ |
| 135 | IDE = -1, /* IDE */ |
| 136 | NA = -2, /* not avaliable */ |
| 137 | RV = -3, /* reserved */ |
| 138 | |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 139 | PIIX_AHCI_DEVICE = 6, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 140 | }; |
| 141 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 142 | struct piix_map_db { |
| 143 | const u32 mask; |
| 144 | const int map[][4]; |
| 145 | }; |
| 146 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | static int piix_init_one (struct pci_dev *pdev, |
| 148 | const struct pci_device_id *ent); |
| 149 | |
Tejun Heo | 573db6b | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 150 | static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes); |
Tejun Heo | ccbe6d5 | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 151 | static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 152 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev); |
| 153 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev); |
| 154 | |
| 155 | static unsigned int in_module_init = 1; |
| 156 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 157 | static const struct pci_device_id piix_pci_tbl[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | #ifdef ATA_ENABLE_PATA |
| 159 | { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata }, |
| 160 | { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata }, |
| 161 | { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata }, |
| 162 | #endif |
| 163 | |
| 164 | /* NOTE: The following PCI ids must be kept in sync with the |
| 165 | * list in drivers/pci/quirks.c. |
| 166 | */ |
| 167 | |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 168 | /* 82801EB (ICH5) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 169 | { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 170 | /* 82801EB (ICH5) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 171 | { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 172 | /* 6300ESB (ICH5 variant with broken PCS present bits) */ |
| 173 | { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata }, |
| 174 | /* 6300ESB pretending RAID */ |
| 175 | { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata }, |
| 176 | /* 82801FB/FW (ICH6/ICH6W) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 177 | { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 178 | /* 82801FR/FRW (ICH6R/ICH6RW) */ |
Jeff Garzik | 1c24a41 | 2005-11-14 18:20:23 -0500 | [diff] [blame] | 179 | { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 180 | /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */ |
| 181 | { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, |
| 182 | /* 82801GB/GR/GH (ICH7, identical to ICH6) */ |
Jeff Garzik | 1c24a41 | 2005-11-14 18:20:23 -0500 | [diff] [blame] | 183 | { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 184 | /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ |
| 185 | { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, |
| 186 | /* Enterprise Southbridge 2 (where's the datasheet?) */ |
Jeff Garzik | 1c24a41 | 2005-11-14 18:20:23 -0500 | [diff] [blame] | 187 | { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 188 | /* SATA Controller 1 IDE (ICH8, no datasheet yet) */ |
Jason Gaston | 012b265 | 2006-01-17 12:28:48 -0800 | [diff] [blame] | 189 | { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 190 | /* SATA Controller 2 IDE (ICH8, ditto) */ |
Jason Gaston | 012b265 | 2006-01-17 12:28:48 -0800 | [diff] [blame] | 191 | { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 192 | /* Mobile SATA Controller IDE (ICH8M, ditto) */ |
| 193 | { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 194 | |
| 195 | { } /* terminate list */ |
| 196 | }; |
| 197 | |
| 198 | static struct pci_driver piix_pci_driver = { |
| 199 | .name = DRV_NAME, |
| 200 | .id_table = piix_pci_tbl, |
| 201 | .probe = piix_init_one, |
| 202 | .remove = ata_pci_remove_one, |
Jens Axboe | 9b84754 | 2006-01-06 09:28:07 +0100 | [diff] [blame] | 203 | .suspend = ata_pci_device_suspend, |
| 204 | .resume = ata_pci_device_resume, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 205 | }; |
| 206 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 207 | static struct scsi_host_template piix_sht = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 208 | .module = THIS_MODULE, |
| 209 | .name = DRV_NAME, |
| 210 | .ioctl = ata_scsi_ioctl, |
| 211 | .queuecommand = ata_scsi_queuecmd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | .can_queue = ATA_DEF_QUEUE, |
| 213 | .this_id = ATA_SHT_THIS_ID, |
| 214 | .sg_tablesize = LIBATA_MAX_PRD, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 215 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 216 | .emulated = ATA_SHT_EMULATED, |
| 217 | .use_clustering = ATA_SHT_USE_CLUSTERING, |
| 218 | .proc_name = DRV_NAME, |
| 219 | .dma_boundary = ATA_DMA_BOUNDARY, |
| 220 | .slave_configure = ata_scsi_slave_config, |
| 221 | .bios_param = ata_std_bios_param, |
Jens Axboe | 9b84754 | 2006-01-06 09:28:07 +0100 | [diff] [blame] | 222 | .resume = ata_scsi_device_resume, |
| 223 | .suspend = ata_scsi_device_suspend, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 224 | }; |
| 225 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 226 | static const struct ata_port_operations piix_pata_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 227 | .port_disable = ata_port_disable, |
| 228 | .set_piomode = piix_set_piomode, |
| 229 | .set_dmamode = piix_set_dmamode, |
| 230 | |
| 231 | .tf_load = ata_tf_load, |
| 232 | .tf_read = ata_tf_read, |
| 233 | .check_status = ata_check_status, |
| 234 | .exec_command = ata_exec_command, |
| 235 | .dev_select = ata_std_dev_select, |
| 236 | |
Tejun Heo | 573db6b | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 237 | .probe_reset = piix_pata_probe_reset, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 238 | |
| 239 | .bmdma_setup = ata_bmdma_setup, |
| 240 | .bmdma_start = ata_bmdma_start, |
| 241 | .bmdma_stop = ata_bmdma_stop, |
| 242 | .bmdma_status = ata_bmdma_status, |
| 243 | .qc_prep = ata_qc_prep, |
| 244 | .qc_issue = ata_qc_issue_prot, |
| 245 | |
| 246 | .eng_timeout = ata_eng_timeout, |
| 247 | |
| 248 | .irq_handler = ata_interrupt, |
| 249 | .irq_clear = ata_bmdma_irq_clear, |
| 250 | |
| 251 | .port_start = ata_port_start, |
| 252 | .port_stop = ata_port_stop, |
Jeff Garzik | aa8f0dc | 2005-05-26 21:54:27 -0400 | [diff] [blame] | 253 | .host_stop = ata_host_stop, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 254 | }; |
| 255 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 256 | static const struct ata_port_operations piix_sata_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 257 | .port_disable = ata_port_disable, |
| 258 | |
| 259 | .tf_load = ata_tf_load, |
| 260 | .tf_read = ata_tf_read, |
| 261 | .check_status = ata_check_status, |
| 262 | .exec_command = ata_exec_command, |
| 263 | .dev_select = ata_std_dev_select, |
| 264 | |
Tejun Heo | ccbe6d5 | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 265 | .probe_reset = piix_sata_probe_reset, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 266 | |
| 267 | .bmdma_setup = ata_bmdma_setup, |
| 268 | .bmdma_start = ata_bmdma_start, |
| 269 | .bmdma_stop = ata_bmdma_stop, |
| 270 | .bmdma_status = ata_bmdma_status, |
| 271 | .qc_prep = ata_qc_prep, |
| 272 | .qc_issue = ata_qc_issue_prot, |
| 273 | |
| 274 | .eng_timeout = ata_eng_timeout, |
| 275 | |
| 276 | .irq_handler = ata_interrupt, |
| 277 | .irq_clear = ata_bmdma_irq_clear, |
| 278 | |
| 279 | .port_start = ata_port_start, |
| 280 | .port_stop = ata_port_stop, |
Jeff Garzik | aa8f0dc | 2005-05-26 21:54:27 -0400 | [diff] [blame] | 281 | .host_stop = ata_host_stop, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 282 | }; |
| 283 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 284 | static struct piix_map_db ich5_map_db = { |
| 285 | .mask = 0x7, |
| 286 | .map = { |
| 287 | /* PM PS SM SS MAP */ |
| 288 | { P0, NA, P1, NA }, /* 000b */ |
| 289 | { P1, NA, P0, NA }, /* 001b */ |
| 290 | { RV, RV, RV, RV }, |
| 291 | { RV, RV, RV, RV }, |
| 292 | { P0, P1, IDE, IDE }, /* 100b */ |
| 293 | { P1, P0, IDE, IDE }, /* 101b */ |
| 294 | { IDE, IDE, P0, P1 }, /* 110b */ |
| 295 | { IDE, IDE, P1, P0 }, /* 111b */ |
| 296 | }, |
| 297 | }; |
| 298 | |
| 299 | static struct piix_map_db ich6_map_db = { |
| 300 | .mask = 0x3, |
| 301 | .map = { |
| 302 | /* PM PS SM SS MAP */ |
Tejun Heo | 79ea24e | 2006-03-31 20:01:50 +0900 | [diff] [blame] | 303 | { P0, P2, P1, P3 }, /* 00b */ |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 304 | { IDE, IDE, P1, P3 }, /* 01b */ |
| 305 | { P0, P2, IDE, IDE }, /* 10b */ |
| 306 | { RV, RV, RV, RV }, |
| 307 | }, |
| 308 | }; |
| 309 | |
| 310 | static struct piix_map_db ich6m_map_db = { |
| 311 | .mask = 0x3, |
| 312 | .map = { |
| 313 | /* PM PS SM SS MAP */ |
Tejun Heo | 79ea24e | 2006-03-31 20:01:50 +0900 | [diff] [blame] | 314 | { P0, P2, RV, RV }, /* 00b */ |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 315 | { RV, RV, RV, RV }, |
| 316 | { P0, P2, IDE, IDE }, /* 10b */ |
| 317 | { RV, RV, RV, RV }, |
| 318 | }, |
| 319 | }; |
| 320 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 321 | static struct ata_port_info piix_port_info[] = { |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 322 | /* piix4_pata */ |
| 323 | { |
| 324 | .sht = &piix_sht, |
| 325 | .host_flags = ATA_FLAG_SLAVE_POSS, |
| 326 | .pio_mask = 0x1f, /* pio0-4 */ |
| 327 | #if 0 |
| 328 | .mwdma_mask = 0x06, /* mwdma1-2 */ |
| 329 | #else |
| 330 | .mwdma_mask = 0x00, /* mwdma broken */ |
| 331 | #endif |
| 332 | .udma_mask = ATA_UDMA_MASK_40C, |
| 333 | .port_ops = &piix_pata_ops, |
| 334 | }, |
| 335 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 336 | /* ich5_pata */ |
| 337 | { |
| 338 | .sht = &piix_sht, |
Tejun Heo | 573db6b | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 339 | .host_flags = ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 340 | .pio_mask = 0x1f, /* pio0-4 */ |
| 341 | #if 0 |
| 342 | .mwdma_mask = 0x06, /* mwdma1-2 */ |
| 343 | #else |
| 344 | .mwdma_mask = 0x00, /* mwdma broken */ |
| 345 | #endif |
| 346 | .udma_mask = 0x3f, /* udma0-5 */ |
| 347 | .port_ops = &piix_pata_ops, |
| 348 | }, |
| 349 | |
| 350 | /* ich5_sata */ |
| 351 | { |
| 352 | .sht = &piix_sht, |
Tejun Heo | ccbe6d5 | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 353 | .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED | |
| 354 | PIIX_FLAG_CHECKINTR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 355 | .pio_mask = 0x1f, /* pio0-4 */ |
| 356 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 357 | .udma_mask = 0x7f, /* udma0-6 */ |
| 358 | .port_ops = &piix_sata_ops, |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 359 | .private_data = &ich5_map_db, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 360 | }, |
| 361 | |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 362 | /* i6300esb_sata */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 363 | { |
| 364 | .sht = &piix_sht, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 365 | .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED | |
Tejun Heo | 219e621 | 2006-03-05 14:28:51 +0900 | [diff] [blame] | 366 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 367 | .pio_mask = 0x1f, /* pio0-4 */ |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 368 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 369 | .udma_mask = 0x7f, /* udma0-6 */ |
| 370 | .port_ops = &piix_sata_ops, |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 371 | .private_data = &ich5_map_db, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 372 | }, |
| 373 | |
| 374 | /* ich6_sata */ |
| 375 | { |
| 376 | .sht = &piix_sht, |
Tejun Heo | ccbe6d5 | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 377 | .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 378 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 379 | .pio_mask = 0x1f, /* pio0-4 */ |
| 380 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 381 | .udma_mask = 0x7f, /* udma0-6 */ |
| 382 | .port_ops = &piix_sata_ops, |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 383 | .private_data = &ich6_map_db, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 384 | }, |
| 385 | |
Jeff Garzik | 1c24a41 | 2005-11-14 18:20:23 -0500 | [diff] [blame] | 386 | /* ich6_sata_ahci */ |
Jason Gaston | c368ca4 | 2005-04-16 15:24:44 -0700 | [diff] [blame] | 387 | { |
| 388 | .sht = &piix_sht, |
Tejun Heo | ccbe6d5 | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 389 | .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 390 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR | |
| 391 | PIIX_FLAG_AHCI, |
Jason Gaston | c368ca4 | 2005-04-16 15:24:44 -0700 | [diff] [blame] | 392 | .pio_mask = 0x1f, /* pio0-4 */ |
| 393 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 394 | .udma_mask = 0x7f, /* udma0-6 */ |
| 395 | .port_ops = &piix_sata_ops, |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 396 | .private_data = &ich6_map_db, |
Jason Gaston | c368ca4 | 2005-04-16 15:24:44 -0700 | [diff] [blame] | 397 | }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 398 | |
| 399 | /* ich6m_sata_ahci */ |
| 400 | { |
| 401 | .sht = &piix_sht, |
| 402 | .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 403 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR | |
| 404 | PIIX_FLAG_AHCI, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 405 | .pio_mask = 0x1f, /* pio0-4 */ |
| 406 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 407 | .udma_mask = 0x7f, /* udma0-6 */ |
| 408 | .port_ops = &piix_sata_ops, |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 409 | .private_data = &ich6m_map_db, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 410 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 411 | }; |
| 412 | |
| 413 | static struct pci_bits piix_enable_bits[] = { |
| 414 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ |
| 415 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ |
| 416 | }; |
| 417 | |
| 418 | MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); |
| 419 | MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); |
| 420 | MODULE_LICENSE("GPL"); |
| 421 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); |
| 422 | MODULE_VERSION(DRV_VERSION); |
| 423 | |
| 424 | /** |
| 425 | * piix_pata_cbl_detect - Probe host controller cable detect info |
| 426 | * @ap: Port for which cable detect info is desired |
| 427 | * |
| 428 | * Read 80c cable indicator from ATA PCI device's PCI config |
| 429 | * register. This register is normally set by firmware (BIOS). |
| 430 | * |
| 431 | * LOCKING: |
| 432 | * None (inherited from caller). |
| 433 | */ |
| 434 | static void piix_pata_cbl_detect(struct ata_port *ap) |
| 435 | { |
| 436 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); |
| 437 | u8 tmp, mask; |
| 438 | |
| 439 | /* no 80c support in host controller? */ |
| 440 | if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0) |
| 441 | goto cbl40; |
| 442 | |
| 443 | /* check BIOS cable detect results */ |
| 444 | mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; |
| 445 | pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); |
| 446 | if ((tmp & mask) == 0) |
| 447 | goto cbl40; |
| 448 | |
| 449 | ap->cbl = ATA_CBL_PATA80; |
| 450 | return; |
| 451 | |
| 452 | cbl40: |
| 453 | ap->cbl = ATA_CBL_PATA40; |
| 454 | ap->udma_mask &= ATA_UDMA_MASK_40C; |
| 455 | } |
| 456 | |
| 457 | /** |
Tejun Heo | 573db6b | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 458 | * piix_pata_probeinit - probeinit for PATA host controller |
| 459 | * @ap: Target port |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 460 | * |
Tejun Heo | 573db6b | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 461 | * Probeinit including cable detection. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 462 | * |
| 463 | * LOCKING: |
| 464 | * None (inherited from caller). |
| 465 | */ |
Tejun Heo | 573db6b | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 466 | static void piix_pata_probeinit(struct ata_port *ap) |
| 467 | { |
| 468 | piix_pata_cbl_detect(ap); |
| 469 | ata_std_probeinit(ap); |
| 470 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 471 | |
Tejun Heo | 573db6b | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 472 | /** |
| 473 | * piix_pata_probe_reset - Perform reset on PATA port and classify |
| 474 | * @ap: Port to reset |
| 475 | * @classes: Resulting classes of attached devices |
| 476 | * |
| 477 | * Reset PATA phy and classify attached devices. |
| 478 | * |
| 479 | * LOCKING: |
| 480 | * None (inherited from caller). |
| 481 | */ |
| 482 | static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 483 | { |
| 484 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); |
| 485 | |
| 486 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 487 | printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id); |
Tejun Heo | 573db6b | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 488 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 489 | } |
| 490 | |
Tejun Heo | 573db6b | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 491 | return ata_drive_probe_reset(ap, piix_pata_probeinit, |
| 492 | ata_std_softreset, NULL, |
| 493 | ata_std_postreset, classes); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 494 | } |
| 495 | |
| 496 | /** |
| 497 | * piix_sata_probe - Probe PCI device for present SATA devices |
| 498 | * @ap: Port associated with the PCI device we wish to probe |
| 499 | * |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 500 | * Reads and configures SATA PCI device's PCI config register |
| 501 | * Port Configuration and Status (PCS) to determine port and |
| 502 | * device availability. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 503 | * |
| 504 | * LOCKING: |
| 505 | * None (inherited from caller). |
| 506 | * |
| 507 | * RETURNS: |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 508 | * Mask of avaliable devices on the port. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 509 | */ |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 510 | static unsigned int piix_sata_probe (struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 511 | { |
| 512 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 513 | const unsigned int *map = ap->host_set->private_data; |
| 514 | int base = 2 * ap->hard_port_no; |
| 515 | unsigned int present_mask = 0; |
| 516 | int port, i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 517 | u8 pcs; |
| 518 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 519 | pci_read_config_byte(pdev, ICH5_PCS, &pcs); |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 520 | DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 521 | |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 522 | /* enable all ports on this ap and wait for them to settle */ |
| 523 | for (i = 0; i < 2; i++) { |
| 524 | port = map[base + i]; |
| 525 | if (port >= 0) |
| 526 | pcs |= 1 << port; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 527 | } |
| 528 | |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 529 | pci_write_config_byte(pdev, ICH5_PCS, pcs); |
| 530 | msleep(100); |
| 531 | |
| 532 | /* let's see which devices are present */ |
| 533 | pci_read_config_byte(pdev, ICH5_PCS, &pcs); |
| 534 | |
| 535 | for (i = 0; i < 2; i++) { |
| 536 | port = map[base + i]; |
| 537 | if (port < 0) |
| 538 | continue; |
Tejun Heo | 219e621 | 2006-03-05 14:28:51 +0900 | [diff] [blame] | 539 | if (ap->flags & PIIX_FLAG_IGNORE_PCS || pcs & 1 << (4 + port)) |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 540 | present_mask |= 1 << i; |
| 541 | else |
| 542 | pcs &= ~(1 << port); |
| 543 | } |
| 544 | |
| 545 | /* disable offline ports on non-AHCI controllers */ |
| 546 | if (!(ap->flags & PIIX_FLAG_AHCI)) |
| 547 | pci_write_config_byte(pdev, ICH5_PCS, pcs); |
| 548 | |
| 549 | DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n", |
| 550 | ap->id, pcs, present_mask); |
| 551 | |
| 552 | return present_mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 553 | } |
| 554 | |
| 555 | /** |
Tejun Heo | ccbe6d5 | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 556 | * piix_sata_probe_reset - Perform reset on SATA port and classify |
| 557 | * @ap: Port to reset |
| 558 | * @classes: Resulting classes of attached devices |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 559 | * |
Tejun Heo | ccbe6d5 | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 560 | * Reset SATA phy and classify attached devices. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 561 | * |
| 562 | * LOCKING: |
| 563 | * None (inherited from caller). |
| 564 | */ |
Tejun Heo | ccbe6d5 | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 565 | static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 566 | { |
| 567 | if (!piix_sata_probe(ap)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 568 | printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id); |
Tejun Heo | ccbe6d5 | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 569 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 570 | } |
| 571 | |
Tejun Heo | ccbe6d5 | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 572 | return ata_drive_probe_reset(ap, ata_std_probeinit, |
| 573 | ata_std_softreset, NULL, |
| 574 | ata_std_postreset, classes); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 575 | } |
| 576 | |
| 577 | /** |
| 578 | * piix_set_piomode - Initialize host controller PATA PIO timings |
| 579 | * @ap: Port whose timings we are configuring |
| 580 | * @adev: um |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 581 | * |
| 582 | * Set PIO mode for device, in host controller PCI config space. |
| 583 | * |
| 584 | * LOCKING: |
| 585 | * None (inherited from caller). |
| 586 | */ |
| 587 | |
| 588 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev) |
| 589 | { |
| 590 | unsigned int pio = adev->pio_mode - XFER_PIO_0; |
| 591 | struct pci_dev *dev = to_pci_dev(ap->host_set->dev); |
| 592 | unsigned int is_slave = (adev->devno != 0); |
| 593 | unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40; |
| 594 | unsigned int slave_port = 0x44; |
| 595 | u16 master_data; |
| 596 | u8 slave_data; |
| 597 | |
| 598 | static const /* ISP RTC */ |
| 599 | u8 timings[][2] = { { 0, 0 }, |
| 600 | { 0, 0 }, |
| 601 | { 1, 0 }, |
| 602 | { 2, 1 }, |
| 603 | { 2, 3 }, }; |
| 604 | |
| 605 | pci_read_config_word(dev, master_port, &master_data); |
| 606 | if (is_slave) { |
| 607 | master_data |= 0x4000; |
| 608 | /* enable PPE, IE and TIME */ |
| 609 | master_data |= 0x0070; |
| 610 | pci_read_config_byte(dev, slave_port, &slave_data); |
| 611 | slave_data &= (ap->hard_port_no ? 0x0f : 0xf0); |
| 612 | slave_data |= |
| 613 | (timings[pio][0] << 2) | |
| 614 | (timings[pio][1] << (ap->hard_port_no ? 4 : 0)); |
| 615 | } else { |
| 616 | master_data &= 0xccf8; |
| 617 | /* enable PPE, IE and TIME */ |
| 618 | master_data |= 0x0007; |
| 619 | master_data |= |
| 620 | (timings[pio][0] << 12) | |
| 621 | (timings[pio][1] << 8); |
| 622 | } |
| 623 | pci_write_config_word(dev, master_port, master_data); |
| 624 | if (is_slave) |
| 625 | pci_write_config_byte(dev, slave_port, slave_data); |
| 626 | } |
| 627 | |
| 628 | /** |
| 629 | * piix_set_dmamode - Initialize host controller PATA PIO timings |
| 630 | * @ap: Port whose timings we are configuring |
| 631 | * @adev: um |
| 632 | * @udma: udma mode, 0 - 6 |
| 633 | * |
| 634 | * Set UDMA mode for device, in host controller PCI config space. |
| 635 | * |
| 636 | * LOCKING: |
| 637 | * None (inherited from caller). |
| 638 | */ |
| 639 | |
| 640 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
| 641 | { |
| 642 | unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */ |
| 643 | struct pci_dev *dev = to_pci_dev(ap->host_set->dev); |
| 644 | u8 maslave = ap->hard_port_no ? 0x42 : 0x40; |
| 645 | u8 speed = udma; |
| 646 | unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno; |
| 647 | int a_speed = 3 << (drive_dn * 4); |
| 648 | int u_flag = 1 << drive_dn; |
| 649 | int v_flag = 0x01 << drive_dn; |
| 650 | int w_flag = 0x10 << drive_dn; |
| 651 | int u_speed = 0; |
| 652 | int sitre; |
| 653 | u16 reg4042, reg4a; |
| 654 | u8 reg48, reg54, reg55; |
| 655 | |
| 656 | pci_read_config_word(dev, maslave, ®4042); |
| 657 | DPRINTK("reg4042 = 0x%04x\n", reg4042); |
| 658 | sitre = (reg4042 & 0x4000) ? 1 : 0; |
| 659 | pci_read_config_byte(dev, 0x48, ®48); |
| 660 | pci_read_config_word(dev, 0x4a, ®4a); |
| 661 | pci_read_config_byte(dev, 0x54, ®54); |
| 662 | pci_read_config_byte(dev, 0x55, ®55); |
| 663 | |
| 664 | switch(speed) { |
| 665 | case XFER_UDMA_4: |
| 666 | case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break; |
| 667 | case XFER_UDMA_6: |
| 668 | case XFER_UDMA_5: |
| 669 | case XFER_UDMA_3: |
| 670 | case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break; |
| 671 | case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break; |
| 672 | case XFER_MW_DMA_2: |
| 673 | case XFER_MW_DMA_1: break; |
| 674 | default: |
| 675 | BUG(); |
| 676 | return; |
| 677 | } |
| 678 | |
| 679 | if (speed >= XFER_UDMA_0) { |
| 680 | if (!(reg48 & u_flag)) |
| 681 | pci_write_config_byte(dev, 0x48, reg48 | u_flag); |
| 682 | if (speed == XFER_UDMA_5) { |
| 683 | pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag); |
| 684 | } else { |
| 685 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); |
| 686 | } |
| 687 | if ((reg4a & a_speed) != u_speed) |
| 688 | pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed); |
| 689 | if (speed > XFER_UDMA_2) { |
| 690 | if (!(reg54 & v_flag)) |
| 691 | pci_write_config_byte(dev, 0x54, reg54 | v_flag); |
| 692 | } else |
| 693 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); |
| 694 | } else { |
| 695 | if (reg48 & u_flag) |
| 696 | pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); |
| 697 | if (reg4a & a_speed) |
| 698 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); |
| 699 | if (reg54 & v_flag) |
| 700 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); |
| 701 | if (reg55 & w_flag) |
| 702 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); |
| 703 | } |
| 704 | } |
| 705 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 706 | #define AHCI_PCI_BAR 5 |
| 707 | #define AHCI_GLOBAL_CTL 0x04 |
| 708 | #define AHCI_ENABLE (1 << 31) |
| 709 | static int piix_disable_ahci(struct pci_dev *pdev) |
| 710 | { |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 711 | void __iomem *mmio; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 712 | u32 tmp; |
| 713 | int rc = 0; |
| 714 | |
| 715 | /* BUG: pci_enable_device has not yet been called. This |
| 716 | * works because this device is usually set up by BIOS. |
| 717 | */ |
| 718 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 719 | if (!pci_resource_start(pdev, AHCI_PCI_BAR) || |
| 720 | !pci_resource_len(pdev, AHCI_PCI_BAR)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 721 | return 0; |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 722 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 723 | mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 724 | if (!mmio) |
| 725 | return -ENOMEM; |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 726 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 727 | tmp = readl(mmio + AHCI_GLOBAL_CTL); |
| 728 | if (tmp & AHCI_ENABLE) { |
| 729 | tmp &= ~AHCI_ENABLE; |
| 730 | writel(tmp, mmio + AHCI_GLOBAL_CTL); |
| 731 | |
| 732 | tmp = readl(mmio + AHCI_GLOBAL_CTL); |
| 733 | if (tmp & AHCI_ENABLE) |
| 734 | rc = -EIO; |
| 735 | } |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 736 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 737 | pci_iounmap(pdev, mmio); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 738 | return rc; |
| 739 | } |
| 740 | |
| 741 | /** |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 742 | * piix_check_450nx_errata - Check for problem 450NX setup |
Randy Dunlap | c893a3a | 2006-01-28 13:15:32 -0500 | [diff] [blame] | 743 | * @ata_dev: the PCI device to check |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 744 | * |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 745 | * Check for the present of 450NX errata #19 and errata #25. If |
| 746 | * they are found return an error code so we can turn off DMA |
| 747 | */ |
| 748 | |
| 749 | static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) |
| 750 | { |
| 751 | struct pci_dev *pdev = NULL; |
| 752 | u16 cfg; |
| 753 | u8 rev; |
| 754 | int no_piix_dma = 0; |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 755 | |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 756 | while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) |
| 757 | { |
| 758 | /* Look for 450NX PXB. Check for problem configurations |
| 759 | A PCI quirk checks bit 6 already */ |
| 760 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); |
| 761 | pci_read_config_word(pdev, 0x41, &cfg); |
| 762 | /* Only on the original revision: IDE DMA can hang */ |
| 763 | if(rev == 0x00) |
| 764 | no_piix_dma = 1; |
| 765 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ |
| 766 | else if(cfg & (1<<14) && rev < 5) |
| 767 | no_piix_dma = 2; |
| 768 | } |
| 769 | if(no_piix_dma) |
| 770 | dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); |
| 771 | if(no_piix_dma == 2) |
| 772 | dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); |
| 773 | return no_piix_dma; |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 774 | } |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 775 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 776 | static void __devinit piix_init_sata_map(struct pci_dev *pdev, |
| 777 | struct ata_port_info *pinfo) |
| 778 | { |
| 779 | struct piix_map_db *map_db = pinfo[0].private_data; |
| 780 | const unsigned int *map; |
| 781 | int i, invalid_map = 0; |
| 782 | u8 map_value; |
| 783 | |
| 784 | pci_read_config_byte(pdev, ICH5_PMR, &map_value); |
| 785 | |
| 786 | map = map_db->map[map_value & map_db->mask]; |
| 787 | |
| 788 | dev_printk(KERN_INFO, &pdev->dev, "MAP ["); |
| 789 | for (i = 0; i < 4; i++) { |
| 790 | switch (map[i]) { |
| 791 | case RV: |
| 792 | invalid_map = 1; |
| 793 | printk(" XX"); |
| 794 | break; |
| 795 | |
| 796 | case NA: |
| 797 | printk(" --"); |
| 798 | break; |
| 799 | |
| 800 | case IDE: |
| 801 | WARN_ON((i & 1) || map[i + 1] != IDE); |
| 802 | pinfo[i / 2] = piix_port_info[ich5_pata]; |
| 803 | i++; |
| 804 | printk(" IDE IDE"); |
| 805 | break; |
| 806 | |
| 807 | default: |
| 808 | printk(" P%d", map[i]); |
| 809 | if (i & 1) |
| 810 | pinfo[i / 2].host_flags |= ATA_FLAG_SLAVE_POSS; |
| 811 | break; |
| 812 | } |
| 813 | } |
| 814 | printk(" ]\n"); |
| 815 | |
| 816 | if (invalid_map) |
| 817 | dev_printk(KERN_ERR, &pdev->dev, |
| 818 | "invalid MAP value %u\n", map_value); |
| 819 | |
| 820 | pinfo[0].private_data = (void *)map; |
| 821 | pinfo[1].private_data = (void *)map; |
| 822 | } |
| 823 | |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 824 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 825 | * piix_init_one - Register PIIX ATA PCI device with kernel services |
| 826 | * @pdev: PCI device to register |
| 827 | * @ent: Entry in piix_pci_tbl matching with @pdev |
| 828 | * |
| 829 | * Called from kernel PCI layer. We probe for combined mode (sigh), |
| 830 | * and then hand over control to libata, for it to do the rest. |
| 831 | * |
| 832 | * LOCKING: |
| 833 | * Inherited from PCI layer (may sleep). |
| 834 | * |
| 835 | * RETURNS: |
| 836 | * Zero on success, or -ERRNO value. |
| 837 | */ |
| 838 | |
| 839 | static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
| 840 | { |
| 841 | static int printed_version; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 842 | struct ata_port_info port_info[2]; |
| 843 | struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] }; |
Tejun Heo | ff0fc14 | 2005-12-18 17:17:07 +0900 | [diff] [blame] | 844 | unsigned long host_flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 845 | |
| 846 | if (!printed_version++) |
Jeff Garzik | 6248e64 | 2005-10-30 06:42:18 -0500 | [diff] [blame] | 847 | dev_printk(KERN_DEBUG, &pdev->dev, |
| 848 | "version " DRV_VERSION "\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 849 | |
| 850 | /* no hotplugging support (FIXME) */ |
| 851 | if (!in_module_init) |
| 852 | return -ENODEV; |
| 853 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 854 | port_info[0] = piix_port_info[ent->driver_data]; |
| 855 | port_info[1] = piix_port_info[ent->driver_data]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 856 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 857 | host_flags = port_info[0].host_flags; |
Tejun Heo | ff0fc14 | 2005-12-18 17:17:07 +0900 | [diff] [blame] | 858 | |
| 859 | if (host_flags & PIIX_FLAG_AHCI) { |
Jeff Garzik | 8a60a07 | 2005-07-31 13:13:24 -0400 | [diff] [blame] | 860 | u8 tmp; |
| 861 | pci_read_config_byte(pdev, PIIX_SCC, &tmp); |
| 862 | if (tmp == PIIX_AHCI_DEVICE) { |
| 863 | int rc = piix_disable_ahci(pdev); |
| 864 | if (rc) |
| 865 | return rc; |
| 866 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 867 | } |
| 868 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 869 | /* Initialize SATA map */ |
| 870 | if (host_flags & ATA_FLAG_SATA) |
| 871 | piix_init_sata_map(pdev, port_info); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 872 | |
| 873 | /* On ICH5, some BIOSen disable the interrupt using the |
| 874 | * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. |
| 875 | * On ICH6, this bit has the same effect, but only when |
| 876 | * MSI is disabled (and it is disabled, as we don't use |
| 877 | * message-signalled interrupts currently). |
| 878 | */ |
Tejun Heo | ff0fc14 | 2005-12-18 17:17:07 +0900 | [diff] [blame] | 879 | if (host_flags & PIIX_FLAG_CHECKINTR) |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 880 | pci_intx(pdev, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 881 | |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 882 | if (piix_check_450nx_errata(pdev)) { |
| 883 | /* This writes into the master table but it does not |
| 884 | really matter for this errata as we will apply it to |
| 885 | all the PIIX devices on the board */ |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 886 | port_info[0].mwdma_mask = 0; |
| 887 | port_info[0].udma_mask = 0; |
| 888 | port_info[1].mwdma_mask = 0; |
| 889 | port_info[1].udma_mask = 0; |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 890 | } |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 891 | return ata_pci_init_one(pdev, ppinfo, 2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 892 | } |
| 893 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 894 | static int __init piix_init(void) |
| 895 | { |
| 896 | int rc; |
| 897 | |
| 898 | DPRINTK("pci_module_init\n"); |
| 899 | rc = pci_module_init(&piix_pci_driver); |
| 900 | if (rc) |
| 901 | return rc; |
| 902 | |
| 903 | in_module_init = 0; |
| 904 | |
| 905 | DPRINTK("done\n"); |
| 906 | return 0; |
| 907 | } |
| 908 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 909 | static void __exit piix_exit(void) |
| 910 | { |
| 911 | pci_unregister_driver(&piix_pci_driver); |
| 912 | } |
| 913 | |
| 914 | module_init(piix_init); |
| 915 | module_exit(piix_exit); |
| 916 | |