Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifdef __KERNEL__ |
Paul Mackerras | 1b92313 | 2005-10-10 22:54:57 +1000 | [diff] [blame] | 2 | #ifndef _ASM_POWERPC_IRQ_H |
| 3 | #define _ASM_POWERPC_IRQ_H |
| 4 | |
| 5 | /* |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the License, or (at your option) any later version. |
| 10 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | |
| 12 | #include <linux/config.h> |
Paul Mackerras | 1b92313 | 2005-10-10 22:54:57 +1000 | [diff] [blame] | 13 | #include <linux/threads.h> |
| 14 | |
| 15 | #include <asm/types.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | #include <asm/atomic.h> |
| 17 | |
Paul Mackerras | 1b92313 | 2005-10-10 22:54:57 +1000 | [diff] [blame] | 18 | /* this number is used when no interrupt has been assigned */ |
| 19 | #define NO_IRQ (-1) |
| 20 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | /* |
| 22 | * These constants are used for passing information about interrupt |
| 23 | * signal polarity and level/edge sensing to the low-level PIC chip |
| 24 | * drivers. |
| 25 | */ |
| 26 | #define IRQ_SENSE_MASK 0x1 |
| 27 | #define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */ |
| 28 | #define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */ |
| 29 | |
| 30 | #define IRQ_POLARITY_MASK 0x2 |
| 31 | #define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */ |
| 32 | #define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */ |
| 33 | |
Karsten Wiese | f26fdd5 | 2005-09-06 15:17:25 -0700 | [diff] [blame] | 34 | /* |
| 35 | * IRQ line status macro IRQ_PER_CPU is used |
| 36 | */ |
| 37 | #define ARCH_HAS_IRQ_PER_CPU |
| 38 | |
Kumar Gala | b671ad2 | 2005-09-21 16:52:55 -0500 | [diff] [blame] | 39 | #define get_irq_desc(irq) (&irq_desc[(irq)]) |
| 40 | |
| 41 | /* Define a way to iterate across irqs. */ |
| 42 | #define for_each_irq(i) \ |
| 43 | for ((i) = 0; (i) < NR_IRQS; ++(i)) |
| 44 | |
Paul Mackerras | 1b92313 | 2005-10-10 22:54:57 +1000 | [diff] [blame] | 45 | #ifdef CONFIG_PPC64 |
| 46 | |
| 47 | /* |
| 48 | * Maximum number of interrupt sources that we can handle. |
| 49 | */ |
| 50 | #define NR_IRQS 512 |
| 51 | |
| 52 | /* Interrupt numbers are virtual in case they are sparsely |
| 53 | * distributed by the hardware. |
| 54 | */ |
| 55 | extern unsigned int virt_irq_to_real_map[NR_IRQS]; |
| 56 | |
Stephen Rothwell | 7d01c88 | 2006-04-04 14:49:48 +1000 | [diff] [blame] | 57 | /* The maximum virtual IRQ number that we support. This |
| 58 | * can be set by the platform and will be reduced by the |
| 59 | * value of __irq_offset_value. It defaults to and is |
| 60 | * capped by (NR_IRQS - 1). |
| 61 | */ |
| 62 | extern unsigned int virt_irq_max; |
| 63 | |
Paul Mackerras | 1b92313 | 2005-10-10 22:54:57 +1000 | [diff] [blame] | 64 | /* Create a mapping for a real_irq if it doesn't already exist. |
| 65 | * Return the virtual irq as a convenience. |
| 66 | */ |
| 67 | int virt_irq_create_mapping(unsigned int real_irq); |
| 68 | void virt_irq_init(void); |
| 69 | |
| 70 | static inline unsigned int virt_irq_to_real(unsigned int virt_irq) |
| 71 | { |
| 72 | return virt_irq_to_real_map[virt_irq]; |
| 73 | } |
| 74 | |
| 75 | extern unsigned int real_irq_to_virt_slowpath(unsigned int real_irq); |
| 76 | |
| 77 | /* |
| 78 | * List of interrupt controllers. |
| 79 | */ |
| 80 | #define IC_INVALID 0 |
| 81 | #define IC_OPEN_PIC 1 |
| 82 | #define IC_PPC_XIC 2 |
Arnd Bergmann | f3f66f5 | 2005-10-31 20:08:37 -0500 | [diff] [blame] | 83 | #define IC_CELL_PIC 3 |
Paul Mackerras | 1b92313 | 2005-10-10 22:54:57 +1000 | [diff] [blame] | 84 | #define IC_ISERIES 4 |
| 85 | |
| 86 | extern u64 ppc64_interrupt_controller; |
| 87 | |
| 88 | #else /* 32-bit */ |
| 89 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 90 | #if defined(CONFIG_40x) |
| 91 | #include <asm/ibm4xx.h> |
| 92 | |
| 93 | #ifndef NR_BOARD_IRQS |
| 94 | #define NR_BOARD_IRQS 0 |
| 95 | #endif |
| 96 | |
| 97 | #ifndef UIC_WIDTH /* Number of interrupts per device */ |
| 98 | #define UIC_WIDTH 32 |
| 99 | #endif |
| 100 | |
| 101 | #ifndef NR_UICS /* number of UIC devices */ |
| 102 | #define NR_UICS 1 |
| 103 | #endif |
| 104 | |
| 105 | #if defined (CONFIG_403) |
| 106 | /* |
| 107 | * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has |
| 108 | * 32 possible interrupts, a majority of which are not implemented on |
| 109 | * all cores. There are six configurable, external interrupt pins and |
| 110 | * there are eight internal interrupts for the on-chip serial port |
| 111 | * (SPU), DMA controller, and JTAG controller. |
| 112 | * |
| 113 | */ |
| 114 | |
| 115 | #define NR_AIC_IRQS 32 |
| 116 | #define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS) |
| 117 | |
| 118 | #elif !defined (CONFIG_403) |
| 119 | |
| 120 | /* |
| 121 | * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32 |
| 122 | * possible interrupts as well. There are seven, configurable external |
| 123 | * interrupt pins and there are 17 internal interrupts for the on-chip |
| 124 | * serial port, DMA controller, on-chip Ethernet controller, PCI, etc. |
| 125 | * |
| 126 | */ |
| 127 | |
| 128 | |
| 129 | #define NR_UIC_IRQS UIC_WIDTH |
| 130 | #define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS) |
| 131 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 132 | |
| 133 | #elif defined(CONFIG_44x) |
| 134 | #include <asm/ibm44x.h> |
| 135 | |
| 136 | #define NR_UIC_IRQS 32 |
| 137 | #define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS) |
| 138 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 139 | #elif defined(CONFIG_8xx) |
| 140 | |
| 141 | /* Now include the board configuration specific associations. |
| 142 | */ |
| 143 | #include <asm/mpc8xx.h> |
| 144 | |
| 145 | /* The MPC8xx cores have 16 possible interrupts. There are eight |
| 146 | * possible level sensitive interrupts assigned and generated internally |
| 147 | * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer. |
| 148 | * There are eight external interrupts (IRQs) that can be configured |
| 149 | * as either level or edge sensitive. |
| 150 | * |
| 151 | * On some implementations, there is also the possibility of an 8259 |
| 152 | * through the PCI and PCI-ISA bridges. |
| 153 | * |
| 154 | * We are "flattening" the interrupt vectors of the cascaded CPM |
| 155 | * and 8259 interrupt controllers so that we can uniquely identify |
| 156 | * any interrupt source with a single integer. |
| 157 | */ |
| 158 | #define NR_SIU_INTS 16 |
| 159 | #define NR_CPM_INTS 32 |
| 160 | #ifndef NR_8259_INTS |
| 161 | #define NR_8259_INTS 0 |
| 162 | #endif |
| 163 | |
| 164 | #define SIU_IRQ_OFFSET 0 |
| 165 | #define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS) |
| 166 | #define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS) |
| 167 | |
| 168 | #define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS) |
| 169 | |
| 170 | /* These values must be zero-based and map 1:1 with the SIU configuration. |
| 171 | * They are used throughout the 8xx I/O subsystem to generate |
| 172 | * interrupt masks, flags, and other control patterns. This is why the |
| 173 | * current kernel assumption of the 8259 as the base controller is such |
| 174 | * a pain in the butt. |
| 175 | */ |
| 176 | #define SIU_IRQ0 (0) /* Highest priority */ |
| 177 | #define SIU_LEVEL0 (1) |
| 178 | #define SIU_IRQ1 (2) |
| 179 | #define SIU_LEVEL1 (3) |
| 180 | #define SIU_IRQ2 (4) |
| 181 | #define SIU_LEVEL2 (5) |
| 182 | #define SIU_IRQ3 (6) |
| 183 | #define SIU_LEVEL3 (7) |
| 184 | #define SIU_IRQ4 (8) |
| 185 | #define SIU_LEVEL4 (9) |
| 186 | #define SIU_IRQ5 (10) |
| 187 | #define SIU_LEVEL5 (11) |
| 188 | #define SIU_IRQ6 (12) |
| 189 | #define SIU_LEVEL6 (13) |
| 190 | #define SIU_IRQ7 (14) |
| 191 | #define SIU_LEVEL7 (15) |
| 192 | |
Vitaly Bordug | 514ccd4 | 2005-09-16 19:28:00 -0700 | [diff] [blame] | 193 | #define MPC8xx_INT_FEC1 SIU_LEVEL1 |
| 194 | #define MPC8xx_INT_FEC2 SIU_LEVEL3 |
| 195 | |
| 196 | #define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1) |
| 197 | #define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2) |
| 198 | #define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3) |
| 199 | #define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4) |
| 200 | #define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1) |
| 201 | #define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2) |
| 202 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 203 | /* The internal interrupts we can configure as we see fit. |
| 204 | * My personal preference is CPM at level 2, which puts it above the |
| 205 | * MBX PCI/ISA/IDE interrupts. |
| 206 | */ |
| 207 | #ifndef PIT_INTERRUPT |
| 208 | #define PIT_INTERRUPT SIU_LEVEL0 |
| 209 | #endif |
| 210 | #ifndef CPM_INTERRUPT |
| 211 | #define CPM_INTERRUPT SIU_LEVEL2 |
| 212 | #endif |
| 213 | #ifndef PCMCIA_INTERRUPT |
| 214 | #define PCMCIA_INTERRUPT SIU_LEVEL6 |
| 215 | #endif |
| 216 | #ifndef DEC_INTERRUPT |
| 217 | #define DEC_INTERRUPT SIU_LEVEL7 |
| 218 | #endif |
| 219 | |
| 220 | /* Some internal interrupt registers use an 8-bit mask for the interrupt |
| 221 | * level instead of a number. |
| 222 | */ |
| 223 | #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) |
| 224 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 225 | #elif defined(CONFIG_83xx) |
| 226 | #include <asm/mpc83xx.h> |
| 227 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 228 | #define NR_IRQS (NR_IPIC_INTS) |
| 229 | |
| 230 | #elif defined(CONFIG_85xx) |
| 231 | /* Now include the board configuration specific associations. |
| 232 | */ |
| 233 | #include <asm/mpc85xx.h> |
| 234 | |
Kumar Gala | 65145e0 | 2005-06-21 17:15:25 -0700 | [diff] [blame] | 235 | /* The MPC8548 openpic has 48 internal interrupts and 12 external |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 236 | * interrupts. |
| 237 | * |
| 238 | * We are "flattening" the interrupt vectors of the cascaded CPM |
| 239 | * so that we can uniquely identify any interrupt source with a |
| 240 | * single integer. |
| 241 | */ |
| 242 | #define NR_CPM_INTS 64 |
Kumar Gala | 65145e0 | 2005-06-21 17:15:25 -0700 | [diff] [blame] | 243 | #define NR_EPIC_INTS 60 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 244 | #ifndef NR_8259_INTS |
| 245 | #define NR_8259_INTS 0 |
| 246 | #endif |
| 247 | #define NUM_8259_INTERRUPTS NR_8259_INTS |
| 248 | |
| 249 | #ifndef CPM_IRQ_OFFSET |
| 250 | #define CPM_IRQ_OFFSET 0 |
| 251 | #endif |
| 252 | |
| 253 | #define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS) |
| 254 | |
| 255 | /* Internal IRQs on MPC85xx OpenPIC */ |
| 256 | |
| 257 | #ifndef MPC85xx_OPENPIC_IRQ_OFFSET |
| 258 | #ifdef CONFIG_CPM2 |
| 259 | #define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS) |
| 260 | #else |
| 261 | #define MPC85xx_OPENPIC_IRQ_OFFSET 0 |
| 262 | #endif |
| 263 | #endif |
| 264 | |
| 265 | /* Not all of these exist on all MPC85xx implementations */ |
| 266 | #define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 267 | #define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 268 | #define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 269 | #define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 270 | #define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 271 | #define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 272 | #define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 273 | #define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 274 | #define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 275 | #define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 276 | #define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 277 | #define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 278 | #define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 279 | #define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 280 | #define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 281 | #define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET) |
Kumar Gala | 5b37b70 | 2005-06-21 17:15:18 -0700 | [diff] [blame] | 282 | #define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 283 | #define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 284 | #define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 285 | #define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 286 | #define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 287 | #define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET) |
Kumar Gala | 5b37b70 | 2005-06-21 17:15:18 -0700 | [diff] [blame] | 288 | #define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 289 | #define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 290 | #define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 291 | #define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 292 | #define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 293 | #define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 294 | #define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 295 | #define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 296 | #define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 297 | #define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 298 | |
| 299 | /* The 12 external interrupt lines */ |
Kumar Gala | 65145e0 | 2005-06-21 17:15:25 -0700 | [diff] [blame] | 300 | #define MPC85xx_IRQ_EXT0 (48 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 301 | #define MPC85xx_IRQ_EXT1 (49 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 302 | #define MPC85xx_IRQ_EXT2 (50 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 303 | #define MPC85xx_IRQ_EXT3 (51 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 304 | #define MPC85xx_IRQ_EXT4 (52 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 305 | #define MPC85xx_IRQ_EXT5 (53 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 306 | #define MPC85xx_IRQ_EXT6 (54 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 307 | #define MPC85xx_IRQ_EXT7 (55 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 308 | #define MPC85xx_IRQ_EXT8 (56 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 309 | #define MPC85xx_IRQ_EXT9 (57 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 310 | #define MPC85xx_IRQ_EXT10 (58 + MPC85xx_OPENPIC_IRQ_OFFSET) |
| 311 | #define MPC85xx_IRQ_EXT11 (59 + MPC85xx_OPENPIC_IRQ_OFFSET) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 312 | |
| 313 | /* CPM related interrupts */ |
| 314 | #define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET) |
| 315 | #define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET) |
| 316 | #define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET) |
| 317 | #define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET) |
| 318 | #define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET) |
| 319 | #define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET) |
| 320 | #define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET) |
| 321 | #define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET) |
| 322 | #define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET) |
| 323 | #define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET) |
| 324 | #define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET) |
| 325 | #define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET) |
| 326 | #define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET) |
| 327 | #define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET) |
| 328 | #define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET) |
| 329 | #define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET) |
| 330 | #define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET) |
| 331 | #define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET) |
| 332 | #define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET) |
| 333 | #define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET) |
| 334 | #define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET) |
| 335 | #define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET) |
| 336 | #define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET) |
| 337 | #define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET) |
| 338 | #define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET) |
| 339 | #define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET) |
| 340 | #define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET) |
| 341 | #define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET) |
| 342 | #define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET) |
| 343 | #define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET) |
| 344 | #define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET) |
| 345 | #define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET) |
| 346 | #define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET) |
| 347 | #define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET) |
| 348 | #define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET) |
| 349 | #define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET) |
| 350 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 351 | #else /* CONFIG_40x + CONFIG_8xx */ |
| 352 | /* |
| 353 | * this is the # irq's for all ppc arch's (pmac/chrp/prep) |
| 354 | * so it is the max of them all |
| 355 | */ |
| 356 | #define NR_IRQS 256 |
Paul Mackerras | 1b92313 | 2005-10-10 22:54:57 +1000 | [diff] [blame] | 357 | #define __DO_IRQ_CANON 1 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 358 | |
| 359 | #ifndef CONFIG_8260 |
| 360 | |
| 361 | #define NUM_8259_INTERRUPTS 16 |
| 362 | |
| 363 | #else /* CONFIG_8260 */ |
| 364 | |
| 365 | /* The 8260 has an internal interrupt controller with a maximum of |
| 366 | * 64 IRQs. We will use NR_IRQs from above since it is large enough. |
| 367 | * Don't be confused by the 8260 documentation where they list an |
| 368 | * "interrupt number" and "interrupt vector". We are only interested |
| 369 | * in the interrupt vector. There are "reserved" holes where the |
| 370 | * vector number increases, but the interrupt number in the table does not. |
| 371 | * (Document errata updates have fixed this...make sure you have up to |
| 372 | * date processor documentation -- Dan). |
| 373 | */ |
| 374 | |
| 375 | #ifndef CPM_IRQ_OFFSET |
| 376 | #define CPM_IRQ_OFFSET 0 |
| 377 | #endif |
| 378 | |
| 379 | #define NR_CPM_INTS 64 |
| 380 | |
| 381 | #define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET) |
| 382 | #define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET) |
| 383 | #define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET) |
| 384 | #define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET) |
| 385 | #define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET) |
| 386 | #define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET) |
| 387 | #define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET) |
| 388 | #define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET) |
| 389 | #define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET) |
| 390 | #define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET) |
| 391 | #define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET) |
Kumar Gala | 8e8fff09 | 2005-09-03 15:55:34 -0700 | [diff] [blame] | 392 | #define SIU_INT_USB ((uint)0x0b + CPM_IRQ_OFFSET) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 393 | #define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET) |
| 394 | #define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET) |
| 395 | #define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET) |
| 396 | #define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET) |
| 397 | #define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET) |
| 398 | #define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET) |
Kumar Gala | 7f7fda0 | 2005-11-10 10:34:33 -0600 | [diff] [blame] | 399 | #define SIU_INT_PCI ((uint)0x12 + CPM_IRQ_OFFSET) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 400 | #define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET) |
| 401 | #define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET) |
| 402 | #define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET) |
| 403 | #define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET) |
| 404 | #define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET) |
| 405 | #define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET) |
| 406 | #define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET) |
| 407 | #define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET) |
| 408 | #define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET) |
| 409 | #define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET) |
| 410 | #define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET) |
| 411 | #define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET) |
| 412 | #define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET) |
| 413 | #define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET) |
| 414 | #define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET) |
| 415 | #define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET) |
| 416 | #define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET) |
| 417 | #define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET) |
| 418 | #define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET) |
| 419 | #define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET) |
| 420 | #define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET) |
| 421 | #define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET) |
| 422 | #define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET) |
| 423 | #define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET) |
| 424 | #define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET) |
| 425 | #define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET) |
| 426 | #define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET) |
| 427 | #define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET) |
| 428 | #define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET) |
| 429 | #define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET) |
| 430 | #define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET) |
| 431 | #define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET) |
| 432 | |
| 433 | #endif /* CONFIG_8260 */ |
| 434 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 435 | #endif |
| 436 | |
| 437 | #define NR_MASK_WORDS ((NR_IRQS + 31) / 32) |
| 438 | /* pedantic: these are long because they are used with set_bit --RR */ |
| 439 | extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 440 | extern atomic_t ppc_n_lost_interrupts; |
| 441 | |
Paul Mackerras | 6d0124f | 2005-10-26 17:19:06 +1000 | [diff] [blame] | 442 | #define virt_irq_create_mapping(x) (x) |
| 443 | |
Paul Mackerras | 1b92313 | 2005-10-10 22:54:57 +1000 | [diff] [blame] | 444 | #endif |
| 445 | |
| 446 | /* |
| 447 | * Because many systems have two overlapping names spaces for |
| 448 | * interrupts (ISA and XICS for example), and the ISA interrupts |
| 449 | * have historically not been easy to renumber, we allow ISA |
| 450 | * interrupts to take values 0 - 15, and shift up the remaining |
| 451 | * interrupts by 0x10. |
| 452 | */ |
| 453 | #define NUM_ISA_INTERRUPTS 0x10 |
| 454 | extern int __irq_offset_value; |
| 455 | |
| 456 | static inline int irq_offset_up(int irq) |
| 457 | { |
| 458 | return(irq + __irq_offset_value); |
| 459 | } |
| 460 | |
| 461 | static inline int irq_offset_down(int irq) |
| 462 | { |
| 463 | return(irq - __irq_offset_value); |
| 464 | } |
| 465 | |
| 466 | static inline int irq_offset_value(void) |
| 467 | { |
| 468 | return __irq_offset_value; |
| 469 | } |
| 470 | |
| 471 | #ifdef __DO_IRQ_CANON |
| 472 | extern int ppc_do_canonicalize_irqs; |
| 473 | #else |
| 474 | #define ppc_do_canonicalize_irqs 0 |
| 475 | #endif |
| 476 | |
| 477 | static __inline__ int irq_canonicalize(int irq) |
| 478 | { |
| 479 | if (ppc_do_canonicalize_irqs && irq == 2) |
| 480 | irq = 9; |
| 481 | return irq; |
| 482 | } |
| 483 | |
| 484 | extern int distribute_irqs; |
| 485 | |
| 486 | struct irqaction; |
| 487 | struct pt_regs; |
| 488 | |
Paul Mackerras | c6622f6 | 2006-02-24 10:06:59 +1100 | [diff] [blame] | 489 | #define __ARCH_HAS_DO_SOFTIRQ |
| 490 | |
| 491 | extern void __do_softirq(void); |
| 492 | |
Paul Mackerras | 1b92313 | 2005-10-10 22:54:57 +1000 | [diff] [blame] | 493 | #ifdef CONFIG_IRQSTACKS |
| 494 | /* |
| 495 | * Per-cpu stacks for handling hard and soft interrupts. |
| 496 | */ |
| 497 | extern struct thread_info *hardirq_ctx[NR_CPUS]; |
| 498 | extern struct thread_info *softirq_ctx[NR_CPUS]; |
| 499 | |
| 500 | extern void irq_ctx_init(void); |
| 501 | extern void call_do_softirq(struct thread_info *tp); |
Stephen Rothwell | d4be4f3 | 2005-11-09 16:19:53 +1100 | [diff] [blame] | 502 | extern int call___do_IRQ(int irq, struct pt_regs *regs, |
Stephen Rothwell | b709c08 | 2005-11-09 13:28:33 +1100 | [diff] [blame] | 503 | struct thread_info *tp); |
Paul Mackerras | 1b92313 | 2005-10-10 22:54:57 +1000 | [diff] [blame] | 504 | |
Paul Mackerras | 1b92313 | 2005-10-10 22:54:57 +1000 | [diff] [blame] | 505 | #else |
| 506 | #define irq_ctx_init() |
| 507 | |
| 508 | #endif /* CONFIG_IRQSTACKS */ |
| 509 | |
Paul Mackerras | f2783c1 | 2005-10-20 09:23:26 +1000 | [diff] [blame] | 510 | extern void do_IRQ(struct pt_regs *regs); |
| 511 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 512 | #endif /* _ASM_IRQ_H */ |
| 513 | #endif /* __KERNEL__ */ |