Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1 | /****************************************************************************** |
| 2 | * |
| 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of version 2 of the GNU General Public License as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | ******************************************************************************/ |
| 15 | #define _HCI_HAL_INIT_C_ |
| 16 | |
| 17 | #include <osdep_service.h> |
| 18 | #include <drv_types.h> |
| 19 | #include <rtw_efuse.h> |
| 20 | |
| 21 | #include <HalPwrSeqCmd.h> |
| 22 | #include <Hal8723PwrSeq.h> |
| 23 | #include <rtl8723a_hal.h> |
| 24 | #include <rtl8723a_led.h> |
| 25 | #include <linux/ieee80211.h> |
| 26 | |
| 27 | #include <usb_ops.h> |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 28 | |
| 29 | static void |
| 30 | _ConfigChipOutEP(struct rtw_adapter *pAdapter, u8 NumOutPipe) |
| 31 | { |
| 32 | u8 value8; |
| 33 | struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter); |
| 34 | |
| 35 | pHalData->OutEpQueueSel = 0; |
| 36 | pHalData->OutEpNumber = 0; |
| 37 | |
| 38 | /* Normal and High queue */ |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 39 | value8 = rtl8723au_read8(pAdapter, (REG_NORMAL_SIE_EP + 1)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 40 | |
| 41 | if (value8 & USB_NORMAL_SIE_EP_MASK) { |
| 42 | pHalData->OutEpQueueSel |= TX_SELE_HQ; |
| 43 | pHalData->OutEpNumber++; |
| 44 | } |
| 45 | |
| 46 | if ((value8 >> USB_NORMAL_SIE_EP_SHIFT) & USB_NORMAL_SIE_EP_MASK) { |
| 47 | pHalData->OutEpQueueSel |= TX_SELE_NQ; |
| 48 | pHalData->OutEpNumber++; |
| 49 | } |
| 50 | |
| 51 | /* Low queue */ |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 52 | value8 = rtl8723au_read8(pAdapter, (REG_NORMAL_SIE_EP + 2)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 53 | if (value8 & USB_NORMAL_SIE_EP_MASK) { |
| 54 | pHalData->OutEpQueueSel |= TX_SELE_LQ; |
| 55 | pHalData->OutEpNumber++; |
| 56 | } |
| 57 | |
| 58 | /* TODO: Error recovery for this case */ |
| 59 | /* RT_ASSERT((NumOutPipe == pHalData->OutEpNumber), |
| 60 | ("Out EP number isn't match! %d(Descriptor) != %d (SIE reg)\n", |
| 61 | (u32)NumOutPipe, (u32)pHalData->OutEpNumber)); */ |
| 62 | } |
| 63 | |
| 64 | static bool rtl8723au_set_queue_pipe_mapping(struct rtw_adapter *pAdapter, |
| 65 | u8 NumInPipe, u8 NumOutPipe) |
| 66 | { |
| 67 | struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter); |
| 68 | bool result = false; |
| 69 | |
| 70 | _ConfigChipOutEP(pAdapter, NumOutPipe); |
| 71 | |
| 72 | /* Normal chip with one IN and one OUT doesn't have interrupt IN EP. */ |
| 73 | if (pHalData->OutEpNumber == 1) { |
| 74 | if (NumInPipe != 1) |
| 75 | return result; |
| 76 | } |
| 77 | |
| 78 | result = Hal_MappingOutPipe23a(pAdapter, NumOutPipe); |
| 79 | |
| 80 | return result; |
| 81 | } |
| 82 | |
Jes Sorensen | 82ccb59 | 2014-05-16 10:04:07 +0200 | [diff] [blame] | 83 | void rtl8723au_chip_configure(struct rtw_adapter *padapter) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 84 | { |
| 85 | struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter); |
| 86 | struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); |
| 87 | |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 88 | pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber; |
| 89 | |
| 90 | rtl8723au_set_queue_pipe_mapping(padapter, |
| 91 | pdvobjpriv->RtNumInPipes, |
| 92 | pdvobjpriv->RtNumOutPipes); |
| 93 | } |
| 94 | |
Jes Sorensen | e04cd3f | 2014-05-16 10:04:44 +0200 | [diff] [blame] | 95 | static int _InitPowerOn(struct rtw_adapter *padapter) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 96 | { |
Jes Sorensen | e04cd3f | 2014-05-16 10:04:44 +0200 | [diff] [blame] | 97 | int status = _SUCCESS; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 98 | u16 value16 = 0; |
| 99 | u8 value8 = 0; |
| 100 | |
| 101 | /* RSV_CTRL 0x1C[7:0] = 0x00 |
| 102 | unlock ISO/CLK/Power control register */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 103 | rtl8723au_write8(padapter, REG_RSV_CTRL, 0x0); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 104 | |
| 105 | /* HW Power on sequence */ |
| 106 | if (!HalPwrSeqCmdParsing23a(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, |
| 107 | PWR_INTF_USB_MSK, rtl8723AU_card_enable_flow)) |
| 108 | return _FAIL; |
| 109 | |
| 110 | /* 0x04[19] = 1, suggest by Jackie 2011.05.09, reset 8051 */ |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 111 | value8 = rtl8723au_read8(padapter, REG_APS_FSMCO+2); |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 112 | rtl8723au_write8(padapter, REG_APS_FSMCO + 2, value8 | BIT(3)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 113 | |
| 114 | /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */ |
| 115 | /* Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. |
| 116 | Added by tynli. 2011.08.31. */ |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 117 | value16 = rtl8723au_read16(padapter, REG_CR); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 118 | value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN | |
| 119 | PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | |
| 120 | ENSEC | CALTMR_EN); |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 121 | rtl8723au_write16(padapter, REG_CR, value16); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 122 | |
| 123 | /* for Efuse PG, suggest by Jackie 2011.11.23 */ |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 124 | PHY_SetBBReg(padapter, REG_EFUSE_CTRL, BIT(28)|BIT(29)|BIT(30), 0x06); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 125 | |
| 126 | return status; |
| 127 | } |
| 128 | |
| 129 | /* Shall USB interface init this? */ |
| 130 | static void _InitInterrupt(struct rtw_adapter *Adapter) |
| 131 | { |
| 132 | u32 value32; |
| 133 | |
| 134 | /* HISR - turn all on */ |
| 135 | value32 = 0xFFFFFFFF; |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 136 | rtl8723au_write32(Adapter, REG_HISR, value32); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 137 | |
| 138 | /* HIMR - turn all on */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 139 | rtl8723au_write32(Adapter, REG_HIMR, value32); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | static void _InitQueueReservedPage(struct rtw_adapter *Adapter) |
| 143 | { |
| 144 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 145 | struct registry_priv *pregistrypriv = &Adapter->registrypriv; |
| 146 | u32 numHQ = 0; |
| 147 | u32 numLQ = 0; |
| 148 | u32 numNQ = 0; |
| 149 | u32 numPubQ; |
| 150 | u32 value32; |
| 151 | u8 value8; |
| 152 | bool bWiFiConfig = pregistrypriv->wifi_spec; |
| 153 | /* u32 txQPageNum, txQPageUnit, txQRemainPage; */ |
| 154 | |
| 155 | { /* for WMM */ |
| 156 | /* RT_ASSERT((outEPNum>= 2), ("for WMM , number of out-ep " |
| 157 | "must more than or equal to 2!\n")); */ |
| 158 | |
| 159 | numPubQ = bWiFiConfig ? |
| 160 | WMM_NORMAL_PAGE_NUM_PUBQ : NORMAL_PAGE_NUM_PUBQ; |
| 161 | |
| 162 | if (pHalData->OutEpQueueSel & TX_SELE_HQ) { |
| 163 | numHQ = bWiFiConfig ? |
| 164 | WMM_NORMAL_PAGE_NUM_HPQ : NORMAL_PAGE_NUM_HPQ; |
| 165 | } |
| 166 | |
| 167 | if (pHalData->OutEpQueueSel & TX_SELE_LQ) { |
| 168 | numLQ = bWiFiConfig ? |
| 169 | WMM_NORMAL_PAGE_NUM_LPQ : NORMAL_PAGE_NUM_LPQ; |
| 170 | } |
| 171 | /* NOTE: This step shall be proceed before |
| 172 | writting REG_RQPN. */ |
| 173 | if (pHalData->OutEpQueueSel & TX_SELE_NQ) { |
| 174 | numNQ = bWiFiConfig ? |
| 175 | WMM_NORMAL_PAGE_NUM_NPQ : NORMAL_PAGE_NUM_NPQ; |
| 176 | } |
| 177 | value8 = (u8)_NPQ(numNQ); |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 178 | rtl8723au_write8(Adapter, REG_RQPN_NPQ, value8); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 179 | } |
| 180 | |
| 181 | /* TX DMA */ |
| 182 | value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN; |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 183 | rtl8723au_write32(Adapter, REG_RQPN, value32); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 184 | } |
| 185 | |
| 186 | static void _InitTxBufferBoundary(struct rtw_adapter *Adapter) |
| 187 | { |
| 188 | struct registry_priv *pregistrypriv = &Adapter->registrypriv; |
| 189 | |
| 190 | u8 txpktbuf_bndy; |
| 191 | |
| 192 | if (!pregistrypriv->wifi_spec) |
| 193 | txpktbuf_bndy = TX_PAGE_BOUNDARY; |
| 194 | else /* for WMM */ |
| 195 | txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY; |
| 196 | |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 197 | rtl8723au_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); |
| 198 | rtl8723au_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); |
| 199 | rtl8723au_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy); |
| 200 | rtl8723au_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy); |
| 201 | rtl8723au_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 202 | } |
| 203 | |
| 204 | static void _InitPageBoundary(struct rtw_adapter *Adapter) |
| 205 | { |
| 206 | /* RX Page Boundary */ |
| 207 | /* srand(static_cast<unsigned int>(time(NULL))); */ |
| 208 | u16 rxff_bndy = 0x27FF;/* rand() % 1) ? 0x27FF : 0x23FF; */ |
| 209 | |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 210 | rtl8723au_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 211 | |
| 212 | /* TODO: ?? shall we set tx boundary? */ |
| 213 | } |
| 214 | |
| 215 | static void |
| 216 | _InitNormalChipRegPriority(struct rtw_adapter *Adapter, u16 beQ, u16 bkQ, |
| 217 | u16 viQ, u16 voQ, u16 mgtQ, u16 hiQ) |
| 218 | { |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 219 | u16 value16 = rtl8723au_read16(Adapter, REG_TRXDMA_CTRL) & 0x7; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 220 | |
| 221 | value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) | |
| 222 | _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) | |
| 223 | _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ); |
| 224 | |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 225 | rtl8723au_write16(Adapter, REG_TRXDMA_CTRL, value16); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | static void _InitNormalChipOneOutEpPriority(struct rtw_adapter *Adapter) |
| 229 | { |
| 230 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 231 | u16 value = 0; |
| 232 | |
| 233 | switch (pHalData->OutEpQueueSel) { |
| 234 | case TX_SELE_HQ: |
| 235 | value = QUEUE_HIGH; |
| 236 | break; |
| 237 | case TX_SELE_LQ: |
| 238 | value = QUEUE_LOW; |
| 239 | break; |
| 240 | case TX_SELE_NQ: |
| 241 | value = QUEUE_NORMAL; |
| 242 | break; |
| 243 | default: |
| 244 | /* RT_ASSERT(false, ("Shall not reach here!\n")); */ |
| 245 | break; |
| 246 | } |
| 247 | |
| 248 | _InitNormalChipRegPriority(Adapter, value, value, value, |
| 249 | value, value, value); |
| 250 | } |
| 251 | |
| 252 | static void _InitNormalChipTwoOutEpPriority(struct rtw_adapter *Adapter) |
| 253 | { |
| 254 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 255 | struct registry_priv *pregistrypriv = &Adapter->registrypriv; |
| 256 | u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; |
| 257 | u16 valueHi = 0; |
| 258 | u16 valueLow = 0; |
| 259 | |
| 260 | switch (pHalData->OutEpQueueSel) { |
| 261 | case (TX_SELE_HQ | TX_SELE_LQ): |
| 262 | valueHi = QUEUE_HIGH; |
| 263 | valueLow = QUEUE_LOW; |
| 264 | break; |
| 265 | case (TX_SELE_NQ | TX_SELE_LQ): |
| 266 | valueHi = QUEUE_NORMAL; |
| 267 | valueLow = QUEUE_LOW; |
| 268 | break; |
| 269 | case (TX_SELE_HQ | TX_SELE_NQ): |
| 270 | valueHi = QUEUE_HIGH; |
| 271 | valueLow = QUEUE_NORMAL; |
| 272 | break; |
| 273 | default: |
| 274 | /* RT_ASSERT(false, ("Shall not reach here!\n")); */ |
| 275 | break; |
| 276 | } |
| 277 | |
| 278 | if (!pregistrypriv->wifi_spec) { |
| 279 | beQ = valueLow; |
| 280 | bkQ = valueLow; |
| 281 | viQ = valueHi; |
| 282 | voQ = valueHi; |
| 283 | mgtQ = valueHi; |
| 284 | hiQ = valueHi; |
| 285 | } else {/* for WMM , CONFIG_OUT_EP_WIFI_MODE */ |
| 286 | beQ = valueLow; |
| 287 | bkQ = valueHi; |
| 288 | viQ = valueHi; |
| 289 | voQ = valueLow; |
| 290 | mgtQ = valueHi; |
| 291 | hiQ = valueHi; |
| 292 | } |
| 293 | |
| 294 | _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ); |
| 295 | } |
| 296 | |
| 297 | static void _InitNormalChipThreeOutEpPriority(struct rtw_adapter *Adapter) |
| 298 | { |
| 299 | struct registry_priv *pregistrypriv = &Adapter->registrypriv; |
| 300 | u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; |
| 301 | |
| 302 | if (!pregistrypriv->wifi_spec) {/* typical setting */ |
| 303 | beQ = QUEUE_LOW; |
| 304 | bkQ = QUEUE_LOW; |
| 305 | viQ = QUEUE_NORMAL; |
| 306 | voQ = QUEUE_HIGH; |
| 307 | mgtQ = QUEUE_HIGH; |
| 308 | hiQ = QUEUE_HIGH; |
| 309 | } else {/* for WMM */ |
| 310 | beQ = QUEUE_LOW; |
| 311 | bkQ = QUEUE_NORMAL; |
| 312 | viQ = QUEUE_NORMAL; |
| 313 | voQ = QUEUE_HIGH; |
| 314 | mgtQ = QUEUE_HIGH; |
| 315 | hiQ = QUEUE_HIGH; |
| 316 | } |
| 317 | _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ); |
| 318 | } |
| 319 | |
| 320 | static void _InitNormalChipQueuePriority(struct rtw_adapter *Adapter) |
| 321 | { |
| 322 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 323 | |
| 324 | switch (pHalData->OutEpNumber) { |
| 325 | case 1: |
| 326 | _InitNormalChipOneOutEpPriority(Adapter); |
| 327 | break; |
| 328 | case 2: |
| 329 | _InitNormalChipTwoOutEpPriority(Adapter); |
| 330 | break; |
| 331 | case 3: |
| 332 | _InitNormalChipThreeOutEpPriority(Adapter); |
| 333 | break; |
| 334 | default: |
| 335 | /* RT_ASSERT(false, ("Shall not reach here!\n")); */ |
| 336 | break; |
| 337 | } |
| 338 | } |
| 339 | |
| 340 | static void _InitQueuePriority(struct rtw_adapter *Adapter) |
| 341 | { |
| 342 | _InitNormalChipQueuePriority(Adapter); |
| 343 | } |
| 344 | |
| 345 | static void _InitNetworkType(struct rtw_adapter *Adapter) |
| 346 | { |
| 347 | u32 value32; |
| 348 | |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 349 | value32 = rtl8723au_read32(Adapter, REG_CR); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 350 | |
| 351 | /* TODO: use the other function to set network type */ |
| 352 | value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP); |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 353 | rtl8723au_write32(Adapter, REG_CR, value32); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 354 | } |
| 355 | |
| 356 | static void _InitTransferPageSize(struct rtw_adapter *Adapter) |
| 357 | { |
| 358 | /* Tx page size is always 128. */ |
| 359 | |
| 360 | u8 value8; |
| 361 | value8 = _PSRX(PBP_128) | _PSTX(PBP_128); |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 362 | rtl8723au_write8(Adapter, REG_PBP, value8); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 363 | } |
| 364 | |
| 365 | static void _InitDriverInfoSize(struct rtw_adapter *Adapter, u8 drvInfoSize) |
| 366 | { |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 367 | rtl8723au_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 368 | } |
| 369 | |
| 370 | static void _InitWMACSetting(struct rtw_adapter *Adapter) |
| 371 | { |
| 372 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 373 | |
| 374 | /* don't turn on AAP, it will allow all packets to driver */ |
| 375 | pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB | RCR_CBSSID_DATA | |
| 376 | RCR_CBSSID_BCN | RCR_APP_ICV | RCR_AMF | |
| 377 | RCR_HTC_LOC_CTRL | RCR_APP_MIC | |
| 378 | RCR_APP_PHYSTS; |
| 379 | |
| 380 | /* some REG_RCR will be modified later by |
| 381 | phy_ConfigMACWithHeaderFile() */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 382 | rtl8723au_write32(Adapter, REG_RCR, pHalData->ReceiveConfig); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 383 | |
| 384 | /* Accept all multicast address */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 385 | rtl8723au_write32(Adapter, REG_MAR, 0xFFFFFFFF); |
| 386 | rtl8723au_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 387 | |
| 388 | /* Accept all data frames */ |
| 389 | /* value16 = 0xFFFF; */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 390 | /* rtl8723au_write16(Adapter, REG_RXFLTMAP2, value16); */ |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 391 | |
| 392 | /* 2010.09.08 hpfan */ |
| 393 | /* Since ADF is removed from RCR, ps-poll will not be indicate |
| 394 | to driver, */ |
| 395 | /* RxFilterMap should mask ps-poll to gurantee AP mode can |
| 396 | rx ps-poll. */ |
| 397 | /* value16 = 0x400; */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 398 | /* rtl8723au_write16(Adapter, REG_RXFLTMAP1, value16); */ |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 399 | |
| 400 | /* Accept all management frames */ |
| 401 | /* value16 = 0xFFFF; */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 402 | /* rtl8723au_write16(Adapter, REG_RXFLTMAP0, value16); */ |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 403 | |
| 404 | /* enable RX_SHIFT bits */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 405 | /* rtl8723au_write8(Adapter, REG_TRXDMA_CTRL, rtl8723au_read8(Adapter, |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 406 | REG_TRXDMA_CTRL)|BIT(1)); */ |
| 407 | } |
| 408 | |
| 409 | static void _InitAdaptiveCtrl(struct rtw_adapter *Adapter) |
| 410 | { |
| 411 | u16 value16; |
| 412 | u32 value32; |
| 413 | |
| 414 | /* Response Rate Set */ |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 415 | value32 = rtl8723au_read32(Adapter, REG_RRSR); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 416 | value32 &= ~RATE_BITMAP_ALL; |
| 417 | value32 |= RATE_RRSR_CCK_ONLY_1M; |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 418 | rtl8723au_write32(Adapter, REG_RRSR, value32); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 419 | |
| 420 | /* CF-END Threshold */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 421 | /* m_spIoBase->rtl8723au_write8(REG_CFEND_TH, 0x1); */ |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 422 | |
| 423 | /* SIFS (used in NAV) */ |
| 424 | value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10); |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 425 | rtl8723au_write16(Adapter, REG_SPEC_SIFS, value16); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 426 | |
| 427 | /* Retry Limit */ |
| 428 | value16 = _LRL(0x30) | _SRL(0x30); |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 429 | rtl8723au_write16(Adapter, REG_RL, value16); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 430 | } |
| 431 | |
| 432 | static void _InitRateFallback(struct rtw_adapter *Adapter) |
| 433 | { |
| 434 | /* Set Data Auto Rate Fallback Retry Count register. */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 435 | rtl8723au_write32(Adapter, REG_DARFRC, 0x00000000); |
| 436 | rtl8723au_write32(Adapter, REG_DARFRC+4, 0x10080404); |
| 437 | rtl8723au_write32(Adapter, REG_RARFRC, 0x04030201); |
| 438 | rtl8723au_write32(Adapter, REG_RARFRC+4, 0x08070605); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 439 | } |
| 440 | |
| 441 | static void _InitEDCA(struct rtw_adapter *Adapter) |
| 442 | { |
| 443 | /* Set Spec SIFS (used in NAV) */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 444 | rtl8723au_write16(Adapter, REG_SPEC_SIFS, 0x100a); |
| 445 | rtl8723au_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 446 | |
| 447 | /* Set SIFS for CCK */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 448 | rtl8723au_write16(Adapter, REG_SIFS_CTX, 0x100a); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 449 | |
| 450 | /* Set SIFS for OFDM */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 451 | rtl8723au_write16(Adapter, REG_SIFS_TRX, 0x100a); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 452 | |
| 453 | /* TXOP */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 454 | rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B); |
| 455 | rtl8723au_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F); |
| 456 | rtl8723au_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324); |
| 457 | rtl8723au_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 458 | } |
| 459 | |
| 460 | static void _InitHWLed(struct rtw_adapter *Adapter) |
| 461 | { |
| 462 | struct led_priv *pledpriv = &Adapter->ledpriv; |
| 463 | |
| 464 | if (pledpriv->LedStrategy != HW_LED) |
| 465 | return; |
| 466 | |
| 467 | /* HW led control */ |
| 468 | /* to do .... */ |
| 469 | /* must consider cases of antenna diversity/ commbo card/solo card/mini card */ |
| 470 | } |
| 471 | |
| 472 | static void _InitRDGSetting(struct rtw_adapter *Adapter) |
| 473 | { |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 474 | rtl8723au_write8(Adapter, REG_RD_CTRL, 0xFF); |
| 475 | rtl8723au_write16(Adapter, REG_RD_NAV_NXT, 0x200); |
| 476 | rtl8723au_write8(Adapter, REG_RD_RESP_PKT_TH, 0x05); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 477 | } |
| 478 | |
| 479 | static void _InitRetryFunction(struct rtw_adapter *Adapter) |
| 480 | { |
| 481 | u8 value8; |
| 482 | |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 483 | value8 = rtl8723au_read8(Adapter, REG_FWHW_TXQ_CTRL); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 484 | value8 |= EN_AMPDU_RTY_NEW; |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 485 | rtl8723au_write8(Adapter, REG_FWHW_TXQ_CTRL, value8); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 486 | |
| 487 | /* Set ACK timeout */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 488 | rtl8723au_write8(Adapter, REG_ACKTO, 0x40); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 489 | } |
| 490 | |
| 491 | /*----------------------------------------------------------------------------- |
| 492 | * Function: usb_AggSettingTxUpdate() |
| 493 | * |
| 494 | * Overview: Seperate TX/RX parameters update independent for TP |
| 495 | * detection and dynamic TX/RX aggreagtion parameters update. |
| 496 | * |
| 497 | * Input: struct rtw_adapter * |
| 498 | * |
| 499 | * Output/Return: NONE |
| 500 | * |
| 501 | * Revised History: |
| 502 | * When Who Remark |
| 503 | * 12/10/2010 MHC Seperate to smaller function. |
| 504 | * |
| 505 | *---------------------------------------------------------------------------*/ |
| 506 | static void usb_AggSettingTxUpdate(struct rtw_adapter *Adapter) |
| 507 | { |
| 508 | } /* usb_AggSettingTxUpdate */ |
| 509 | |
| 510 | /*----------------------------------------------------------------------------- |
| 511 | * Function: usb_AggSettingRxUpdate() |
| 512 | * |
| 513 | * Overview: Seperate TX/RX parameters update independent for TP |
| 514 | * detection and dynamic TX/RX aggreagtion parameters update. |
| 515 | * |
| 516 | * Input: struct rtw_adapter * |
| 517 | * |
| 518 | * Output/Return: NONE |
| 519 | * |
| 520 | * Revised History: |
| 521 | * When Who Remark |
| 522 | * 12/10/2010 MHC Seperate to smaller function. |
| 523 | * |
| 524 | *---------------------------------------------------------------------------*/ |
| 525 | static void usb_AggSettingRxUpdate(struct rtw_adapter *Adapter) |
| 526 | { |
| 527 | } /* usb_AggSettingRxUpdate */ |
| 528 | |
| 529 | static void InitUsbAggregationSetting(struct rtw_adapter *Adapter) |
| 530 | { |
| 531 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 532 | |
| 533 | /* Tx aggregation setting */ |
| 534 | usb_AggSettingTxUpdate(Adapter); |
| 535 | |
| 536 | /* Rx aggregation setting */ |
| 537 | usb_AggSettingRxUpdate(Adapter); |
| 538 | |
| 539 | /* 201/12/10 MH Add for USB agg mode dynamic switch. */ |
| 540 | pHalData->UsbRxHighSpeedMode = false; |
| 541 | } |
| 542 | |
| 543 | static void _InitOperationMode(struct rtw_adapter *Adapter) |
| 544 | { |
| 545 | } |
| 546 | |
| 547 | static void _InitRFType(struct rtw_adapter *Adapter) |
| 548 | { |
| 549 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 550 | bool is92CU = IS_92C_SERIAL(pHalData->VersionID); |
| 551 | |
| 552 | pHalData->rf_chip = RF_6052; |
| 553 | |
| 554 | if (is92CU == false) { |
| 555 | pHalData->rf_type = RF_1T1R; |
| 556 | DBG_8723A("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n"); |
| 557 | return; |
| 558 | } |
| 559 | |
| 560 | /* TODO: Consider that EEPROM set 92CU to 1T1R later. */ |
| 561 | /* Force to overwrite setting according to chip version. Ignore |
| 562 | EEPROM setting. */ |
| 563 | /* pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R; */ |
| 564 | MSG_8723A("Set RF Chip ID to RF_6052 and RF type to %d.\n", |
| 565 | pHalData->rf_type); |
| 566 | } |
| 567 | |
| 568 | /* Set CCK and OFDM Block "ON" */ |
| 569 | static void _BBTurnOnBlock(struct rtw_adapter *Adapter) |
| 570 | { |
| 571 | PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1); |
| 572 | PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1); |
| 573 | } |
| 574 | |
| 575 | #define MgntActSet_RF_State(...) |
| 576 | static void _RfPowerSave(struct rtw_adapter *padapter) |
| 577 | { |
| 578 | } |
| 579 | |
| 580 | enum { |
| 581 | Antenna_Lfet = 1, |
| 582 | Antenna_Right = 2, |
| 583 | }; |
| 584 | |
| 585 | enum rt_rf_power_state RfOnOffDetect23a(struct rtw_adapter *pAdapter) |
| 586 | { |
| 587 | /* struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter); */ |
| 588 | u8 val8; |
| 589 | enum rt_rf_power_state rfpowerstate = rf_off; |
| 590 | |
| 591 | if (pAdapter->pwrctrlpriv.bHWPowerdown) { |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 592 | val8 = rtl8723au_read8(pAdapter, REG_HSISR); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 593 | DBG_8723A("pwrdown, 0x5c(BIT7) =%02x\n", val8); |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 594 | rfpowerstate = (val8 & BIT(7)) ? rf_off : rf_on; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 595 | } else { /* rf on/off */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 596 | rtl8723au_write8(pAdapter, REG_MAC_PINMUX_CFG, |
| 597 | rtl8723au_read8(pAdapter, REG_MAC_PINMUX_CFG) & |
| 598 | ~BIT(3)); |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 599 | val8 = rtl8723au_read8(pAdapter, REG_GPIO_IO_SEL); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 600 | DBG_8723A("GPIO_IN =%02x\n", val8); |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 601 | rfpowerstate = (val8 & BIT(3)) ? rf_on : rf_off; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 602 | } |
| 603 | return rfpowerstate; |
| 604 | } /* HalDetectPwrDownMode */ |
| 605 | |
| 606 | void _ps_open_RF23a(struct rtw_adapter *padapter); |
| 607 | |
Jes Sorensen | c7772697 | 2014-05-16 10:04:16 +0200 | [diff] [blame] | 608 | static int rtl8723au_hal_init(struct rtw_adapter *Adapter) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 609 | { |
Jes Sorensen | c7772697 | 2014-05-16 10:04:16 +0200 | [diff] [blame] | 610 | u8 val8 = 0; |
| 611 | u32 boundary; |
| 612 | int status = _SUCCESS; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 613 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 614 | struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv; |
| 615 | struct registry_priv *pregistrypriv = &Adapter->registrypriv; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 616 | |
| 617 | unsigned long init_start_time = jiffies; |
| 618 | |
| 619 | #define HAL_INIT_PROFILE_TAG(stage) do {} while (0) |
| 620 | |
| 621 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN); |
| 622 | if (Adapter->pwrctrlpriv.bkeepfwalive) { |
| 623 | _ps_open_RF23a(Adapter); |
| 624 | |
| 625 | if (pHalData->bIQKInitialized) { |
| 626 | rtl8723a_phy_iq_calibrate(Adapter, true); |
| 627 | } else { |
| 628 | rtl8723a_phy_iq_calibrate(Adapter, false); |
| 629 | pHalData->bIQKInitialized = true; |
| 630 | } |
| 631 | rtl8723a_odm_check_tx_power_tracking(Adapter); |
| 632 | rtl8723a_phy_lc_calibrate(Adapter); |
| 633 | |
| 634 | goto exit; |
| 635 | } |
| 636 | |
| 637 | /* Check if MAC has already power on. by tynli. 2011.05.27. */ |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 638 | val8 = rtl8723au_read8(Adapter, REG_CR); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 639 | RT_TRACE(_module_hci_hal_init_c_, _drv_info_, |
| 640 | ("%s: REG_CR 0x100 = 0x%02x\n", __func__, val8)); |
| 641 | /* Fix 92DU-VC S3 hang with the reason is that secondary mac is not |
| 642 | initialized. */ |
| 643 | /* 0x100 value of first mac is 0xEA while 0x100 value of secondary |
| 644 | is 0x00 */ |
| 645 | if (val8 == 0xEA) { |
| 646 | pHalData->bMACFuncEnable = false; |
| 647 | } else { |
| 648 | pHalData->bMACFuncEnable = true; |
| 649 | RT_TRACE(_module_hci_hal_init_c_, _drv_info_, |
| 650 | ("%s: MAC has already power on\n", __func__)); |
| 651 | } |
| 652 | |
| 653 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON); |
| 654 | status = _InitPowerOn(Adapter); |
| 655 | if (status == _FAIL) { |
| 656 | RT_TRACE(_module_hci_hal_init_c_, _drv_err_, |
| 657 | ("Failed to init power on!\n")); |
| 658 | goto exit; |
| 659 | } |
| 660 | |
| 661 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT); |
| 662 | if (!pregistrypriv->wifi_spec) { |
| 663 | boundary = TX_PAGE_BOUNDARY; |
| 664 | } else { |
| 665 | /* for WMM */ |
| 666 | boundary = WMM_NORMAL_TX_PAGE_BOUNDARY; |
| 667 | } |
| 668 | |
| 669 | if (!pHalData->bMACFuncEnable) { |
| 670 | status = InitLLTTable23a(Adapter, boundary); |
| 671 | if (status == _FAIL) { |
| 672 | RT_TRACE(_module_hci_hal_init_c_, _drv_err_, |
| 673 | ("Failed to init LLT table\n")); |
| 674 | goto exit; |
| 675 | } |
| 676 | } |
| 677 | |
| 678 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01); |
| 679 | if (pHalData->bRDGEnable) |
| 680 | _InitRDGSetting(Adapter); |
| 681 | |
| 682 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW); |
| 683 | status = rtl8723a_FirmwareDownload(Adapter); |
| 684 | if (status != _SUCCESS) { |
| 685 | Adapter->bFWReady = false; |
| 686 | pHalData->fw_ractrl = false; |
| 687 | DBG_8723A("fw download fail!\n"); |
| 688 | goto exit; |
| 689 | } else { |
| 690 | Adapter->bFWReady = true; |
| 691 | pHalData->fw_ractrl = true; |
| 692 | DBG_8723A("fw download ok!\n"); |
| 693 | } |
| 694 | |
| 695 | rtl8723a_InitializeFirmwareVars(Adapter); |
| 696 | |
| 697 | if (pwrctrlpriv->reg_rfoff == true) { |
| 698 | pwrctrlpriv->rf_pwrstate = rf_off; |
| 699 | } |
| 700 | |
| 701 | /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */ |
| 702 | /* HW GPIO pin. Before PHY_RFConfig8192C. */ |
| 703 | /* HalDetectPwrDownMode(Adapter); */ |
| 704 | /* 2010/08/26 MH If Efuse does not support sective suspend then disable the function. */ |
| 705 | /* HalDetectSelectiveSuspendMode(Adapter); */ |
| 706 | |
| 707 | /* Set RF type for BB/RF configuration */ |
| 708 | _InitRFType(Adapter);/* _ReadRFType() */ |
| 709 | |
| 710 | /* Save target channel */ |
| 711 | /* <Roger_Notes> Current Channel will be updated again later. */ |
| 712 | pHalData->CurrentChannel = 6;/* default set to 6 */ |
| 713 | |
| 714 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC); |
| 715 | status = PHY_MACConfig8723A(Adapter); |
| 716 | if (status == _FAIL) { |
| 717 | DBG_8723A("PHY_MACConfig8723A fault !!\n"); |
| 718 | goto exit; |
| 719 | } |
| 720 | |
| 721 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB); |
| 722 | /* */ |
| 723 | /* d. Initialize BB related configurations. */ |
| 724 | /* */ |
| 725 | status = PHY_BBConfig8723A(Adapter); |
| 726 | if (status == _FAIL) { |
| 727 | DBG_8723A("PHY_BBConfig8723A fault !!\n"); |
| 728 | goto exit; |
| 729 | } |
| 730 | |
| 731 | /* Add for tx power by rate fine tune. We need to call the function after BB config. */ |
| 732 | /* Because the tx power by rate table is inited in BB config. */ |
| 733 | |
| 734 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF); |
| 735 | status = PHY_RFConfig8723A(Adapter); |
| 736 | if (status == _FAIL) { |
| 737 | DBG_8723A("PHY_RFConfig8723A fault !!\n"); |
| 738 | goto exit; |
| 739 | } |
| 740 | |
| 741 | /* reducing 80M spur */ |
| 742 | PHY_SetBBReg(Adapter, RF_T_METER, bMaskDWord, 0x0381808d); |
| 743 | PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83); |
| 744 | PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff82); |
| 745 | PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83); |
| 746 | |
| 747 | /* RFSW Control */ |
| 748 | PHY_SetBBReg(Adapter, rFPGA0_TxInfo, bMaskDWord, 0x00000003); /* 0x804[14]= 0 */ |
| 749 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFInterfaceSW, bMaskDWord, 0x07000760); /* 0x870[6:5]= b'11 */ |
| 750 | PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, 0x66F60210); /* 0x860[6:5]= b'00 */ |
| 751 | |
| 752 | RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("%s: 0x870 = value 0x%x\n", __func__, PHY_QueryBBReg(Adapter, 0x870, bMaskDWord))); |
| 753 | |
| 754 | /* */ |
| 755 | /* Joseph Note: Keep RfRegChnlVal for later use. */ |
| 756 | /* */ |
| 757 | pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (enum RF_RADIO_PATH)0, RF_CHNLBW, bRFRegOffsetMask); |
| 758 | pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (enum RF_RADIO_PATH)1, RF_CHNLBW, bRFRegOffsetMask); |
| 759 | |
| 760 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02); |
| 761 | if (!pHalData->bMACFuncEnable) { |
| 762 | _InitQueueReservedPage(Adapter); |
| 763 | _InitTxBufferBoundary(Adapter); |
| 764 | } |
| 765 | _InitQueuePriority(Adapter); |
| 766 | _InitPageBoundary(Adapter); |
| 767 | _InitTransferPageSize(Adapter); |
| 768 | |
| 769 | /* Get Rx PHY status in order to report RSSI and others. */ |
| 770 | _InitDriverInfoSize(Adapter, DRVINFO_SZ); |
| 771 | |
| 772 | _InitInterrupt(Adapter); |
Jes Sorensen | 3c5660e | 2014-04-09 23:20:19 +0200 | [diff] [blame] | 773 | hw_var_set_macaddr(Adapter, Adapter->eeprompriv.mac_addr); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 774 | _InitNetworkType(Adapter);/* set msr */ |
| 775 | _InitWMACSetting(Adapter); |
| 776 | _InitAdaptiveCtrl(Adapter); |
| 777 | _InitEDCA(Adapter); |
| 778 | _InitRateFallback(Adapter); |
| 779 | _InitRetryFunction(Adapter); |
| 780 | InitUsbAggregationSetting(Adapter); |
| 781 | _InitOperationMode(Adapter);/* todo */ |
| 782 | rtl8723a_InitBeaconParameters(Adapter); |
| 783 | |
| 784 | _InitHWLed(Adapter); |
| 785 | |
| 786 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK); |
| 787 | _BBTurnOnBlock(Adapter); |
| 788 | /* NicIFSetMacAddress(padapter, padapter->PermanentAddress); */ |
| 789 | |
| 790 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY); |
| 791 | invalidate_cam_all23a(Adapter); |
| 792 | |
| 793 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11); |
| 794 | /* 2010/12/17 MH We need to set TX power according to EFUSE content at first. */ |
| 795 | PHY_SetTxPowerLevel8723A(Adapter, pHalData->CurrentChannel); |
| 796 | |
| 797 | rtl8723a_InitAntenna_Selection(Adapter); |
| 798 | |
| 799 | /* HW SEQ CTRL */ |
| 800 | /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 801 | rtl8723au_write8(Adapter, REG_HWSEQ_CTRL, 0xFF); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 802 | |
| 803 | /* */ |
| 804 | /* Disable BAR, suggested by Scott */ |
| 805 | /* 2010.04.09 add by hpfan */ |
| 806 | /* */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 807 | rtl8723au_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 808 | |
| 809 | if (pregistrypriv->wifi_spec) |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 810 | rtl8723au_write16(Adapter, REG_FAST_EDCA_CTRL, 0); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 811 | |
| 812 | /* Move by Neo for USB SS from above setp */ |
| 813 | _RfPowerSave(Adapter); |
| 814 | |
| 815 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK); |
| 816 | /* 2010/08/26 MH Merge from 8192CE. */ |
| 817 | /* sherry masked that it has been done in _RfPowerSave */ |
| 818 | /* 20110927 */ |
| 819 | /* recovery for 8192cu and 9723Au 20111017 */ |
| 820 | if (pwrctrlpriv->rf_pwrstate == rf_on) { |
| 821 | if (pHalData->bIQKInitialized) { |
| 822 | rtl8723a_phy_iq_calibrate(Adapter, true); |
| 823 | } else { |
| 824 | rtl8723a_phy_iq_calibrate(Adapter, false); |
| 825 | pHalData->bIQKInitialized = true; |
| 826 | } |
| 827 | |
| 828 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK); |
| 829 | rtl8723a_odm_check_tx_power_tracking(Adapter); |
| 830 | |
| 831 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK); |
| 832 | rtl8723a_phy_lc_calibrate(Adapter); |
| 833 | |
| 834 | #ifdef CONFIG_8723AU_BT_COEXIST |
| 835 | rtl8723a_SingleDualAntennaDetection(Adapter); |
| 836 | #endif |
| 837 | } |
| 838 | |
| 839 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC21); |
| 840 | /* fixed USB interface interference issue */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 841 | rtl8723au_write8(Adapter, 0xfe40, 0xe0); |
| 842 | rtl8723au_write8(Adapter, 0xfe41, 0x8d); |
| 843 | rtl8723au_write8(Adapter, 0xfe42, 0x80); |
| 844 | rtl8723au_write32(Adapter, 0x20c, 0xfd0320); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 845 | /* Solve too many protocol error on USB bus */ |
| 846 | if (!IS_81xxC_VENDOR_UMC_A_CUT(pHalData->VersionID)) { |
| 847 | /* 0xE6 = 0x94 */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 848 | rtl8723au_write8(Adapter, 0xFE40, 0xE6); |
| 849 | rtl8723au_write8(Adapter, 0xFE41, 0x94); |
| 850 | rtl8723au_write8(Adapter, 0xFE42, 0x80); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 851 | |
| 852 | /* 0xE0 = 0x19 */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 853 | rtl8723au_write8(Adapter, 0xFE40, 0xE0); |
| 854 | rtl8723au_write8(Adapter, 0xFE41, 0x19); |
| 855 | rtl8723au_write8(Adapter, 0xFE42, 0x80); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 856 | |
| 857 | /* 0xE5 = 0x91 */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 858 | rtl8723au_write8(Adapter, 0xFE40, 0xE5); |
| 859 | rtl8723au_write8(Adapter, 0xFE41, 0x91); |
| 860 | rtl8723au_write8(Adapter, 0xFE42, 0x80); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 861 | |
| 862 | /* 0xE2 = 0x81 */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 863 | rtl8723au_write8(Adapter, 0xFE40, 0xE2); |
| 864 | rtl8723au_write8(Adapter, 0xFE41, 0x81); |
| 865 | rtl8723au_write8(Adapter, 0xFE42, 0x80); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 866 | |
| 867 | } |
| 868 | |
| 869 | /* HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); */ |
| 870 | /* _InitPABias(Adapter); */ |
| 871 | |
| 872 | #ifdef CONFIG_8723AU_BT_COEXIST |
| 873 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BT_COEXIST); |
| 874 | /* Init BT hw config. */ |
| 875 | BT_InitHwConfig(Adapter); |
| 876 | #endif |
| 877 | |
| 878 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM); |
| 879 | rtl8723a_InitHalDm(Adapter); |
| 880 | |
| 881 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC31); |
Jes Sorensen | 6883e7c | 2014-04-09 23:20:41 +0200 | [diff] [blame] | 882 | rtl8723a_set_nav_upper(Adapter, WiFiNavUpperUs); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 883 | |
| 884 | /* 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, but we need to fin root cause. */ |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 885 | if (((rtl8723au_read32(Adapter, rFPGA0_RFMOD) & 0xFF000000) != |
| 886 | 0x83000000)) { |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 887 | PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(24), 1); |
| 888 | RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("%s: IQK fail recorver\n", __func__)); |
| 889 | } |
| 890 | |
| 891 | /* ack for xmit mgmt frames. */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 892 | rtl8723au_write32(Adapter, REG_FWHW_TXQ_CTRL, |
| 893 | rtl8723au_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 894 | |
| 895 | exit: |
| 896 | HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END); |
| 897 | |
| 898 | DBG_8723A("%s in %dms\n", __func__, |
| 899 | jiffies_to_msecs(jiffies - init_start_time)); |
| 900 | return status; |
| 901 | } |
| 902 | |
| 903 | static void phy_SsPwrSwitch92CU(struct rtw_adapter *Adapter, |
| 904 | enum rt_rf_power_state eRFPowerState, |
| 905 | int bRegSSPwrLvl) |
| 906 | { |
| 907 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 908 | u8 value8; |
| 909 | u8 bytetmp; |
| 910 | |
| 911 | switch (eRFPowerState) { |
| 912 | case rf_on: |
| 913 | if (bRegSSPwrLvl == 1) { |
| 914 | /* 1. Enable MAC Clock. Can not be enabled now. */ |
| 915 | /* WriteXBYTE(REG_SYS_CLKR+1, |
| 916 | ReadXBYTE(REG_SYS_CLKR+1) | BIT(3)); */ |
| 917 | |
| 918 | /* 2. Force PWM, Enable SPS18_LDO_Marco_Block */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 919 | rtl8723au_write8(Adapter, REG_SPS0_CTRL, |
| 920 | rtl8723au_read8(Adapter, REG_SPS0_CTRL) | |
| 921 | BIT(0) | BIT(3)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 922 | |
| 923 | /* 3. restore BB, AFE control register. */ |
| 924 | /* RF */ |
| 925 | if (pHalData->rf_type == RF_2T2R) |
| 926 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 927 | 0x380038, 1); |
| 928 | else |
| 929 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 930 | 0x38, 1); |
| 931 | PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1); |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 932 | PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 0); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 933 | |
| 934 | /* AFE */ |
| 935 | if (pHalData->rf_type == RF_2T2R) |
| 936 | PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord, |
| 937 | 0x63DB25A0); |
| 938 | else if (pHalData->rf_type == RF_1T1R) |
| 939 | PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord, |
| 940 | 0x631B25A0); |
| 941 | |
| 942 | /* 4. issue 3-wire command that RF set to Rx idle |
| 943 | mode. This is used to re-write the RX idle mode. */ |
| 944 | /* We can only prvide a usual value instead and then |
| 945 | HW will modify the value by itself. */ |
| 946 | PHY_SetRFReg(Adapter, RF_PATH_A, 0, |
| 947 | bRFRegOffsetMask, 0x32D95); |
| 948 | if (pHalData->rf_type == RF_2T2R) { |
| 949 | PHY_SetRFReg(Adapter, RF_PATH_B, 0, |
| 950 | bRFRegOffsetMask, 0x32D95); |
| 951 | } |
| 952 | } else { /* Level 2 or others. */ |
| 953 | /* h. AFE_PLL_CTRL 0x28[7:0] = 0x80 |
| 954 | disable AFE PLL */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 955 | rtl8723au_write8(Adapter, REG_AFE_PLL_CTRL, 0x81); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 956 | |
| 957 | /* i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F |
| 958 | gated AFE DIG_CLOCK */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 959 | rtl8723au_write16(Adapter, REG_AFE_XTAL_CTRL, 0x800F); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 960 | mdelay(1); |
| 961 | |
| 962 | /* 2. Force PWM, Enable SPS18_LDO_Marco_Block */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 963 | rtl8723au_write8(Adapter, REG_SPS0_CTRL, |
| 964 | rtl8723au_read8(Adapter, REG_SPS0_CTRL) | |
| 965 | BIT(0) | BIT(3)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 966 | |
| 967 | /* 3. restore BB, AFE control register. */ |
| 968 | /* RF */ |
| 969 | if (pHalData->rf_type == RF_2T2R) |
| 970 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 971 | 0x380038, 1); |
| 972 | else |
| 973 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 974 | 0x38, 1); |
| 975 | PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1); |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 976 | PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 0); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 977 | |
| 978 | /* AFE */ |
| 979 | if (pHalData->rf_type == RF_2T2R) |
| 980 | PHY_SetBBReg(Adapter, rRx_Wait_CCA, |
| 981 | bMaskDWord, 0x63DB25A0); |
| 982 | else if (pHalData->rf_type == RF_1T1R) |
| 983 | PHY_SetBBReg(Adapter, rRx_Wait_CCA, |
| 984 | bMaskDWord, 0x631B25A0); |
| 985 | |
| 986 | /* 4. issue 3-wire command that RF set to Rx idle |
| 987 | mode. This is used to re-write the RX idle mode. */ |
| 988 | /* We can only prvide a usual value instead and |
| 989 | then HW will modify the value by itself. */ |
| 990 | PHY_SetRFReg(Adapter, RF_PATH_A, 0, |
| 991 | bRFRegOffsetMask, 0x32D95); |
| 992 | if (pHalData->rf_type == RF_2T2R) { |
| 993 | PHY_SetRFReg(Adapter, RF_PATH_B, 0, |
| 994 | bRFRegOffsetMask, 0x32D95); |
| 995 | } |
| 996 | |
| 997 | /* 5. gated MAC Clock */ |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 998 | bytetmp = rtl8723au_read8(Adapter, REG_APSD_CTRL); |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 999 | rtl8723au_write8(Adapter, REG_APSD_CTRL, |
| 1000 | bytetmp & ~BIT(6)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1001 | |
| 1002 | mdelay(10); |
| 1003 | |
| 1004 | /* Set BB reset at first */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1005 | /* 0x16 */ |
| 1006 | rtl8723au_write8(Adapter, REG_SYS_FUNC_EN, 0x17); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1007 | |
| 1008 | /* Enable TX */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1009 | rtl8723au_write8(Adapter, REG_TXPAUSE, 0x0); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1010 | } |
| 1011 | break; |
| 1012 | case rf_sleep: |
| 1013 | case rf_off: |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 1014 | value8 = rtl8723au_read8(Adapter, REG_SPS0_CTRL) ; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1015 | if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)) |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 1016 | value8 &= ~BIT(0); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1017 | else |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 1018 | value8 &= ~(BIT(0) | BIT(3)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1019 | if (bRegSSPwrLvl == 1) { |
| 1020 | RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL1\n")); |
| 1021 | /* Disable RF and BB only for SelectSuspend. */ |
| 1022 | |
| 1023 | /* 1. Set BB/RF to shutdown. */ |
| 1024 | /* (1) Reg878[5:3]= 0 RF rx_code for |
| 1025 | preamble power saving */ |
| 1026 | /* (2)Reg878[21:19]= 0 Turn off RF-B */ |
| 1027 | /* (3) RegC04[7:4]= 0 Turn off all paths |
| 1028 | for packet detection */ |
| 1029 | /* (4) Reg800[1] = 1 enable preamble power |
| 1030 | saving */ |
| 1031 | Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = |
| 1032 | PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 1033 | bMaskDWord); |
| 1034 | Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = |
| 1035 | PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, |
| 1036 | bMaskDWord); |
| 1037 | Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = |
| 1038 | PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, |
| 1039 | bMaskDWord); |
| 1040 | if (pHalData->rf_type == RF_2T2R) { |
| 1041 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 1042 | 0x380038, 0); |
| 1043 | } else if (pHalData->rf_type == RF_1T1R) { |
| 1044 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 1045 | 0x38, 0); |
| 1046 | } |
| 1047 | PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0); |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 1048 | PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 1); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1049 | |
| 1050 | /* 2 .AFE control register to power down. bit[30:22] */ |
| 1051 | Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = |
| 1052 | PHY_QueryBBReg(Adapter, rRx_Wait_CCA, |
| 1053 | bMaskDWord); |
| 1054 | if (pHalData->rf_type == RF_2T2R) |
| 1055 | PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord, |
| 1056 | 0x00DB25A0); |
| 1057 | else if (pHalData->rf_type == RF_1T1R) |
| 1058 | PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord, |
| 1059 | 0x001B25A0); |
| 1060 | |
| 1061 | /* 3. issue 3-wire command that RF set to power down.*/ |
| 1062 | PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0); |
| 1063 | if (pHalData->rf_type == RF_2T2R) |
| 1064 | PHY_SetRFReg(Adapter, RF_PATH_B, 0, |
| 1065 | bRFRegOffsetMask, 0); |
| 1066 | |
| 1067 | /* 4. Force PFM , disable SPS18_LDO_Marco_Block */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1068 | rtl8723au_write8(Adapter, REG_SPS0_CTRL, value8); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1069 | } else { /* Level 2 or others. */ |
| 1070 | RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL2\n")); |
| 1071 | { |
| 1072 | u8 eRFPath = RF_PATH_A, value8 = 0; |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1073 | rtl8723au_write8(Adapter, REG_TXPAUSE, 0xFF); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1074 | PHY_SetRFReg(Adapter, |
| 1075 | (enum RF_RADIO_PATH)eRFPath, |
| 1076 | 0x0, bMaskByte0, 0x0); |
| 1077 | value8 |= APSDOFF; |
| 1078 | /* 0x40 */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1079 | rtl8723au_write8(Adapter, REG_APSD_CTRL, |
| 1080 | value8); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1081 | |
| 1082 | /* After switch APSD, we need to delay |
| 1083 | for stability */ |
| 1084 | mdelay(10); |
| 1085 | |
| 1086 | /* Set BB reset at first */ |
| 1087 | value8 = 0 ; |
| 1088 | value8 |= (FEN_USBD | FEN_USBA | |
| 1089 | FEN_BB_GLB_RSTn); |
| 1090 | /* 0x16 */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1091 | rtl8723au_write8(Adapter, REG_SYS_FUNC_EN, |
| 1092 | value8); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1093 | } |
| 1094 | |
| 1095 | /* Disable RF and BB only for SelectSuspend. */ |
| 1096 | |
| 1097 | /* 1. Set BB/RF to shutdown. */ |
| 1098 | /* (1) Reg878[5:3]= 0 RF rx_code for |
| 1099 | preamble power saving */ |
| 1100 | /* (2)Reg878[21:19]= 0 Turn off RF-B */ |
| 1101 | /* (3) RegC04[7:4]= 0 Turn off all paths for |
| 1102 | packet detection */ |
| 1103 | /* (4) Reg800[1] = 1 enable preamble power |
| 1104 | saving */ |
| 1105 | Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = |
| 1106 | PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 1107 | bMaskDWord); |
| 1108 | Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = |
| 1109 | PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, |
| 1110 | bMaskDWord); |
| 1111 | Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = |
| 1112 | PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, |
| 1113 | bMaskDWord); |
| 1114 | if (pHalData->rf_type == RF_2T2R) |
| 1115 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 1116 | 0x380038, 0); |
| 1117 | else if (pHalData->rf_type == RF_1T1R) |
| 1118 | PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, |
| 1119 | 0x38, 0); |
| 1120 | PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0); |
Jes Sorensen | 05f07e7 | 2014-05-16 10:03:44 +0200 | [diff] [blame] | 1121 | PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 1); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1122 | |
| 1123 | /* 2 .AFE control register to power down. bit[30:22] */ |
| 1124 | Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = |
| 1125 | PHY_QueryBBReg(Adapter, rRx_Wait_CCA, |
| 1126 | bMaskDWord); |
| 1127 | if (pHalData->rf_type == RF_2T2R) |
| 1128 | PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord, |
| 1129 | 0x00DB25A0); |
| 1130 | else if (pHalData->rf_type == RF_1T1R) |
| 1131 | PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord, |
| 1132 | 0x001B25A0); |
| 1133 | |
| 1134 | /* 3. issue 3-wire command that RF set to power down. */ |
| 1135 | PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0); |
| 1136 | if (pHalData->rf_type == RF_2T2R) |
| 1137 | PHY_SetRFReg(Adapter, RF_PATH_B, 0, |
| 1138 | bRFRegOffsetMask, 0); |
| 1139 | |
| 1140 | /* 4. Force PFM , disable SPS18_LDO_Marco_Block */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1141 | rtl8723au_write8(Adapter, REG_SPS0_CTRL, value8); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1142 | |
| 1143 | /* 2010/10/13 MH/Isaachsu exchange sequence. */ |
| 1144 | /* h. AFE_PLL_CTRL 0x28[7:0] = 0x80 |
| 1145 | disable AFE PLL */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1146 | rtl8723au_write8(Adapter, REG_AFE_PLL_CTRL, 0x80); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1147 | mdelay(1); |
| 1148 | |
| 1149 | /* i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F |
| 1150 | gated AFE DIG_CLOCK */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1151 | rtl8723au_write16(Adapter, REG_AFE_XTAL_CTRL, 0xA80F); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1152 | } |
| 1153 | break; |
| 1154 | default: |
| 1155 | break; |
| 1156 | } |
| 1157 | |
| 1158 | } /* phy_PowerSwitch92CU */ |
| 1159 | |
| 1160 | void _ps_open_RF23a(struct rtw_adapter *padapter) |
| 1161 | { |
| 1162 | /* here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified */ |
| 1163 | phy_SsPwrSwitch92CU(padapter, rf_on, 1); |
| 1164 | } |
| 1165 | |
| 1166 | static void CardDisableRTL8723U(struct rtw_adapter *Adapter) |
| 1167 | { |
| 1168 | u8 u1bTmp; |
| 1169 | |
| 1170 | DBG_8723A("CardDisableRTL8723U\n"); |
| 1171 | /* USB-MF Card Disable Flow */ |
| 1172 | /* 1. Run LPS WL RFOFF flow */ |
| 1173 | HalPwrSeqCmdParsing23a(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, |
| 1174 | PWR_INTF_USB_MSK, rtl8723AU_enter_lps_flow); |
| 1175 | |
| 1176 | /* 2. 0x1F[7:0] = 0 turn off RF */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1177 | rtl8723au_write8(Adapter, REG_RF_CTRL, 0x00); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1178 | |
| 1179 | /* ==== Reset digital sequence ====== */ |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 1180 | if ((rtl8723au_read8(Adapter, REG_MCUFWDL) & BIT(7)) && |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1181 | Adapter->bFWReady) /* 8051 RAM code */ |
| 1182 | rtl8723a_FirmwareSelfReset(Adapter); |
| 1183 | |
| 1184 | /* Reset MCU. Suggested by Filen. 2011.01.26. by tynli. */ |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 1185 | u1bTmp = rtl8723au_read8(Adapter, REG_SYS_FUNC_EN+1); |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1186 | rtl8723au_write8(Adapter, REG_SYS_FUNC_EN+1, u1bTmp & ~BIT(2)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1187 | |
| 1188 | /* g. MCUFWDL 0x80[1:0]= 0 reset MCU ready status */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1189 | rtl8723au_write8(Adapter, REG_MCUFWDL, 0x00); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1190 | |
| 1191 | /* ==== Reset digital sequence end ====== */ |
| 1192 | /* Card disable power action flow */ |
| 1193 | HalPwrSeqCmdParsing23a(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, |
| 1194 | PWR_INTF_USB_MSK, |
| 1195 | rtl8723AU_card_disable_flow); |
| 1196 | |
| 1197 | /* Reset MCU IO Wrapper, added by Roger, 2011.08.30. */ |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 1198 | u1bTmp = rtl8723au_read8(Adapter, REG_RSV_CTRL + 1); |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1199 | rtl8723au_write8(Adapter, REG_RSV_CTRL+1, u1bTmp & ~BIT(0)); |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 1200 | u1bTmp = rtl8723au_read8(Adapter, REG_RSV_CTRL + 1); |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1201 | rtl8723au_write8(Adapter, REG_RSV_CTRL+1, u1bTmp | BIT(0)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1202 | |
| 1203 | /* 7. RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */ |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1204 | rtl8723au_write8(Adapter, REG_RSV_CTRL, 0x0e); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1205 | } |
| 1206 | |
Jes Sorensen | c7772697 | 2014-05-16 10:04:16 +0200 | [diff] [blame] | 1207 | static int rtl8723au_hal_deinit(struct rtw_adapter *padapter) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1208 | { |
| 1209 | DBG_8723A("==> %s\n", __func__); |
| 1210 | |
| 1211 | #ifdef CONFIG_8723AU_BT_COEXIST |
| 1212 | BT_HaltProcess(padapter); |
| 1213 | #endif |
| 1214 | /* 2011/02/18 To Fix RU LNA power leakage problem. We need to |
| 1215 | execute below below in Adapter init and halt sequence. |
| 1216 | According to EEchou's opinion, we can enable the ability for all */ |
| 1217 | /* IC. Accord to johnny's opinion, only RU need the support. */ |
| 1218 | CardDisableRTL8723U(padapter); |
| 1219 | |
| 1220 | return _SUCCESS; |
| 1221 | } |
| 1222 | |
Jes Sorensen | 1aaa376 | 2014-05-16 10:04:05 +0200 | [diff] [blame] | 1223 | int rtl8723au_inirp_init(struct rtw_adapter *Adapter) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1224 | { |
| 1225 | u8 i; |
| 1226 | struct recv_buf *precvbuf; |
Jes Sorensen | 1aaa376 | 2014-05-16 10:04:05 +0200 | [diff] [blame] | 1227 | int status; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1228 | struct recv_priv *precvpriv = &Adapter->recvpriv; |
Jes Sorensen | ad899b1 | 2014-05-16 10:04:31 +0200 | [diff] [blame] | 1229 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1230 | |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1231 | status = _SUCCESS; |
| 1232 | |
| 1233 | RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("===> usb_inirp_init\n")); |
| 1234 | |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1235 | /* issue Rx irp to receive data */ |
| 1236 | precvbuf = (struct recv_buf *)precvpriv->precv_buf; |
| 1237 | for (i = 0; i < NR_RECVBUFF; i++) { |
Jes Sorensen | 68552a9 | 2014-05-16 10:05:10 +0200 | [diff] [blame] | 1238 | if (rtl8723au_read_port(Adapter, RECV_BULK_IN_ADDR, 0, |
| 1239 | precvbuf) == _FAIL) { |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1240 | RT_TRACE(_module_hci_hal_init_c_, _drv_err_, |
| 1241 | ("usb_rx_init: usb_read_port error\n")); |
| 1242 | status = _FAIL; |
| 1243 | goto exit; |
| 1244 | } |
| 1245 | precvbuf++; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1246 | } |
Jes Sorensen | 68552a9 | 2014-05-16 10:05:10 +0200 | [diff] [blame] | 1247 | if (rtl8723au_read_interrupt(Adapter, RECV_INT_IN_ADDR) == _FAIL) { |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1248 | RT_TRACE(_module_hci_hal_init_c_, _drv_err_, |
| 1249 | ("usb_rx_init: usb_read_interrupt error\n")); |
| 1250 | status = _FAIL; |
| 1251 | } |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 1252 | pHalData->IntrMask[0] = rtl8723au_read32(Adapter, REG_USB_HIMR); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1253 | MSG_8723A("pHalData->IntrMask = 0x%04x\n", pHalData->IntrMask[0]); |
| 1254 | pHalData->IntrMask[0] |= UHIMR_C2HCMD|UHIMR_CPWM; |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1255 | rtl8723au_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1256 | exit: |
| 1257 | RT_TRACE(_module_hci_hal_init_c_, _drv_info_, |
| 1258 | ("<=== usb_inirp_init\n")); |
| 1259 | return status; |
| 1260 | } |
| 1261 | |
Jes Sorensen | 1aaa376 | 2014-05-16 10:04:05 +0200 | [diff] [blame] | 1262 | int rtl8723au_inirp_deinit(struct rtw_adapter *Adapter) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1263 | { |
| 1264 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 1265 | |
| 1266 | RT_TRACE(_module_hci_hal_init_c_, _drv_info_, |
| 1267 | ("\n ===> usb_rx_deinit\n")); |
Jes Sorensen | 68552a9 | 2014-05-16 10:05:10 +0200 | [diff] [blame] | 1268 | rtl8723au_read_port_cancel(Adapter); |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 1269 | pHalData->IntrMask[0] = rtl8723au_read32(Adapter, REG_USB_HIMR); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1270 | MSG_8723A("%s pHalData->IntrMask = 0x%04x\n", __func__, |
| 1271 | pHalData->IntrMask[0]); |
| 1272 | pHalData->IntrMask[0] = 0x0; |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1273 | rtl8723au_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1274 | RT_TRACE(_module_hci_hal_init_c_, _drv_info_, |
| 1275 | ("\n <=== usb_rx_deinit\n")); |
| 1276 | return _SUCCESS; |
| 1277 | } |
| 1278 | |
| 1279 | static void _ReadBoardType(struct rtw_adapter *Adapter, u8 *PROMContent, |
| 1280 | bool AutoloadFail) |
| 1281 | { |
| 1282 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 1283 | u8 boardType = BOARD_USB_DONGLE; |
| 1284 | |
| 1285 | if (AutoloadFail) { |
| 1286 | if (IS_8723_SERIES(pHalData->VersionID)) |
| 1287 | pHalData->rf_type = RF_1T1R; |
| 1288 | else |
| 1289 | pHalData->rf_type = RF_2T2R; |
| 1290 | pHalData->BoardType = boardType; |
| 1291 | return; |
| 1292 | } |
| 1293 | |
| 1294 | boardType = PROMContent[EEPROM_NORMAL_BoardType]; |
| 1295 | boardType &= BOARD_TYPE_NORMAL_MASK;/* bit[7:5] */ |
| 1296 | boardType >>= 5; |
| 1297 | |
| 1298 | pHalData->BoardType = boardType; |
| 1299 | MSG_8723A("_ReadBoardType(%x)\n", pHalData->BoardType); |
| 1300 | |
| 1301 | if (boardType == BOARD_USB_High_PA) |
| 1302 | pHalData->ExternalPA = 1; |
| 1303 | } |
| 1304 | |
| 1305 | static void _ReadLEDSetting(struct rtw_adapter *Adapter, u8 *PROMContent, |
| 1306 | bool AutoloadFail) |
| 1307 | { |
| 1308 | struct led_priv *pledpriv = &Adapter->ledpriv; |
| 1309 | |
| 1310 | pledpriv->LedStrategy = HW_LED; |
| 1311 | } |
| 1312 | |
| 1313 | static void Hal_EfuseParsePIDVID_8723AU(struct rtw_adapter *pAdapter, |
| 1314 | u8 *hwinfo, bool AutoLoadFail) |
| 1315 | { |
| 1316 | struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter); |
| 1317 | |
| 1318 | if (AutoLoadFail) { |
| 1319 | pHalData->EEPROMVID = 0; |
| 1320 | pHalData->EEPROMPID = 0; |
| 1321 | } else { |
| 1322 | /* VID, PID */ |
| 1323 | pHalData->EEPROMVID = |
| 1324 | le16_to_cpu(*(u16 *)&hwinfo[EEPROM_VID_8723AU]); |
| 1325 | pHalData->EEPROMPID = |
| 1326 | le16_to_cpu(*(u16 *)&hwinfo[EEPROM_PID_8723AU]); |
| 1327 | } |
| 1328 | |
| 1329 | MSG_8723A("EEPROM VID = 0x%4x\n", pHalData->EEPROMVID); |
| 1330 | MSG_8723A("EEPROM PID = 0x%4x\n", pHalData->EEPROMPID); |
| 1331 | } |
| 1332 | |
| 1333 | static void Hal_EfuseParseMACAddr_8723AU(struct rtw_adapter *padapter, |
| 1334 | u8 *hwinfo, bool AutoLoadFail) |
| 1335 | { |
| 1336 | u16 i; |
| 1337 | u8 sMacAddr[ETH_ALEN] = {0x00, 0xE0, 0x4C, 0x87, 0x23, 0x00}; |
| 1338 | struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); |
| 1339 | |
| 1340 | if (AutoLoadFail) { |
| 1341 | for (i = 0; i < 6; i++) |
| 1342 | pEEPROM->mac_addr[i] = sMacAddr[i]; |
| 1343 | } else { |
| 1344 | /* Read Permanent MAC address */ |
| 1345 | memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723AU], |
| 1346 | ETH_ALEN); |
| 1347 | } |
| 1348 | |
| 1349 | RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, |
| 1350 | ("Hal_EfuseParseMACAddr_8723AU: Permanent Address =%02x:%02x:" |
| 1351 | "%02x:%02x:%02x:%02x\n", |
| 1352 | pEEPROM->mac_addr[0], pEEPROM->mac_addr[1], |
| 1353 | pEEPROM->mac_addr[2], pEEPROM->mac_addr[3], |
| 1354 | pEEPROM->mac_addr[4], pEEPROM->mac_addr[5])); |
| 1355 | } |
| 1356 | |
| 1357 | static void readAdapterInfo(struct rtw_adapter *padapter) |
| 1358 | { |
| 1359 | struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); |
| 1360 | /* struct hal_data_8723a * pHalData = GET_HAL_DATA(padapter); */ |
| 1361 | u8 hwinfo[HWSET_MAX_SIZE]; |
| 1362 | |
| 1363 | Hal_InitPGData(padapter, hwinfo); |
| 1364 | Hal_EfuseParseIDCode(padapter, hwinfo); |
| 1365 | Hal_EfuseParsePIDVID_8723AU(padapter, hwinfo, |
| 1366 | pEEPROM->bautoload_fail_flag); |
| 1367 | Hal_EfuseParseEEPROMVer(padapter, hwinfo, |
| 1368 | pEEPROM->bautoload_fail_flag); |
| 1369 | Hal_EfuseParseMACAddr_8723AU(padapter, hwinfo, |
| 1370 | pEEPROM->bautoload_fail_flag); |
| 1371 | Hal_EfuseParsetxpowerinfo_8723A(padapter, hwinfo, |
| 1372 | pEEPROM->bautoload_fail_flag); |
| 1373 | _ReadBoardType(padapter, hwinfo, pEEPROM->bautoload_fail_flag); |
| 1374 | Hal_EfuseParseBTCoexistInfo_8723A(padapter, hwinfo, |
| 1375 | pEEPROM->bautoload_fail_flag); |
| 1376 | |
| 1377 | rtl8723a_EfuseParseChnlPlan(padapter, hwinfo, |
| 1378 | pEEPROM->bautoload_fail_flag); |
| 1379 | Hal_EfuseParseThermalMeter_8723A(padapter, hwinfo, |
| 1380 | pEEPROM->bautoload_fail_flag); |
| 1381 | _ReadLEDSetting(padapter, hwinfo, pEEPROM->bautoload_fail_flag); |
| 1382 | /* _ReadRFSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); */ |
| 1383 | /* _ReadPSSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); */ |
| 1384 | Hal_EfuseParseAntennaDiversity(padapter, hwinfo, |
| 1385 | pEEPROM->bautoload_fail_flag); |
| 1386 | |
| 1387 | Hal_EfuseParseEEPROMVer(padapter, hwinfo, pEEPROM->bautoload_fail_flag); |
| 1388 | Hal_EfuseParseCustomerID(padapter, hwinfo, |
| 1389 | pEEPROM->bautoload_fail_flag); |
| 1390 | Hal_EfuseParseRateIndicationOption(padapter, hwinfo, |
| 1391 | pEEPROM->bautoload_fail_flag); |
| 1392 | Hal_EfuseParseXtal_8723A(padapter, hwinfo, |
| 1393 | pEEPROM->bautoload_fail_flag); |
| 1394 | /* */ |
| 1395 | /* The following part initialize some vars by PG info. */ |
| 1396 | /* */ |
| 1397 | Hal_InitChannelPlan23a(padapter); |
| 1398 | |
| 1399 | /* hal_CustomizedBehavior_8723U(Adapter); */ |
| 1400 | |
| 1401 | /* Adapter->bDongle = (PROMContent[EEPROM_EASY_REPLACEMENT] == 1)? 0: 1; */ |
| 1402 | DBG_8723A("%s(): REPLACEMENT = %x\n", __func__, padapter->bDongle); |
| 1403 | } |
| 1404 | |
| 1405 | static void _ReadPROMContent(struct rtw_adapter *Adapter) |
| 1406 | { |
| 1407 | struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter); |
| 1408 | u8 eeValue; |
| 1409 | |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 1410 | eeValue = rtl8723au_read8(Adapter, REG_9346CR); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1411 | /* To check system boot selection. */ |
| 1412 | pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false; |
| 1413 | pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true; |
| 1414 | |
| 1415 | DBG_8723A("Boot from %s, Autoload %s !\n", |
| 1416 | (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"), |
| 1417 | (pEEPROM->bautoload_fail_flag ? "Fail" : "OK")); |
| 1418 | |
| 1419 | readAdapterInfo(Adapter); |
| 1420 | } |
| 1421 | |
| 1422 | static void _ReadRFType(struct rtw_adapter *Adapter) |
| 1423 | { |
| 1424 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 1425 | |
| 1426 | pHalData->rf_chip = RF_6052; |
| 1427 | } |
| 1428 | |
| 1429 | static void _ReadSilmComboMode(struct rtw_adapter *Adapter) |
| 1430 | { |
| 1431 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 1432 | |
| 1433 | pHalData->SlimComboDbg = false; /* Default is not debug mode. */ |
| 1434 | } |
| 1435 | |
| 1436 | /* */ |
| 1437 | /* Description: */ |
| 1438 | /* We should set Efuse cell selection to WiFi cell in default. */ |
| 1439 | /* */ |
| 1440 | /* Assumption: */ |
| 1441 | /* PASSIVE_LEVEL */ |
| 1442 | /* */ |
| 1443 | /* Added by Roger, 2010.11.23. */ |
| 1444 | /* */ |
| 1445 | static void hal_EfuseCellSel(struct rtw_adapter *Adapter) |
| 1446 | { |
| 1447 | u32 value32; |
| 1448 | |
Jes Sorensen | 050abc4 | 2014-05-16 10:05:08 +0200 | [diff] [blame] | 1449 | value32 = rtl8723au_read32(Adapter, EFUSE_TEST); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1450 | value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1451 | rtl8723au_write32(Adapter, EFUSE_TEST, value32); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1452 | } |
| 1453 | |
Jes Sorensen | 1f4746f | 2014-05-16 10:03:58 +0200 | [diff] [blame] | 1454 | void rtl8723a_read_adapter_info(struct rtw_adapter *Adapter) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1455 | { |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1456 | unsigned long start = jiffies; |
| 1457 | |
Jes Sorensen | 1f4746f | 2014-05-16 10:03:58 +0200 | [diff] [blame] | 1458 | /* Read EEPROM size before call any EEPROM function */ |
| 1459 | Adapter->EepromAddressSize = GetEEPROMSize8723A(Adapter); |
| 1460 | |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1461 | MSG_8723A("====> _ReadAdapterInfo8723AU\n"); |
| 1462 | |
| 1463 | hal_EfuseCellSel(Adapter); |
| 1464 | |
| 1465 | _ReadRFType(Adapter);/* rf_chip -> _InitRFType() */ |
| 1466 | _ReadPROMContent(Adapter); |
| 1467 | |
| 1468 | /* 2010/10/25 MH THe function must be called after |
| 1469 | borad_type & IC-Version recognize. */ |
| 1470 | _ReadSilmComboMode(Adapter); |
| 1471 | |
| 1472 | /* MSG_8723A("%s()(done), rf_chip = 0x%x, rf_type = 0x%x\n", |
| 1473 | __func__, pHalData->rf_chip, pHalData->rf_type); */ |
| 1474 | |
| 1475 | MSG_8723A("<==== _ReadAdapterInfo8723AU in %d ms\n", |
| 1476 | jiffies_to_msecs(jiffies - start)); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1477 | } |
| 1478 | |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1479 | /* */ |
| 1480 | /* Description: */ |
| 1481 | /* Query setting of specified variable. */ |
| 1482 | /* */ |
Jes Sorensen | 39f1a8e | 2014-05-16 10:04:20 +0200 | [diff] [blame] | 1483 | int GetHalDefVar8192CUsb(struct rtw_adapter *Adapter, |
| 1484 | enum hal_def_variable eVariable, void *pValue) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1485 | { |
Jes Sorensen | 39f1a8e | 2014-05-16 10:04:20 +0200 | [diff] [blame] | 1486 | struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); |
| 1487 | int bResult = _SUCCESS; |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1488 | |
| 1489 | switch (eVariable) { |
| 1490 | case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB: |
| 1491 | *((int *)pValue) = pHalData->dmpriv.UndecoratedSmoothedPWDB; |
| 1492 | break; |
| 1493 | case HAL_DEF_IS_SUPPORT_ANT_DIV: |
| 1494 | break; |
| 1495 | case HAL_DEF_CURRENT_ANTENNA: |
| 1496 | break; |
| 1497 | case HAL_DEF_DRVINFO_SZ: |
| 1498 | *((u32 *)pValue) = DRVINFO_SZ; |
| 1499 | break; |
| 1500 | case HAL_DEF_MAX_RECVBUF_SZ: |
| 1501 | *((u32 *)pValue) = MAX_RECVBUF_SZ; |
| 1502 | break; |
| 1503 | case HAL_DEF_RX_PACKET_OFFSET: |
| 1504 | *((u32 *)pValue) = RXDESC_SIZE + DRVINFO_SZ; |
| 1505 | break; |
| 1506 | case HAL_DEF_DBG_DUMP_RXPKT: |
| 1507 | *((u8 *)pValue) = pHalData->bDumpRxPkt; |
| 1508 | break; |
| 1509 | case HAL_DEF_DBG_DM_FUNC: |
| 1510 | *((u32 *)pValue) = pHalData->odmpriv.SupportAbility; |
| 1511 | break; |
| 1512 | case HW_VAR_MAX_RX_AMPDU_FACTOR: |
| 1513 | *((u32 *)pValue) = IEEE80211_HT_MAX_AMPDU_64K; |
| 1514 | break; |
| 1515 | case HW_DEF_ODM_DBG_FLAG: |
| 1516 | { |
| 1517 | struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; |
| 1518 | printk("pDM_Odm->DebugComponents = 0x%llx\n", |
| 1519 | pDM_Odm->DebugComponents); |
| 1520 | } |
| 1521 | break; |
| 1522 | default: |
| 1523 | /* RT_TRACE(COMP_INIT, DBG_WARNING, ("GetHalDefVar8192CUsb(): " |
| 1524 | "Unkown variable: %d!\n", eVariable)); */ |
| 1525 | bResult = _FAIL; |
| 1526 | break; |
| 1527 | } |
| 1528 | |
| 1529 | return bResult; |
| 1530 | } |
| 1531 | |
Jes Sorensen | ac4cbc6 | 2014-05-16 10:04:19 +0200 | [diff] [blame] | 1532 | void rtl8723a_update_ramask(struct rtw_adapter *padapter, |
| 1533 | u32 mac_id, u8 rssi_level) |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1534 | { |
| 1535 | u8 init_rate = 0; |
| 1536 | u8 networkType, raid; |
| 1537 | u32 mask, rate_bitmap; |
| 1538 | u8 shortGIrate = false; |
| 1539 | int supportRateNum = 0; |
| 1540 | struct sta_info *psta; |
| 1541 | struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter); |
| 1542 | struct dm_priv *pdmpriv = &pHalData->dmpriv; |
| 1543 | struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; |
| 1544 | struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; |
| 1545 | struct wlan_bssid_ex *cur_network = &pmlmeinfo->network; |
| 1546 | |
| 1547 | if (mac_id >= NUM_STA) /* CAM_SIZE */ |
| 1548 | return; |
| 1549 | |
| 1550 | psta = pmlmeinfo->FW_sta_info[mac_id].psta; |
| 1551 | if (psta == NULL) |
| 1552 | return; |
| 1553 | |
| 1554 | switch (mac_id) { |
| 1555 | case 0:/* for infra mode */ |
| 1556 | supportRateNum = |
| 1557 | rtw_get_rateset_len23a(cur_network->SupportedRates); |
| 1558 | networkType = judge_network_type23a(padapter, |
| 1559 | cur_network->SupportedRates, |
| 1560 | supportRateNum) & 0xf; |
| 1561 | /* pmlmeext->cur_wireless_mode = networkType; */ |
| 1562 | raid = networktype_to_raid23a(networkType); |
| 1563 | |
| 1564 | mask = update_supported_rate23a(cur_network->SupportedRates, |
| 1565 | supportRateNum); |
| 1566 | mask |= (pmlmeinfo->HT_enable) ? |
| 1567 | update_MSC_rate23a(&pmlmeinfo->HT_caps) : 0; |
| 1568 | |
| 1569 | if (support_short_GI23a(padapter, &pmlmeinfo->HT_caps)) |
| 1570 | shortGIrate = true; |
| 1571 | break; |
| 1572 | |
| 1573 | case 1:/* for broadcast/multicast */ |
| 1574 | supportRateNum = rtw_get_rateset_len23a( |
| 1575 | pmlmeinfo->FW_sta_info[mac_id].SupportedRates); |
| 1576 | if (pmlmeext->cur_wireless_mode & WIRELESS_11B) |
| 1577 | networkType = WIRELESS_11B; |
| 1578 | else |
| 1579 | networkType = WIRELESS_11G; |
| 1580 | raid = networktype_to_raid23a(networkType); |
| 1581 | |
| 1582 | mask = update_basic_rate23a(cur_network->SupportedRates, |
| 1583 | supportRateNum); |
| 1584 | break; |
| 1585 | |
| 1586 | default: /* for each sta in IBSS */ |
| 1587 | supportRateNum = rtw_get_rateset_len23a( |
| 1588 | pmlmeinfo->FW_sta_info[mac_id].SupportedRates); |
| 1589 | networkType = judge_network_type23a(padapter, |
| 1590 | pmlmeinfo->FW_sta_info[mac_id].SupportedRates, |
| 1591 | supportRateNum) & 0xf; |
| 1592 | /* pmlmeext->cur_wireless_mode = networkType; */ |
| 1593 | raid = networktype_to_raid23a(networkType); |
| 1594 | |
| 1595 | mask = update_supported_rate23a(cur_network->SupportedRates, |
| 1596 | supportRateNum); |
| 1597 | |
| 1598 | /* todo: support HT in IBSS */ |
| 1599 | break; |
| 1600 | } |
| 1601 | |
| 1602 | /* mask &= 0x0fffffff; */ |
| 1603 | rate_bitmap = 0x0fffffff; |
| 1604 | rate_bitmap = ODM_Get_Rate_Bitmap23a(&pHalData->odmpriv, |
| 1605 | mac_id, mask, rssi_level); |
Jes Sorensen | 316f621 | 2014-05-21 09:38:03 +0200 | [diff] [blame^] | 1606 | DBG_8723A("%s => mac_id:%d, networkType:0x%02x, " |
| 1607 | "mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n", |
| 1608 | __func__, mac_id, networkType, mask, rssi_level, rate_bitmap); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1609 | |
| 1610 | mask &= rate_bitmap; |
| 1611 | mask |= ((raid<<28)&0xf0000000); |
| 1612 | |
| 1613 | init_rate = get_highest_rate_idx23a(mask)&0x3f; |
| 1614 | |
| 1615 | if (pHalData->fw_ractrl == true) { |
| 1616 | u8 arg = 0; |
| 1617 | |
| 1618 | /* arg = (cam_idx-4)&0x1f;MACID */ |
| 1619 | arg = mac_id&0x1f;/* MACID */ |
| 1620 | |
| 1621 | arg |= BIT(7); |
| 1622 | |
| 1623 | if (shortGIrate == true) |
| 1624 | arg |= BIT(5); |
| 1625 | |
| 1626 | DBG_8723A("update raid entry, mask = 0x%x, arg = 0x%x\n", |
| 1627 | mask, arg); |
| 1628 | |
| 1629 | rtl8723a_set_raid_cmd(padapter, mask, arg); |
| 1630 | } else { |
| 1631 | if (shortGIrate == true) |
| 1632 | init_rate |= BIT(6); |
| 1633 | |
Jes Sorensen | edbfd67 | 2014-05-16 10:05:09 +0200 | [diff] [blame] | 1634 | rtl8723au_write8(padapter, (REG_INIDATA_RATE_SEL+mac_id), |
| 1635 | init_rate); |
Larry Finger | f7c92d2 | 2014-03-28 21:37:39 -0500 | [diff] [blame] | 1636 | } |
| 1637 | |
| 1638 | /* set ra_id */ |
| 1639 | psta->raid = raid; |
| 1640 | psta->init_rate = init_rate; |
| 1641 | |
| 1642 | /* set correct initial date rate for each mac_id */ |
| 1643 | pdmpriv->INIDATA_RATE[mac_id] = init_rate; |
| 1644 | } |
| 1645 | |
Jes Sorensen | c7772697 | 2014-05-16 10:04:16 +0200 | [diff] [blame] | 1646 | int rtw_hal_init23a(struct rtw_adapter *padapter) |
| 1647 | { |
| 1648 | int status; |
| 1649 | |
| 1650 | padapter->hw_init_completed = false; |
| 1651 | |
| 1652 | status = rtl8723au_hal_init(padapter); |
| 1653 | |
| 1654 | if (status == _SUCCESS) { |
| 1655 | padapter->hw_init_completed = true; |
| 1656 | |
| 1657 | if (padapter->registrypriv.notch_filter == 1) |
| 1658 | rtl8723a_notch_filter(padapter, 1); |
| 1659 | } else { |
| 1660 | padapter->hw_init_completed = false; |
| 1661 | DBG_8723A("rtw_hal_init23a: hal__init fail\n"); |
| 1662 | } |
| 1663 | |
| 1664 | RT_TRACE(_module_hal_init_c_, _drv_err_, |
| 1665 | ("-rtl871x_hal_init:status = 0x%x\n", status)); |
| 1666 | |
| 1667 | return status; |
| 1668 | } |
| 1669 | |
| 1670 | int rtw_hal_deinit23a(struct rtw_adapter *padapter) |
| 1671 | { |
| 1672 | int status; |
| 1673 | |
| 1674 | status = rtl8723au_hal_deinit(padapter); |
| 1675 | |
| 1676 | if (status == _SUCCESS) |
| 1677 | padapter->hw_init_completed = false; |
| 1678 | else |
| 1679 | DBG_8723A("\n rtw_hal_deinit23a: hal_init fail\n"); |
| 1680 | return status; |
| 1681 | } |