Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 28 | #include "linux/string.h" |
| 29 | #include "linux/bitops.h" |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 30 | #include "drmP.h" |
| 31 | #include "drm.h" |
| 32 | #include "i915_drm.h" |
| 33 | #include "i915_drv.h" |
| 34 | |
| 35 | /** @file i915_gem_tiling.c |
| 36 | * |
| 37 | * Support for managing tiling state of buffer objects. |
| 38 | * |
| 39 | * The idea behind tiling is to increase cache hit rates by rearranging |
| 40 | * pixel data so that a group of pixel accesses are in the same cacheline. |
| 41 | * Performance improvement from doing this on the back/depth buffer are on |
| 42 | * the order of 30%. |
| 43 | * |
| 44 | * Intel architectures make this somewhat more complicated, though, by |
| 45 | * adjustments made to addressing of data when the memory is in interleaved |
| 46 | * mode (matched pairs of DIMMS) to improve memory bandwidth. |
| 47 | * For interleaved memory, the CPU sends every sequential 64 bytes |
| 48 | * to an alternate memory channel so it can get the bandwidth from both. |
| 49 | * |
| 50 | * The GPU also rearranges its accesses for increased bandwidth to interleaved |
| 51 | * memory, and it matches what the CPU does for non-tiled. However, when tiled |
| 52 | * it does it a little differently, since one walks addresses not just in the |
| 53 | * X direction but also Y. So, along with alternating channels when bit |
| 54 | * 6 of the address flips, it also alternates when other bits flip -- Bits 9 |
| 55 | * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines) |
| 56 | * are common to both the 915 and 965-class hardware. |
| 57 | * |
| 58 | * The CPU also sometimes XORs in higher bits as well, to improve |
| 59 | * bandwidth doing strided access like we do so frequently in graphics. This |
| 60 | * is called "Channel XOR Randomization" in the MCH documentation. The result |
| 61 | * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address |
| 62 | * decode. |
| 63 | * |
| 64 | * All of this bit 6 XORing has an effect on our memory management, |
| 65 | * as we need to make sure that the 3d driver can correctly address object |
| 66 | * contents. |
| 67 | * |
| 68 | * If we don't have interleaved memory, all tiling is safe and no swizzling is |
| 69 | * required. |
| 70 | * |
| 71 | * When bit 17 is XORed in, we simply refuse to tile at all. Bit |
| 72 | * 17 is not just a page offset, so as we page an objet out and back in, |
| 73 | * individual pages in it will have different bit 17 addresses, resulting in |
| 74 | * each 64 bytes being swapped with its neighbor! |
| 75 | * |
| 76 | * Otherwise, if interleaved, we have to tell the 3d driver what the address |
| 77 | * swizzling it needs to do is, since it's writing with the CPU to the pages |
| 78 | * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the |
| 79 | * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling |
| 80 | * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order |
| 81 | * to match what the GPU expects. |
| 82 | */ |
| 83 | |
| 84 | /** |
| 85 | * Detects bit 6 swizzling of address lookup between IGD access and CPU |
| 86 | * access through main memory. |
| 87 | */ |
| 88 | void |
| 89 | i915_gem_detect_bit_6_swizzle(struct drm_device *dev) |
| 90 | { |
| 91 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 92 | uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; |
| 93 | uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; |
| 94 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 95 | if (IS_IRONLAKE(dev) || IS_GEN6(dev)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 96 | /* On Ironlake whatever DRAM config, GPU always do |
Zhenyu Wang | 553bd14 | 2009-09-02 10:57:52 +0800 | [diff] [blame] | 97 | * same swizzling setup. |
| 98 | */ |
| 99 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
| 100 | swizzle_y = I915_BIT_6_SWIZZLE_9; |
| 101 | } else if (!IS_I9XX(dev)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 102 | /* As far as we know, the 865 doesn't have these bit 6 |
| 103 | * swizzling issues. |
| 104 | */ |
| 105 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
| 106 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
Eric Anholt | 568d9a8 | 2009-03-12 16:27:11 -0700 | [diff] [blame] | 107 | } else if (IS_MOBILE(dev)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 108 | uint32_t dcc; |
| 109 | |
Eric Anholt | 568d9a8 | 2009-03-12 16:27:11 -0700 | [diff] [blame] | 110 | /* On mobile 9xx chipsets, channel interleave by the CPU is |
| 111 | * determined by DCC. For single-channel, neither the CPU |
| 112 | * nor the GPU do swizzling. For dual channel interleaved, |
| 113 | * the GPU's interleave is bit 9 and 10 for X tiled, and bit |
| 114 | * 9 for Y tiled. The CPU's interleave is independent, and |
| 115 | * can be based on either bit 11 (haven't seen this yet) or |
| 116 | * bit 17 (common). |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 117 | */ |
| 118 | dcc = I915_READ(DCC); |
| 119 | switch (dcc & DCC_ADDRESSING_MODE_MASK) { |
| 120 | case DCC_ADDRESSING_MODE_SINGLE_CHANNEL: |
| 121 | case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC: |
| 122 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
| 123 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
| 124 | break; |
| 125 | case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED: |
Eric Anholt | 568d9a8 | 2009-03-12 16:27:11 -0700 | [diff] [blame] | 126 | if (dcc & DCC_CHANNEL_XOR_DISABLE) { |
| 127 | /* This is the base swizzling by the GPU for |
| 128 | * tiled buffers. |
| 129 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 130 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
| 131 | swizzle_y = I915_BIT_6_SWIZZLE_9; |
Eric Anholt | 568d9a8 | 2009-03-12 16:27:11 -0700 | [diff] [blame] | 132 | } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { |
| 133 | /* Bit 11 swizzling by the CPU in addition. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 134 | swizzle_x = I915_BIT_6_SWIZZLE_9_10_11; |
| 135 | swizzle_y = I915_BIT_6_SWIZZLE_9_11; |
| 136 | } else { |
Eric Anholt | 568d9a8 | 2009-03-12 16:27:11 -0700 | [diff] [blame] | 137 | /* Bit 17 swizzling by the CPU in addition. */ |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 138 | swizzle_x = I915_BIT_6_SWIZZLE_9_10_17; |
| 139 | swizzle_y = I915_BIT_6_SWIZZLE_9_17; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 140 | } |
| 141 | break; |
| 142 | } |
| 143 | if (dcc == 0xffffffff) { |
| 144 | DRM_ERROR("Couldn't read from MCHBAR. " |
| 145 | "Disabling tiling.\n"); |
| 146 | swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; |
| 147 | swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; |
| 148 | } |
| 149 | } else { |
| 150 | /* The 965, G33, and newer, have a very flexible memory |
| 151 | * configuration. It will enable dual-channel mode |
| 152 | * (interleaving) on as much memory as it can, and the GPU |
| 153 | * will additionally sometimes enable different bit 6 |
| 154 | * swizzling for tiled objects from the CPU. |
| 155 | * |
| 156 | * Here's what I found on the G965: |
| 157 | * slot fill memory size swizzling |
| 158 | * 0A 0B 1A 1B 1-ch 2-ch |
| 159 | * 512 0 0 0 512 0 O |
| 160 | * 512 0 512 0 16 1008 X |
| 161 | * 512 0 0 512 16 1008 X |
| 162 | * 0 512 0 512 16 1008 X |
| 163 | * 1024 1024 1024 0 2048 1024 O |
| 164 | * |
| 165 | * We could probably detect this based on either the DRB |
| 166 | * matching, which was the case for the swizzling required in |
| 167 | * the table above, or from the 1-ch value being less than |
| 168 | * the minimum size of a rank. |
| 169 | */ |
| 170 | if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) { |
| 171 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
| 172 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
| 173 | } else { |
| 174 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
| 175 | swizzle_y = I915_BIT_6_SWIZZLE_9; |
| 176 | } |
| 177 | } |
| 178 | |
| 179 | dev_priv->mm.bit_6_swizzle_x = swizzle_x; |
| 180 | dev_priv->mm.bit_6_swizzle_y = swizzle_y; |
| 181 | } |
| 182 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 183 | /* Check pitch constriants for all chips & tiling formats */ |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 184 | bool |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 185 | i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) |
| 186 | { |
| 187 | int tile_width; |
| 188 | |
| 189 | /* Linear is always fine */ |
| 190 | if (tiling_mode == I915_TILING_NONE) |
| 191 | return true; |
| 192 | |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 193 | if (!IS_I9XX(dev) || |
| 194 | (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 195 | tile_width = 128; |
| 196 | else |
| 197 | tile_width = 512; |
| 198 | |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 199 | /* check maximum stride & object size */ |
| 200 | if (IS_I965G(dev)) { |
| 201 | /* i965 stores the end address of the gtt mapping in the fence |
| 202 | * reg, so dont bother to check the size */ |
| 203 | if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) |
| 204 | return false; |
Daniel Vetter | c36a2a6 | 2010-04-17 15:12:03 +0200 | [diff] [blame] | 205 | } else if (IS_GEN3(dev) || IS_GEN2(dev)) { |
| 206 | if (stride > 8192) |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 207 | return false; |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 208 | |
Daniel Vetter | c36a2a6 | 2010-04-17 15:12:03 +0200 | [diff] [blame] | 209 | if (IS_GEN3(dev)) { |
| 210 | if (size > I830_FENCE_MAX_SIZE_VAL << 20) |
| 211 | return false; |
| 212 | } else { |
| 213 | if (size > I830_FENCE_MAX_SIZE_VAL << 19) |
| 214 | return false; |
| 215 | } |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 216 | } |
| 217 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 218 | /* 965+ just needs multiples of tile width */ |
| 219 | if (IS_I965G(dev)) { |
| 220 | if (stride & (tile_width - 1)) |
| 221 | return false; |
| 222 | return true; |
| 223 | } |
| 224 | |
| 225 | /* Pre-965 needs power of two tile widths */ |
| 226 | if (stride < tile_width) |
| 227 | return false; |
| 228 | |
| 229 | if (stride & (stride - 1)) |
| 230 | return false; |
| 231 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 232 | return true; |
| 233 | } |
| 234 | |
Owain Ainsworth | f590d27 | 2010-02-18 15:33:00 +0000 | [diff] [blame] | 235 | bool |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 236 | i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, int tiling_mode) |
| 237 | { |
| 238 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 239 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 240 | |
| 241 | if (obj_priv->gtt_space == NULL) |
| 242 | return true; |
| 243 | |
| 244 | if (tiling_mode == I915_TILING_NONE) |
| 245 | return true; |
| 246 | |
| 247 | if (!IS_I965G(dev)) { |
| 248 | if (obj_priv->gtt_offset & (obj->size - 1)) |
| 249 | return false; |
| 250 | if (IS_I9XX(dev)) { |
| 251 | if (obj_priv->gtt_offset & ~I915_FENCE_START_MASK) |
| 252 | return false; |
| 253 | } else { |
| 254 | if (obj_priv->gtt_offset & ~I830_FENCE_START_MASK) |
| 255 | return false; |
| 256 | } |
| 257 | } |
| 258 | |
| 259 | return true; |
| 260 | } |
| 261 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 262 | /** |
| 263 | * Sets the tiling mode of an object, returning the required swizzling of |
| 264 | * bit 6 of addresses in the object. |
| 265 | */ |
| 266 | int |
| 267 | i915_gem_set_tiling(struct drm_device *dev, void *data, |
| 268 | struct drm_file *file_priv) |
| 269 | { |
| 270 | struct drm_i915_gem_set_tiling *args = data; |
| 271 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 272 | struct drm_gem_object *obj; |
| 273 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 274 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 275 | |
| 276 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 277 | if (obj == NULL) |
| 278 | return -EINVAL; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 279 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 280 | |
Chris Wilson | 72daad4 | 2009-01-30 21:10:22 +0000 | [diff] [blame] | 281 | if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) { |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 282 | drm_gem_object_unreference_unlocked(obj); |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 283 | return -EINVAL; |
Chris Wilson | 72daad4 | 2009-01-30 21:10:22 +0000 | [diff] [blame] | 284 | } |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 285 | |
Daniel Vetter | 31770bd | 2010-04-23 23:01:01 +0200 | [diff] [blame^] | 286 | if (obj_priv->pin_count) { |
| 287 | drm_gem_object_unreference_unlocked(obj); |
| 288 | return -EBUSY; |
| 289 | } |
| 290 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 291 | if (args->tiling_mode == I915_TILING_NONE) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 292 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 293 | args->stride = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 294 | } else { |
| 295 | if (args->tiling_mode == I915_TILING_X) |
| 296 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; |
| 297 | else |
| 298 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 299 | |
| 300 | /* Hide bit 17 swizzling from the user. This prevents old Mesa |
| 301 | * from aborting the application on sw fallbacks to bit 17, |
| 302 | * and we use the pread/pwrite bit17 paths to swizzle for it. |
| 303 | * If there was a user that was relying on the swizzle |
| 304 | * information for drm_intel_bo_map()ed reads/writes this would |
| 305 | * break it, but we don't have any of those. |
| 306 | */ |
| 307 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) |
| 308 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9; |
| 309 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) |
| 310 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; |
| 311 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 312 | /* If we can't handle the swizzling, make it untiled. */ |
| 313 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) { |
| 314 | args->tiling_mode = I915_TILING_NONE; |
| 315 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 316 | args->stride = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 317 | } |
| 318 | } |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 319 | |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 320 | mutex_lock(&dev->struct_mutex); |
| 321 | if (args->tiling_mode != obj_priv->tiling_mode || |
| 322 | args->stride != obj_priv->stride) { |
| 323 | /* We need to rebind the object if its current allocation |
| 324 | * no longer meets the alignment restrictions for its new |
| 325 | * tiling mode. Otherwise we can just leave it alone, but |
| 326 | * need to ensure that any fence register is cleared. |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 327 | */ |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 328 | if (!i915_gem_object_fence_offset_ok(obj, args->tiling_mode)) |
Daniel Vetter | fe30519 | 2010-03-18 09:22:12 +0100 | [diff] [blame] | 329 | ret = i915_gem_object_unbind(obj); |
| 330 | else if (obj_priv->fence_reg != I915_FENCE_REG_NONE) |
| 331 | ret = i915_gem_object_put_fence_reg(obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 332 | else |
Daniel Vetter | fe30519 | 2010-03-18 09:22:12 +0100 | [diff] [blame] | 333 | i915_gem_release_mmap(obj); |
| 334 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 335 | if (ret != 0) { |
| 336 | WARN(ret != -ERESTARTSYS, |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 337 | "failed to reset object for tiling switch"); |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 338 | args->tiling_mode = obj_priv->tiling_mode; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 339 | args->stride = obj_priv->stride; |
| 340 | goto err; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 341 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 342 | |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 343 | obj_priv->tiling_mode = args->tiling_mode; |
| 344 | obj_priv->stride = args->stride; |
| 345 | } |
| 346 | err: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 347 | drm_gem_object_unreference(obj); |
Chris Wilson | d687310 | 2009-02-08 19:07:51 +0000 | [diff] [blame] | 348 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 349 | |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 350 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 351 | } |
| 352 | |
| 353 | /** |
| 354 | * Returns the current tiling mode and required bit 6 swizzling for the object. |
| 355 | */ |
| 356 | int |
| 357 | i915_gem_get_tiling(struct drm_device *dev, void *data, |
| 358 | struct drm_file *file_priv) |
| 359 | { |
| 360 | struct drm_i915_gem_get_tiling *args = data; |
| 361 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 362 | struct drm_gem_object *obj; |
| 363 | struct drm_i915_gem_object *obj_priv; |
| 364 | |
| 365 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 366 | if (obj == NULL) |
| 367 | return -EINVAL; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 368 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 369 | |
| 370 | mutex_lock(&dev->struct_mutex); |
| 371 | |
| 372 | args->tiling_mode = obj_priv->tiling_mode; |
| 373 | switch (obj_priv->tiling_mode) { |
| 374 | case I915_TILING_X: |
| 375 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; |
| 376 | break; |
| 377 | case I915_TILING_Y: |
| 378 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; |
| 379 | break; |
| 380 | case I915_TILING_NONE: |
| 381 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
| 382 | break; |
| 383 | default: |
| 384 | DRM_ERROR("unknown tiling mode\n"); |
| 385 | } |
| 386 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 387 | /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */ |
| 388 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) |
| 389 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9; |
| 390 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) |
| 391 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; |
| 392 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 393 | drm_gem_object_unreference(obj); |
Chris Wilson | d687310 | 2009-02-08 19:07:51 +0000 | [diff] [blame] | 394 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 395 | |
| 396 | return 0; |
| 397 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 398 | |
| 399 | /** |
| 400 | * Swap every 64 bytes of this page around, to account for it having a new |
| 401 | * bit 17 of its physical address and therefore being interpreted differently |
| 402 | * by the GPU. |
| 403 | */ |
| 404 | static int |
| 405 | i915_gem_swizzle_page(struct page *page) |
| 406 | { |
| 407 | char *vaddr; |
| 408 | int i; |
| 409 | char temp[64]; |
| 410 | |
| 411 | vaddr = kmap(page); |
| 412 | if (vaddr == NULL) |
| 413 | return -ENOMEM; |
| 414 | |
| 415 | for (i = 0; i < PAGE_SIZE; i += 128) { |
| 416 | memcpy(temp, &vaddr[i], 64); |
| 417 | memcpy(&vaddr[i], &vaddr[i + 64], 64); |
| 418 | memcpy(&vaddr[i + 64], temp, 64); |
| 419 | } |
| 420 | |
| 421 | kunmap(page); |
| 422 | |
| 423 | return 0; |
| 424 | } |
| 425 | |
| 426 | void |
| 427 | i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj) |
| 428 | { |
| 429 | struct drm_device *dev = obj->dev; |
| 430 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 431 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 432 | int page_count = obj->size >> PAGE_SHIFT; |
| 433 | int i; |
| 434 | |
| 435 | if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17) |
| 436 | return; |
| 437 | |
| 438 | if (obj_priv->bit_17 == NULL) |
| 439 | return; |
| 440 | |
| 441 | for (i = 0; i < page_count; i++) { |
| 442 | char new_bit_17 = page_to_phys(obj_priv->pages[i]) >> 17; |
| 443 | if ((new_bit_17 & 0x1) != |
| 444 | (test_bit(i, obj_priv->bit_17) != 0)) { |
| 445 | int ret = i915_gem_swizzle_page(obj_priv->pages[i]); |
| 446 | if (ret != 0) { |
| 447 | DRM_ERROR("Failed to swizzle page\n"); |
| 448 | return; |
| 449 | } |
| 450 | set_page_dirty(obj_priv->pages[i]); |
| 451 | } |
| 452 | } |
| 453 | } |
| 454 | |
| 455 | void |
| 456 | i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj) |
| 457 | { |
| 458 | struct drm_device *dev = obj->dev; |
| 459 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 460 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 461 | int page_count = obj->size >> PAGE_SHIFT; |
| 462 | int i; |
| 463 | |
| 464 | if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17) |
| 465 | return; |
| 466 | |
| 467 | if (obj_priv->bit_17 == NULL) { |
| 468 | obj_priv->bit_17 = kmalloc(BITS_TO_LONGS(page_count) * |
| 469 | sizeof(long), GFP_KERNEL); |
| 470 | if (obj_priv->bit_17 == NULL) { |
| 471 | DRM_ERROR("Failed to allocate memory for bit 17 " |
| 472 | "record\n"); |
| 473 | return; |
| 474 | } |
| 475 | } |
| 476 | |
| 477 | for (i = 0; i < page_count; i++) { |
| 478 | if (page_to_phys(obj_priv->pages[i]) & (1 << 17)) |
| 479 | __set_bit(i, obj_priv->bit_17); |
| 480 | else |
| 481 | __clear_bit(i, obj_priv->bit_17); |
| 482 | } |
| 483 | } |