Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/include/linux/clk-provider.h |
| 3 | * |
| 4 | * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> |
| 5 | * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | #ifndef __LINUX_CLK_PROVIDER_H |
| 12 | #define __LINUX_CLK_PROVIDER_H |
| 13 | |
Gerhard Sittig | aa514ce | 2013-07-22 14:14:40 +0200 | [diff] [blame] | 14 | #include <linux/io.h> |
Maxime Ripard | 355bb16 | 2014-08-30 21:18:00 +0200 | [diff] [blame] | 15 | #include <linux/of.h> |
Stephen Boyd | 5cb05a1 | 2016-05-16 11:05:16 +0530 | [diff] [blame] | 16 | #include <linux/mutex.h> |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 17 | |
| 18 | #ifdef CONFIG_COMMON_CLK |
| 19 | |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 20 | /* |
| 21 | * flags used across common struct clk. these flags should only affect the |
| 22 | * top-level framework. custom flags for dealing with hardware specifics |
| 23 | * belong in struct clk_foo |
| 24 | */ |
| 25 | #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ |
| 26 | #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ |
| 27 | #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ |
| 28 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ |
Stephen Boyd | b9610e7 | 2016-06-01 14:56:57 -0700 | [diff] [blame] | 29 | /* unused */ |
Rajendra Nayak | f7d8caa | 2012-06-01 14:02:47 +0530 | [diff] [blame] | 30 | #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ |
Ulf Hansson | a093bde | 2012-08-31 14:21:28 +0200 | [diff] [blame] | 31 | #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 32 | #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ |
Boris BREZILLON | 5279fc4 | 2013-12-21 10:34:47 +0100 | [diff] [blame] | 33 | #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ |
Bartlomiej Zolnierkiewicz | d8d9198 | 2015-04-03 18:43:44 +0200 | [diff] [blame] | 34 | #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ |
Heiko Stuebner | 2eb8c71 | 2015-12-22 22:27:58 +0100 | [diff] [blame] | 35 | #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ |
Lee Jones | 32b9b10 | 2016-02-11 13:19:09 -0800 | [diff] [blame] | 36 | #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ |
Dong Aisheng | a4b3518 | 2016-06-30 17:31:13 +0800 | [diff] [blame] | 37 | /* parents need enable during gate/ungate, set rate and re-parent */ |
| 38 | #define CLK_OPS_PARENT_ENABLE BIT(12) |
Michael Turquette | e9b8c59 | 2017-04-21 12:27:39 +0530 | [diff] [blame] | 39 | #define CLK_ENABLE_HAND_OFF BIT(13) /* enable clock when registered. */ |
| 40 | /* |
| 41 | * hand-off enable_count & prepare_count |
| 42 | * to first consumer that enables clk |
| 43 | */ |
Taniya Das | 8436bd7 | 2016-11-21 17:50:13 +0530 | [diff] [blame] | 44 | #define CLK_IS_MEASURE BIT(14) /* measure clock */ |
Deepak Katragadda | bfb9650 | 2018-02-07 10:37:41 -0800 | [diff] [blame] | 45 | /* do not call clk_change_rate on the clock's children */ |
| 46 | #define CLK_CHILD_NO_RATE_PROP BIT(15) |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 47 | |
Stephen Boyd | 61ae765 | 2015-06-22 17:13:49 -0700 | [diff] [blame] | 48 | struct clk; |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 49 | struct clk_hw; |
Tomeu Vizoso | 035a61c | 2015-01-23 12:03:30 +0100 | [diff] [blame] | 50 | struct clk_core; |
Alex Elder | c646cbf | 2014-03-21 06:43:56 -0500 | [diff] [blame] | 51 | struct dentry; |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 52 | |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 53 | /** |
Boris Brezillon | 0817b62 | 2015-07-07 20:48:08 +0200 | [diff] [blame] | 54 | * struct clk_rate_request - Structure encoding the clk constraints that |
| 55 | * a clock user might require. |
| 56 | * |
| 57 | * @rate: Requested clock rate. This field will be adjusted by |
| 58 | * clock drivers according to hardware capabilities. |
| 59 | * @min_rate: Minimum rate imposed by clk users. |
Masahiro Yamada | 1971dfb | 2015-11-05 18:02:34 +0900 | [diff] [blame] | 60 | * @max_rate: Maximum rate imposed by clk users. |
Boris Brezillon | 0817b62 | 2015-07-07 20:48:08 +0200 | [diff] [blame] | 61 | * @best_parent_rate: The best parent rate a parent can provide to fulfill the |
| 62 | * requested constraints. |
| 63 | * @best_parent_hw: The most appropriate parent clock that fulfills the |
| 64 | * requested constraints. |
| 65 | * |
| 66 | */ |
| 67 | struct clk_rate_request { |
| 68 | unsigned long rate; |
| 69 | unsigned long min_rate; |
| 70 | unsigned long max_rate; |
| 71 | unsigned long best_parent_rate; |
| 72 | struct clk_hw *best_parent_hw; |
| 73 | }; |
| 74 | |
| 75 | /** |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 76 | * struct clk_ops - Callback operations for hardware clocks; these are to |
| 77 | * be provided by the clock implementation, and will be called by drivers |
| 78 | * through the clk_* api. |
| 79 | * |
| 80 | * @prepare: Prepare the clock for enabling. This must not return until |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 81 | * the clock is fully prepared, and it's safe to call clk_enable. |
| 82 | * This callback is intended to allow clock implementations to |
| 83 | * do any initialisation that may sleep. Called with |
| 84 | * prepare_lock held. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 85 | * |
| 86 | * @unprepare: Release the clock from its prepared state. This will typically |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 87 | * undo any work done in the @prepare callback. Called with |
| 88 | * prepare_lock held. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 89 | * |
Ulf Hansson | 3d6ee28 | 2013-03-12 20:26:02 +0100 | [diff] [blame] | 90 | * @is_prepared: Queries the hardware to determine if the clock is prepared. |
| 91 | * This function is allowed to sleep. Optional, if this op is not |
| 92 | * set then the prepare count will be used. |
| 93 | * |
Ulf Hansson | 3cc8247 | 2013-03-12 20:26:04 +0100 | [diff] [blame] | 94 | * @unprepare_unused: Unprepare the clock atomically. Only called from |
| 95 | * clk_disable_unused for prepare clocks with special needs. |
| 96 | * Called with prepare mutex held. This function may sleep. |
| 97 | * |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 98 | * @enable: Enable the clock atomically. This must not return until the |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 99 | * clock is generating a valid clock signal, usable by consumer |
| 100 | * devices. Called with enable_lock held. This function must not |
| 101 | * sleep. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 102 | * |
| 103 | * @disable: Disable the clock atomically. Called with enable_lock held. |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 104 | * This function must not sleep. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 105 | * |
Stephen Boyd | 119c712 | 2012-10-03 23:38:53 -0700 | [diff] [blame] | 106 | * @is_enabled: Queries the hardware to determine if the clock is enabled. |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 107 | * This function must not sleep. Optional, if this op is not |
| 108 | * set then the enable count will be used. |
Stephen Boyd | 119c712 | 2012-10-03 23:38:53 -0700 | [diff] [blame] | 109 | * |
Mike Turquette | 7c045a5 | 2012-12-04 11:00:35 -0800 | [diff] [blame] | 110 | * @disable_unused: Disable the clock atomically. Only called from |
| 111 | * clk_disable_unused for gate clocks with special needs. |
| 112 | * Called with enable_lock held. This function must not |
| 113 | * sleep. |
| 114 | * |
Stephen Boyd | 7ce3e8c | 2012-10-03 23:38:54 -0700 | [diff] [blame] | 115 | * @recalc_rate Recalculate the rate of this clock, by querying hardware. The |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 116 | * parent rate is an input parameter. It is up to the caller to |
| 117 | * ensure that the prepare_mutex is held across this call. |
| 118 | * Returns the calculated rate. Optional, but recommended - if |
| 119 | * this op is not set then clock rate will be initialized to 0. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 120 | * |
| 121 | * @round_rate: Given a target rate as input, returns the closest rate actually |
Geert Uytterhoeven | 54e7301 | 2014-04-22 15:11:42 +0200 | [diff] [blame] | 122 | * supported by the clock. The parent rate is an input/output |
| 123 | * parameter. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 124 | * |
James Hogan | 71472c0 | 2013-07-29 12:25:00 +0100 | [diff] [blame] | 125 | * @determine_rate: Given a target rate as input, returns the closest rate |
| 126 | * actually supported by the clock, and optionally the parent clock |
| 127 | * that should be used to provide the clock rate. |
| 128 | * |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 129 | * @set_parent: Change the input source of this clock; for clocks with multiple |
Geert Uytterhoeven | 54e7301 | 2014-04-22 15:11:42 +0200 | [diff] [blame] | 130 | * possible parents specify a new parent by passing in the index |
| 131 | * as a u8 corresponding to the parent in either the .parent_names |
| 132 | * or .parents arrays. This function in affect translates an |
| 133 | * array index into the value programmed into the hardware. |
| 134 | * Returns 0 on success, -EERROR otherwise. |
| 135 | * |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 136 | * @get_parent: Queries the hardware to determine the parent of a clock. The |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 137 | * return value is a u8 which specifies the index corresponding to |
| 138 | * the parent clock. This index can be applied to either the |
| 139 | * .parent_names or .parents arrays. In short, this function |
| 140 | * translates the parent value read from hardware into an array |
| 141 | * index. Currently only called when the clock is initialized by |
| 142 | * __clk_init. This callback is mandatory for clocks with |
| 143 | * multiple parents. It is optional (and unnecessary) for clocks |
| 144 | * with 0 or 1 parents. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 145 | * |
Shawn Guo | 1c0035d | 2012-04-12 20:50:18 +0800 | [diff] [blame] | 146 | * @set_rate: Change the rate of this clock. The requested rate is specified |
| 147 | * by the second argument, which should typically be the return |
| 148 | * of .round_rate call. The third argument gives the parent rate |
| 149 | * which is likely helpful for most .set_rate implementation. |
| 150 | * Returns 0 on success, -EERROR otherwise. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 151 | * |
Stephen Boyd | 3fa2252 | 2014-01-15 10:47:22 -0800 | [diff] [blame] | 152 | * @set_rate_and_parent: Change the rate and the parent of this clock. The |
| 153 | * requested rate is specified by the second argument, which |
| 154 | * should typically be the return of .round_rate call. The |
| 155 | * third argument gives the parent rate which is likely helpful |
| 156 | * for most .set_rate_and_parent implementation. The fourth |
| 157 | * argument gives the parent index. This callback is optional (and |
| 158 | * unnecessary) for clocks with 0 or 1 parents as well as |
| 159 | * for clocks that can tolerate switching the rate and the parent |
| 160 | * separately via calls to .set_parent and .set_rate. |
| 161 | * Returns 0 on success, -EERROR otherwise. |
| 162 | * |
Geert Uytterhoeven | 54e7301 | 2014-04-22 15:11:42 +0200 | [diff] [blame] | 163 | * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy |
| 164 | * is expressed in ppb (parts per billion). The parent accuracy is |
| 165 | * an input parameter. |
| 166 | * Returns the calculated accuracy. Optional - if this op is not |
| 167 | * set then clock accuracy will be initialized to parent accuracy |
| 168 | * or 0 (perfect clock) if clock has no parent. |
| 169 | * |
Maxime Ripard | 9824cf7 | 2014-07-14 13:53:27 +0200 | [diff] [blame] | 170 | * @get_phase: Queries the hardware to get the current phase of a clock. |
| 171 | * Returned values are 0-359 degrees on success, negative |
| 172 | * error codes on failure. |
| 173 | * |
Mike Turquette | e59c537 | 2014-02-18 21:21:25 -0800 | [diff] [blame] | 174 | * @set_phase: Shift the phase this clock signal in degrees specified |
| 175 | * by the second argument. Valid values for degrees are |
| 176 | * 0-359. Return 0 on success, otherwise -EERROR. |
| 177 | * |
Geert Uytterhoeven | 54e7301 | 2014-04-22 15:11:42 +0200 | [diff] [blame] | 178 | * @init: Perform platform-specific initialization magic. |
| 179 | * This is not not used by any of the basic clock types. |
| 180 | * Please consider other ways of solving initialization problems |
| 181 | * before using this callback, as its use is discouraged. |
| 182 | * |
Alex Elder | c646cbf | 2014-03-21 06:43:56 -0500 | [diff] [blame] | 183 | * @debug_init: Set up type-specific debugfs entries for this clock. This |
| 184 | * is called once, after the debugfs directory entry for this |
| 185 | * clock has been created. The dentry pointer representing that |
| 186 | * directory is provided as an argument. Called with |
| 187 | * prepare_lock held. Returns 0 on success, -EERROR otherwise. |
| 188 | * |
Taniya Das | 63c20c7 | 2016-06-15 12:15:01 +0530 | [diff] [blame] | 189 | * @set_flags: Set custom flags which deal with hardware specifics. Returns 0 |
| 190 | * on success, -EERROR otherwise. |
Stephen Boyd | 3fa2252 | 2014-01-15 10:47:22 -0800 | [diff] [blame] | 191 | * |
Taniya Das | 2dd2572 | 2016-11-14 11:26:02 +0530 | [diff] [blame] | 192 | * @list_registers: Queries the hardware to get the current register contents. |
| 193 | * This callback is optional. |
| 194 | * |
Taniya Das | 876112d | 2016-11-14 11:54:02 +0530 | [diff] [blame] | 195 | * @list_rate: On success, return the nth supported frequency for a given |
| 196 | * clock that is below rate_max. Return -ENXIO in case there is |
| 197 | * no frequency table. |
| 198 | * |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 199 | * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow |
| 200 | * implementations to split any work between atomic (enable) and sleepable |
| 201 | * (prepare) contexts. If enabling a clock requires code that might sleep, |
| 202 | * this must be done in clk_prepare. Clock enable code that will never be |
Stephen Boyd | 7ce3e8c | 2012-10-03 23:38:54 -0700 | [diff] [blame] | 203 | * called in a sleepable context may be implemented in clk_enable. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 204 | * |
| 205 | * Typically, drivers will call clk_prepare when a clock may be needed later |
| 206 | * (eg. when a device is opened), and clk_enable when the clock is actually |
| 207 | * required (eg. from an interrupt). Note that clk_prepare MUST have been |
| 208 | * called before clk_enable. |
| 209 | */ |
| 210 | struct clk_ops { |
| 211 | int (*prepare)(struct clk_hw *hw); |
| 212 | void (*unprepare)(struct clk_hw *hw); |
Ulf Hansson | 3d6ee28 | 2013-03-12 20:26:02 +0100 | [diff] [blame] | 213 | int (*is_prepared)(struct clk_hw *hw); |
Ulf Hansson | 3cc8247 | 2013-03-12 20:26:04 +0100 | [diff] [blame] | 214 | void (*unprepare_unused)(struct clk_hw *hw); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 215 | int (*enable)(struct clk_hw *hw); |
| 216 | void (*disable)(struct clk_hw *hw); |
| 217 | int (*is_enabled)(struct clk_hw *hw); |
Mike Turquette | 7c045a5 | 2012-12-04 11:00:35 -0800 | [diff] [blame] | 218 | void (*disable_unused)(struct clk_hw *hw); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 219 | unsigned long (*recalc_rate)(struct clk_hw *hw, |
| 220 | unsigned long parent_rate); |
Geert Uytterhoeven | 54e7301 | 2014-04-22 15:11:42 +0200 | [diff] [blame] | 221 | long (*round_rate)(struct clk_hw *hw, unsigned long rate, |
| 222 | unsigned long *parent_rate); |
Boris Brezillon | 0817b62 | 2015-07-07 20:48:08 +0200 | [diff] [blame] | 223 | int (*determine_rate)(struct clk_hw *hw, |
| 224 | struct clk_rate_request *req); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 225 | int (*set_parent)(struct clk_hw *hw, u8 index); |
| 226 | u8 (*get_parent)(struct clk_hw *hw); |
Geert Uytterhoeven | 54e7301 | 2014-04-22 15:11:42 +0200 | [diff] [blame] | 227 | int (*set_rate)(struct clk_hw *hw, unsigned long rate, |
| 228 | unsigned long parent_rate); |
Stephen Boyd | 3fa2252 | 2014-01-15 10:47:22 -0800 | [diff] [blame] | 229 | int (*set_rate_and_parent)(struct clk_hw *hw, |
| 230 | unsigned long rate, |
| 231 | unsigned long parent_rate, u8 index); |
Boris BREZILLON | 5279fc4 | 2013-12-21 10:34:47 +0100 | [diff] [blame] | 232 | unsigned long (*recalc_accuracy)(struct clk_hw *hw, |
| 233 | unsigned long parent_accuracy); |
Maxime Ripard | 9824cf7 | 2014-07-14 13:53:27 +0200 | [diff] [blame] | 234 | int (*get_phase)(struct clk_hw *hw); |
Mike Turquette | e59c537 | 2014-02-18 21:21:25 -0800 | [diff] [blame] | 235 | int (*set_phase)(struct clk_hw *hw, int degrees); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 236 | void (*init)(struct clk_hw *hw); |
Alex Elder | c646cbf | 2014-03-21 06:43:56 -0500 | [diff] [blame] | 237 | int (*debug_init)(struct clk_hw *hw, struct dentry *dentry); |
Taniya Das | 63c20c7 | 2016-06-15 12:15:01 +0530 | [diff] [blame] | 238 | int (*set_flags)(struct clk_hw *hw, unsigned int flags); |
Taniya Das | 2dd2572 | 2016-11-14 11:26:02 +0530 | [diff] [blame] | 239 | void (*list_registers)(struct seq_file *f, |
| 240 | struct clk_hw *hw); |
Taniya Das | 876112d | 2016-11-14 11:54:02 +0530 | [diff] [blame] | 241 | long (*list_rate)(struct clk_hw *hw, unsigned int n, |
| 242 | unsigned long rate_max); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 243 | }; |
| 244 | |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 245 | /** |
| 246 | * struct clk_init_data - holds init data that's common to all clocks and is |
| 247 | * shared between the clock provider and the common clock framework. |
| 248 | * |
| 249 | * @name: clock name |
| 250 | * @ops: operations this clock supports |
| 251 | * @parent_names: array of string names for all possible parents |
| 252 | * @num_parents: number of possible parents |
| 253 | * @flags: framework-level hints and quirks |
Stephen Boyd | 5cb05a1 | 2016-05-16 11:05:16 +0530 | [diff] [blame] | 254 | * @vdd_class: voltage scaling requirement class |
| 255 | * @rate_max: maximum clock rate in Hz supported at each voltage level |
| 256 | * @num_rate_max: number of maximum voltage level supported |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 257 | */ |
| 258 | struct clk_init_data { |
| 259 | const char *name; |
| 260 | const struct clk_ops *ops; |
Sascha Hauer | 2893c37 | 2015-03-31 20:16:52 +0200 | [diff] [blame] | 261 | const char * const *parent_names; |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 262 | u8 num_parents; |
| 263 | unsigned long flags; |
Stephen Boyd | 5cb05a1 | 2016-05-16 11:05:16 +0530 | [diff] [blame] | 264 | struct clk_vdd_class *vdd_class; |
| 265 | unsigned long *rate_max; |
| 266 | int num_rate_max; |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 267 | }; |
| 268 | |
Stephen Boyd | 5cb05a1 | 2016-05-16 11:05:16 +0530 | [diff] [blame] | 269 | struct regulator; |
| 270 | |
| 271 | /** |
| 272 | * struct clk_vdd_class - Voltage scaling class |
| 273 | * @class_name: name of the class |
| 274 | * @regulator: array of regulators |
| 275 | * @num_regulators: size of regulator array. Standard regulator APIs will be |
| 276 | used if this field > 0 |
| 277 | * @set_vdd: function to call when applying a new voltage setting |
| 278 | * @vdd_uv: sorted 2D array of legal voltage settings. Indexed by level, then |
| 279 | regulator |
| 280 | * @level_votes: array of votes for each level |
| 281 | * @num_levels: specifies the size of level_votes array |
Taniya Das | eee50c8 | 2016-12-03 19:06:59 +0530 | [diff] [blame] | 282 | * @skip_handoff: do not vote for the max possible voltage during init |
| 283 | * @use_max_uV: use INT_MAX for max_uV when calling regulator_set_voltage |
Stephen Boyd | 5cb05a1 | 2016-05-16 11:05:16 +0530 | [diff] [blame] | 284 | * @cur_level: the currently set voltage level |
| 285 | * @lock: lock to protect this struct |
| 286 | */ |
| 287 | struct clk_vdd_class { |
| 288 | const char *class_name; |
| 289 | struct regulator **regulator; |
| 290 | int num_regulators; |
| 291 | int (*set_vdd)(struct clk_vdd_class *v_class, int level); |
| 292 | int *vdd_uv; |
| 293 | int *level_votes; |
| 294 | int num_levels; |
Taniya Das | eee50c8 | 2016-12-03 19:06:59 +0530 | [diff] [blame] | 295 | bool skip_handoff; |
| 296 | bool use_max_uV; |
Stephen Boyd | 5cb05a1 | 2016-05-16 11:05:16 +0530 | [diff] [blame] | 297 | unsigned long cur_level; |
| 298 | struct mutex lock; |
| 299 | }; |
| 300 | |
| 301 | #define DEFINE_VDD_CLASS(_name, _set_vdd, _num_levels) \ |
| 302 | struct clk_vdd_class _name = { \ |
| 303 | .class_name = #_name, \ |
| 304 | .set_vdd = _set_vdd, \ |
| 305 | .level_votes = (int [_num_levels]) {}, \ |
| 306 | .num_levels = _num_levels, \ |
| 307 | .cur_level = _num_levels, \ |
| 308 | .lock = __MUTEX_INITIALIZER(_name.lock) \ |
| 309 | } |
| 310 | |
| 311 | #define DEFINE_VDD_REGULATORS(_name, _num_levels, _num_regulators, _vdd_uv) \ |
| 312 | struct clk_vdd_class _name = { \ |
| 313 | .class_name = #_name, \ |
| 314 | .vdd_uv = _vdd_uv, \ |
| 315 | .regulator = (struct regulator * [_num_regulators]) {}, \ |
| 316 | .num_regulators = _num_regulators, \ |
| 317 | .level_votes = (int [_num_levels]) {}, \ |
| 318 | .num_levels = _num_levels, \ |
| 319 | .cur_level = _num_levels, \ |
| 320 | .lock = __MUTEX_INITIALIZER(_name.lock) \ |
| 321 | } |
| 322 | |
| 323 | #define DEFINE_VDD_REGS_INIT(_name, _num_regulators) \ |
| 324 | struct clk_vdd_class _name = { \ |
| 325 | .class_name = #_name, \ |
| 326 | .regulator = (struct regulator * [_num_regulators]) {}, \ |
| 327 | .num_regulators = _num_regulators, \ |
| 328 | .lock = __MUTEX_INITIALIZER(_name.lock) \ |
| 329 | } |
| 330 | |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 331 | /** |
| 332 | * struct clk_hw - handle for traversing from a struct clk to its corresponding |
| 333 | * hardware-specific structure. struct clk_hw should be declared within struct |
| 334 | * clk_foo and then referenced by the struct clk instance that uses struct |
| 335 | * clk_foo's clk_ops |
| 336 | * |
Tomeu Vizoso | 035a61c | 2015-01-23 12:03:30 +0100 | [diff] [blame] | 337 | * @core: pointer to the struct clk_core instance that points back to this |
| 338 | * struct clk_hw instance |
| 339 | * |
| 340 | * @clk: pointer to the per-user struct clk instance that can be used to call |
| 341 | * into the clk API |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 342 | * |
| 343 | * @init: pointer to struct clk_init_data that contains the init data shared |
| 344 | * with the common clock framework. |
| 345 | */ |
| 346 | struct clk_hw { |
Tomeu Vizoso | 035a61c | 2015-01-23 12:03:30 +0100 | [diff] [blame] | 347 | struct clk_core *core; |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 348 | struct clk *clk; |
Mark Brown | dc4cd94 | 2012-05-14 15:12:42 +0100 | [diff] [blame] | 349 | const struct clk_init_data *init; |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 350 | }; |
| 351 | |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 352 | /* |
| 353 | * DOC: Basic clock implementations common to many platforms |
| 354 | * |
| 355 | * Each basic clock hardware type is comprised of a structure describing the |
| 356 | * clock hardware, implementations of the relevant callbacks in struct clk_ops, |
| 357 | * unique flags for that hardware type, a registration function and an |
| 358 | * alternative macro for static initialization |
| 359 | */ |
| 360 | |
| 361 | /** |
| 362 | * struct clk_fixed_rate - fixed-rate clock |
| 363 | * @hw: handle between common and hardware-specific interfaces |
| 364 | * @fixed_rate: constant frequency of clock |
| 365 | */ |
| 366 | struct clk_fixed_rate { |
| 367 | struct clk_hw hw; |
| 368 | unsigned long fixed_rate; |
Boris BREZILLON | 0903ea6 | 2013-12-21 10:34:48 +0100 | [diff] [blame] | 369 | unsigned long fixed_accuracy; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 370 | u8 flags; |
| 371 | }; |
| 372 | |
Geliang Tang | 5fd9c05 | 2016-01-08 23:51:46 +0800 | [diff] [blame] | 373 | #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) |
| 374 | |
Shawn Guo | bffad66 | 2012-03-27 15:23:23 +0800 | [diff] [blame] | 375 | extern const struct clk_ops clk_fixed_rate_ops; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 376 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
| 377 | const char *parent_name, unsigned long flags, |
| 378 | unsigned long fixed_rate); |
Stephen Boyd | 26ef56b | 2016-02-07 00:34:13 -0800 | [diff] [blame] | 379 | struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name, |
| 380 | const char *parent_name, unsigned long flags, |
| 381 | unsigned long fixed_rate); |
Boris BREZILLON | 0903ea6 | 2013-12-21 10:34:48 +0100 | [diff] [blame] | 382 | struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, |
| 383 | const char *name, const char *parent_name, unsigned long flags, |
| 384 | unsigned long fixed_rate, unsigned long fixed_accuracy); |
Masahiro Yamada | 0b225e4 | 2016-01-06 13:25:10 +0900 | [diff] [blame] | 385 | void clk_unregister_fixed_rate(struct clk *clk); |
Stephen Boyd | 26ef56b | 2016-02-07 00:34:13 -0800 | [diff] [blame] | 386 | struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev, |
| 387 | const char *name, const char *parent_name, unsigned long flags, |
| 388 | unsigned long fixed_rate, unsigned long fixed_accuracy); |
Masahiro Yamada | 5244563 | 2016-05-22 14:33:35 +0900 | [diff] [blame] | 389 | void clk_hw_unregister_fixed_rate(struct clk_hw *hw); |
Stephen Boyd | 26ef56b | 2016-02-07 00:34:13 -0800 | [diff] [blame] | 390 | |
Grant Likely | 015ba40 | 2012-04-07 21:39:39 -0500 | [diff] [blame] | 391 | void of_fixed_clk_setup(struct device_node *np); |
| 392 | |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 393 | /** |
| 394 | * struct clk_gate - gating clock |
| 395 | * |
| 396 | * @hw: handle between common and hardware-specific interfaces |
| 397 | * @reg: register controlling gate |
| 398 | * @bit_idx: single bit controlling gate |
| 399 | * @flags: hardware-specific flags |
| 400 | * @lock: register lock |
| 401 | * |
| 402 | * Clock which can gate its output. Implements .enable & .disable |
| 403 | * |
| 404 | * Flags: |
Viresh Kumar | 1f73f31 | 2012-04-17 16:45:35 +0530 | [diff] [blame] | 405 | * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 406 | * enable the clock. Setting this flag does the opposite: setting the bit |
| 407 | * disable the clock and clearing it enables the clock |
Haojian Zhuang | 0457799 | 2013-06-08 22:47:19 +0800 | [diff] [blame] | 408 | * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 409 | * of this register, and mask of gate bits are in higher 16-bit of this |
| 410 | * register. While setting the gate bits, higher 16-bit should also be |
| 411 | * updated to indicate changing gate bits. |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 412 | */ |
| 413 | struct clk_gate { |
| 414 | struct clk_hw hw; |
| 415 | void __iomem *reg; |
| 416 | u8 bit_idx; |
| 417 | u8 flags; |
| 418 | spinlock_t *lock; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 419 | }; |
| 420 | |
Geliang Tang | 5fd9c05 | 2016-01-08 23:51:46 +0800 | [diff] [blame] | 421 | #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) |
| 422 | |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 423 | #define CLK_GATE_SET_TO_DISABLE BIT(0) |
Haojian Zhuang | 0457799 | 2013-06-08 22:47:19 +0800 | [diff] [blame] | 424 | #define CLK_GATE_HIWORD_MASK BIT(1) |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 425 | |
Shawn Guo | bffad66 | 2012-03-27 15:23:23 +0800 | [diff] [blame] | 426 | extern const struct clk_ops clk_gate_ops; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 427 | struct clk *clk_register_gate(struct device *dev, const char *name, |
| 428 | const char *parent_name, unsigned long flags, |
| 429 | void __iomem *reg, u8 bit_idx, |
| 430 | u8 clk_gate_flags, spinlock_t *lock); |
Stephen Boyd | e270d8c | 2016-02-06 23:54:45 -0800 | [diff] [blame] | 431 | struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name, |
| 432 | const char *parent_name, unsigned long flags, |
| 433 | void __iomem *reg, u8 bit_idx, |
| 434 | u8 clk_gate_flags, spinlock_t *lock); |
Krzysztof Kozlowski | 4e3c021 | 2015-01-05 10:52:40 +0100 | [diff] [blame] | 435 | void clk_unregister_gate(struct clk *clk); |
Stephen Boyd | e270d8c | 2016-02-06 23:54:45 -0800 | [diff] [blame] | 436 | void clk_hw_unregister_gate(struct clk_hw *hw); |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 437 | |
Rajendra Nayak | 357c3f0 | 2012-06-29 19:06:32 +0530 | [diff] [blame] | 438 | struct clk_div_table { |
| 439 | unsigned int val; |
| 440 | unsigned int div; |
| 441 | }; |
| 442 | |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 443 | /** |
| 444 | * struct clk_divider - adjustable divider clock |
| 445 | * |
| 446 | * @hw: handle between common and hardware-specific interfaces |
| 447 | * @reg: register containing the divider |
| 448 | * @shift: shift to the divider bit field |
| 449 | * @width: width of the divider bit field |
Rajendra Nayak | 357c3f0 | 2012-06-29 19:06:32 +0530 | [diff] [blame] | 450 | * @table: array of value/divider pairs, last entry should have div = 0 |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 451 | * @lock: register lock |
| 452 | * |
| 453 | * Clock with an adjustable divider affecting its output frequency. Implements |
| 454 | * .recalc_rate, .set_rate and .round_rate |
| 455 | * |
| 456 | * Flags: |
| 457 | * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 458 | * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is |
| 459 | * the raw value read from the register, with the value of zero considered |
Soren Brinkmann | 056b2053 | 2013-04-02 15:36:56 -0700 | [diff] [blame] | 460 | * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 461 | * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 462 | * the hardware register |
Soren Brinkmann | 056b2053 | 2013-04-02 15:36:56 -0700 | [diff] [blame] | 463 | * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have |
| 464 | * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. |
| 465 | * Some hardware implementations gracefully handle this case and allow a |
| 466 | * zero divisor by not modifying their input clock |
| 467 | * (divide by one / bypass). |
Haojian Zhuang | d57dfe7 | 2013-06-08 22:47:18 +0800 | [diff] [blame] | 468 | * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 469 | * of this register, and mask of divider bits are in higher 16-bit of this |
| 470 | * register. While setting the divider bits, higher 16-bit should also be |
| 471 | * updated to indicate changing divider bits. |
Maxime COQUELIN | 774b514 | 2014-01-29 17:24:07 +0100 | [diff] [blame] | 472 | * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded |
| 473 | * to the closest integer instead of the up one. |
Heiko Stuebner | 79c6ab5 | 2014-05-23 18:32:15 +0530 | [diff] [blame] | 474 | * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should |
| 475 | * not be changed by the clock framework. |
Jim Quinlan | afe76c8f | 2015-05-15 15:45:47 -0400 | [diff] [blame] | 476 | * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED |
| 477 | * except when the value read from the register is zero, the divisor is |
| 478 | * 2^width of the field. |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 479 | */ |
| 480 | struct clk_divider { |
| 481 | struct clk_hw hw; |
| 482 | void __iomem *reg; |
| 483 | u8 shift; |
| 484 | u8 width; |
| 485 | u8 flags; |
Rajendra Nayak | 357c3f0 | 2012-06-29 19:06:32 +0530 | [diff] [blame] | 486 | const struct clk_div_table *table; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 487 | spinlock_t *lock; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 488 | }; |
| 489 | |
Geliang Tang | 5fd9c05 | 2016-01-08 23:51:46 +0800 | [diff] [blame] | 490 | #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) |
| 491 | |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 492 | #define CLK_DIVIDER_ONE_BASED BIT(0) |
| 493 | #define CLK_DIVIDER_POWER_OF_TWO BIT(1) |
Soren Brinkmann | 056b2053 | 2013-04-02 15:36:56 -0700 | [diff] [blame] | 494 | #define CLK_DIVIDER_ALLOW_ZERO BIT(2) |
Haojian Zhuang | d57dfe7 | 2013-06-08 22:47:18 +0800 | [diff] [blame] | 495 | #define CLK_DIVIDER_HIWORD_MASK BIT(3) |
Maxime COQUELIN | 774b514 | 2014-01-29 17:24:07 +0100 | [diff] [blame] | 496 | #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) |
Heiko Stuebner | 79c6ab5 | 2014-05-23 18:32:15 +0530 | [diff] [blame] | 497 | #define CLK_DIVIDER_READ_ONLY BIT(5) |
Jim Quinlan | afe76c8f | 2015-05-15 15:45:47 -0400 | [diff] [blame] | 498 | #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) |
Vicky Wallace | 9c866bb | 2017-05-05 12:21:28 -0700 | [diff] [blame] | 499 | #define CLK_DIVIDER_ROUND_KHZ BIT(7) |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 500 | |
Shawn Guo | bffad66 | 2012-03-27 15:23:23 +0800 | [diff] [blame] | 501 | extern const struct clk_ops clk_divider_ops; |
Heiko Stuebner | 5035981 | 2016-01-21 21:53:09 +0100 | [diff] [blame] | 502 | extern const struct clk_ops clk_divider_ro_ops; |
Stephen Boyd | bca9690 | 2015-01-19 18:05:29 -0800 | [diff] [blame] | 503 | |
| 504 | unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, |
| 505 | unsigned int val, const struct clk_div_table *table, |
| 506 | unsigned long flags); |
| 507 | long divider_round_rate(struct clk_hw *hw, unsigned long rate, |
| 508 | unsigned long *prate, const struct clk_div_table *table, |
| 509 | u8 width, unsigned long flags); |
| 510 | int divider_get_val(unsigned long rate, unsigned long parent_rate, |
| 511 | const struct clk_div_table *table, u8 width, |
| 512 | unsigned long flags); |
| 513 | |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 514 | struct clk *clk_register_divider(struct device *dev, const char *name, |
| 515 | const char *parent_name, unsigned long flags, |
| 516 | void __iomem *reg, u8 shift, u8 width, |
| 517 | u8 clk_divider_flags, spinlock_t *lock); |
Stephen Boyd | eb7d264 | 2016-02-06 23:26:37 -0800 | [diff] [blame] | 518 | struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name, |
| 519 | const char *parent_name, unsigned long flags, |
| 520 | void __iomem *reg, u8 shift, u8 width, |
| 521 | u8 clk_divider_flags, spinlock_t *lock); |
Rajendra Nayak | 357c3f0 | 2012-06-29 19:06:32 +0530 | [diff] [blame] | 522 | struct clk *clk_register_divider_table(struct device *dev, const char *name, |
| 523 | const char *parent_name, unsigned long flags, |
| 524 | void __iomem *reg, u8 shift, u8 width, |
| 525 | u8 clk_divider_flags, const struct clk_div_table *table, |
| 526 | spinlock_t *lock); |
Stephen Boyd | eb7d264 | 2016-02-06 23:26:37 -0800 | [diff] [blame] | 527 | struct clk_hw *clk_hw_register_divider_table(struct device *dev, |
| 528 | const char *name, const char *parent_name, unsigned long flags, |
| 529 | void __iomem *reg, u8 shift, u8 width, |
| 530 | u8 clk_divider_flags, const struct clk_div_table *table, |
| 531 | spinlock_t *lock); |
Krzysztof Kozlowski | 4e3c021 | 2015-01-05 10:52:40 +0100 | [diff] [blame] | 532 | void clk_unregister_divider(struct clk *clk); |
Stephen Boyd | eb7d264 | 2016-02-06 23:26:37 -0800 | [diff] [blame] | 533 | void clk_hw_unregister_divider(struct clk_hw *hw); |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 534 | |
| 535 | /** |
| 536 | * struct clk_mux - multiplexer clock |
| 537 | * |
| 538 | * @hw: handle between common and hardware-specific interfaces |
| 539 | * @reg: register controlling multiplexer |
| 540 | * @shift: shift to multiplexer bit field |
| 541 | * @width: width of mutliplexer bit field |
James Hogan | 3566d40 | 2013-03-25 14:35:07 +0000 | [diff] [blame] | 542 | * @flags: hardware-specific flags |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 543 | * @lock: register lock |
| 544 | * |
| 545 | * Clock with multiple selectable parents. Implements .get_parent, .set_parent |
| 546 | * and .recalc_rate |
| 547 | * |
| 548 | * Flags: |
| 549 | * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 |
Viresh Kumar | 1f73f31 | 2012-04-17 16:45:35 +0530 | [diff] [blame] | 550 | * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) |
Haojian Zhuang | ba492e9 | 2013-06-08 22:47:17 +0800 | [diff] [blame] | 551 | * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this |
Geert Uytterhoeven | 725b418 | 2014-04-22 15:11:41 +0200 | [diff] [blame] | 552 | * register, and mask of mux bits are in higher 16-bit of this register. |
| 553 | * While setting the mux bits, higher 16-bit should also be updated to |
| 554 | * indicate changing mux bits. |
Stephen Boyd | 15a02c1 | 2015-01-19 18:05:28 -0800 | [diff] [blame] | 555 | * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired |
| 556 | * frequency. |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 557 | */ |
| 558 | struct clk_mux { |
| 559 | struct clk_hw hw; |
| 560 | void __iomem *reg; |
Peter De Schrijver | ce4f331 | 2013-03-22 14:07:53 +0200 | [diff] [blame] | 561 | u32 *table; |
| 562 | u32 mask; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 563 | u8 shift; |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 564 | u8 flags; |
| 565 | spinlock_t *lock; |
| 566 | }; |
| 567 | |
Geliang Tang | 5fd9c05 | 2016-01-08 23:51:46 +0800 | [diff] [blame] | 568 | #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) |
| 569 | |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 570 | #define CLK_MUX_INDEX_ONE BIT(0) |
| 571 | #define CLK_MUX_INDEX_BIT BIT(1) |
Haojian Zhuang | ba492e9 | 2013-06-08 22:47:17 +0800 | [diff] [blame] | 572 | #define CLK_MUX_HIWORD_MASK BIT(2) |
Stephen Boyd | 15a02c1 | 2015-01-19 18:05:28 -0800 | [diff] [blame] | 573 | #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ |
| 574 | #define CLK_MUX_ROUND_CLOSEST BIT(4) |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 575 | |
Shawn Guo | bffad66 | 2012-03-27 15:23:23 +0800 | [diff] [blame] | 576 | extern const struct clk_ops clk_mux_ops; |
Tomasz Figa | c57acd1 | 2013-07-23 01:49:18 +0200 | [diff] [blame] | 577 | extern const struct clk_ops clk_mux_ro_ops; |
Peter De Schrijver | ce4f331 | 2013-03-22 14:07:53 +0200 | [diff] [blame] | 578 | |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 579 | struct clk *clk_register_mux(struct device *dev, const char *name, |
Sascha Hauer | 2893c37 | 2015-03-31 20:16:52 +0200 | [diff] [blame] | 580 | const char * const *parent_names, u8 num_parents, |
| 581 | unsigned long flags, |
Mike Turquette | 9d9f78e | 2012-03-15 23:11:20 -0700 | [diff] [blame] | 582 | void __iomem *reg, u8 shift, u8 width, |
| 583 | u8 clk_mux_flags, spinlock_t *lock); |
Stephen Boyd | 264b317 | 2016-02-07 00:05:48 -0800 | [diff] [blame] | 584 | struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name, |
| 585 | const char * const *parent_names, u8 num_parents, |
| 586 | unsigned long flags, |
| 587 | void __iomem *reg, u8 shift, u8 width, |
| 588 | u8 clk_mux_flags, spinlock_t *lock); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 589 | |
Peter De Schrijver | ce4f331 | 2013-03-22 14:07:53 +0200 | [diff] [blame] | 590 | struct clk *clk_register_mux_table(struct device *dev, const char *name, |
Sascha Hauer | 2893c37 | 2015-03-31 20:16:52 +0200 | [diff] [blame] | 591 | const char * const *parent_names, u8 num_parents, |
| 592 | unsigned long flags, |
Peter De Schrijver | ce4f331 | 2013-03-22 14:07:53 +0200 | [diff] [blame] | 593 | void __iomem *reg, u8 shift, u32 mask, |
| 594 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); |
Stephen Boyd | 264b317 | 2016-02-07 00:05:48 -0800 | [diff] [blame] | 595 | struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name, |
| 596 | const char * const *parent_names, u8 num_parents, |
| 597 | unsigned long flags, |
| 598 | void __iomem *reg, u8 shift, u32 mask, |
| 599 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); |
Peter De Schrijver | ce4f331 | 2013-03-22 14:07:53 +0200 | [diff] [blame] | 600 | |
Krzysztof Kozlowski | 4e3c021 | 2015-01-05 10:52:40 +0100 | [diff] [blame] | 601 | void clk_unregister_mux(struct clk *clk); |
Stephen Boyd | 264b317 | 2016-02-07 00:05:48 -0800 | [diff] [blame] | 602 | void clk_hw_unregister_mux(struct clk_hw *hw); |
Krzysztof Kozlowski | 4e3c021 | 2015-01-05 10:52:40 +0100 | [diff] [blame] | 603 | |
Gregory CLEMENT | 79b1664 | 2013-04-12 13:57:44 +0200 | [diff] [blame] | 604 | void of_fixed_factor_clk_setup(struct device_node *node); |
| 605 | |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 606 | /** |
Sascha Hauer | f0948f5 | 2012-05-03 15:36:14 +0530 | [diff] [blame] | 607 | * struct clk_fixed_factor - fixed multiplier and divider clock |
| 608 | * |
| 609 | * @hw: handle between common and hardware-specific interfaces |
| 610 | * @mult: multiplier |
| 611 | * @div: divider |
| 612 | * |
| 613 | * Clock with a fixed multiplier and divider. The output frequency is the |
| 614 | * parent clock rate divided by div and multiplied by mult. |
| 615 | * Implements .recalc_rate, .set_rate and .round_rate |
| 616 | */ |
| 617 | |
| 618 | struct clk_fixed_factor { |
| 619 | struct clk_hw hw; |
| 620 | unsigned int mult; |
| 621 | unsigned int div; |
| 622 | }; |
| 623 | |
Geliang Tang | 5fd9c05 | 2016-01-08 23:51:46 +0800 | [diff] [blame] | 624 | #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) |
| 625 | |
Daniel Thompson | 3037e9e | 2015-06-10 21:04:54 +0100 | [diff] [blame] | 626 | extern const struct clk_ops clk_fixed_factor_ops; |
Sascha Hauer | f0948f5 | 2012-05-03 15:36:14 +0530 | [diff] [blame] | 627 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, |
| 628 | const char *parent_name, unsigned long flags, |
| 629 | unsigned int mult, unsigned int div); |
Masahiro Yamada | cbf9591 | 2016-01-06 13:25:09 +0900 | [diff] [blame] | 630 | void clk_unregister_fixed_factor(struct clk *clk); |
Stephen Boyd | 0759ac8 | 2016-02-07 00:11:06 -0800 | [diff] [blame] | 631 | struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, |
| 632 | const char *name, const char *parent_name, unsigned long flags, |
| 633 | unsigned int mult, unsigned int div); |
| 634 | void clk_hw_unregister_fixed_factor(struct clk_hw *hw); |
Sascha Hauer | f0948f5 | 2012-05-03 15:36:14 +0530 | [diff] [blame] | 635 | |
Heikki Krogerus | e2d0e90 | 2014-05-15 16:40:25 +0300 | [diff] [blame] | 636 | /** |
| 637 | * struct clk_fractional_divider - adjustable fractional divider clock |
| 638 | * |
| 639 | * @hw: handle between common and hardware-specific interfaces |
| 640 | * @reg: register containing the divider |
| 641 | * @mshift: shift to the numerator bit field |
| 642 | * @mwidth: width of the numerator bit field |
| 643 | * @nshift: shift to the denominator bit field |
| 644 | * @nwidth: width of the denominator bit field |
| 645 | * @lock: register lock |
| 646 | * |
| 647 | * Clock with adjustable fractional divider affecting its output frequency. |
| 648 | */ |
Heikki Krogerus | e2d0e90 | 2014-05-15 16:40:25 +0300 | [diff] [blame] | 649 | struct clk_fractional_divider { |
| 650 | struct clk_hw hw; |
| 651 | void __iomem *reg; |
| 652 | u8 mshift; |
Andy Shevchenko | 934e253 | 2015-09-22 18:54:09 +0300 | [diff] [blame] | 653 | u8 mwidth; |
Heikki Krogerus | e2d0e90 | 2014-05-15 16:40:25 +0300 | [diff] [blame] | 654 | u32 mmask; |
| 655 | u8 nshift; |
Andy Shevchenko | 934e253 | 2015-09-22 18:54:09 +0300 | [diff] [blame] | 656 | u8 nwidth; |
Heikki Krogerus | e2d0e90 | 2014-05-15 16:40:25 +0300 | [diff] [blame] | 657 | u32 nmask; |
| 658 | u8 flags; |
| 659 | spinlock_t *lock; |
| 660 | }; |
| 661 | |
Geliang Tang | 5fd9c05 | 2016-01-08 23:51:46 +0800 | [diff] [blame] | 662 | #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) |
| 663 | |
Heikki Krogerus | e2d0e90 | 2014-05-15 16:40:25 +0300 | [diff] [blame] | 664 | extern const struct clk_ops clk_fractional_divider_ops; |
| 665 | struct clk *clk_register_fractional_divider(struct device *dev, |
| 666 | const char *name, const char *parent_name, unsigned long flags, |
| 667 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, |
| 668 | u8 clk_divider_flags, spinlock_t *lock); |
Stephen Boyd | 39b44cf | 2016-02-07 00:15:09 -0800 | [diff] [blame] | 669 | struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, |
| 670 | const char *name, const char *parent_name, unsigned long flags, |
| 671 | void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, |
| 672 | u8 clk_divider_flags, spinlock_t *lock); |
| 673 | void clk_hw_unregister_fractional_divider(struct clk_hw *hw); |
Heikki Krogerus | e2d0e90 | 2014-05-15 16:40:25 +0300 | [diff] [blame] | 674 | |
Maxime Ripard | f2e0a53 | 2015-05-19 22:19:33 +0200 | [diff] [blame] | 675 | /** |
| 676 | * struct clk_multiplier - adjustable multiplier clock |
| 677 | * |
| 678 | * @hw: handle between common and hardware-specific interfaces |
| 679 | * @reg: register containing the multiplier |
| 680 | * @shift: shift to the multiplier bit field |
| 681 | * @width: width of the multiplier bit field |
| 682 | * @lock: register lock |
| 683 | * |
| 684 | * Clock with an adjustable multiplier affecting its output frequency. |
| 685 | * Implements .recalc_rate, .set_rate and .round_rate |
| 686 | * |
| 687 | * Flags: |
| 688 | * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read |
| 689 | * from the register, with 0 being a valid value effectively |
| 690 | * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is |
| 691 | * set, then a null multiplier will be considered as a bypass, |
| 692 | * leaving the parent rate unmodified. |
| 693 | * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be |
| 694 | * rounded to the closest integer instead of the down one. |
| 695 | */ |
| 696 | struct clk_multiplier { |
| 697 | struct clk_hw hw; |
| 698 | void __iomem *reg; |
| 699 | u8 shift; |
| 700 | u8 width; |
| 701 | u8 flags; |
| 702 | spinlock_t *lock; |
| 703 | }; |
| 704 | |
Geliang Tang | 5fd9c05 | 2016-01-08 23:51:46 +0800 | [diff] [blame] | 705 | #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) |
| 706 | |
Maxime Ripard | f2e0a53 | 2015-05-19 22:19:33 +0200 | [diff] [blame] | 707 | #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) |
| 708 | #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) |
| 709 | |
| 710 | extern const struct clk_ops clk_multiplier_ops; |
| 711 | |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 712 | /*** |
| 713 | * struct clk_composite - aggregate clock of mux, divider and gate clocks |
| 714 | * |
| 715 | * @hw: handle between common and hardware-specific interfaces |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 716 | * @mux_hw: handle between composite and hardware-specific mux clock |
| 717 | * @rate_hw: handle between composite and hardware-specific rate clock |
| 718 | * @gate_hw: handle between composite and hardware-specific gate clock |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 719 | * @mux_ops: clock ops for mux |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 720 | * @rate_ops: clock ops for rate |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 721 | * @gate_ops: clock ops for gate |
| 722 | */ |
| 723 | struct clk_composite { |
| 724 | struct clk_hw hw; |
| 725 | struct clk_ops ops; |
| 726 | |
| 727 | struct clk_hw *mux_hw; |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 728 | struct clk_hw *rate_hw; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 729 | struct clk_hw *gate_hw; |
| 730 | |
| 731 | const struct clk_ops *mux_ops; |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 732 | const struct clk_ops *rate_ops; |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 733 | const struct clk_ops *gate_ops; |
| 734 | }; |
| 735 | |
Geliang Tang | 5fd9c05 | 2016-01-08 23:51:46 +0800 | [diff] [blame] | 736 | #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) |
| 737 | |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 738 | struct clk *clk_register_composite(struct device *dev, const char *name, |
Sascha Hauer | 2893c37 | 2015-03-31 20:16:52 +0200 | [diff] [blame] | 739 | const char * const *parent_names, int num_parents, |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 740 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
Mike Turquette | d3a1c7b | 2013-04-11 11:31:36 -0700 | [diff] [blame] | 741 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 742 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
| 743 | unsigned long flags); |
Maxime Ripard | 92a39d9 | 2016-03-23 17:38:24 +0100 | [diff] [blame] | 744 | void clk_unregister_composite(struct clk *clk); |
Stephen Boyd | 49cb392 | 2016-02-07 00:20:31 -0800 | [diff] [blame] | 745 | struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, |
| 746 | const char * const *parent_names, int num_parents, |
| 747 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
| 748 | struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
| 749 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
| 750 | unsigned long flags); |
| 751 | void clk_hw_unregister_composite(struct clk_hw *hw); |
Prashant Gaikwad | ece7009 | 2013-03-20 17:30:34 +0530 | [diff] [blame] | 752 | |
Jyri Sarha | c873d14 | 2014-09-05 15:21:34 +0300 | [diff] [blame] | 753 | /*** |
| 754 | * struct clk_gpio_gate - gpio gated clock |
| 755 | * |
| 756 | * @hw: handle between common and hardware-specific interfaces |
| 757 | * @gpiod: gpio descriptor |
| 758 | * |
| 759 | * Clock with a gpio control for enabling and disabling the parent clock. |
| 760 | * Implements .enable, .disable and .is_enabled |
| 761 | */ |
| 762 | |
| 763 | struct clk_gpio { |
| 764 | struct clk_hw hw; |
| 765 | struct gpio_desc *gpiod; |
| 766 | }; |
| 767 | |
Geliang Tang | 5fd9c05 | 2016-01-08 23:51:46 +0800 | [diff] [blame] | 768 | #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) |
| 769 | |
Jyri Sarha | c873d14 | 2014-09-05 15:21:34 +0300 | [diff] [blame] | 770 | extern const struct clk_ops clk_gpio_gate_ops; |
| 771 | struct clk *clk_register_gpio_gate(struct device *dev, const char *name, |
Martin Fuzzey | 820ad97 | 2015-03-18 14:53:17 +0100 | [diff] [blame] | 772 | const char *parent_name, unsigned gpio, bool active_low, |
Jyri Sarha | c873d14 | 2014-09-05 15:21:34 +0300 | [diff] [blame] | 773 | unsigned long flags); |
Stephen Boyd | b120743 | 2016-02-07 00:27:55 -0800 | [diff] [blame] | 774 | struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, |
| 775 | const char *parent_name, unsigned gpio, bool active_low, |
| 776 | unsigned long flags); |
| 777 | void clk_hw_unregister_gpio_gate(struct clk_hw *hw); |
Jyri Sarha | c873d14 | 2014-09-05 15:21:34 +0300 | [diff] [blame] | 778 | |
Sascha Hauer | f0948f5 | 2012-05-03 15:36:14 +0530 | [diff] [blame] | 779 | /** |
Sergej Sawazki | 80eeb1f | 2015-06-28 16:24:55 +0200 | [diff] [blame] | 780 | * struct clk_gpio_mux - gpio controlled clock multiplexer |
| 781 | * |
| 782 | * @hw: see struct clk_gpio |
| 783 | * @gpiod: gpio descriptor to select the parent of this clock multiplexer |
| 784 | * |
| 785 | * Clock with a gpio control for selecting the parent clock. |
| 786 | * Implements .get_parent, .set_parent and .determine_rate |
| 787 | */ |
| 788 | |
| 789 | extern const struct clk_ops clk_gpio_mux_ops; |
| 790 | struct clk *clk_register_gpio_mux(struct device *dev, const char *name, |
Stephen Boyd | 37bff2c | 2015-07-24 09:31:29 -0700 | [diff] [blame] | 791 | const char * const *parent_names, u8 num_parents, unsigned gpio, |
Sergej Sawazki | 80eeb1f | 2015-06-28 16:24:55 +0200 | [diff] [blame] | 792 | bool active_low, unsigned long flags); |
Stephen Boyd | b120743 | 2016-02-07 00:27:55 -0800 | [diff] [blame] | 793 | struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, |
| 794 | const char * const *parent_names, u8 num_parents, unsigned gpio, |
| 795 | bool active_low, unsigned long flags); |
| 796 | void clk_hw_unregister_gpio_mux(struct clk_hw *hw); |
Sergej Sawazki | 80eeb1f | 2015-06-28 16:24:55 +0200 | [diff] [blame] | 797 | |
Sergej Sawazki | 80eeb1f | 2015-06-28 16:24:55 +0200 | [diff] [blame] | 798 | /** |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 799 | * clk_register - allocate a new clock, register it and return an opaque cookie |
| 800 | * @dev: device that is registering this clock |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 801 | * @hw: link to hardware-specific clock data |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 802 | * |
| 803 | * clk_register is the primary interface for populating the clock tree with new |
| 804 | * clock nodes. It returns a pointer to the newly allocated struct clk which |
| 805 | * cannot be dereferenced by driver code but may be used in conjuction with the |
Mike Turquette | d1302a3 | 2012-03-29 14:30:40 -0700 | [diff] [blame] | 806 | * rest of the clock API. In the event of an error clk_register will return an |
| 807 | * error code; drivers must test for an error code after calling clk_register. |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 808 | */ |
Saravana Kannan | 0197b3e | 2012-04-25 22:58:56 -0700 | [diff] [blame] | 809 | struct clk *clk_register(struct device *dev, struct clk_hw *hw); |
Stephen Boyd | 46c8773 | 2012-09-24 13:38:04 -0700 | [diff] [blame] | 810 | struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 811 | |
Stephen Boyd | 4143804 | 2016-02-05 17:02:52 -0800 | [diff] [blame] | 812 | int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); |
| 813 | int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); |
| 814 | |
Mark Brown | 1df5c93 | 2012-04-18 09:07:12 +0100 | [diff] [blame] | 815 | void clk_unregister(struct clk *clk); |
Stephen Boyd | 46c8773 | 2012-09-24 13:38:04 -0700 | [diff] [blame] | 816 | void devm_clk_unregister(struct device *dev, struct clk *clk); |
Mark Brown | 1df5c93 | 2012-04-18 09:07:12 +0100 | [diff] [blame] | 817 | |
Stephen Boyd | 4143804 | 2016-02-05 17:02:52 -0800 | [diff] [blame] | 818 | void clk_hw_unregister(struct clk_hw *hw); |
| 819 | void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw); |
| 820 | |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 821 | /* helper functions */ |
Geert Uytterhoeven | b76281c | 2015-10-16 14:35:21 +0200 | [diff] [blame] | 822 | const char *__clk_get_name(const struct clk *clk); |
Stephen Boyd | e7df6f6 | 2015-08-12 13:04:56 -0700 | [diff] [blame] | 823 | const char *clk_hw_get_name(const struct clk_hw *hw); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 824 | struct clk_hw *__clk_get_hw(struct clk *clk); |
Stephen Boyd | e7df6f6 | 2015-08-12 13:04:56 -0700 | [diff] [blame] | 825 | unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); |
| 826 | struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); |
| 827 | struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, |
Stephen Boyd | 1a9c069 | 2015-06-25 15:55:14 -0700 | [diff] [blame] | 828 | unsigned int index); |
Linus Torvalds | 9387468 | 2012-12-11 11:25:08 -0800 | [diff] [blame] | 829 | unsigned int __clk_get_enable_count(struct clk *clk); |
Stephen Boyd | e7df6f6 | 2015-08-12 13:04:56 -0700 | [diff] [blame] | 830 | unsigned long clk_hw_get_rate(const struct clk_hw *hw); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 831 | unsigned long __clk_get_flags(struct clk *clk); |
Stephen Boyd | e7df6f6 | 2015-08-12 13:04:56 -0700 | [diff] [blame] | 832 | unsigned long clk_hw_get_flags(const struct clk_hw *hw); |
| 833 | bool clk_hw_is_prepared(const struct clk_hw *hw); |
Joachim Eastwood | be68bf8 | 2015-10-24 18:55:22 +0200 | [diff] [blame] | 834 | bool clk_hw_is_enabled(const struct clk_hw *hw); |
Stephen Boyd | 2ac6b1f | 2012-10-03 23:38:55 -0700 | [diff] [blame] | 835 | bool __clk_is_enabled(struct clk *clk); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 836 | struct clk *__clk_lookup(const char *name); |
Boris Brezillon | 0817b62 | 2015-07-07 20:48:08 +0200 | [diff] [blame] | 837 | int __clk_mux_determine_rate(struct clk_hw *hw, |
| 838 | struct clk_rate_request *req); |
| 839 | int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); |
| 840 | int __clk_mux_determine_rate_closest(struct clk_hw *hw, |
| 841 | struct clk_rate_request *req); |
Tomeu Vizoso | 42c8654 | 2015-03-11 11:34:25 +0100 | [diff] [blame] | 842 | void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); |
Stephen Boyd | 9783c0d | 2015-07-16 12:50:27 -0700 | [diff] [blame] | 843 | void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, |
| 844 | unsigned long max_rate); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 845 | |
Taniya Das | d9744c1 | 2016-08-19 10:08:28 +0530 | [diff] [blame] | 846 | unsigned long clk_aggregate_rate(struct clk_hw *hw, |
| 847 | const struct clk_core *parent); |
| 848 | |
Javier Martinez Canillas | 2e65d8b | 2015-02-12 14:58:29 +0100 | [diff] [blame] | 849 | static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) |
| 850 | { |
| 851 | dst->clk = src->clk; |
| 852 | dst->core = src->core; |
| 853 | } |
| 854 | |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 855 | /* |
| 856 | * FIXME clock api without lock protection |
| 857 | */ |
Stephen Boyd | 1a9c069 | 2015-06-25 15:55:14 -0700 | [diff] [blame] | 858 | unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 859 | |
Grant Likely | 766e6a4 | 2012-04-09 14:50:06 -0500 | [diff] [blame] | 860 | struct of_device_id; |
| 861 | |
| 862 | typedef void (*of_clk_init_cb_t)(struct device_node *); |
| 863 | |
Sebastian Hesselbarth | 0b151de | 2013-05-01 02:58:28 +0200 | [diff] [blame] | 864 | struct clk_onecell_data { |
| 865 | struct clk **clks; |
| 866 | unsigned int clk_num; |
| 867 | }; |
| 868 | |
Stephen Boyd | 0861e5b | 2016-02-05 17:38:26 -0800 | [diff] [blame] | 869 | struct clk_hw_onecell_data { |
Masahiro Yamada | 5963f19 | 2016-09-23 21:29:36 +0900 | [diff] [blame] | 870 | unsigned int num; |
Stephen Boyd | 0861e5b | 2016-02-05 17:38:26 -0800 | [diff] [blame] | 871 | struct clk_hw *hws[]; |
| 872 | }; |
| 873 | |
Tero Kristo | 819b486 | 2013-10-22 11:39:36 +0300 | [diff] [blame] | 874 | extern struct of_device_id __clk_of_table; |
| 875 | |
Rob Herring | 54196cc | 2014-05-08 16:09:24 -0500 | [diff] [blame] | 876 | #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) |
Sebastian Hesselbarth | 0b151de | 2013-05-01 02:58:28 +0200 | [diff] [blame] | 877 | |
Ricardo Ribalda Delgado | c7296c5 | 2016-07-05 18:23:25 +0200 | [diff] [blame] | 878 | /* |
| 879 | * Use this macro when you have a driver that requires two initialization |
| 880 | * routines, one at of_clk_init(), and one at platform device probe |
| 881 | */ |
| 882 | #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ |
Shawn Guo | 339e1e5 | 2016-10-08 16:59:38 +0800 | [diff] [blame] | 883 | static void __init name##_of_clk_init_driver(struct device_node *np) \ |
Ricardo Ribalda Delgado | c7296c5 | 2016-07-05 18:23:25 +0200 | [diff] [blame] | 884 | { \ |
| 885 | of_node_clear_flag(np, OF_POPULATED); \ |
| 886 | fn(np); \ |
| 887 | } \ |
| 888 | OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver) |
| 889 | |
Sebastian Hesselbarth | 0b151de | 2013-05-01 02:58:28 +0200 | [diff] [blame] | 890 | #ifdef CONFIG_OF |
Grant Likely | 766e6a4 | 2012-04-09 14:50:06 -0500 | [diff] [blame] | 891 | int of_clk_add_provider(struct device_node *np, |
| 892 | struct clk *(*clk_src_get)(struct of_phandle_args *args, |
| 893 | void *data), |
| 894 | void *data); |
Stephen Boyd | 0861e5b | 2016-02-05 17:38:26 -0800 | [diff] [blame] | 895 | int of_clk_add_hw_provider(struct device_node *np, |
| 896 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, |
| 897 | void *data), |
| 898 | void *data); |
Grant Likely | 766e6a4 | 2012-04-09 14:50:06 -0500 | [diff] [blame] | 899 | void of_clk_del_provider(struct device_node *np); |
| 900 | struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, |
| 901 | void *data); |
Stephen Boyd | 0861e5b | 2016-02-05 17:38:26 -0800 | [diff] [blame] | 902 | struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, |
| 903 | void *data); |
Shawn Guo | 494bfec | 2012-08-22 21:36:27 +0800 | [diff] [blame] | 904 | struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); |
Stephen Boyd | 0861e5b | 2016-02-05 17:38:26 -0800 | [diff] [blame] | 905 | struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, |
| 906 | void *data); |
Stephen Boyd | 929e7f3 | 2016-02-19 15:52:32 -0800 | [diff] [blame] | 907 | unsigned int of_clk_get_parent_count(struct device_node *np); |
Dinh Nguyen | 2e61dfb | 2015-06-05 11:26:13 -0500 | [diff] [blame] | 908 | int of_clk_parent_fill(struct device_node *np, const char **parents, |
| 909 | unsigned int size); |
Grant Likely | 766e6a4 | 2012-04-09 14:50:06 -0500 | [diff] [blame] | 910 | const char *of_clk_get_parent_name(struct device_node *np, int index); |
Lee Jones | d56f899 | 2016-02-11 13:19:11 -0800 | [diff] [blame] | 911 | int of_clk_detect_critical(struct device_node *np, int index, |
| 912 | unsigned long *flags); |
Grant Likely | 766e6a4 | 2012-04-09 14:50:06 -0500 | [diff] [blame] | 913 | void of_clk_init(const struct of_device_id *matches); |
| 914 | |
Sebastian Hesselbarth | 0b151de | 2013-05-01 02:58:28 +0200 | [diff] [blame] | 915 | #else /* !CONFIG_OF */ |
Prashant Gaikwad | f2f6c25 | 2013-01-04 12:30:52 +0530 | [diff] [blame] | 916 | |
Sebastian Hesselbarth | 0b151de | 2013-05-01 02:58:28 +0200 | [diff] [blame] | 917 | static inline int of_clk_add_provider(struct device_node *np, |
| 918 | struct clk *(*clk_src_get)(struct of_phandle_args *args, |
| 919 | void *data), |
| 920 | void *data) |
| 921 | { |
| 922 | return 0; |
| 923 | } |
Stephen Boyd | 0861e5b | 2016-02-05 17:38:26 -0800 | [diff] [blame] | 924 | static inline int of_clk_add_hw_provider(struct device_node *np, |
| 925 | struct clk_hw *(*get)(struct of_phandle_args *clkspec, |
| 926 | void *data), |
| 927 | void *data) |
| 928 | { |
| 929 | return 0; |
| 930 | } |
Geert Uytterhoeven | 20dd882 | 2015-10-29 22:12:56 +0100 | [diff] [blame] | 931 | static inline void of_clk_del_provider(struct device_node *np) {} |
Sebastian Hesselbarth | 0b151de | 2013-05-01 02:58:28 +0200 | [diff] [blame] | 932 | static inline struct clk *of_clk_src_simple_get( |
| 933 | struct of_phandle_args *clkspec, void *data) |
| 934 | { |
| 935 | return ERR_PTR(-ENOENT); |
| 936 | } |
Stephen Boyd | 0861e5b | 2016-02-05 17:38:26 -0800 | [diff] [blame] | 937 | static inline struct clk_hw * |
| 938 | of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) |
| 939 | { |
| 940 | return ERR_PTR(-ENOENT); |
| 941 | } |
Sebastian Hesselbarth | 0b151de | 2013-05-01 02:58:28 +0200 | [diff] [blame] | 942 | static inline struct clk *of_clk_src_onecell_get( |
| 943 | struct of_phandle_args *clkspec, void *data) |
| 944 | { |
| 945 | return ERR_PTR(-ENOENT); |
| 946 | } |
Stephen Boyd | 0861e5b | 2016-02-05 17:38:26 -0800 | [diff] [blame] | 947 | static inline struct clk_hw * |
| 948 | of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) |
| 949 | { |
| 950 | return ERR_PTR(-ENOENT); |
| 951 | } |
Rafał Miłecki | d42c047 | 2016-08-26 14:58:07 +0200 | [diff] [blame] | 952 | static inline unsigned int of_clk_get_parent_count(struct device_node *np) |
Stephen Boyd | 679c51c | 2015-10-26 11:55:34 -0700 | [diff] [blame] | 953 | { |
| 954 | return 0; |
| 955 | } |
| 956 | static inline int of_clk_parent_fill(struct device_node *np, |
| 957 | const char **parents, unsigned int size) |
| 958 | { |
| 959 | return 0; |
| 960 | } |
Sebastian Hesselbarth | 0b151de | 2013-05-01 02:58:28 +0200 | [diff] [blame] | 961 | static inline const char *of_clk_get_parent_name(struct device_node *np, |
| 962 | int index) |
| 963 | { |
| 964 | return NULL; |
| 965 | } |
Lee Jones | d56f899 | 2016-02-11 13:19:11 -0800 | [diff] [blame] | 966 | static inline int of_clk_detect_critical(struct device_node *np, int index, |
| 967 | unsigned long *flags) |
| 968 | { |
| 969 | return 0; |
| 970 | } |
Geert Uytterhoeven | 20dd882 | 2015-10-29 22:12:56 +0100 | [diff] [blame] | 971 | static inline void of_clk_init(const struct of_device_id *matches) {} |
Sebastian Hesselbarth | 0b151de | 2013-05-01 02:58:28 +0200 | [diff] [blame] | 972 | #endif /* CONFIG_OF */ |
Gerhard Sittig | aa514ce | 2013-07-22 14:14:40 +0200 | [diff] [blame] | 973 | |
| 974 | /* |
| 975 | * wrap access to peripherals in accessor routines |
| 976 | * for improved portability across platforms |
| 977 | */ |
| 978 | |
Gerhard Sittig | 6d8cdb6 | 2013-11-30 23:51:24 +0100 | [diff] [blame] | 979 | #if IS_ENABLED(CONFIG_PPC) |
| 980 | |
| 981 | static inline u32 clk_readl(u32 __iomem *reg) |
| 982 | { |
| 983 | return ioread32be(reg); |
| 984 | } |
| 985 | |
| 986 | static inline void clk_writel(u32 val, u32 __iomem *reg) |
| 987 | { |
| 988 | iowrite32be(val, reg); |
| 989 | } |
| 990 | |
| 991 | #else /* platform dependent I/O accessors */ |
| 992 | |
Gerhard Sittig | aa514ce | 2013-07-22 14:14:40 +0200 | [diff] [blame] | 993 | static inline u32 clk_readl(u32 __iomem *reg) |
| 994 | { |
| 995 | return readl(reg); |
| 996 | } |
| 997 | |
| 998 | static inline void clk_writel(u32 val, u32 __iomem *reg) |
| 999 | { |
| 1000 | writel(val, reg); |
| 1001 | } |
| 1002 | |
Gerhard Sittig | 6d8cdb6 | 2013-11-30 23:51:24 +0100 | [diff] [blame] | 1003 | #endif /* platform dependent I/O accessors */ |
| 1004 | |
Peter De Schrijver | fb2b3c9 | 2014-06-26 18:00:53 +0300 | [diff] [blame] | 1005 | #ifdef CONFIG_DEBUG_FS |
Tomeu Vizoso | 61c7cdd | 2014-12-02 08:54:21 +0100 | [diff] [blame] | 1006 | struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode, |
Peter De Schrijver | fb2b3c9 | 2014-06-26 18:00:53 +0300 | [diff] [blame] | 1007 | void *data, const struct file_operations *fops); |
| 1008 | #endif |
Shefali Jain | 0dc6e78 | 2017-11-27 13:06:27 +0530 | [diff] [blame] | 1009 | #else |
| 1010 | struct of_device_id; |
| 1011 | |
| 1012 | static inline void __init of_clk_init(const struct of_device_id *matches) |
| 1013 | { |
| 1014 | } |
Peter De Schrijver | fb2b3c9 | 2014-06-26 18:00:53 +0300 | [diff] [blame] | 1015 | |
Mike Turquette | b2476490 | 2012-03-15 23:11:19 -0700 | [diff] [blame] | 1016 | #endif /* CONFIG_COMMON_CLK */ |
| 1017 | #endif /* CLK_PROVIDER_H */ |