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Sam Ravnborga00736e2008-06-19 20:26:19 +02001#ifndef _SPARC64_TSB_H
2#define _SPARC64_TSB_H
3
4/* The sparc64 TSB is similar to the powerpc hashtables. It's a
5 * power-of-2 sized table of TAG/PTE pairs. The cpu precomputes
6 * pointers into this table for 8K and 64K page sizes, and also a
7 * comparison TAG based upon the virtual address and context which
8 * faults.
9 *
10 * TLB miss trap handler software does the actual lookup via something
11 * of the form:
12 *
13 * ldxa [%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1
14 * ldxa [%g0] ASI_{D,I}MMU, %g6
15 * sllx %g6, 22, %g6
16 * srlx %g6, 22, %g6
17 * ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4
18 * cmp %g4, %g6
19 * bne,pn %xcc, tsb_miss_{d,i}tlb
20 * mov FAULT_CODE_{D,I}TLB, %g3
21 * stxa %g5, [%g0] ASI_{D,I}TLB_DATA_IN
22 * retry
23 *
24 *
25 * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
26 * PTE. The TAG is of the same layout as the TLB TAG TARGET mmu
27 * register which is:
28 *
29 * -------------------------------------------------
30 * | - | CONTEXT | - | VADDR bits 63:22 |
31 * -------------------------------------------------
32 * 63 61 60 48 47 42 41 0
33 *
34 * But actually, since we use per-mm TSB's, we zero out the CONTEXT
35 * field.
36 *
37 * Like the powerpc hashtables we need to use locking in order to
38 * synchronize while we update the entries. PTE updates need locking
39 * as well.
40 *
41 * We need to carefully choose a lock bits for the TSB entry. We
42 * choose to use bit 47 in the tag. Also, since we never map anything
43 * at page zero in context zero, we use zero as an invalid tag entry.
44 * When the lock bit is set, this forces a tag comparison failure.
45 */
46
47#define TSB_TAG_LOCK_BIT 47
48#define TSB_TAG_LOCK_HIGH (1 << (TSB_TAG_LOCK_BIT - 32))
49
50#define TSB_TAG_INVALID_BIT 46
51#define TSB_TAG_INVALID_HIGH (1 << (TSB_TAG_INVALID_BIT - 32))
52
Sam Ravnborga00736e2008-06-19 20:26:19 +020053/* Some cpus support physical address quad loads. We want to use
54 * those if possible so we don't need to hard-lock the TSB mapping
55 * into the TLB. We encode some instruction patching in order to
56 * support this.
57 *
58 * The kernel TSB is locked into the TLB by virtue of being in the
59 * kernel image, so we don't play these games for swapper_tsb access.
60 */
61#ifndef __ASSEMBLY__
62struct tsb_ldquad_phys_patch_entry {
63 unsigned int addr;
64 unsigned int sun4u_insn;
65 unsigned int sun4v_insn;
66};
67extern struct tsb_ldquad_phys_patch_entry __tsb_ldquad_phys_patch,
68 __tsb_ldquad_phys_patch_end;
69
70struct tsb_phys_patch_entry {
71 unsigned int addr;
72 unsigned int insn;
73};
74extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
75#endif
76#define TSB_LOAD_QUAD(TSB, REG) \
77661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
78 .section .tsb_ldquad_phys_patch, "ax"; \
79 .word 661b; \
80 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
81 ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
82 .previous
83
84#define TSB_LOAD_TAG_HIGH(TSB, REG) \
85661: lduwa [TSB] ASI_N, REG; \
86 .section .tsb_phys_patch, "ax"; \
87 .word 661b; \
88 lduwa [TSB] ASI_PHYS_USE_EC, REG; \
89 .previous
90
91#define TSB_LOAD_TAG(TSB, REG) \
92661: ldxa [TSB] ASI_N, REG; \
93 .section .tsb_phys_patch, "ax"; \
94 .word 661b; \
95 ldxa [TSB] ASI_PHYS_USE_EC, REG; \
96 .previous
97
98#define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \
99661: casa [TSB] ASI_N, REG1, REG2; \
100 .section .tsb_phys_patch, "ax"; \
101 .word 661b; \
102 casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
103 .previous
104
105#define TSB_CAS_TAG(TSB, REG1, REG2) \
106661: casxa [TSB] ASI_N, REG1, REG2; \
107 .section .tsb_phys_patch, "ax"; \
108 .word 661b; \
109 casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
110 .previous
111
112#define TSB_STORE(ADDR, VAL) \
113661: stxa VAL, [ADDR] ASI_N; \
114 .section .tsb_phys_patch, "ax"; \
115 .word 661b; \
116 stxa VAL, [ADDR] ASI_PHYS_USE_EC; \
117 .previous
118
119#define TSB_LOCK_TAG(TSB, REG1, REG2) \
12099: TSB_LOAD_TAG_HIGH(TSB, REG1); \
121 sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
122 andcc REG1, REG2, %g0; \
123 bne,pn %icc, 99b; \
124 nop; \
125 TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
126 cmp REG1, REG2; \
127 bne,pn %icc, 99b; \
128 nop; \
Sam Ravnborga00736e2008-06-19 20:26:19 +0200129
130#define TSB_WRITE(TSB, TTE, TAG) \
131 add TSB, 0x8, TSB; \
132 TSB_STORE(TSB, TTE); \
133 sub TSB, 0x8, TSB; \
Sam Ravnborga00736e2008-06-19 20:26:19 +0200134 TSB_STORE(TSB, TAG);
135
136#define KTSB_LOAD_QUAD(TSB, REG) \
137 ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG;
138
139#define KTSB_STORE(ADDR, VAL) \
140 stxa VAL, [ADDR] ASI_N;
141
142#define KTSB_LOCK_TAG(TSB, REG1, REG2) \
14399: lduwa [TSB] ASI_N, REG1; \
144 sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\
145 andcc REG1, REG2, %g0; \
146 bne,pn %icc, 99b; \
147 nop; \
148 casa [TSB] ASI_N, REG1, REG2;\
149 cmp REG1, REG2; \
150 bne,pn %icc, 99b; \
151 nop; \
Sam Ravnborga00736e2008-06-19 20:26:19 +0200152
153#define KTSB_WRITE(TSB, TTE, TAG) \
154 add TSB, 0x8, TSB; \
155 stxa TTE, [TSB] ASI_N; \
156 sub TSB, 0x8, TSB; \
Sam Ravnborga00736e2008-06-19 20:26:19 +0200157 stxa TAG, [TSB] ASI_N;
158
159 /* Do a kernel page table walk. Leaves physical PTE pointer in
160 * REG1. Jumps to FAIL_LABEL on early page table walk termination.
161 * VADDR will not be clobbered, but REG2 will.
162 */
163#define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL) \
164 sethi %hi(swapper_pg_dir), REG1; \
165 or REG1, %lo(swapper_pg_dir), REG1; \
166 sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
167 srlx REG2, 64 - PAGE_SHIFT, REG2; \
168 andn REG2, 0x3, REG2; \
169 lduw [REG1 + REG2], REG1; \
170 brz,pn REG1, FAIL_LABEL; \
171 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
172 srlx REG2, 64 - PAGE_SHIFT, REG2; \
173 sllx REG1, 11, REG1; \
174 andn REG2, 0x3, REG2; \
175 lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
176 brz,pn REG1, FAIL_LABEL; \
177 sllx VADDR, 64 - PMD_SHIFT, REG2; \
178 srlx REG2, 64 - PAGE_SHIFT, REG2; \
179 sllx REG1, 11, REG1; \
180 andn REG2, 0x7, REG2; \
181 add REG1, REG2, REG1;
182
183 /* Do a user page table walk in MMU globals. Leaves physical PTE
184 * pointer in REG1. Jumps to FAIL_LABEL on early page table walk
185 * termination. Physical base of page tables is in PHYS_PGD which
186 * will not be modified.
187 *
188 * VADDR will not be clobbered, but REG1 and REG2 will.
189 */
190#define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL) \
191 sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
192 srlx REG2, 64 - PAGE_SHIFT, REG2; \
193 andn REG2, 0x3, REG2; \
194 lduwa [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \
195 brz,pn REG1, FAIL_LABEL; \
196 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
197 srlx REG2, 64 - PAGE_SHIFT, REG2; \
198 sllx REG1, 11, REG1; \
199 andn REG2, 0x3, REG2; \
200 lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
201 brz,pn REG1, FAIL_LABEL; \
202 sllx VADDR, 64 - PMD_SHIFT, REG2; \
203 srlx REG2, 64 - PAGE_SHIFT, REG2; \
204 sllx REG1, 11, REG1; \
205 andn REG2, 0x7, REG2; \
206 add REG1, REG2, REG1;
207
208/* Lookup a OBP mapping on VADDR in the prom_trans[] table at TL>0.
209 * If no entry is found, FAIL_LABEL will be branched to. On success
210 * the resulting PTE value will be left in REG1. VADDR is preserved
211 * by this routine.
212 */
213#define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \
214 sethi %hi(prom_trans), REG1; \
215 or REG1, %lo(prom_trans), REG1; \
21697: ldx [REG1 + 0x00], REG2; \
217 brz,pn REG2, FAIL_LABEL; \
218 nop; \
219 ldx [REG1 + 0x08], REG3; \
220 add REG2, REG3, REG3; \
221 cmp REG2, VADDR; \
222 bgu,pt %xcc, 98f; \
223 cmp VADDR, REG3; \
224 bgeu,pt %xcc, 98f; \
225 ldx [REG1 + 0x10], REG3; \
226 sub VADDR, REG2, REG2; \
227 ba,pt %xcc, 99f; \
228 add REG3, REG2, REG1; \
22998: ba,pt %xcc, 97b; \
230 add REG1, (3 * 8), REG1; \
23199:
232
233 /* We use a 32K TSB for the whole kernel, this allows to
234 * handle about 16MB of modules and vmalloc mappings without
235 * incurring many hash conflicts.
236 */
237#define KERNEL_TSB_SIZE_BYTES (32 * 1024)
238#define KERNEL_TSB_NENTRIES \
239 (KERNEL_TSB_SIZE_BYTES / 16)
240#define KERNEL_TSB4M_NENTRIES 4096
241
242 /* Do a kernel TSB lookup at tl>0 on VADDR+TAG, branch to OK_LABEL
243 * on TSB hit. REG1, REG2, REG3, and REG4 are used as temporaries
244 * and the found TTE will be left in REG1. REG3 and REG4 must
245 * be an even/odd pair of registers.
246 *
247 * VADDR and TAG will be preserved and not clobbered by this macro.
248 */
249#define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
250 sethi %hi(swapper_tsb), REG1; \
251 or REG1, %lo(swapper_tsb), REG1; \
252 srlx VADDR, PAGE_SHIFT, REG2; \
253 and REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \
254 sllx REG2, 4, REG2; \
255 add REG1, REG2, REG2; \
256 KTSB_LOAD_QUAD(REG2, REG3); \
257 cmp REG3, TAG; \
258 be,a,pt %xcc, OK_LABEL; \
259 mov REG4, REG1;
260
261#ifndef CONFIG_DEBUG_PAGEALLOC
262 /* This version uses a trick, the TAG is already (VADDR >> 22) so
263 * we can make use of that for the index computation.
264 */
265#define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
266 sethi %hi(swapper_4m_tsb), REG1; \
267 or REG1, %lo(swapper_4m_tsb), REG1; \
268 and TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \
269 sllx REG2, 4, REG2; \
270 add REG1, REG2, REG2; \
271 KTSB_LOAD_QUAD(REG2, REG3); \
272 cmp REG3, TAG; \
273 be,a,pt %xcc, OK_LABEL; \
274 mov REG4, REG1;
275#endif
276
277#endif /* !(_SPARC64_TSB_H) */