Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2004, 2005 by Ralf Baechle |
| 7 | * Copyright (C) 2005 by MIPS Technologies, Inc. |
| 8 | */ |
| 9 | #include <linux/oprofile.h> |
| 10 | #include <linux/interrupt.h> |
| 11 | #include <linux/smp.h> |
| 12 | |
| 13 | #include "op_impl.h" |
| 14 | |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 15 | #define M_PERFCTL_EXL (1UL << 0) |
| 16 | #define M_PERFCTL_KERNEL (1UL << 1) |
| 17 | #define M_PERFCTL_SUPERVISOR (1UL << 2) |
| 18 | #define M_PERFCTL_USER (1UL << 3) |
| 19 | #define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) |
| 20 | #define M_PERFCTL_EVENT(event) ((event) << 5) |
| 21 | #define M_PERFCTL_VPEID(vpe) ((vpe) << 16) |
| 22 | #define M_PERFCTL_MT_EN(filter) ((filter) << 20) |
| 23 | #define M_TC_EN_ALL M_PERFCTL_MT_EN(0) |
| 24 | #define M_TC_EN_VPE M_PERFCTL_MT_EN(1) |
| 25 | #define M_TC_EN_TC M_PERFCTL_MT_EN(2) |
| 26 | #define M_PERFCTL_TCID(tcid) ((tcid) << 22) |
| 27 | #define M_PERFCTL_WIDE (1UL << 30) |
| 28 | #define M_PERFCTL_MORE (1UL << 31) |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 29 | |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 30 | #define M_COUNTER_OVERFLOW (1UL << 31) |
| 31 | |
| 32 | #ifdef CONFIG_MIPS_MT_SMP |
| 33 | #define WHAT (M_TC_EN_VPE | M_PERFCTL_VPEID(smp_processor_id())) |
| 34 | #else |
| 35 | #define WHAT 0 |
| 36 | #endif |
| 37 | |
| 38 | #define __define_perf_accessors(r, n, np) \ |
| 39 | \ |
| 40 | static inline unsigned int r_c0_ ## r ## n(void) \ |
| 41 | { \ |
| 42 | unsigned int cpu = smp_processor_id(); \ |
| 43 | \ |
| 44 | switch (cpu) { \ |
| 45 | case 0: \ |
| 46 | return read_c0_ ## r ## n(); \ |
| 47 | case 1: \ |
| 48 | return read_c0_ ## r ## np(); \ |
| 49 | default: \ |
| 50 | BUG(); \ |
| 51 | } \ |
Thiemo Seufer | 30f244a | 2006-07-07 10:38:51 +0100 | [diff] [blame] | 52 | return 0; \ |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 53 | } \ |
| 54 | \ |
| 55 | static inline void w_c0_ ## r ## n(unsigned int value) \ |
| 56 | { \ |
| 57 | unsigned int cpu = smp_processor_id(); \ |
| 58 | \ |
| 59 | switch (cpu) { \ |
| 60 | case 0: \ |
| 61 | write_c0_ ## r ## n(value); \ |
| 62 | return; \ |
| 63 | case 1: \ |
| 64 | write_c0_ ## r ## np(value); \ |
| 65 | return; \ |
| 66 | default: \ |
| 67 | BUG(); \ |
| 68 | } \ |
Thiemo Seufer | 30f244a | 2006-07-07 10:38:51 +0100 | [diff] [blame] | 69 | return; \ |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 70 | } \ |
| 71 | |
| 72 | __define_perf_accessors(perfcntr, 0, 2) |
| 73 | __define_perf_accessors(perfcntr, 1, 3) |
| 74 | __define_perf_accessors(perfcntr, 2, 2) |
| 75 | __define_perf_accessors(perfcntr, 3, 2) |
| 76 | |
| 77 | __define_perf_accessors(perfctrl, 0, 2) |
| 78 | __define_perf_accessors(perfctrl, 1, 3) |
| 79 | __define_perf_accessors(perfctrl, 2, 2) |
| 80 | __define_perf_accessors(perfctrl, 3, 2) |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 81 | |
Atsushi Nemoto | 1acf1ca | 2006-05-23 16:42:38 +0900 | [diff] [blame] | 82 | struct op_mips_model op_model_mipsxx_ops; |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 83 | |
| 84 | static struct mipsxx_register_config { |
| 85 | unsigned int control[4]; |
| 86 | unsigned int counter[4]; |
| 87 | } reg; |
| 88 | |
| 89 | /* Compute all of the registers in preparation for enabling profiling. */ |
| 90 | |
| 91 | static void mipsxx_reg_setup(struct op_counter_config *ctr) |
| 92 | { |
Atsushi Nemoto | 1acf1ca | 2006-05-23 16:42:38 +0900 | [diff] [blame] | 93 | unsigned int counters = op_model_mipsxx_ops.num_counters; |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 94 | int i; |
| 95 | |
| 96 | /* Compute the performance counter control word. */ |
| 97 | /* For now count kernel and user mode */ |
| 98 | for (i = 0; i < counters; i++) { |
| 99 | reg.control[i] = 0; |
| 100 | reg.counter[i] = 0; |
| 101 | |
| 102 | if (!ctr[i].enabled) |
| 103 | continue; |
| 104 | |
| 105 | reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) | |
| 106 | M_PERFCTL_INTERRUPT_ENABLE; |
| 107 | if (ctr[i].kernel) |
| 108 | reg.control[i] |= M_PERFCTL_KERNEL; |
| 109 | if (ctr[i].user) |
| 110 | reg.control[i] |= M_PERFCTL_USER; |
| 111 | if (ctr[i].exl) |
| 112 | reg.control[i] |= M_PERFCTL_EXL; |
| 113 | reg.counter[i] = 0x80000000 - ctr[i].count; |
| 114 | } |
| 115 | } |
| 116 | |
| 117 | /* Program all of the registers in preparation for enabling profiling. */ |
| 118 | |
| 119 | static void mipsxx_cpu_setup (void *args) |
| 120 | { |
Atsushi Nemoto | 1acf1ca | 2006-05-23 16:42:38 +0900 | [diff] [blame] | 121 | unsigned int counters = op_model_mipsxx_ops.num_counters; |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 122 | |
| 123 | switch (counters) { |
| 124 | case 4: |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 125 | w_c0_perfctrl3(0); |
| 126 | w_c0_perfcntr3(reg.counter[3]); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 127 | case 3: |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 128 | w_c0_perfctrl2(0); |
| 129 | w_c0_perfcntr2(reg.counter[2]); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 130 | case 2: |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 131 | w_c0_perfctrl1(0); |
| 132 | w_c0_perfcntr1(reg.counter[1]); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 133 | case 1: |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 134 | w_c0_perfctrl0(0); |
| 135 | w_c0_perfcntr0(reg.counter[0]); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 136 | } |
| 137 | } |
| 138 | |
| 139 | /* Start all counters on current CPU */ |
| 140 | static void mipsxx_cpu_start(void *args) |
| 141 | { |
Atsushi Nemoto | 1acf1ca | 2006-05-23 16:42:38 +0900 | [diff] [blame] | 142 | unsigned int counters = op_model_mipsxx_ops.num_counters; |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 143 | |
| 144 | switch (counters) { |
| 145 | case 4: |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 146 | w_c0_perfctrl3(WHAT | reg.control[3]); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 147 | case 3: |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 148 | w_c0_perfctrl2(WHAT | reg.control[2]); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 149 | case 2: |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 150 | w_c0_perfctrl1(WHAT | reg.control[1]); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 151 | case 1: |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 152 | w_c0_perfctrl0(WHAT | reg.control[0]); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 153 | } |
| 154 | } |
| 155 | |
| 156 | /* Stop all counters on current CPU */ |
| 157 | static void mipsxx_cpu_stop(void *args) |
| 158 | { |
Atsushi Nemoto | 1acf1ca | 2006-05-23 16:42:38 +0900 | [diff] [blame] | 159 | unsigned int counters = op_model_mipsxx_ops.num_counters; |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 160 | |
| 161 | switch (counters) { |
| 162 | case 4: |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 163 | w_c0_perfctrl3(0); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 164 | case 3: |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 165 | w_c0_perfctrl2(0); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 166 | case 2: |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 167 | w_c0_perfctrl1(0); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 168 | case 1: |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 169 | w_c0_perfctrl0(0); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 170 | } |
| 171 | } |
| 172 | |
Ralf Baechle | ba339c0 | 2005-12-09 12:29:38 +0000 | [diff] [blame] | 173 | static int mipsxx_perfcount_handler(struct pt_regs *regs) |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 174 | { |
Atsushi Nemoto | 1acf1ca | 2006-05-23 16:42:38 +0900 | [diff] [blame] | 175 | unsigned int counters = op_model_mipsxx_ops.num_counters; |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 176 | unsigned int control; |
| 177 | unsigned int counter; |
Ralf Baechle | ba339c0 | 2005-12-09 12:29:38 +0000 | [diff] [blame] | 178 | int handled = 0; |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 179 | |
| 180 | switch (counters) { |
| 181 | #define HANDLE_COUNTER(n) \ |
| 182 | case n + 1: \ |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 183 | control = r_c0_perfctrl ## n(); \ |
| 184 | counter = r_c0_perfcntr ## n(); \ |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 185 | if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \ |
| 186 | (counter & M_COUNTER_OVERFLOW)) { \ |
| 187 | oprofile_add_sample(regs, n); \ |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 188 | w_c0_perfcntr ## n(reg.counter[n]); \ |
Ralf Baechle | ba339c0 | 2005-12-09 12:29:38 +0000 | [diff] [blame] | 189 | handled = 1; \ |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 190 | } |
| 191 | HANDLE_COUNTER(3) |
| 192 | HANDLE_COUNTER(2) |
| 193 | HANDLE_COUNTER(1) |
| 194 | HANDLE_COUNTER(0) |
| 195 | } |
Ralf Baechle | ba339c0 | 2005-12-09 12:29:38 +0000 | [diff] [blame] | 196 | |
| 197 | return handled; |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 198 | } |
| 199 | |
| 200 | #define M_CONFIG1_PC (1 << 4) |
| 201 | |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 202 | static inline int __n_counters(void) |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 203 | { |
| 204 | if (!(read_c0_config1() & M_CONFIG1_PC)) |
| 205 | return 0; |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 206 | if (!(r_c0_perfctrl0() & M_PERFCTL_MORE)) |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 207 | return 1; |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 208 | if (!(r_c0_perfctrl1() & M_PERFCTL_MORE)) |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 209 | return 2; |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 210 | if (!(r_c0_perfctrl2() & M_PERFCTL_MORE)) |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 211 | return 3; |
| 212 | |
| 213 | return 4; |
| 214 | } |
| 215 | |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 216 | static inline int n_counters(void) |
| 217 | { |
| 218 | int counters = __n_counters(); |
| 219 | |
| 220 | #ifndef CONFIG_SMP |
| 221 | if (current_cpu_data.cputype == CPU_34K) |
| 222 | return counters >> 1; |
| 223 | #endif |
| 224 | |
| 225 | return counters; |
| 226 | } |
| 227 | |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 228 | static inline void reset_counters(int counters) |
| 229 | { |
| 230 | switch (counters) { |
| 231 | case 4: |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 232 | w_c0_perfctrl3(0); |
| 233 | w_c0_perfcntr3(0); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 234 | case 3: |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 235 | w_c0_perfctrl2(0); |
| 236 | w_c0_perfcntr2(0); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 237 | case 2: |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 238 | w_c0_perfctrl1(0); |
| 239 | w_c0_perfcntr1(0); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 240 | case 1: |
Ralf Baechle | 92c7b62 | 2006-06-23 18:39:00 +0100 | [diff] [blame] | 241 | w_c0_perfctrl0(0); |
| 242 | w_c0_perfcntr0(0); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 243 | } |
| 244 | } |
| 245 | |
| 246 | static int __init mipsxx_init(void) |
| 247 | { |
| 248 | int counters; |
| 249 | |
| 250 | counters = n_counters(); |
Ralf Baechle | 9efeae9 | 2005-12-09 12:34:45 +0000 | [diff] [blame] | 251 | if (counters == 0) { |
| 252 | printk(KERN_ERR "Oprofile: CPU has no performance counters\n"); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 253 | return -ENODEV; |
Ralf Baechle | 9efeae9 | 2005-12-09 12:34:45 +0000 | [diff] [blame] | 254 | } |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 255 | |
| 256 | reset_counters(counters); |
| 257 | |
Atsushi Nemoto | 1acf1ca | 2006-05-23 16:42:38 +0900 | [diff] [blame] | 258 | op_model_mipsxx_ops.num_counters = counters; |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 259 | switch (current_cpu_data.cputype) { |
Ralf Baechle | 2065988 | 2005-12-09 12:42:13 +0000 | [diff] [blame] | 260 | case CPU_20KC: |
Atsushi Nemoto | 1acf1ca | 2006-05-23 16:42:38 +0900 | [diff] [blame] | 261 | op_model_mipsxx_ops.cpu_type = "mips/20K"; |
Ralf Baechle | 2065988 | 2005-12-09 12:42:13 +0000 | [diff] [blame] | 262 | break; |
| 263 | |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 264 | case CPU_24K: |
Atsushi Nemoto | 1acf1ca | 2006-05-23 16:42:38 +0900 | [diff] [blame] | 265 | op_model_mipsxx_ops.cpu_type = "mips/24K"; |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 266 | break; |
| 267 | |
Ralf Baechle | 2065988 | 2005-12-09 12:42:13 +0000 | [diff] [blame] | 268 | case CPU_25KF: |
Atsushi Nemoto | 1acf1ca | 2006-05-23 16:42:38 +0900 | [diff] [blame] | 269 | op_model_mipsxx_ops.cpu_type = "mips/25K"; |
Ralf Baechle | 2065988 | 2005-12-09 12:42:13 +0000 | [diff] [blame] | 270 | break; |
| 271 | |
Ralf Baechle | fcfd980 | 2006-02-01 17:54:30 +0000 | [diff] [blame] | 272 | case CPU_34K: |
Atsushi Nemoto | 1acf1ca | 2006-05-23 16:42:38 +0900 | [diff] [blame] | 273 | op_model_mipsxx_ops.cpu_type = "mips/34K"; |
Ralf Baechle | fcfd980 | 2006-02-01 17:54:30 +0000 | [diff] [blame] | 274 | break; |
Chris Dearman | c620953 | 2006-05-02 14:08:46 +0100 | [diff] [blame] | 275 | |
| 276 | case CPU_74K: |
Atsushi Nemoto | 1acf1ca | 2006-05-23 16:42:38 +0900 | [diff] [blame] | 277 | op_model_mipsxx_ops.cpu_type = "mips/74K"; |
Chris Dearman | c620953 | 2006-05-02 14:08:46 +0100 | [diff] [blame] | 278 | break; |
Ralf Baechle | fcfd980 | 2006-02-01 17:54:30 +0000 | [diff] [blame] | 279 | |
Ralf Baechle | 2065988 | 2005-12-09 12:42:13 +0000 | [diff] [blame] | 280 | case CPU_5KC: |
Atsushi Nemoto | 1acf1ca | 2006-05-23 16:42:38 +0900 | [diff] [blame] | 281 | op_model_mipsxx_ops.cpu_type = "mips/5K"; |
Ralf Baechle | 2065988 | 2005-12-09 12:42:13 +0000 | [diff] [blame] | 282 | break; |
| 283 | |
Mark Mason | c03bc12 | 2006-01-17 12:06:32 -0800 | [diff] [blame] | 284 | case CPU_SB1: |
| 285 | case CPU_SB1A: |
Atsushi Nemoto | 1acf1ca | 2006-05-23 16:42:38 +0900 | [diff] [blame] | 286 | op_model_mipsxx_ops.cpu_type = "mips/sb1"; |
Mark Mason | c03bc12 | 2006-01-17 12:06:32 -0800 | [diff] [blame] | 287 | break; |
| 288 | |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 289 | default: |
| 290 | printk(KERN_ERR "Profiling unsupported for this CPU\n"); |
| 291 | |
| 292 | return -ENODEV; |
| 293 | } |
| 294 | |
| 295 | perf_irq = mipsxx_perfcount_handler; |
| 296 | |
| 297 | return 0; |
| 298 | } |
| 299 | |
| 300 | static void mipsxx_exit(void) |
| 301 | { |
Atsushi Nemoto | 1acf1ca | 2006-05-23 16:42:38 +0900 | [diff] [blame] | 302 | reset_counters(op_model_mipsxx_ops.num_counters); |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 303 | |
| 304 | perf_irq = null_perf_irq; |
| 305 | } |
| 306 | |
Atsushi Nemoto | 1acf1ca | 2006-05-23 16:42:38 +0900 | [diff] [blame] | 307 | struct op_mips_model op_model_mipsxx_ops = { |
Ralf Baechle | 5417673 | 2005-02-07 02:54:29 +0000 | [diff] [blame] | 308 | .reg_setup = mipsxx_reg_setup, |
| 309 | .cpu_setup = mipsxx_cpu_setup, |
| 310 | .init = mipsxx_init, |
| 311 | .exit = mipsxx_exit, |
| 312 | .cpu_start = mipsxx_cpu_start, |
| 313 | .cpu_stop = mipsxx_cpu_stop, |
| 314 | }; |