blob: 6186f03d84f37c8aa696d3df504e722a5cd36b38 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/slab.h>
10#include <linux/module.h>
11#include <linux/cpumask.h>
Shaohua Li7d715a62008-02-25 09:46:41 +080012#include <linux/pci-aspm.h>
Bjorn Helgaas284f5f92012-04-30 15:21:02 -060013#include <asm-generic/pci-bridge.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090014#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070015
16#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
17#define CARDBUS_RESERVE_BUSNR 3
Linus Torvalds1da177e2005-04-16 15:20:36 -070018
Yinghai Lu67cdc822012-05-17 18:51:12 -070019struct resource busn_resource = {
20 .name = "PCI busn",
21 .start = 0,
22 .end = 255,
23 .flags = IORESOURCE_BUS,
24};
25
Linus Torvalds1da177e2005-04-16 15:20:36 -070026/* Ugh. Need to stop exporting this to modules. */
27LIST_HEAD(pci_root_buses);
28EXPORT_SYMBOL(pci_root_buses);
29
Yinghai Lu5cc62c22012-05-17 18:51:11 -070030static LIST_HEAD(pci_domain_busn_res_list);
31
32struct pci_domain_busn_res {
33 struct list_head list;
34 struct resource res;
35 int domain_nr;
36};
37
38static struct resource *get_pci_domain_busn_res(int domain_nr)
39{
40 struct pci_domain_busn_res *r;
41
42 list_for_each_entry(r, &pci_domain_busn_res_list, list)
43 if (r->domain_nr == domain_nr)
44 return &r->res;
45
46 r = kzalloc(sizeof(*r), GFP_KERNEL);
47 if (!r)
48 return NULL;
49
50 r->domain_nr = domain_nr;
51 r->res.start = 0;
52 r->res.end = 0xff;
53 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
54
55 list_add_tail(&r->list, &pci_domain_busn_res_list);
56
57 return &r->res;
58}
59
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080060static int find_anything(struct device *dev, void *data)
61{
62 return 1;
63}
Linus Torvalds1da177e2005-04-16 15:20:36 -070064
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070065/*
66 * Some device drivers need know if pci is initiated.
67 * Basically, we think pci is not initiated when there
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080068 * is no device to be found on the pci_bus_type.
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070069 */
70int no_pci_devices(void)
71{
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080072 struct device *dev;
73 int no_devices;
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070074
Greg Kroah-Hartman70308922008-02-13 22:30:39 -080075 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
76 no_devices = (dev == NULL);
77 put_device(dev);
78 return no_devices;
79}
Zhang, Yanmined4aaad2007-07-15 23:39:39 -070080EXPORT_SYMBOL(no_pci_devices);
81
Linus Torvalds1da177e2005-04-16 15:20:36 -070082/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070083 * PCI Bus Class
84 */
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040085static void release_pcibus_dev(struct device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070086{
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040087 struct pci_bus *pci_bus = to_pci_bus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -070088
89 if (pci_bus->bridge)
90 put_device(pci_bus->bridge);
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -070091 pci_bus_remove_resources(pci_bus);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +100092 pci_release_bus_of_node(pci_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -070093 kfree(pci_bus);
94}
95
96static struct class pcibus_class = {
97 .name = "pci_bus",
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -040098 .dev_release = &release_pcibus_dev,
Yinghai Lub9d320f2011-05-12 17:11:39 -070099 .dev_attrs = pcibus_dev_attrs,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100};
101
102static int __init pcibus_class_init(void)
103{
104 return class_register(&pcibus_class);
105}
106postcore_initcall(pcibus_class_init);
107
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400108static u64 pci_size(u64 base, u64 maxbase, u64 mask)
Yinghai Lu07eddf32006-11-29 13:53:10 -0800109{
110 u64 size = mask & maxbase; /* Find the significant bits */
111 if (!size)
112 return 0;
113
114 /* Get the lowest of them to find the decode size, and
115 from that the extent. */
116 size = (size & ~(size-1)) - 1;
117
118 /* base == maxbase can be valid only if the BAR has
119 already been programmed with all 1s. */
120 if (base == maxbase && ((base | size) & mask) != mask)
121 return 0;
122
123 return size;
124}
125
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600126static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
Yinghai Lu07eddf32006-11-29 13:53:10 -0800127{
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600128 u32 mem_type;
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600129 unsigned long flags;
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600130
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400131 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600132 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
133 flags |= IORESOURCE_IO;
134 return flags;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400135 }
136
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600137 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
138 flags |= IORESOURCE_MEM;
139 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
140 flags |= IORESOURCE_PREFETCH;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400141
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600142 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
143 switch (mem_type) {
144 case PCI_BASE_ADDRESS_MEM_TYPE_32:
145 break;
146 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600147 /* 1M mem BAR treated as 32-bit BAR */
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600148 break;
149 case PCI_BASE_ADDRESS_MEM_TYPE_64:
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600150 flags |= IORESOURCE_MEM_64;
151 break;
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600152 default:
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600153 /* mem unknown type treated as 32-bit BAR */
Bjorn Helgaas8d6a6a42011-06-14 13:04:29 -0600154 break;
155 }
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600156 return flags;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400157}
158
Yu Zhao0b400c72008-11-22 02:40:40 +0800159/**
160 * pci_read_base - read a PCI BAR
161 * @dev: the PCI device
162 * @type: type of the BAR
163 * @res: resource buffer to be filled in
164 * @pos: BAR position in the config space
165 *
166 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400167 */
Yu Zhao0b400c72008-11-22 02:40:40 +0800168int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400169 struct resource *res, unsigned int pos)
170{
171 u32 l, sz, mask;
Jacob Pan253d2e52010-07-16 10:19:22 -0700172 u16 orig_cmd;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700173 struct pci_bus_region region;
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600174 bool bar_too_big = false, bar_disabled = false;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400175
Michael S. Tsirkin1ed67432009-10-29 17:24:59 +0200176 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400177
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600178 /* No printks while decoding is disabled! */
Jacob Pan253d2e52010-07-16 10:19:22 -0700179 if (!dev->mmio_always_on) {
180 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
181 pci_write_config_word(dev, PCI_COMMAND,
182 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
183 }
184
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400185 res->name = pci_name(dev);
186
187 pci_read_config_dword(dev, pos, &l);
Michael S. Tsirkin1ed67432009-10-29 17:24:59 +0200188 pci_write_config_dword(dev, pos, l | mask);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400189 pci_read_config_dword(dev, pos, &sz);
190 pci_write_config_dword(dev, pos, l);
191
192 /*
193 * All bits set in sz means the device isn't working properly.
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600194 * If the BAR isn't implemented, all bits must be 0. If it's a
195 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
196 * 1 must be clear.
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400197 */
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600198 if (!sz || sz == 0xffffffff)
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400199 goto fail;
200
201 /*
202 * I don't know how l can have all bits set. Copied from old code.
203 * Maybe it fixes a bug on some ancient platform.
204 */
205 if (l == 0xffffffff)
206 l = 0;
207
208 if (type == pci_bar_unknown) {
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600209 res->flags = decode_bar(dev, l);
210 res->flags |= IORESOURCE_SIZEALIGN;
211 if (res->flags & IORESOURCE_IO) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400212 l &= PCI_BASE_ADDRESS_IO_MASK;
David S. Miller5aceca92011-05-23 17:12:22 -0700213 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400214 } else {
215 l &= PCI_BASE_ADDRESS_MEM_MASK;
216 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
217 }
218 } else {
219 res->flags |= (l & IORESOURCE_ROM_ENABLE);
220 l &= PCI_ROM_ADDRESS_MASK;
221 mask = (u32)PCI_ROM_ADDRESS_MASK;
222 }
223
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600224 if (res->flags & IORESOURCE_MEM_64) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400225 u64 l64 = l;
226 u64 sz64 = sz;
227 u64 mask64 = mask | (u64)~0 << 32;
228
229 pci_read_config_dword(dev, pos + 4, &l);
230 pci_write_config_dword(dev, pos + 4, ~0);
231 pci_read_config_dword(dev, pos + 4, &sz);
232 pci_write_config_dword(dev, pos + 4, l);
233
234 l64 |= ((u64)l << 32);
235 sz64 |= ((u64)sz << 32);
236
237 sz64 = pci_size(l64, sz64, mask64);
238
239 if (!sz64)
240 goto fail;
241
Matthew Wilcoxcc5499c2008-07-28 13:39:00 -0400242 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600243 bar_too_big = true;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400244 goto fail;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600245 }
246
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600247 if ((sizeof(resource_size_t) < 8) && l) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400248 /* Address above 32-bit boundary; disable the BAR */
249 pci_write_config_dword(dev, pos, 0);
250 pci_write_config_dword(dev, pos + 4, 0);
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700251 region.start = 0;
252 region.end = sz64;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -0700253 pcibios_bus_to_resource(dev, res, &region);
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600254 bar_disabled = true;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400255 } else {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700256 region.start = l64;
257 region.end = l64 + sz64;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -0700258 pcibios_bus_to_resource(dev, res, &region);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400259 }
260 } else {
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600261 sz = pci_size(l, sz, mask);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400262
Bjorn Helgaas45aa23b2010-04-22 09:02:43 -0600263 if (!sz)
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400264 goto fail;
265
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700266 region.start = l;
267 region.end = l + sz;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -0700268 pcibios_bus_to_resource(dev, res, &region);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400269 }
270
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600271 goto out;
272
273
274fail:
275 res->flags = 0;
276out:
Bjorn Helgaasbbffe432012-07-06 12:08:18 -0600277 if (!dev->mmio_always_on)
278 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
279
Bjorn Helgaas0ff95142012-08-23 10:53:08 -0600280 if (bar_too_big)
281 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n", pos);
282 if (res->flags && !bar_disabled)
283 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
284
Bjorn Helgaas28c68212011-06-14 13:04:35 -0600285 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
Yinghai Lu07eddf32006-11-29 13:53:10 -0800286}
287
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
289{
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400290 unsigned int pos, reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400292 for (pos = 0; pos < howmany; pos++) {
293 struct resource *res = &dev->resource[pos];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400295 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296 }
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400297
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298 if (rom) {
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400299 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300 dev->rom_base_reg = rom;
Matthew Wilcox6ac665c2008-07-28 13:38:59 -0400301 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
302 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
303 IORESOURCE_SIZEALIGN;
304 __pci_read_base(dev, pci_bar_mem32, res, rom);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305 }
306}
307
Bill Pemberton15856ad2012-11-21 15:35:00 -0500308static void pci_read_bridge_io(struct pci_bus *child)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309{
310 struct pci_dev *dev = child->self;
311 u8 io_base_lo, io_limit_lo;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600312 unsigned long io_mask, io_granularity, base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700313 struct pci_bus_region region;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600314 struct resource *res;
315
316 io_mask = PCI_IO_RANGE_MASK;
317 io_granularity = 0x1000;
318 if (dev->io_window_1k) {
319 /* Support 1K I/O space granularity */
320 io_mask = PCI_IO_1K_RANGE_MASK;
321 io_granularity = 0x400;
322 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324 res = child->resource[0];
325 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
326 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600327 base = (io_base_lo & io_mask) << 8;
328 limit = (io_limit_lo & io_mask) << 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329
330 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
331 u16 io_base_hi, io_limit_hi;
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600332
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
334 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600335 base |= ((unsigned long) io_base_hi << 16);
336 limit |= ((unsigned long) io_limit_hi << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337 }
338
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600339 if (base <= limit) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700341 region.start = base;
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -0600342 region.end = limit + io_granularity - 1;
343 pcibios_bus_to_resource(dev, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600344 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700346}
347
Bill Pemberton15856ad2012-11-21 15:35:00 -0500348static void pci_read_bridge_mmio(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700349{
350 struct pci_dev *dev = child->self;
351 u16 mem_base_lo, mem_limit_lo;
352 unsigned long base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700353 struct pci_bus_region region;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700354 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700355
356 res = child->resource[1];
357 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
358 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600359 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
360 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600361 if (base <= limit) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700363 region.start = base;
364 region.end = limit + 0xfffff;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -0700365 pcibios_bus_to_resource(dev, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600366 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700368}
369
Bill Pemberton15856ad2012-11-21 15:35:00 -0500370static void pci_read_bridge_mmio_pref(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700371{
372 struct pci_dev *dev = child->self;
373 u16 mem_base_lo, mem_limit_lo;
374 unsigned long base, limit;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700375 struct pci_bus_region region;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700376 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700377
378 res = child->resource[2];
379 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
380 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600381 base = ((unsigned long) mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
382 limit = ((unsigned long) mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383
384 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
385 u32 mem_base_hi, mem_limit_hi;
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600386
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
388 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
389
390 /*
391 * Some bridges set the base > limit by default, and some
392 * (broken) BIOSes do not initialize them. If we find
393 * this, just assume they are not being used.
394 */
395 if (mem_base_hi <= mem_limit_hi) {
396#if BITS_PER_LONG == 64
Bjorn Helgaas8f38eac2012-06-19 07:45:44 -0600397 base |= ((unsigned long) mem_base_hi) << 32;
398 limit |= ((unsigned long) mem_limit_hi) << 32;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399#else
400 if (mem_base_hi || mem_limit_hi) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600401 dev_err(&dev->dev, "can't handle 64-bit "
402 "address space for bridge\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403 return;
404 }
405#endif
406 }
407 }
Bjorn Helgaas5dde3832012-07-09 13:38:41 -0600408 if (base <= limit) {
Yinghai Lu1f82de12009-04-23 20:48:32 -0700409 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
410 IORESOURCE_MEM | IORESOURCE_PREFETCH;
411 if (res->flags & PCI_PREF_RANGE_TYPE_64)
412 res->flags |= IORESOURCE_MEM_64;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700413 region.start = base;
414 region.end = limit + 0xfffff;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -0700415 pcibios_bus_to_resource(dev, res, &region);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600416 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417 }
418}
419
Bill Pemberton15856ad2012-11-21 15:35:00 -0500420void pci_read_bridge_bases(struct pci_bus *child)
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700421{
422 struct pci_dev *dev = child->self;
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700423 struct resource *res;
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700424 int i;
425
426 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
427 return;
428
Yinghai Lub918c622012-05-17 18:51:11 -0700429 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
430 &child->busn_res,
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700431 dev->transparent ? " (subtractive decode)" : "");
432
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700433 pci_bus_remove_resources(child);
434 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
435 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
436
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700437 pci_read_bridge_io(child);
438 pci_read_bridge_mmio(child);
439 pci_read_bridge_mmio_pref(child);
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700440
441 if (dev->transparent) {
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700442 pci_bus_for_each_resource(child->parent, res, i) {
443 if (res) {
444 pci_bus_add_resource(child, res,
445 PCI_SUBTRACTIVE_DECODE);
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700446 dev_printk(KERN_DEBUG, &dev->dev,
447 " bridge window %pR (subtractive decode)\n",
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700448 res);
449 }
Bjorn Helgaas2adf7512010-02-23 10:24:26 -0700450 }
451 }
Bjorn Helgaasfa27b2d2010-02-23 10:24:21 -0700452}
453
Sam Ravnborg96bde062007-03-26 21:53:30 -0800454static struct pci_bus * pci_alloc_bus(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455{
456 struct pci_bus *b;
457
Eric Sesterhennf5afe802006-02-28 15:34:49 +0100458 b = kzalloc(sizeof(*b), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459 if (b) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460 INIT_LIST_HEAD(&b->node);
461 INIT_LIST_HEAD(&b->children);
462 INIT_LIST_HEAD(&b->devices);
Alex Chiangf46753c2008-06-10 15:28:50 -0600463 INIT_LIST_HEAD(&b->slots);
Bjorn Helgaas2fe2abf2010-02-23 10:24:36 -0700464 INIT_LIST_HEAD(&b->resources);
Matthew Wilcox3749c512009-12-13 08:11:32 -0500465 b->max_bus_speed = PCI_SPEED_UNKNOWN;
466 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700467 }
468 return b;
469}
470
Yinghai Lu7b543662012-04-02 18:31:53 -0700471static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
472{
473 struct pci_host_bridge *bridge;
474
475 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
476 if (bridge) {
477 INIT_LIST_HEAD(&bridge->windows);
478 bridge->bus = b;
479 }
480
481 return bridge;
482}
483
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500484static unsigned char pcix_bus_speed[] = {
485 PCI_SPEED_UNKNOWN, /* 0 */
486 PCI_SPEED_66MHz_PCIX, /* 1 */
487 PCI_SPEED_100MHz_PCIX, /* 2 */
488 PCI_SPEED_133MHz_PCIX, /* 3 */
489 PCI_SPEED_UNKNOWN, /* 4 */
490 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
491 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
492 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
493 PCI_SPEED_UNKNOWN, /* 8 */
494 PCI_SPEED_66MHz_PCIX_266, /* 9 */
495 PCI_SPEED_100MHz_PCIX_266, /* A */
496 PCI_SPEED_133MHz_PCIX_266, /* B */
497 PCI_SPEED_UNKNOWN, /* C */
498 PCI_SPEED_66MHz_PCIX_533, /* D */
499 PCI_SPEED_100MHz_PCIX_533, /* E */
500 PCI_SPEED_133MHz_PCIX_533 /* F */
501};
502
Matthew Wilcox3749c512009-12-13 08:11:32 -0500503static unsigned char pcie_link_speed[] = {
504 PCI_SPEED_UNKNOWN, /* 0 */
505 PCIE_SPEED_2_5GT, /* 1 */
506 PCIE_SPEED_5_0GT, /* 2 */
Matthew Wilcox9dfd97f2009-12-13 08:11:35 -0500507 PCIE_SPEED_8_0GT, /* 3 */
Matthew Wilcox3749c512009-12-13 08:11:32 -0500508 PCI_SPEED_UNKNOWN, /* 4 */
509 PCI_SPEED_UNKNOWN, /* 5 */
510 PCI_SPEED_UNKNOWN, /* 6 */
511 PCI_SPEED_UNKNOWN, /* 7 */
512 PCI_SPEED_UNKNOWN, /* 8 */
513 PCI_SPEED_UNKNOWN, /* 9 */
514 PCI_SPEED_UNKNOWN, /* A */
515 PCI_SPEED_UNKNOWN, /* B */
516 PCI_SPEED_UNKNOWN, /* C */
517 PCI_SPEED_UNKNOWN, /* D */
518 PCI_SPEED_UNKNOWN, /* E */
519 PCI_SPEED_UNKNOWN /* F */
520};
521
522void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
523{
Bjorn Helgaas231afea2012-12-05 13:51:18 -0700524 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
Matthew Wilcox3749c512009-12-13 08:11:32 -0500525}
526EXPORT_SYMBOL_GPL(pcie_update_link_speed);
527
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500528static unsigned char agp_speeds[] = {
529 AGP_UNKNOWN,
530 AGP_1X,
531 AGP_2X,
532 AGP_4X,
533 AGP_8X
534};
535
536static enum pci_bus_speed agp_speed(int agp3, int agpstat)
537{
538 int index = 0;
539
540 if (agpstat & 4)
541 index = 3;
542 else if (agpstat & 2)
543 index = 2;
544 else if (agpstat & 1)
545 index = 1;
546 else
547 goto out;
548
549 if (agp3) {
550 index += 2;
551 if (index == 5)
552 index = 0;
553 }
554
555 out:
556 return agp_speeds[index];
557}
558
559
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500560static void pci_set_bus_speed(struct pci_bus *bus)
561{
562 struct pci_dev *bridge = bus->self;
563 int pos;
564
Matthew Wilcox45b4cdd52009-12-13 08:11:34 -0500565 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
566 if (!pos)
567 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
568 if (pos) {
569 u32 agpstat, agpcmd;
570
571 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
572 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
573
574 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
575 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
576 }
577
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500578 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
579 if (pos) {
580 u16 status;
581 enum pci_bus_speed max;
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500582
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700583 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
584 &status);
585
586 if (status & PCI_X_SSTATUS_533MHZ) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500587 max = PCI_SPEED_133MHz_PCIX_533;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700588 } else if (status & PCI_X_SSTATUS_266MHZ) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500589 max = PCI_SPEED_133MHz_PCIX_266;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700590 } else if (status & PCI_X_SSTATUS_133MHZ) {
591 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) {
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500592 max = PCI_SPEED_133MHz_PCIX_ECC;
593 } else {
594 max = PCI_SPEED_133MHz_PCIX;
595 }
596 } else {
597 max = PCI_SPEED_66MHz_PCIX;
598 }
599
600 bus->max_bus_speed = max;
Bjorn Helgaas7793eea2012-12-05 13:51:17 -0700601 bus->cur_bus_speed = pcix_bus_speed[
602 (status & PCI_X_SSTATUS_FREQ) >> 6];
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500603
604 return;
605 }
606
607 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
608 if (pos) {
609 u32 linkcap;
610 u16 linksta;
611
Jiang Liu59875ae2012-07-24 17:20:06 +0800612 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
Bjorn Helgaas231afea2012-12-05 13:51:18 -0700613 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500614
Jiang Liu59875ae2012-07-24 17:20:06 +0800615 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500616 pcie_update_link_speed(bus, linksta);
617 }
618}
619
620
Adrian Bunkcbd4e052008-04-18 13:53:55 -0700621static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
622 struct pci_dev *bridge, int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700623{
624 struct pci_bus *child;
625 int i;
626
627 /*
628 * Allocate a new bus, and inherit stuff from the parent..
629 */
630 child = pci_alloc_bus();
631 if (!child)
632 return NULL;
633
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634 child->parent = parent;
635 child->ops = parent->ops;
636 child->sysdata = parent->sysdata;
Michael S. Tsirkin6e325a62006-02-14 18:52:22 +0200637 child->bus_flags = parent->bus_flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -0400639 /* initialize some portions of the bus device, but don't register it
640 * now as the parent is not properly set up yet. This device will get
641 * registered later in pci_bus_add_devices()
642 */
643 child->dev.class = &pcibus_class;
Kay Sievers1a927132008-10-30 02:17:49 +0100644 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645
646 /*
647 * Set up the primary, secondary and subordinate
648 * bus numbers.
649 */
Yinghai Lub918c622012-05-17 18:51:11 -0700650 child->number = child->busn_res.start = busnr;
651 child->primary = parent->busn_res.start;
652 child->busn_res.end = 0xff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653
Yu Zhao3789fa82008-11-22 02:41:07 +0800654 if (!bridge)
655 return child;
656
657 child->self = bridge;
658 child->bridge = get_device(&bridge->dev);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +1000659 pci_set_bus_of_node(child);
Matthew Wilcox9be60ca2009-12-13 08:11:33 -0500660 pci_set_bus_speed(child);
661
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662 /* Set up default resource pointers and names.. */
Yu Zhaofde09c62008-11-22 02:39:32 +0800663 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
665 child->resource[i]->name = child->name;
666 }
667 bridge->subordinate = child;
668
669 return child;
670}
671
Sam Ravnborg451124a2008-02-02 22:33:43 +0100672struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673{
674 struct pci_bus *child;
675
676 child = pci_alloc_child_bus(parent, dev, busnr);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700677 if (child) {
Zhang Yanmind71374d2006-06-02 12:35:43 +0800678 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679 list_add_tail(&child->node, &parent->children);
Zhang Yanmind71374d2006-06-02 12:35:43 +0800680 up_write(&pci_bus_sem);
Rajesh Shahe4ea9bb2005-04-28 00:25:48 -0700681 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700682 return child;
683}
684
Sam Ravnborg96bde062007-03-26 21:53:30 -0800685static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700686{
687 struct pci_bus *parent = child->parent;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700688
689 /* Attempts to fix that up are really dangerous unless
690 we're going to re-assign all bus numbers. */
691 if (!pcibios_assign_all_busses())
692 return;
693
Yinghai Lub918c622012-05-17 18:51:11 -0700694 while (parent->parent && parent->busn_res.end < max) {
695 parent->busn_res.end = max;
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700696 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
697 parent = parent->parent;
698 }
699}
700
Linus Torvalds1da177e2005-04-16 15:20:36 -0700701/*
702 * If it's a bridge, configure it and scan the bus behind it.
703 * For CardBus bridges, we don't scan behind as the devices will
704 * be handled by the bridge driver itself.
705 *
706 * We need to process bridges in two passes -- first we scan those
707 * already configured by the BIOS and after we are done with all of
708 * them, we proceed to assigning numbers to the remaining buses in
709 * order to avoid overlaps between old and new bus numbers.
710 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500711int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700712{
713 struct pci_bus *child;
714 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
Dominik Brodowski49887942005-12-08 16:53:12 +0100715 u32 buses, i, j = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716 u16 bctl;
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600717 u8 primary, secondary, subordinate;
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100718 int broken = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719
720 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600721 primary = buses & 0xFF;
722 secondary = (buses >> 8) & 0xFF;
723 subordinate = (buses >> 16) & 0xFF;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700724
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600725 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
726 secondary, subordinate, pass);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700727
Yinghai Lu71f6bd42012-01-30 12:25:24 +0100728 if (!primary && (primary != bus->number) && secondary && subordinate) {
729 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
730 primary = bus->number;
731 }
732
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100733 /* Check if setup is sensible at all */
734 if (!pass &&
Yinghai Lu1965f662012-09-10 17:19:33 -0700735 (primary != bus->number || secondary <= bus->number ||
736 secondary > subordinate)) {
737 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
738 secondary, subordinate);
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100739 broken = 1;
740 }
741
Linus Torvalds1da177e2005-04-16 15:20:36 -0700742 /* Disable MasterAbortMode during probing to avoid reporting
743 of bus errors (in some architectures) */
744 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
745 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
746 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
747
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600748 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
749 !is_cardbus && !broken) {
750 unsigned int cmax;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751 /*
752 * Bus already configured by firmware, process it in the first
753 * pass and just note the configuration.
754 */
755 if (pass)
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000756 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757
758 /*
759 * If we already got to this bus through a different bridge,
Alex Chiang74710de2009-03-20 14:56:10 -0600760 * don't re-add it. This can happen with the i450NX chipset.
761 *
762 * However, we continue to descend down the hierarchy and
763 * scan remaining child buses.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700764 */
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600765 child = pci_find_bus(pci_domain_nr(bus), secondary);
Alex Chiang74710de2009-03-20 14:56:10 -0600766 if (!child) {
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600767 child = pci_add_new_bus(bus, dev, secondary);
Alex Chiang74710de2009-03-20 14:56:10 -0600768 if (!child)
769 goto out;
Bjorn Helgaas99ddd552010-03-16 15:52:58 -0600770 child->primary = primary;
Yinghai Lubc76b732012-05-17 18:51:13 -0700771 pci_bus_insert_busn_res(child, secondary, subordinate);
Alex Chiang74710de2009-03-20 14:56:10 -0600772 child->bridge_ctl = bctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700773 }
774
Linus Torvalds1da177e2005-04-16 15:20:36 -0700775 cmax = pci_scan_child_bus(child);
776 if (cmax > max)
777 max = cmax;
Yinghai Lub918c622012-05-17 18:51:11 -0700778 if (child->busn_res.end > max)
779 max = child->busn_res.end;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780 } else {
781 /*
782 * We need to assign a number to this bus which we always
783 * do in the second pass.
784 */
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700785 if (!pass) {
Benjamin Herrenschmidta1c19892008-10-21 10:06:29 +1100786 if (pcibios_assign_all_busses() || broken)
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700787 /* Temporarily disable forwarding of the
788 configuration cycles on all bridges in
789 this bus segment to avoid possible
790 conflicts in the second pass between two
791 bridges programmed with overlapping
792 bus ranges. */
793 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
794 buses & ~0xffffff);
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000795 goto out;
Ivan Kokshaysky12f44f42005-09-22 21:06:31 -0700796 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797
798 /* Clear errors */
799 pci_write_config_word(dev, PCI_STATUS, 0xffff);
800
Rajesh Shahcc574502005-04-28 00:25:47 -0700801 /* Prevent assigning a bus number that already exists.
Tiejun Chenb1a98b62011-06-02 11:02:50 +0800802 * This can happen when a bridge is hot-plugged, so in
803 * this case we only re-scan this bus. */
804 child = pci_find_bus(pci_domain_nr(bus), max+1);
805 if (!child) {
806 child = pci_add_new_bus(bus, dev, ++max);
807 if (!child)
808 goto out;
Yinghai Lubc76b732012-05-17 18:51:13 -0700809 pci_bus_insert_busn_res(child, max, 0xff);
Tiejun Chenb1a98b62011-06-02 11:02:50 +0800810 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700811 buses = (buses & 0xff000000)
812 | ((unsigned int)(child->primary) << 0)
Yinghai Lub918c622012-05-17 18:51:11 -0700813 | ((unsigned int)(child->busn_res.start) << 8)
814 | ((unsigned int)(child->busn_res.end) << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700815
816 /*
817 * yenta.c forces a secondary latency timer of 176.
818 * Copy that behaviour here.
819 */
820 if (is_cardbus) {
821 buses &= ~0xff000000;
822 buses |= CARDBUS_LATENCY_TIMER << 24;
823 }
Jesper Juhl7c867c82011-01-24 21:14:33 +0100824
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825 /*
826 * We need to blast all three values with a single write.
827 */
828 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
829
830 if (!is_cardbus) {
Gary Hade11949252007-10-08 16:24:16 -0700831 child->bridge_ctl = bctl;
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700832 /*
833 * Adjust subordinate busnr in parent buses.
834 * We do this before scanning for children because
835 * some devices may not be detected if the bios
836 * was lazy.
837 */
838 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700839 /* Now we can scan all subordinate buses... */
840 max = pci_scan_child_bus(child);
Kristen Accardie3ac86d2006-01-17 16:57:01 -0800841 /*
842 * now fix it up again since we have found
843 * the real value of max.
844 */
845 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700846 } else {
847 /*
848 * For CardBus bridges, we leave 4 bus numbers
849 * as cards with a PCI-to-PCI bridge can be
850 * inserted later.
851 */
Dominik Brodowski49887942005-12-08 16:53:12 +0100852 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
853 struct pci_bus *parent = bus;
Rajesh Shahcc574502005-04-28 00:25:47 -0700854 if (pci_find_bus(pci_domain_nr(bus),
855 max+i+1))
856 break;
Dominik Brodowski49887942005-12-08 16:53:12 +0100857 while (parent->parent) {
858 if ((!pcibios_assign_all_busses()) &&
Yinghai Lub918c622012-05-17 18:51:11 -0700859 (parent->busn_res.end > max) &&
860 (parent->busn_res.end <= max+i)) {
Dominik Brodowski49887942005-12-08 16:53:12 +0100861 j = 1;
862 }
863 parent = parent->parent;
864 }
865 if (j) {
866 /*
867 * Often, there are two cardbus bridges
868 * -- try to leave one valid bus number
869 * for each one.
870 */
871 i /= 2;
872 break;
873 }
874 }
Rajesh Shahcc574502005-04-28 00:25:47 -0700875 max += i;
Greg Kroah-Hartman26f674a2005-06-02 15:41:48 -0700876 pci_fixup_parent_subordinate_busnr(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700877 }
878 /*
879 * Set the subordinate bus number to its real value.
880 */
Yinghai Lubc76b732012-05-17 18:51:13 -0700881 pci_bus_update_busn_res_end(child, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700882 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
883 }
884
Gary Hadecb3576f2008-02-08 14:00:52 -0800885 sprintf(child->name,
886 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
887 pci_domain_nr(bus), child->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700888
Bernhard Kaindld55bef52007-07-30 20:35:13 +0200889 /* Has only triggered on CardBus, fixup is in yenta_socket */
Dominik Brodowski49887942005-12-08 16:53:12 +0100890 while (bus->parent) {
Yinghai Lub918c622012-05-17 18:51:11 -0700891 if ((child->busn_res.end > bus->busn_res.end) ||
892 (child->number > bus->busn_res.end) ||
Dominik Brodowski49887942005-12-08 16:53:12 +0100893 (child->number < bus->number) ||
Yinghai Lub918c622012-05-17 18:51:11 -0700894 (child->busn_res.end < bus->number)) {
895 dev_info(&child->dev, "%pR %s "
896 "hidden behind%s bridge %s %pR\n",
897 &child->busn_res,
898 (bus->number > child->busn_res.end &&
899 bus->busn_res.end < child->number) ?
Joe Perchesa6f29a92007-11-19 17:48:29 -0800900 "wholly" : "partially",
901 bus->self->transparent ? " transparent" : "",
Bjorn Helgaas865df572009-11-04 10:32:57 -0700902 dev_name(&bus->dev),
Yinghai Lub918c622012-05-17 18:51:11 -0700903 &bus->busn_res);
Dominik Brodowski49887942005-12-08 16:53:12 +0100904 }
905 bus = bus->parent;
906 }
907
Ralf Baechlebbe8f9a2006-02-14 16:23:57 +0000908out:
909 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
910
Linus Torvalds1da177e2005-04-16 15:20:36 -0700911 return max;
912}
913
914/*
915 * Read interrupt line and base address registers.
916 * The architecture-dependent code can tweak these, of course.
917 */
918static void pci_read_irq(struct pci_dev *dev)
919{
920 unsigned char irq;
921
922 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
Kristen Accardiffeff782005-11-02 16:24:32 -0800923 dev->pin = irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924 if (irq)
925 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
926 dev->irq = irq;
927}
928
Benjamin Herrenschmidtbb209c82010-01-26 17:10:03 +0000929void set_pcie_port_type(struct pci_dev *pdev)
Yu Zhao480b93b2009-03-20 11:25:14 +0800930{
931 int pos;
932 u16 reg16;
933
934 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
935 if (!pos)
936 return;
937 pdev->is_pcie = 1;
Kenji Kaneshige0efea002009-11-05 12:05:11 +0900938 pdev->pcie_cap = pos;
Yu Zhao480b93b2009-03-20 11:25:14 +0800939 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
Yijing Wang786e2282012-07-24 17:20:02 +0800940 pdev->pcie_flags_reg = reg16;
Jon Masonb03e7492011-07-20 15:20:54 -0500941 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
942 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
Yu Zhao480b93b2009-03-20 11:25:14 +0800943}
944
Benjamin Herrenschmidtbb209c82010-01-26 17:10:03 +0000945void set_pcie_hotplug_bridge(struct pci_dev *pdev)
Eric W. Biederman28760482009-09-09 14:09:24 -0700946{
Eric W. Biederman28760482009-09-09 14:09:24 -0700947 u32 reg32;
948
Jiang Liu59875ae2012-07-24 17:20:06 +0800949 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
Eric W. Biederman28760482009-09-09 14:09:24 -0700950 if (reg32 & PCI_EXP_SLTCAP_HPC)
951 pdev->is_hotplug_bridge = 1;
952}
953
Bartlomiej Zolnierkiewicz01abc2a2007-04-23 23:19:36 +0200954#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
Randy Dunlap76e6a1d2006-12-29 16:47:29 -0800955
Linus Torvalds1da177e2005-04-16 15:20:36 -0700956/**
957 * pci_setup_device - fill in class and map information of a device
958 * @dev: the device structure to fill
959 *
960 * Initialize the device structure with information about the device's
961 * vendor,class,memory and IO-space addresses,IRQ lines etc.
962 * Called at initialisation of the PCI subsystem and by CardBus services.
Yu Zhao480b93b2009-03-20 11:25:14 +0800963 * Returns 0 on success and negative if unknown type of device (not normal,
964 * bridge or CardBus).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700965 */
Yu Zhao480b93b2009-03-20 11:25:14 +0800966int pci_setup_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700967{
968 u32 class;
Yu Zhao480b93b2009-03-20 11:25:14 +0800969 u8 hdr_type;
970 struct pci_slot *slot;
Gabe Blackbc577d22009-10-06 10:45:19 -0500971 int pos = 0;
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -0700972 struct pci_bus_region region;
973 struct resource *res;
Yu Zhao480b93b2009-03-20 11:25:14 +0800974
975 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
976 return -EIO;
977
978 dev->sysdata = dev->bus->sysdata;
979 dev->dev.parent = dev->bus->bridge;
980 dev->dev.bus = &pci_bus_type;
Yinghai Lu4e15c462012-11-05 15:20:34 -0500981 dev->dev.type = &pci_dev_type;
Yu Zhao480b93b2009-03-20 11:25:14 +0800982 dev->hdr_type = hdr_type & 0x7f;
983 dev->multifunction = !!(hdr_type & 0x80);
Yu Zhao480b93b2009-03-20 11:25:14 +0800984 dev->error_state = pci_channel_io_normal;
985 set_pcie_port_type(dev);
986
987 list_for_each_entry(slot, &dev->bus->slots, list)
988 if (PCI_SLOT(dev->devfn) == slot->number)
989 dev->slot = slot;
990
991 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
992 set this higher, assuming the system even supports it. */
993 dev->dma_mask = 0xffffffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700994
Greg Kroah-Hartmaneebfcfb2008-07-02 13:24:49 -0700995 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
996 dev->bus->number, PCI_SLOT(dev->devfn),
997 PCI_FUNC(dev->devfn));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700998
999 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
Auke Kokb8a3a522007-06-08 15:46:30 -07001000 dev->revision = class & 0xff;
Yinghai Lu2dd8ba92012-02-19 14:50:12 -08001001 dev->class = class >> 8; /* upper 3 bytes */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001002
Yinghai Lu2dd8ba92012-02-19 14:50:12 -08001003 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1004 dev->vendor, dev->device, dev->hdr_type, dev->class);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001005
Yu Zhao853346e2009-03-21 22:05:11 +08001006 /* need to have dev->class ready */
1007 dev->cfg_size = pci_cfg_space_size(dev);
1008
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009 /* "Unknown power state" */
Daniel Ritz3fe9d192005-08-17 15:32:19 -07001010 dev->current_state = PCI_UNKNOWN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001011
1012 /* Early fixups, before probing the BARs */
1013 pci_fixup_device(pci_fixup_early, dev);
Yu Zhaof79b1b12009-05-28 00:25:05 +08001014 /* device class may be changed after fixup */
1015 class = dev->class >> 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001016
1017 switch (dev->hdr_type) { /* header type */
1018 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1019 if (class == PCI_CLASS_BRIDGE_PCI)
1020 goto bad;
1021 pci_read_irq(dev);
1022 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1023 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1024 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
Alan Cox368c73d2006-10-04 00:41:26 +01001025
1026 /*
1027 * Do the ugly legacy mode stuff here rather than broken chip
1028 * quirk code. Legacy mode ATA controllers have fixed
1029 * addresses. These are not always echoed in BAR0-3, and
1030 * BAR0-3 in a few cases contain junk!
1031 */
1032 if (class == PCI_CLASS_STORAGE_IDE) {
1033 u8 progif;
1034 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1035 if ((progif & 1) == 0) {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001036 region.start = 0x1F0;
1037 region.end = 0x1F7;
1038 res = &dev->resource[0];
1039 res->flags = LEGACY_IO_RESOURCE;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -07001040 pcibios_bus_to_resource(dev, res, &region);
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001041 region.start = 0x3F6;
1042 region.end = 0x3F6;
1043 res = &dev->resource[1];
1044 res->flags = LEGACY_IO_RESOURCE;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -07001045 pcibios_bus_to_resource(dev, res, &region);
Alan Cox368c73d2006-10-04 00:41:26 +01001046 }
1047 if ((progif & 4) == 0) {
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001048 region.start = 0x170;
1049 region.end = 0x177;
1050 res = &dev->resource[2];
1051 res->flags = LEGACY_IO_RESOURCE;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -07001052 pcibios_bus_to_resource(dev, res, &region);
Bjorn Helgaas5bfa14e2012-02-23 20:19:00 -07001053 region.start = 0x376;
1054 region.end = 0x376;
1055 res = &dev->resource[3];
1056 res->flags = LEGACY_IO_RESOURCE;
Bjorn Helgaasfb127cb2012-02-23 20:19:04 -07001057 pcibios_bus_to_resource(dev, res, &region);
Alan Cox368c73d2006-10-04 00:41:26 +01001058 }
1059 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001060 break;
1061
1062 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1063 if (class != PCI_CLASS_BRIDGE_PCI)
1064 goto bad;
1065 /* The PCI-to-PCI bridge spec requires that subtractive
1066 decoding (i.e. transparent) bridge must have programming
1067 interface code of 0x01. */
Kristen Accardi3efd2732005-11-02 16:55:49 -08001068 pci_read_irq(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001069 dev->transparent = ((dev->class & 0xff) == 1);
1070 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
Eric W. Biederman28760482009-09-09 14:09:24 -07001071 set_pcie_hotplug_bridge(dev);
Gabe Blackbc577d22009-10-06 10:45:19 -05001072 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1073 if (pos) {
1074 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1075 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1076 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077 break;
1078
1079 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1080 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1081 goto bad;
1082 pci_read_irq(dev);
1083 pci_read_bases(dev, 1, 0);
1084 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1085 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1086 break;
1087
1088 default: /* unknown header */
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06001089 dev_err(&dev->dev, "unknown header type %02x, "
1090 "ignoring device\n", dev->hdr_type);
Yu Zhao480b93b2009-03-20 11:25:14 +08001091 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001092
1093 bad:
Yinghai Lu2dd8ba92012-02-19 14:50:12 -08001094 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header "
1095 "type %02x)\n", dev->class, dev->hdr_type);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001096 dev->class = PCI_CLASS_NOT_DEFINED;
1097 }
1098
1099 /* We found a fine healthy device, go go go... */
1100 return 0;
1101}
1102
Zhao, Yu201de562008-10-13 19:49:55 +08001103static void pci_release_capabilities(struct pci_dev *dev)
1104{
1105 pci_vpd_release(dev);
Yu Zhaod1b054d2009-03-20 11:25:11 +08001106 pci_iov_release(dev);
Yinghai Luf7968412012-02-11 00:18:30 -08001107 pci_free_cap_save_buffers(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001108}
1109
Linus Torvalds1da177e2005-04-16 15:20:36 -07001110/**
1111 * pci_release_dev - free a pci device structure when all users of it are finished.
1112 * @dev: device that's been disconnected
1113 *
1114 * Will be called only by the device core when all users of this pci device are
1115 * done.
1116 */
1117static void pci_release_dev(struct device *dev)
1118{
1119 struct pci_dev *pci_dev;
1120
1121 pci_dev = to_pci_dev(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001122 pci_release_capabilities(pci_dev);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001123 pci_release_of_node(pci_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001124 kfree(pci_dev);
1125}
1126
1127/**
1128 * pci_cfg_space_size - get the configuration space size of the PCI device.
Randy Dunlap8f7020d2005-10-23 11:57:38 -07001129 * @dev: PCI device
Linus Torvalds1da177e2005-04-16 15:20:36 -07001130 *
1131 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1132 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1133 * access it. Maybe we don't have a way to generate extended config space
1134 * accesses, or the device is behind a reverse Express bridge. So we try
1135 * reading the dword at 0x100 which must either be 0 or a valid extended
1136 * capability header.
1137 */
Yinghai Lu70b9f7d2008-04-28 16:27:23 -07001138int pci_cfg_space_size_ext(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001139{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001140 u32 status;
Zhao, Yu557848c2008-10-13 19:18:07 +08001141 int pos = PCI_CFG_SPACE_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142
Zhao, Yu557848c2008-10-13 19:18:07 +08001143 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001144 goto fail;
1145 if (status == 0xffffffff)
1146 goto fail;
1147
1148 return PCI_CFG_SPACE_EXP_SIZE;
1149
1150 fail:
1151 return PCI_CFG_SPACE_SIZE;
1152}
1153
Yinghai Lu57741a72008-02-15 01:32:50 -08001154int pci_cfg_space_size(struct pci_dev *dev)
1155{
Yinghai Lu70b9f7d2008-04-28 16:27:23 -07001156 int pos;
1157 u32 status;
Yinghai Ludfadd9ed2009-03-08 21:35:37 -07001158 u16 class;
1159
1160 class = dev->class >> 8;
1161 if (class == PCI_CLASS_BRIDGE_HOST)
1162 return pci_cfg_space_size_ext(dev);
Yinghai Lu70b9f7d2008-04-28 16:27:23 -07001163
Jiang Liu59875ae2012-07-24 17:20:06 +08001164 if (!pci_is_pcie(dev)) {
Yinghai Lu70b9f7d2008-04-28 16:27:23 -07001165 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1166 if (!pos)
1167 goto fail;
1168
1169 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1170 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1171 goto fail;
1172 }
1173
1174 return pci_cfg_space_size_ext(dev);
1175
1176 fail:
1177 return PCI_CFG_SPACE_SIZE;
Yinghai Lu57741a72008-02-15 01:32:50 -08001178}
1179
Linus Torvalds1da177e2005-04-16 15:20:36 -07001180static void pci_release_bus_bridge_dev(struct device *dev)
1181{
Yinghai Lu7b543662012-04-02 18:31:53 -07001182 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
1183
Yinghai Lu4fa26492012-04-02 18:31:53 -07001184 if (bridge->release_fn)
1185 bridge->release_fn(bridge);
Yinghai Lu7b543662012-04-02 18:31:53 -07001186
1187 pci_free_resource_list(&bridge->windows);
1188
1189 kfree(bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001190}
1191
Michael Ellerman65891212007-04-05 17:19:08 +10001192struct pci_dev *alloc_pci_dev(void)
1193{
1194 struct pci_dev *dev;
1195
1196 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1197 if (!dev)
1198 return NULL;
1199
Michael Ellerman65891212007-04-05 17:19:08 +10001200 INIT_LIST_HEAD(&dev->bus_list);
1201
1202 return dev;
1203}
1204EXPORT_SYMBOL(alloc_pci_dev);
1205
Yinghai Luefdc87d2012-01-27 10:55:10 -08001206bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1207 int crs_timeout)
1208{
1209 int delay = 1;
1210
1211 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1212 return false;
1213
1214 /* some broken boards return 0 or ~0 if a slot is empty: */
1215 if (*l == 0xffffffff || *l == 0x00000000 ||
1216 *l == 0x0000ffff || *l == 0xffff0000)
1217 return false;
1218
1219 /* Configuration request Retry Status */
1220 while (*l == 0xffff0001) {
1221 if (!crs_timeout)
1222 return false;
1223
1224 msleep(delay);
1225 delay *= 2;
1226 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1227 return false;
1228 /* Card hasn't responded in 60 seconds? Must be stuck. */
1229 if (delay > crs_timeout) {
1230 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1231 "responding\n", pci_domain_nr(bus),
1232 bus->number, PCI_SLOT(devfn),
1233 PCI_FUNC(devfn));
1234 return false;
1235 }
1236 }
1237
1238 return true;
1239}
1240EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1241
Linus Torvalds1da177e2005-04-16 15:20:36 -07001242/*
1243 * Read the config data for a PCI device, sanity-check it
1244 * and fill in the dev structure...
1245 */
Adrian Bunk7f7b5de2008-04-18 13:53:55 -07001246static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001247{
1248 struct pci_dev *dev;
1249 u32 l;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001250
Yinghai Luefdc87d2012-01-27 10:55:10 -08001251 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001252 return NULL;
1253
Michael Ellermanbab41e92007-04-05 17:19:09 +10001254 dev = alloc_pci_dev();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001255 if (!dev)
1256 return NULL;
1257
Linus Torvalds1da177e2005-04-16 15:20:36 -07001258 dev->bus = bus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001259 dev->devfn = devfn;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001260 dev->vendor = l & 0xffff;
1261 dev->device = (l >> 16) & 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001262
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001263 pci_set_of_node(dev);
1264
Yu Zhao480b93b2009-03-20 11:25:14 +08001265 if (pci_setup_device(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001266 kfree(dev);
1267 return NULL;
1268 }
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001269
1270 return dev;
1271}
1272
Zhao, Yu201de562008-10-13 19:49:55 +08001273static void pci_init_capabilities(struct pci_dev *dev)
1274{
1275 /* MSI/MSI-X list */
1276 pci_msi_init_pci_dev(dev);
1277
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01001278 /* Buffers for saving PCIe and PCI-X capabilities */
1279 pci_allocate_cap_save_buffers(dev);
1280
Zhao, Yu201de562008-10-13 19:49:55 +08001281 /* Power Management */
1282 pci_pm_init(dev);
Jesse Barneseb9c39d2008-12-17 12:10:05 -08001283 platform_pci_wakeup_init(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001284
1285 /* Vital Product Data */
1286 pci_vpd_pci22_init(dev);
Yu Zhao58c3a722008-10-14 14:02:53 +08001287
1288 /* Alternative Routing-ID Forwarding */
1289 pci_enable_ari(dev);
Yu Zhaod1b054d2009-03-20 11:25:11 +08001290
1291 /* Single Root I/O Virtualization */
1292 pci_iov_init(dev);
Allen Kayae21ee62009-10-07 10:27:17 -07001293
1294 /* Enable ACS P2P upstream forwarding */
Chris Wright5d990b62009-12-04 12:15:21 -08001295 pci_enable_acs(dev);
Zhao, Yu201de562008-10-13 19:49:55 +08001296}
1297
Sam Ravnborg96bde062007-03-26 21:53:30 -08001298void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001299{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001300 device_initialize(&dev->dev);
1301 dev->dev.release = pci_release_dev;
1302 pci_dev_get(dev);
1303
Linus Torvalds1da177e2005-04-16 15:20:36 -07001304 dev->dev.dma_mask = &dev->dma_mask;
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001305 dev->dev.dma_parms = &dev->dma_parms;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001306 dev->dev.coherent_dma_mask = 0xffffffffull;
1307
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001308 pci_set_dma_max_seg_size(dev, 65536);
FUJITA Tomonori59fc67d2008-02-04 22:28:14 -08001309 pci_set_dma_seg_boundary(dev, 0xffffffff);
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08001310
Linus Torvalds1da177e2005-04-16 15:20:36 -07001311 /* Fix up broken headers */
1312 pci_fixup_device(pci_fixup_header, dev);
1313
Yinghai Lu2069ecf2012-02-15 21:40:31 -08001314 /* moved out from quirk header fixup code */
1315 pci_reassigndev_resource_alignment(dev);
1316
Rafael J. Wysocki4b77b0a2009-09-09 23:49:59 +02001317 /* Clear the state_saved flag. */
1318 dev->state_saved = false;
1319
Zhao, Yu201de562008-10-13 19:49:55 +08001320 /* Initialize various capabilities */
1321 pci_init_capabilities(dev);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001322
Linus Torvalds1da177e2005-04-16 15:20:36 -07001323 /*
1324 * Add the device to our list of discovered devices
1325 * and the bus list for fixup functions, etc.
1326 */
Zhang Yanmind71374d2006-06-02 12:35:43 +08001327 down_write(&pci_bus_sem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001328 list_add_tail(&dev->bus_list, &bus->devices);
Zhang Yanmind71374d2006-06-02 12:35:43 +08001329 up_write(&pci_bus_sem);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001330}
1331
Sam Ravnborg451124a2008-02-02 22:33:43 +01001332struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001333{
1334 struct pci_dev *dev;
1335
Trent Piepho90bdb312009-03-20 14:56:00 -06001336 dev = pci_get_slot(bus, devfn);
1337 if (dev) {
1338 pci_dev_put(dev);
1339 return dev;
1340 }
1341
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001342 dev = pci_scan_device(bus, devfn);
1343 if (!dev)
1344 return NULL;
1345
1346 pci_device_add(dev, bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001347
1348 return dev;
1349}
Adrian Bunkb73e9682007-11-21 15:07:11 -08001350EXPORT_SYMBOL(pci_scan_single_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001351
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001352static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
1353{
1354 u16 cap;
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001355 unsigned pos, next_fn;
1356
1357 if (!dev)
1358 return 0;
1359
1360 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001361 if (!pos)
1362 return 0;
1363 pci_read_config_word(dev, pos + 4, &cap);
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001364 next_fn = cap >> 8;
1365 if (next_fn <= fn)
1366 return 0;
1367 return next_fn;
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001368}
1369
1370static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
1371{
1372 return (fn + 1) % 8;
1373}
1374
1375static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
1376{
1377 return 0;
1378}
1379
1380static int only_one_child(struct pci_bus *bus)
1381{
1382 struct pci_dev *parent = bus->self;
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06001383
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001384 if (!parent || !pci_is_pcie(parent))
1385 return 0;
Yijing Wang62f87c02012-07-24 17:20:03 +08001386 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06001387 return 1;
Yijing Wang62f87c02012-07-24 17:20:03 +08001388 if (pci_pcie_type(parent) == PCI_EXP_TYPE_DOWNSTREAM &&
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06001389 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001390 return 1;
1391 return 0;
1392}
1393
Linus Torvalds1da177e2005-04-16 15:20:36 -07001394/**
1395 * pci_scan_slot - scan a PCI slot on a bus for devices.
1396 * @bus: PCI bus to scan
1397 * @devfn: slot number to scan (must have zero function.)
1398 *
1399 * Scan a PCI slot on the specified PCI bus for devices, adding
1400 * discovered devices to the @bus->devices list. New devices
Greg Kroah-Hartman8a1bc902008-02-14 14:56:56 -08001401 * will not have is_added set.
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001402 *
1403 * Returns the number of new devices found.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001404 */
Sam Ravnborg96bde062007-03-26 21:53:30 -08001405int pci_scan_slot(struct pci_bus *bus, int devfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001406{
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001407 unsigned fn, nr = 0;
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001408 struct pci_dev *dev;
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001409 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
1410
1411 if (only_one_child(bus) && (devfn > 0))
1412 return 0; /* Already scanned the entire slot */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001413
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001414 dev = pci_scan_single_device(bus, devfn);
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001415 if (!dev)
1416 return 0;
1417 if (!dev->is_added)
Trent Piepho1b69dfc2009-03-20 14:56:05 -06001418 nr++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001419
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001420 if (pci_ari_enabled(bus))
1421 next_fn = next_ari_fn;
Matthew Wilcox4fb88c12010-01-17 14:01:41 -07001422 else if (dev->multifunction)
Matthew Wilcoxf07852d2009-12-13 08:10:02 -05001423 next_fn = next_trad_fn;
1424
1425 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
1426 dev = pci_scan_single_device(bus, devfn + fn);
1427 if (dev) {
1428 if (!dev->is_added)
1429 nr++;
1430 dev->multifunction = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001431 }
1432 }
Shaohua Li7d715a62008-02-25 09:46:41 +08001433
Shaohua Li149e1632008-07-23 10:32:31 +08001434 /* only one slot has pcie device */
1435 if (bus->self && nr)
Shaohua Li7d715a62008-02-25 09:46:41 +08001436 pcie_aspm_init_link_state(bus->self);
1437
Linus Torvalds1da177e2005-04-16 15:20:36 -07001438 return nr;
1439}
1440
Jon Masonb03e7492011-07-20 15:20:54 -05001441static int pcie_find_smpss(struct pci_dev *dev, void *data)
1442{
1443 u8 *smpss = data;
1444
1445 if (!pci_is_pcie(dev))
1446 return 0;
1447
1448 /* For PCIE hotplug enabled slots not connected directly to a
1449 * PCI-E root port, there can be problems when hotplugging
1450 * devices. This is due to the possibility of hotplugging a
1451 * device into the fabric with a smaller MPS that the devices
1452 * currently running have configured. Modifying the MPS on the
1453 * running devices could cause a fatal bus error due to an
1454 * incoming frame being larger than the newly configured MPS.
1455 * To work around this, the MPS for the entire fabric must be
1456 * set to the minimum size. Any devices hotplugged into this
1457 * fabric will have the minimum MPS set. If the PCI hotplug
1458 * slot is directly connected to the root port and there are not
1459 * other devices on the fabric (which seems to be the most
1460 * common case), then this is not an issue and MPS discovery
1461 * will occur as normal.
1462 */
1463 if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
Benjamin Herrenschmidt1a4b1a42011-09-13 15:16:33 -03001464 (dev->bus->self &&
Yijing Wang62f87c02012-07-24 17:20:03 +08001465 pci_pcie_type(dev->bus->self) != PCI_EXP_TYPE_ROOT_PORT)))
Jon Masonb03e7492011-07-20 15:20:54 -05001466 *smpss = 0;
1467
1468 if (*smpss > dev->pcie_mpss)
1469 *smpss = dev->pcie_mpss;
1470
1471 return 0;
1472}
1473
1474static void pcie_write_mps(struct pci_dev *dev, int mps)
1475{
Jon Mason62f392e2011-10-14 14:56:14 -05001476 int rc;
Jon Masonb03e7492011-07-20 15:20:54 -05001477
1478 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
Jon Mason62f392e2011-10-14 14:56:14 -05001479 mps = 128 << dev->pcie_mpss;
Jon Masonb03e7492011-07-20 15:20:54 -05001480
Yijing Wang62f87c02012-07-24 17:20:03 +08001481 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1482 dev->bus->self)
Jon Mason62f392e2011-10-14 14:56:14 -05001483 /* For "Performance", the assumption is made that
Jon Masonb03e7492011-07-20 15:20:54 -05001484 * downstream communication will never be larger than
1485 * the MRRS. So, the MPS only needs to be configured
1486 * for the upstream communication. This being the case,
1487 * walk from the top down and set the MPS of the child
1488 * to that of the parent bus.
Jon Mason62f392e2011-10-14 14:56:14 -05001489 *
1490 * Configure the device MPS with the smaller of the
1491 * device MPSS or the bridge MPS (which is assumed to be
1492 * properly configured at this point to the largest
1493 * allowable MPS based on its parent bus).
Jon Masonb03e7492011-07-20 15:20:54 -05001494 */
Jon Mason62f392e2011-10-14 14:56:14 -05001495 mps = min(mps, pcie_get_mps(dev->bus->self));
Jon Masonb03e7492011-07-20 15:20:54 -05001496 }
1497
1498 rc = pcie_set_mps(dev, mps);
1499 if (rc)
1500 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1501}
1502
Jon Mason62f392e2011-10-14 14:56:14 -05001503static void pcie_write_mrrs(struct pci_dev *dev)
Jon Masonb03e7492011-07-20 15:20:54 -05001504{
Jon Mason62f392e2011-10-14 14:56:14 -05001505 int rc, mrrs;
Jon Masonb03e7492011-07-20 15:20:54 -05001506
Jon Masoned2888e2011-09-08 16:41:18 -05001507 /* In the "safe" case, do not configure the MRRS. There appear to be
1508 * issues with setting MRRS to 0 on a number of devices.
1509 */
Jon Masoned2888e2011-09-08 16:41:18 -05001510 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1511 return;
Jon Masonb03e7492011-07-20 15:20:54 -05001512
Jon Masoned2888e2011-09-08 16:41:18 -05001513 /* For Max performance, the MRRS must be set to the largest supported
1514 * value. However, it cannot be configured larger than the MPS the
Jon Mason62f392e2011-10-14 14:56:14 -05001515 * device or the bus can support. This should already be properly
1516 * configured by a prior call to pcie_write_mps.
Jon Masoned2888e2011-09-08 16:41:18 -05001517 */
Jon Mason62f392e2011-10-14 14:56:14 -05001518 mrrs = pcie_get_mps(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05001519
1520 /* MRRS is a R/W register. Invalid values can be written, but a
Jon Masoned2888e2011-09-08 16:41:18 -05001521 * subsequent read will verify if the value is acceptable or not.
Jon Masonb03e7492011-07-20 15:20:54 -05001522 * If the MRRS value provided is not acceptable (e.g., too large),
1523 * shrink the value until it is acceptable to the HW.
1524 */
1525 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1526 rc = pcie_set_readrq(dev, mrrs);
Jon Mason62f392e2011-10-14 14:56:14 -05001527 if (!rc)
1528 break;
Jon Masonb03e7492011-07-20 15:20:54 -05001529
Jon Mason62f392e2011-10-14 14:56:14 -05001530 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
Jon Masonb03e7492011-07-20 15:20:54 -05001531 mrrs /= 2;
1532 }
Jon Mason62f392e2011-10-14 14:56:14 -05001533
1534 if (mrrs < 128)
1535 dev_err(&dev->dev, "MRRS was unable to be configured with a "
1536 "safe value. If problems are experienced, try running "
1537 "with pci=pcie_bus_safe.\n");
Jon Masonb03e7492011-07-20 15:20:54 -05001538}
1539
1540static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1541{
Jon Masona513a992011-10-14 14:56:16 -05001542 int mps, orig_mps;
Jon Masonb03e7492011-07-20 15:20:54 -05001543
1544 if (!pci_is_pcie(dev))
1545 return 0;
1546
Jon Masona513a992011-10-14 14:56:16 -05001547 mps = 128 << *(u8 *)data;
1548 orig_mps = pcie_get_mps(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05001549
1550 pcie_write_mps(dev, mps);
Jon Mason62f392e2011-10-14 14:56:14 -05001551 pcie_write_mrrs(dev);
Jon Masonb03e7492011-07-20 15:20:54 -05001552
Jon Masona513a992011-10-14 14:56:16 -05001553 dev_info(&dev->dev, "PCI-E Max Payload Size set to %4d/%4d (was %4d), "
1554 "Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss,
1555 orig_mps, pcie_get_readrq(dev));
Jon Masonb03e7492011-07-20 15:20:54 -05001556
1557 return 0;
1558}
1559
Jon Masona513a992011-10-14 14:56:16 -05001560/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
Jon Masonb03e7492011-07-20 15:20:54 -05001561 * parents then children fashion. If this changes, then this code will not
1562 * work as designed.
1563 */
1564void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss)
1565{
Jon Mason5f39e672011-10-03 09:50:20 -05001566 u8 smpss;
Jon Masonb03e7492011-07-20 15:20:54 -05001567
Jon Masonb03e7492011-07-20 15:20:54 -05001568 if (!pci_is_pcie(bus->self))
1569 return;
1570
Jon Mason5f39e672011-10-03 09:50:20 -05001571 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
1572 return;
1573
1574 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1575 * to be aware to the MPS of the destination. To work around this,
1576 * simply force the MPS of the entire system to the smallest possible.
1577 */
1578 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1579 smpss = 0;
1580
Jon Masonb03e7492011-07-20 15:20:54 -05001581 if (pcie_bus_config == PCIE_BUS_SAFE) {
Jon Mason5f39e672011-10-03 09:50:20 -05001582 smpss = mpss;
1583
Jon Masonb03e7492011-07-20 15:20:54 -05001584 pcie_find_smpss(bus->self, &smpss);
1585 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1586 }
1587
1588 pcie_bus_configure_set(bus->self, &smpss);
1589 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1590}
Jon Masondebc3b72011-08-02 00:01:18 -05001591EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
Jon Masonb03e7492011-07-20 15:20:54 -05001592
Bill Pemberton15856ad2012-11-21 15:35:00 -05001593unsigned int pci_scan_child_bus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001594{
Yinghai Lub918c622012-05-17 18:51:11 -07001595 unsigned int devfn, pass, max = bus->busn_res.start;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001596 struct pci_dev *dev;
1597
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001598 dev_dbg(&bus->dev, "scanning bus\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001599
1600 /* Go find them, Rover! */
1601 for (devfn = 0; devfn < 0x100; devfn += 8)
1602 pci_scan_slot(bus, devfn);
1603
Yu Zhaoa28724b2009-03-20 11:25:13 +08001604 /* Reserve buses for SR-IOV capability. */
1605 max += pci_iov_bus_range(bus);
1606
Linus Torvalds1da177e2005-04-16 15:20:36 -07001607 /*
1608 * After performing arch-dependent fixup of the bus, look behind
1609 * all PCI-to-PCI bridges on this bus.
1610 */
Alex Chiang74710de2009-03-20 14:56:10 -06001611 if (!bus->is_added) {
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001612 dev_dbg(&bus->dev, "fixups for bus\n");
Alex Chiang74710de2009-03-20 14:56:10 -06001613 pcibios_fixup_bus(bus);
1614 if (pci_is_root_bus(bus))
1615 bus->is_added = 1;
1616 }
1617
Linus Torvalds1da177e2005-04-16 15:20:36 -07001618 for (pass=0; pass < 2; pass++)
1619 list_for_each_entry(dev, &bus->devices, bus_list) {
1620 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1621 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1622 max = pci_scan_bridge(bus, dev, max, pass);
1623 }
1624
1625 /*
1626 * We've scanned the bus and so we know all about what's on
1627 * the other side of any bridges that may be on this bus plus
1628 * any devices.
1629 *
1630 * Return how far we've got finding sub-buses.
1631 */
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001632 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001633 return max;
1634}
1635
Bjorn Helgaas166c6372011-10-28 16:25:45 -06001636struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1637 struct pci_ops *ops, void *sysdata, struct list_head *resources)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001638{
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001639 int error;
Bjorn Helgaas5a21d702012-02-23 20:18:59 -07001640 struct pci_host_bridge *bridge;
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001641 struct pci_bus *b, *b2;
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001642 struct pci_host_bridge_window *window, *n;
Bjorn Helgaasa9d9f522011-10-28 16:25:40 -06001643 struct resource *res;
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001644 resource_size_t offset;
1645 char bus_addr[64];
1646 char *fmt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001647
Linus Torvalds1da177e2005-04-16 15:20:36 -07001648
Bjorn Helgaas5a21d702012-02-23 20:18:59 -07001649 b = pci_alloc_bus();
1650 if (!b)
Yinghai Lu7b543662012-04-02 18:31:53 -07001651 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001652
1653 b->sysdata = sysdata;
1654 b->ops = ops;
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001655 b2 = pci_find_bus(pci_domain_nr(b), bus);
1656 if (b2) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001657 /* If we already got to this bus through a different bridge, ignore it */
Bjorn Helgaas0207c352009-11-04 10:32:52 -07001658 dev_dbg(&b2->dev, "bus already known\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001659 goto err_out;
1660 }
Zhang Yanmind71374d2006-06-02 12:35:43 +08001661
Yinghai Lu7b543662012-04-02 18:31:53 -07001662 bridge = pci_alloc_host_bridge(b);
1663 if (!bridge)
1664 goto err_out;
1665
1666 bridge->dev.parent = parent;
1667 bridge->dev.release = pci_release_bus_bridge_dev;
1668 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1669 error = device_register(&bridge->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001670 if (error)
Yinghai Lu7b543662012-04-02 18:31:53 -07001671 goto bridge_dev_reg_err;
1672 b->bridge = get_device(&bridge->dev);
Rafael J. Wysockia1e4d722010-02-08 19:16:33 +01001673 device_enable_async_suspend(b->bridge);
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001674 pci_set_bus_of_node(b);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001675
Yinghai Lu0d358f22008-02-19 03:20:41 -08001676 if (!parent)
1677 set_dev_node(b->bridge, pcibus_to_node(b));
1678
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001679 b->dev.class = &pcibus_class;
1680 b->dev.parent = b->bridge;
Kay Sievers1a927132008-10-30 02:17:49 +01001681 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
Greg Kroah-Hartmanfd7d1ce2007-05-22 22:47:54 -04001682 error = device_register(&b->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001683 if (error)
1684 goto class_dev_reg_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001685
1686 /* Create legacy_io and legacy_mem files for this bus */
1687 pci_create_legacy_files(b);
1688
Yinghai Lub918c622012-05-17 18:51:11 -07001689 b->number = b->busn_res.start = bus;
Bjorn Helgaas166c6372011-10-28 16:25:45 -06001690
Bjorn Helgaasa9d9f522011-10-28 16:25:40 -06001691 if (parent)
1692 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
1693 else
1694 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
1695
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001696 /* Add initial resources to the bus */
1697 list_for_each_entry_safe(window, n, resources, list) {
1698 list_move_tail(&window->list, &bridge->windows);
1699 res = window->res;
1700 offset = window->offset;
Yinghai Luf848ffb2012-05-17 18:51:12 -07001701 if (res->flags & IORESOURCE_BUS)
1702 pci_bus_insert_busn_res(b, bus, res->end);
1703 else
1704 pci_bus_add_resource(b, res, 0);
Bjorn Helgaas0efd5aa2012-02-23 20:19:00 -07001705 if (offset) {
1706 if (resource_type(res) == IORESOURCE_IO)
1707 fmt = " (bus address [%#06llx-%#06llx])";
1708 else
1709 fmt = " (bus address [%#010llx-%#010llx])";
1710 snprintf(bus_addr, sizeof(bus_addr), fmt,
1711 (unsigned long long) (res->start - offset),
1712 (unsigned long long) (res->end - offset));
1713 } else
1714 bus_addr[0] = '\0';
1715 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
Bjorn Helgaasa9d9f522011-10-28 16:25:40 -06001716 }
1717
Bjorn Helgaasa5390aa2012-02-23 20:18:59 -07001718 down_write(&pci_bus_sem);
1719 list_add_tail(&b->node, &pci_root_buses);
1720 up_write(&pci_bus_sem);
1721
Linus Torvalds1da177e2005-04-16 15:20:36 -07001722 return b;
1723
Linus Torvalds1da177e2005-04-16 15:20:36 -07001724class_dev_reg_err:
Yinghai Lu7b543662012-04-02 18:31:53 -07001725 put_device(&bridge->dev);
1726 device_unregister(&bridge->dev);
1727bridge_dev_reg_err:
Bjorn Helgaas5a21d702012-02-23 20:18:59 -07001728 kfree(bridge);
Yinghai Lu7b543662012-04-02 18:31:53 -07001729err_out:
1730 kfree(b);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001731 return NULL;
1732}
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001733
Yinghai Lu98a35832012-05-18 11:35:50 -06001734int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
1735{
1736 struct resource *res = &b->busn_res;
1737 struct resource *parent_res, *conflict;
1738
1739 res->start = bus;
1740 res->end = bus_max;
1741 res->flags = IORESOURCE_BUS;
1742
1743 if (!pci_is_root_bus(b))
1744 parent_res = &b->parent->busn_res;
1745 else {
1746 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
1747 res->flags |= IORESOURCE_PCI_FIXED;
1748 }
1749
1750 conflict = insert_resource_conflict(parent_res, res);
1751
1752 if (conflict)
1753 dev_printk(KERN_DEBUG, &b->dev,
1754 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
1755 res, pci_is_root_bus(b) ? "domain " : "",
1756 parent_res, conflict->name, conflict);
Yinghai Lu98a35832012-05-18 11:35:50 -06001757
1758 return conflict == NULL;
1759}
1760
1761int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
1762{
1763 struct resource *res = &b->busn_res;
1764 struct resource old_res = *res;
1765 resource_size_t size;
1766 int ret;
1767
1768 if (res->start > bus_max)
1769 return -EINVAL;
1770
1771 size = bus_max - res->start + 1;
1772 ret = adjust_resource(res, res->start, size);
1773 dev_printk(KERN_DEBUG, &b->dev,
1774 "busn_res: %pR end %s updated to %02x\n",
1775 &old_res, ret ? "can not be" : "is", bus_max);
1776
1777 if (!ret && !res->parent)
1778 pci_bus_insert_busn_res(b, res->start, res->end);
1779
1780 return ret;
1781}
1782
1783void pci_bus_release_busn_res(struct pci_bus *b)
1784{
1785 struct resource *res = &b->busn_res;
1786 int ret;
1787
1788 if (!res->flags || !res->parent)
1789 return;
1790
1791 ret = release_resource(res);
1792 dev_printk(KERN_DEBUG, &b->dev,
1793 "busn_res: %pR %s released\n",
1794 res, ret ? "can not be" : "is");
1795}
1796
Bill Pemberton15856ad2012-11-21 15:35:00 -05001797struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06001798 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1799{
Yinghai Lu4d99f522012-05-17 18:51:12 -07001800 struct pci_host_bridge_window *window;
1801 bool found = false;
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06001802 struct pci_bus *b;
Yinghai Lu4d99f522012-05-17 18:51:12 -07001803 int max;
1804
1805 list_for_each_entry(window, resources, list)
1806 if (window->res->flags & IORESOURCE_BUS) {
1807 found = true;
1808 break;
1809 }
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06001810
1811 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
1812 if (!b)
1813 return NULL;
1814
Yinghai Lu4d99f522012-05-17 18:51:12 -07001815 if (!found) {
1816 dev_info(&b->dev,
1817 "No busn resource found for root bus, will use [bus %02x-ff]\n",
1818 bus);
1819 pci_bus_insert_busn_res(b, bus, 255);
1820 }
1821
1822 max = pci_scan_child_bus(b);
1823
1824 if (!found)
1825 pci_bus_update_busn_res_end(b, max);
1826
Bjorn Helgaasa2ebb822011-10-28 16:25:50 -06001827 pci_bus_add_devices(b);
1828 return b;
1829}
1830EXPORT_SYMBOL(pci_scan_root_bus);
1831
Bjorn Helgaas7e00fe22011-10-28 16:26:05 -06001832/* Deprecated; use pci_scan_root_bus() instead */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001833struct pci_bus *pci_scan_bus_parented(struct device *parent,
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001834 int bus, struct pci_ops *ops, void *sysdata)
1835{
Bjorn Helgaas1e39ae92011-10-28 16:26:00 -06001836 LIST_HEAD(resources);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001837 struct pci_bus *b;
1838
Bjorn Helgaas1e39ae92011-10-28 16:26:00 -06001839 pci_add_resource(&resources, &ioport_resource);
1840 pci_add_resource(&resources, &iomem_resource);
Yinghai Lu857c3b62012-05-17 18:51:12 -07001841 pci_add_resource(&resources, &busn_resource);
Bjorn Helgaas1e39ae92011-10-28 16:26:00 -06001842 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001843 if (b)
Yinghai Lu857c3b62012-05-17 18:51:12 -07001844 pci_scan_child_bus(b);
Bjorn Helgaas1e39ae92011-10-28 16:26:00 -06001845 else
1846 pci_free_resource_list(&resources);
Paul Mackerrascdb9b9f2005-09-06 09:31:03 +10001847 return b;
1848}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001849EXPORT_SYMBOL(pci_scan_bus_parented);
1850
Bill Pemberton15856ad2012-11-21 15:35:00 -05001851struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06001852 void *sysdata)
1853{
1854 LIST_HEAD(resources);
1855 struct pci_bus *b;
1856
1857 pci_add_resource(&resources, &ioport_resource);
1858 pci_add_resource(&resources, &iomem_resource);
Yinghai Lu857c3b62012-05-17 18:51:12 -07001859 pci_add_resource(&resources, &busn_resource);
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06001860 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
1861 if (b) {
Yinghai Lu857c3b62012-05-17 18:51:12 -07001862 pci_scan_child_bus(b);
Bjorn Helgaasde4b2f72011-10-28 16:25:55 -06001863 pci_bus_add_devices(b);
1864 } else {
1865 pci_free_resource_list(&resources);
1866 }
1867 return b;
1868}
1869EXPORT_SYMBOL(pci_scan_bus);
1870
Alex Chiang3ed4fd92009-03-20 14:56:25 -06001871/**
Yinghai Lu2f320522012-01-21 02:08:22 -08001872 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
1873 * @bridge: PCI bridge for the bus to scan
1874 *
1875 * Scan a PCI bus and child buses for new devices, add them,
1876 * and enable them, resizing bridge mmio/io resource if necessary
1877 * and possible. The caller must ensure the child devices are already
1878 * removed for resizing to occur.
1879 *
1880 * Returns the max number of subordinate bus discovered.
1881 */
1882unsigned int __ref pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
1883{
1884 unsigned int max;
1885 struct pci_bus *bus = bridge->subordinate;
1886
1887 max = pci_scan_child_bus(bus);
1888
1889 pci_assign_unassigned_bridge_resources(bridge);
1890
1891 pci_bus_add_devices(bus);
1892
1893 return max;
1894}
1895
Yinghai Lua5213a32012-10-30 14:31:21 -06001896/**
1897 * pci_rescan_bus - scan a PCI bus for devices.
1898 * @bus: PCI bus to scan
1899 *
1900 * Scan a PCI bus and child buses for new devices, adds them,
1901 * and enables them.
1902 *
1903 * Returns the max number of subordinate bus discovered.
1904 */
1905unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1906{
1907 unsigned int max;
1908
1909 max = pci_scan_child_bus(bus);
1910 pci_assign_unassigned_bus_resources(bus);
Yinghai Lue164f652012-10-30 14:31:26 -06001911 pci_enable_bridges(bus);
Yinghai Lua5213a32012-10-30 14:31:21 -06001912 pci_bus_add_devices(bus);
1913
1914 return max;
1915}
1916EXPORT_SYMBOL_GPL(pci_rescan_bus);
1917
Linus Torvalds1da177e2005-04-16 15:20:36 -07001918EXPORT_SYMBOL(pci_add_new_bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001919EXPORT_SYMBOL(pci_scan_slot);
1920EXPORT_SYMBOL(pci_scan_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001921EXPORT_SYMBOL_GPL(pci_scan_child_bus);
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001922
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05001923static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001924{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05001925 const struct pci_dev *a = to_pci_dev(d_a);
1926 const struct pci_dev *b = to_pci_dev(d_b);
1927
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001928 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1929 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1930
1931 if (a->bus->number < b->bus->number) return -1;
1932 else if (a->bus->number > b->bus->number) return 1;
1933
1934 if (a->devfn < b->devfn) return -1;
1935 else if (a->devfn > b->devfn) return 1;
1936
1937 return 0;
1938}
1939
Greg Kroah-Hartman5ff580c2008-02-14 14:56:56 -08001940void __init pci_sort_breadthfirst(void)
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001941{
Greg Kroah-Hartman99178b02008-08-26 11:00:57 -05001942 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
Matt Domsch6b4b78f2006-09-29 15:23:23 -05001943}