Maxime Ripard | d4da2eb | 2012-11-14 20:17:04 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Maxime Ripard |
| 3 | * |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
| 5 | * |
| 6 | * The code contained herein is licensed under the GNU General Public |
| 7 | * License. You may obtain a copy of the GNU General Public License |
| 8 | * Version 2 or later at the following locations: |
| 9 | * |
| 10 | * http://www.opensource.org/licenses/gpl-license.html |
| 11 | * http://www.gnu.org/copyleft/gpl.html |
| 12 | */ |
| 13 | |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 14 | /include/ "skeleton.dtsi" |
Maxime Ripard | d4da2eb | 2012-11-14 20:17:04 +0100 | [diff] [blame] | 15 | |
| 16 | / { |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 17 | interrupt-parent = <&intc>; |
| 18 | |
| 19 | cpus { |
Arnd Bergmann | 8b2efa89 | 2013-06-10 16:48:36 +0200 | [diff] [blame] | 20 | #address-cells = <1>; |
| 21 | #size-cells = <0>; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 22 | cpu@0 { |
Lorenzo Pieralisi | 14c44aa | 2013-04-18 18:41:57 +0100 | [diff] [blame] | 23 | device_type = "cpu"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 24 | compatible = "arm,cortex-a8"; |
Lorenzo Pieralisi | 14c44aa | 2013-04-18 18:41:57 +0100 | [diff] [blame] | 25 | reg = <0x0>; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 26 | }; |
| 27 | }; |
| 28 | |
Maxime Ripard | d4da2eb | 2012-11-14 20:17:04 +0100 | [diff] [blame] | 29 | memory { |
| 30 | reg = <0x40000000 0x20000000>; |
| 31 | }; |
Maxime Ripard | 9e2dcb2 | 2013-01-18 22:30:36 +0100 | [diff] [blame] | 32 | |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 33 | clocks { |
| 34 | #address-cells = <1>; |
| 35 | #size-cells = <1>; |
| 36 | ranges; |
| 37 | |
| 38 | /* |
| 39 | * This is a dummy clock, to be used as placeholder on |
| 40 | * other mux clocks when a specific parent clock is not |
| 41 | * yet implemented. It should be dropped when the driver |
| 42 | * is complete. |
| 43 | */ |
| 44 | dummy: dummy { |
| 45 | #clock-cells = <0>; |
| 46 | compatible = "fixed-clock"; |
| 47 | clock-frequency = <0>; |
| 48 | }; |
| 49 | |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 50 | osc24M: osc24M@01c20050 { |
| 51 | #clock-cells = <0>; |
| 52 | compatible = "allwinner,sun4i-osc-clk"; |
| 53 | reg = <0x01c20050 0x4>; |
Emilio López | 92fd6e0 | 2013-04-09 10:48:04 -0300 | [diff] [blame] | 54 | clock-frequency = <24000000>; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 55 | }; |
| 56 | |
| 57 | osc32k: osc32k { |
| 58 | #clock-cells = <0>; |
| 59 | compatible = "fixed-clock"; |
| 60 | clock-frequency = <32768>; |
| 61 | }; |
| 62 | |
| 63 | pll1: pll1@01c20000 { |
| 64 | #clock-cells = <0>; |
| 65 | compatible = "allwinner,sun4i-pll1-clk"; |
| 66 | reg = <0x01c20000 0x4>; |
| 67 | clocks = <&osc24M>; |
| 68 | }; |
| 69 | |
| 70 | /* dummy is 200M */ |
| 71 | cpu: cpu@01c20054 { |
| 72 | #clock-cells = <0>; |
| 73 | compatible = "allwinner,sun4i-cpu-clk"; |
| 74 | reg = <0x01c20054 0x4>; |
| 75 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; |
| 76 | }; |
| 77 | |
| 78 | axi: axi@01c20054 { |
| 79 | #clock-cells = <0>; |
| 80 | compatible = "allwinner,sun4i-axi-clk"; |
| 81 | reg = <0x01c20054 0x4>; |
| 82 | clocks = <&cpu>; |
| 83 | }; |
| 84 | |
| 85 | axi_gates: axi_gates@01c2005c { |
| 86 | #clock-cells = <1>; |
| 87 | compatible = "allwinner,sun4i-axi-gates-clk"; |
| 88 | reg = <0x01c2005c 0x4>; |
| 89 | clocks = <&axi>; |
| 90 | clock-output-names = "axi_dram"; |
| 91 | }; |
| 92 | |
| 93 | ahb: ahb@01c20054 { |
| 94 | #clock-cells = <0>; |
| 95 | compatible = "allwinner,sun4i-ahb-clk"; |
| 96 | reg = <0x01c20054 0x4>; |
| 97 | clocks = <&axi>; |
| 98 | }; |
| 99 | |
| 100 | ahb_gates: ahb_gates@01c20060 { |
| 101 | #clock-cells = <1>; |
Maxime Ripard | 70be4ee6 | 2013-04-19 22:14:41 +0200 | [diff] [blame] | 102 | compatible = "allwinner,sun5i-a13-ahb-gates-clk"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 103 | reg = <0x01c20060 0x8>; |
| 104 | clocks = <&ahb>; |
Maxime Ripard | 70be4ee6 | 2013-04-19 22:14:41 +0200 | [diff] [blame] | 105 | clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", |
| 106 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", |
| 107 | "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram", |
| 108 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer", |
| 109 | "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be", |
| 110 | "ahb_de_fe", "ahb_iep", "ahb_mali400"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 111 | }; |
| 112 | |
| 113 | apb0: apb0@01c20054 { |
| 114 | #clock-cells = <0>; |
| 115 | compatible = "allwinner,sun4i-apb0-clk"; |
| 116 | reg = <0x01c20054 0x4>; |
| 117 | clocks = <&ahb>; |
| 118 | }; |
| 119 | |
| 120 | apb0_gates: apb0_gates@01c20068 { |
| 121 | #clock-cells = <1>; |
Maxime Ripard | 70be4ee6 | 2013-04-19 22:14:41 +0200 | [diff] [blame] | 122 | compatible = "allwinner,sun5i-a13-apb0-gates-clk"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 123 | reg = <0x01c20068 0x4>; |
| 124 | clocks = <&apb0>; |
Maxime Ripard | 70be4ee6 | 2013-04-19 22:14:41 +0200 | [diff] [blame] | 125 | clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 126 | }; |
| 127 | |
Maxime Ripard | 70be4ee6 | 2013-04-19 22:14:41 +0200 | [diff] [blame] | 128 | /* dummy is pll6 */ |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 129 | apb1_mux: apb1_mux@01c20058 { |
| 130 | #clock-cells = <0>; |
| 131 | compatible = "allwinner,sun4i-apb1-mux-clk"; |
| 132 | reg = <0x01c20058 0x4>; |
| 133 | clocks = <&osc24M>, <&dummy>, <&osc32k>; |
| 134 | }; |
| 135 | |
| 136 | apb1: apb1@01c20058 { |
| 137 | #clock-cells = <0>; |
| 138 | compatible = "allwinner,sun4i-apb1-clk"; |
| 139 | reg = <0x01c20058 0x4>; |
| 140 | clocks = <&apb1_mux>; |
| 141 | }; |
| 142 | |
| 143 | apb1_gates: apb1_gates@01c2006c { |
| 144 | #clock-cells = <1>; |
Maxime Ripard | 70be4ee6 | 2013-04-19 22:14:41 +0200 | [diff] [blame] | 145 | compatible = "allwinner,sun5i-a13-apb1-gates-clk"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 146 | reg = <0x01c2006c 0x4>; |
| 147 | clocks = <&apb1>; |
| 148 | clock-output-names = "apb1_i2c0", "apb1_i2c1", |
Maxime Ripard | 70be4ee6 | 2013-04-19 22:14:41 +0200 | [diff] [blame] | 149 | "apb1_i2c2", "apb1_uart1", "apb1_uart3"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 150 | }; |
| 151 | }; |
| 152 | |
Maxime Ripard | 278fe8b | 2013-08-03 16:07:36 +0200 | [diff] [blame] | 153 | soc@01c00000 { |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 154 | compatible = "simple-bus"; |
| 155 | #address-cells = <1>; |
| 156 | #size-cells = <1>; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 157 | ranges; |
| 158 | |
| 159 | intc: interrupt-controller@01c20400 { |
Maxime Ripard | 6def126 | 2013-03-24 19:20:52 +0100 | [diff] [blame] | 160 | compatible = "allwinner,sun4i-ic"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 161 | reg = <0x01c20400 0x400>; |
| 162 | interrupt-controller; |
| 163 | #interrupt-cells = <1>; |
| 164 | }; |
| 165 | |
Maxime Ripard | e10911e | 2013-01-27 19:26:05 +0100 | [diff] [blame] | 166 | pio: pinctrl@01c20800 { |
Maxime Ripard | 9e2dcb2 | 2013-01-18 22:30:36 +0100 | [diff] [blame] | 167 | compatible = "allwinner,sun5i-a13-pinctrl"; |
| 168 | reg = <0x01c20800 0x400>; |
Maxime Ripard | 39138bc | 2013-04-06 15:00:48 +0200 | [diff] [blame] | 169 | interrupts = <28>; |
Emilio López | 36386d6 | 2013-03-27 18:20:41 -0300 | [diff] [blame] | 170 | clocks = <&apb0_gates 5>; |
Maxime Ripard | e10911e | 2013-01-27 19:26:05 +0100 | [diff] [blame] | 171 | gpio-controller; |
Maxime Ripard | 39138bc | 2013-04-06 15:00:48 +0200 | [diff] [blame] | 172 | interrupt-controller; |
Maxime Ripard | 9e2dcb2 | 2013-01-18 22:30:36 +0100 | [diff] [blame] | 173 | #address-cells = <1>; |
| 174 | #size-cells = <0>; |
Maxime Ripard | e10911e | 2013-01-27 19:26:05 +0100 | [diff] [blame] | 175 | #gpio-cells = <3>; |
Maxime Ripard | 4348cc6 | 2013-01-18 22:30:37 +0100 | [diff] [blame] | 176 | |
| 177 | uart1_pins_a: uart1@0 { |
| 178 | allwinner,pins = "PE10", "PE11"; |
| 179 | allwinner,function = "uart1"; |
| 180 | allwinner,drive = <0>; |
| 181 | allwinner,pull = <0>; |
| 182 | }; |
| 183 | |
| 184 | uart1_pins_b: uart1@1 { |
| 185 | allwinner,pins = "PG3", "PG4"; |
| 186 | allwinner,function = "uart1"; |
| 187 | allwinner,drive = <0>; |
| 188 | allwinner,pull = <0>; |
| 189 | }; |
Maxime Ripard | b4d7c23 | 2013-03-10 13:36:02 +0100 | [diff] [blame] | 190 | |
| 191 | i2c0_pins_a: i2c0@0 { |
| 192 | allwinner,pins = "PB0", "PB1"; |
| 193 | allwinner,function = "i2c0"; |
| 194 | allwinner,drive = <0>; |
| 195 | allwinner,pull = <0>; |
| 196 | }; |
| 197 | |
| 198 | i2c1_pins_a: i2c1@0 { |
| 199 | allwinner,pins = "PB15", "PB16"; |
| 200 | allwinner,function = "i2c1"; |
| 201 | allwinner,drive = <0>; |
| 202 | allwinner,pull = <0>; |
| 203 | }; |
| 204 | |
| 205 | i2c2_pins_a: i2c2@0 { |
| 206 | allwinner,pins = "PB17", "PB18"; |
| 207 | allwinner,function = "i2c2"; |
| 208 | allwinner,drive = <0>; |
| 209 | allwinner,pull = <0>; |
| 210 | }; |
Maxime Ripard | 9e2dcb2 | 2013-01-18 22:30:36 +0100 | [diff] [blame] | 211 | }; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 212 | |
| 213 | timer@01c20c00 { |
Maxime Ripard | b6e1a53 | 2013-03-24 19:00:17 +0100 | [diff] [blame] | 214 | compatible = "allwinner,sun4i-timer"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 215 | reg = <0x01c20c00 0x90>; |
| 216 | interrupts = <22>; |
| 217 | clocks = <&osc24M>; |
| 218 | }; |
| 219 | |
| 220 | wdt: watchdog@01c20c90 { |
Maxime Ripard | 0b19b7c | 2013-03-24 19:32:34 +0100 | [diff] [blame] | 221 | compatible = "allwinner,sun4i-wdt"; |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 222 | reg = <0x01c20c90 0x10>; |
| 223 | }; |
| 224 | |
Oliver Schinagl | 2bad969 | 2013-09-03 12:33:28 +0200 | [diff] [blame] | 225 | sid: eeprom@01c23800 { |
| 226 | compatible = "allwinner,sun4i-sid"; |
| 227 | reg = <0x01c23800 0x10>; |
| 228 | }; |
| 229 | |
Maxime Ripard | 69144e3 | 2013-03-13 20:07:37 +0100 | [diff] [blame] | 230 | uart1: serial@01c28400 { |
| 231 | compatible = "snps,dw-apb-uart"; |
| 232 | reg = <0x01c28400 0x400>; |
| 233 | interrupts = <2>; |
| 234 | reg-shift = <2>; |
| 235 | reg-io-width = <4>; |
| 236 | clocks = <&apb1_gates 17>; |
| 237 | status = "disabled"; |
| 238 | }; |
| 239 | |
| 240 | uart3: serial@01c28c00 { |
| 241 | compatible = "snps,dw-apb-uart"; |
| 242 | reg = <0x01c28c00 0x400>; |
| 243 | interrupts = <4>; |
| 244 | reg-shift = <2>; |
| 245 | reg-io-width = <4>; |
| 246 | clocks = <&apb1_gates 19>; |
| 247 | status = "disabled"; |
| 248 | }; |
Maxime Ripard | f1741fd | 2013-03-10 13:34:36 +0100 | [diff] [blame] | 249 | |
| 250 | i2c0: i2c@01c2ac00 { |
| 251 | compatible = "allwinner,sun4i-i2c"; |
| 252 | reg = <0x01c2ac00 0x400>; |
| 253 | interrupts = <7>; |
| 254 | clocks = <&apb1_gates 0>; |
| 255 | clock-frequency = <100000>; |
| 256 | status = "disabled"; |
| 257 | }; |
| 258 | |
| 259 | i2c1: i2c@01c2b000 { |
| 260 | compatible = "allwinner,sun4i-i2c"; |
| 261 | reg = <0x01c2b000 0x400>; |
| 262 | interrupts = <8>; |
| 263 | clocks = <&apb1_gates 1>; |
| 264 | clock-frequency = <100000>; |
| 265 | status = "disabled"; |
| 266 | }; |
| 267 | |
| 268 | i2c2: i2c@01c2b400 { |
| 269 | compatible = "allwinner,sun4i-i2c"; |
| 270 | reg = <0x01c2b400 0x400>; |
| 271 | interrupts = <9>; |
| 272 | clocks = <&apb1_gates 2>; |
| 273 | clock-frequency = <100000>; |
| 274 | status = "disabled"; |
| 275 | }; |
Maxime Ripard | 9e2dcb2 | 2013-01-18 22:30:36 +0100 | [diff] [blame] | 276 | }; |
Maxime Ripard | d4da2eb | 2012-11-14 20:17:04 +0100 | [diff] [blame] | 277 | }; |