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Tony Lindgren1dbae812005-11-10 14:26:51 +00001/*
2 * linux/arch/arm/mach-omap2/timer-gp.c
3 *
4 * OMAP2 GP timer support.
5 *
Kevin Hilman5a3a3882007-11-12 23:24:02 -08006 * Update to use new clocksource/clockevent layers
7 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 *
10 * Original driver:
Tony Lindgren1dbae812005-11-10 14:26:51 +000011 * Copyright (C) 2005 Nokia Corporation
12 * Author: Paul Mundt <paul.mundt@nokia.com>
Jan Engelhardt96de0e22007-10-19 23:21:04 +020013 * Juha Yrjölä <juha.yrjola@nokia.com>
Timo Teras77900a22006-06-26 16:16:12 -070014 * OMAP Dual-mode timer framework support by Timo Teras
Tony Lindgren1dbae812005-11-10 14:26:51 +000015 *
16 * Some parts based off of TI's 24xx code:
17 *
18 * Copyright (C) 2004 Texas Instruments, Inc.
19 *
20 * Roughly modelled after the OMAP1 MPU timer code.
21 *
22 * This file is subject to the terms and conditions of the GNU General Public
23 * License. See the file "COPYING" in the main directory of this archive
24 * for more details.
25 */
26#include <linux/init.h>
27#include <linux/time.h>
28#include <linux/interrupt.h>
29#include <linux/err.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000030#include <linux/clk.h>
Timo Teras77900a22006-06-26 16:16:12 -070031#include <linux/delay.h>
Dirk Behmee6687292006-12-06 17:14:00 -080032#include <linux/irq.h>
Kevin Hilman5a3a3882007-11-12 23:24:02 -080033#include <linux/clocksource.h>
34#include <linux/clockchips.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000035
Tony Lindgren1dbae812005-11-10 14:26:51 +000036#include <asm/mach/time.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010037#include <mach/dmtimer.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000038
Timo Teras77900a22006-06-26 16:16:12 -070039static struct omap_dm_timer *gptimer;
Kevin Hilman5a3a3882007-11-12 23:24:02 -080040static struct clock_event_device clockevent_gpt;
Tony Lindgren1dbae812005-11-10 14:26:51 +000041
Linus Torvalds0cd61b62006-10-06 10:53:39 -070042static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
Tony Lindgren1dbae812005-11-10 14:26:51 +000043{
Kevin Hilman5a3a3882007-11-12 23:24:02 -080044 struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
45 struct clock_event_device *evt = &clockevent_gpt;
Tony Lindgren1dbae812005-11-10 14:26:51 +000046
Kevin Hilman5a3a3882007-11-12 23:24:02 -080047 omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
48
49 evt->event_handler(evt);
Tony Lindgren1dbae812005-11-10 14:26:51 +000050 return IRQ_HANDLED;
51}
52
53static struct irqaction omap2_gp_timer_irq = {
54 .name = "gp timer",
Bernhard Walleb30faba2007-05-08 00:35:39 -070055 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
Tony Lindgren1dbae812005-11-10 14:26:51 +000056 .handler = omap2_gp_timer_interrupt,
57};
58
Kevin Hilman5a3a3882007-11-12 23:24:02 -080059static int omap2_gp_timer_set_next_event(unsigned long cycles,
60 struct clock_event_device *evt)
Tony Lindgren1dbae812005-11-10 14:26:51 +000061{
Richard Woodruff3fddd092008-07-03 12:24:30 +030062 omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles);
Tony Lindgren1dbae812005-11-10 14:26:51 +000063
Kevin Hilman5a3a3882007-11-12 23:24:02 -080064 return 0;
65}
66
67static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
68 struct clock_event_device *evt)
69{
70 u32 period;
71
72 omap_dm_timer_stop(gptimer);
73
74 switch (mode) {
75 case CLOCK_EVT_MODE_PERIODIC:
76 period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
77 period -= 1;
78
Richard Woodruff3fddd092008-07-03 12:24:30 +030079 omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
Kevin Hilman5a3a3882007-11-12 23:24:02 -080080 break;
81 case CLOCK_EVT_MODE_ONESHOT:
82 break;
83 case CLOCK_EVT_MODE_UNUSED:
84 case CLOCK_EVT_MODE_SHUTDOWN:
85 case CLOCK_EVT_MODE_RESUME:
86 break;
87 }
88}
89
90static struct clock_event_device clockevent_gpt = {
91 .name = "gp timer",
92 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
93 .shift = 32,
94 .set_next_event = omap2_gp_timer_set_next_event,
95 .set_mode = omap2_gp_timer_set_mode,
96};
97
98static void __init omap2_gp_clockevent_init(void)
99{
100 u32 tick_rate;
101
Timo Terase32f7ec2006-06-26 16:16:13 -0700102 gptimer = omap_dm_timer_request_specific(1);
Timo Teras77900a22006-06-26 16:16:12 -0700103 BUG_ON(gptimer == NULL);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000104
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800105#if defined(CONFIG_OMAP_32K_TIMER)
106 omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
107#else
Timo Teras77900a22006-06-26 16:16:12 -0700108 omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800109#endif
110 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
Tony Lindgren1dbae812005-11-10 14:26:51 +0000111
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800112 omap2_gp_timer_irq.dev_id = (void *)gptimer;
Timo Teras77900a22006-06-26 16:16:12 -0700113 setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800114 omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
115
116 clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
117 clockevent_gpt.shift);
118 clockevent_gpt.max_delta_ns =
119 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
120 clockevent_gpt.min_delta_ns =
121 clockevent_delta2ns(1, &clockevent_gpt);
122
Rusty Russell320ab2b2008-12-13 21:20:26 +1030123 clockevent_gpt.cpumask = cpumask_of(0);
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800124 clockevents_register_device(&clockevent_gpt);
125}
126
127#ifdef CONFIG_OMAP_32K_TIMER
128/*
129 * When 32k-timer is enabled, don't use GPTimer for clocksource
130 * instead, just leave default clocksource which uses the 32k
131 * sync counter. See clocksource setup in see plat-omap/common.c.
132 */
133
134static inline void __init omap2_gp_clocksource_init(void) {}
135#else
136/*
137 * clocksource
138 */
139static struct omap_dm_timer *gpt_clocksource;
140static cycle_t clocksource_read_cycles(void)
141{
142 return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
143}
144
145static struct clocksource clocksource_gpt = {
146 .name = "gp timer",
147 .rating = 300,
148 .read = clocksource_read_cycles,
149 .mask = CLOCKSOURCE_MASK(32),
150 .shift = 24,
151 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
152};
153
154/* Setup free-running counter for clocksource */
155static void __init omap2_gp_clocksource_init(void)
156{
157 static struct omap_dm_timer *gpt;
158 u32 tick_rate, tick_period;
159 static char err1[] __initdata = KERN_ERR
160 "%s: failed to request dm-timer\n";
161 static char err2[] __initdata = KERN_ERR
162 "%s: can't register clocksource!\n";
163
164 gpt = omap_dm_timer_request();
165 if (!gpt)
166 printk(err1, clocksource_gpt.name);
167 gpt_clocksource = gpt;
168
169 omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
170 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
171 tick_period = (tick_rate / HZ) - 1;
172
Richard Woodruff3fddd092008-07-03 12:24:30 +0300173 omap_dm_timer_set_load_start(gpt, 1, 0);
Kevin Hilman5a3a3882007-11-12 23:24:02 -0800174
175 clocksource_gpt.mult =
176 clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
177 if (clocksource_register(&clocksource_gpt))
178 printk(err2, clocksource_gpt.name);
179}
180#endif
181
182static void __init omap2_gp_timer_init(void)
183{
184 omap_dm_timer_init();
185
186 omap2_gp_clockevent_init();
187 omap2_gp_clocksource_init();
Tony Lindgren1dbae812005-11-10 14:26:51 +0000188}
189
190struct sys_timer omap_timer = {
191 .init = omap2_gp_timer_init,
192};