Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2 | * Performance events x86 architecture code |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 3 | * |
Ingo Molnar | 9814451 | 2009-04-29 14:52:50 +0200 | [diff] [blame] | 4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
| 5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar |
| 6 | * Copyright (C) 2009 Jaswinder Singh Rajput |
| 7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter |
| 8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 11 | * |
| 12 | * For licencing details see kernel-base/COPYING |
| 13 | */ |
| 14 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 15 | #include <linux/perf_event.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 16 | #include <linux/capability.h> |
| 17 | #include <linux/notifier.h> |
| 18 | #include <linux/hardirq.h> |
| 19 | #include <linux/kprobes.h> |
Thomas Gleixner | 4ac1329 | 2008-12-09 21:43:39 +0100 | [diff] [blame] | 20 | #include <linux/module.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 21 | #include <linux/kdebug.h> |
| 22 | #include <linux/sched.h> |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 23 | #include <linux/uaccess.h> |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 24 | #include <linux/highmem.h> |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 25 | #include <linux/cpu.h> |
Peter Zijlstra | 272d30b | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 26 | #include <linux/bitops.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 27 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 28 | #include <asm/apic.h> |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 29 | #include <asm/stacktrace.h> |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 30 | #include <asm/nmi.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 31 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 32 | static u64 perf_event_mask __read_mostly; |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 33 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 34 | /* The maximal number of PEBS events: */ |
| 35 | #define MAX_PEBS_EVENTS 4 |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 36 | |
| 37 | /* The size of a BTS record in bytes: */ |
| 38 | #define BTS_RECORD_SIZE 24 |
| 39 | |
| 40 | /* The size of a per-cpu BTS buffer in bytes: */ |
Markus Metzger | 5622f29 | 2009-09-15 13:00:23 +0200 | [diff] [blame] | 41 | #define BTS_BUFFER_SIZE (BTS_RECORD_SIZE * 2048) |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 42 | |
| 43 | /* The BTS overflow threshold in bytes from the end of the buffer: */ |
Markus Metzger | 5622f29 | 2009-09-15 13:00:23 +0200 | [diff] [blame] | 44 | #define BTS_OVFL_TH (BTS_RECORD_SIZE * 128) |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 45 | |
| 46 | |
| 47 | /* |
| 48 | * Bits in the debugctlmsr controlling branch tracing. |
| 49 | */ |
| 50 | #define X86_DEBUGCTL_TR (1 << 6) |
| 51 | #define X86_DEBUGCTL_BTS (1 << 7) |
| 52 | #define X86_DEBUGCTL_BTINT (1 << 8) |
| 53 | #define X86_DEBUGCTL_BTS_OFF_OS (1 << 9) |
| 54 | #define X86_DEBUGCTL_BTS_OFF_USR (1 << 10) |
| 55 | |
| 56 | /* |
| 57 | * A debug store configuration. |
| 58 | * |
| 59 | * We only support architectures that use 64bit fields. |
| 60 | */ |
| 61 | struct debug_store { |
| 62 | u64 bts_buffer_base; |
| 63 | u64 bts_index; |
| 64 | u64 bts_absolute_maximum; |
| 65 | u64 bts_interrupt_threshold; |
| 66 | u64 pebs_buffer_base; |
| 67 | u64 pebs_index; |
| 68 | u64 pebs_absolute_maximum; |
| 69 | u64 pebs_interrupt_threshold; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 70 | u64 pebs_event_reset[MAX_PEBS_EVENTS]; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 71 | }; |
| 72 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 73 | struct event_constraint { |
Peter Zijlstra | c91e0f5 | 2010-01-22 15:25:59 +0100 | [diff] [blame] | 74 | union { |
| 75 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
| 76 | u64 idxmsk64[1]; |
| 77 | }; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 78 | int code; |
| 79 | int cmask; |
Peter Zijlstra | 272d30b | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 80 | int weight; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 81 | }; |
| 82 | |
Stephane Eranian | 38331f6 | 2010-02-08 17:17:01 +0200 | [diff] [blame] | 83 | struct amd_nb { |
| 84 | int nb_id; /* NorthBridge id */ |
| 85 | int refcnt; /* reference count */ |
| 86 | struct perf_event *owners[X86_PMC_IDX_MAX]; |
| 87 | struct event_constraint event_constraints[X86_PMC_IDX_MAX]; |
| 88 | }; |
| 89 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 90 | struct cpu_hw_events { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 91 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 92 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
Mike Galbraith | 4b39fd9 | 2009-01-23 14:36:16 +0100 | [diff] [blame] | 93 | unsigned long interrupts; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 94 | int enabled; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 95 | struct debug_store *ds; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 96 | |
| 97 | int n_events; |
| 98 | int n_added; |
| 99 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 100 | u64 tags[X86_PMC_IDX_MAX]; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 101 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
Stephane Eranian | 38331f6 | 2010-02-08 17:17:01 +0200 | [diff] [blame] | 102 | struct amd_nb *amd_nb; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 103 | }; |
| 104 | |
Peter Zijlstra | fce877e | 2010-01-29 13:25:12 +0100 | [diff] [blame] | 105 | #define __EVENT_CONSTRAINT(c, n, m, w) {\ |
Peter Zijlstra | c91e0f5 | 2010-01-22 15:25:59 +0100 | [diff] [blame] | 106 | { .idxmsk64[0] = (n) }, \ |
| 107 | .code = (c), \ |
| 108 | .cmask = (m), \ |
Peter Zijlstra | fce877e | 2010-01-29 13:25:12 +0100 | [diff] [blame] | 109 | .weight = (w), \ |
Peter Zijlstra | c91e0f5 | 2010-01-22 15:25:59 +0100 | [diff] [blame] | 110 | } |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 111 | |
Peter Zijlstra | fce877e | 2010-01-29 13:25:12 +0100 | [diff] [blame] | 112 | #define EVENT_CONSTRAINT(c, n, m) \ |
| 113 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n)) |
| 114 | |
Peter Zijlstra | ed8777f | 2010-01-27 23:07:46 +0100 | [diff] [blame] | 115 | #define INTEL_EVENT_CONSTRAINT(c, n) \ |
| 116 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK) |
Peter Zijlstra | 8433be1 | 2010-01-22 15:38:26 +0100 | [diff] [blame] | 117 | |
Peter Zijlstra | ed8777f | 2010-01-27 23:07:46 +0100 | [diff] [blame] | 118 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
| 119 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_FIXED_MASK) |
Peter Zijlstra | 8433be1 | 2010-01-22 15:38:26 +0100 | [diff] [blame] | 120 | |
Peter Zijlstra | ed8777f | 2010-01-27 23:07:46 +0100 | [diff] [blame] | 121 | #define EVENT_CONSTRAINT_END \ |
| 122 | EVENT_CONSTRAINT(0, 0, 0) |
| 123 | |
| 124 | #define for_each_event_constraint(e, c) \ |
| 125 | for ((e) = (c); (e)->cmask; (e)++) |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 126 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 127 | /* |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 128 | * struct x86_pmu - generic x86 pmu |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 129 | */ |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 130 | struct x86_pmu { |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 131 | const char *name; |
| 132 | int version; |
Yong Wang | a328810 | 2009-06-03 13:12:55 +0800 | [diff] [blame] | 133 | int (*handle_irq)(struct pt_regs *); |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 134 | void (*disable_all)(void); |
| 135 | void (*enable_all)(void); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 136 | void (*enable)(struct hw_perf_event *, int); |
| 137 | void (*disable)(struct hw_perf_event *, int); |
Jaswinder Singh Rajput | 169e41e | 2009-02-28 18:37:49 +0530 | [diff] [blame] | 138 | unsigned eventsel; |
| 139 | unsigned perfctr; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 140 | u64 (*event_map)(int); |
| 141 | u64 (*raw_event)(u64); |
Jaswinder Singh Rajput | 169e41e | 2009-02-28 18:37:49 +0530 | [diff] [blame] | 142 | int max_events; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 143 | int num_events; |
| 144 | int num_events_fixed; |
| 145 | int event_bits; |
| 146 | u64 event_mask; |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 147 | int apic; |
Robert Richter | c619b8f | 2009-04-29 12:47:23 +0200 | [diff] [blame] | 148 | u64 max_period; |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 149 | u64 intel_ctrl; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 150 | void (*enable_bts)(u64 config); |
| 151 | void (*disable_bts)(void); |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 152 | |
| 153 | struct event_constraint * |
| 154 | (*get_event_constraints)(struct cpu_hw_events *cpuc, |
| 155 | struct perf_event *event); |
| 156 | |
Peter Zijlstra | c91e0f5 | 2010-01-22 15:25:59 +0100 | [diff] [blame] | 157 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, |
| 158 | struct perf_event *event); |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 159 | struct event_constraint *event_constraints; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 160 | }; |
| 161 | |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 162 | static struct x86_pmu x86_pmu __read_mostly; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 163 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 164 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 165 | .enabled = 1, |
| 166 | }; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 167 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 168 | static int x86_perf_event_set_period(struct perf_event *event, |
| 169 | struct hw_perf_event *hwc, int idx); |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 170 | |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 171 | /* |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 172 | * Generalized hw caching related hw_event table, filled |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 173 | * in on a per model basis. A value of 0 means |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 174 | * 'not supported', -1 means 'hw_event makes no sense on |
| 175 | * this CPU', any other value means the raw hw_event |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 176 | * ID. |
| 177 | */ |
| 178 | |
| 179 | #define C(x) PERF_COUNT_HW_CACHE_##x |
| 180 | |
| 181 | static u64 __read_mostly hw_cache_event_ids |
| 182 | [PERF_COUNT_HW_CACHE_MAX] |
| 183 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 184 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; |
| 185 | |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 186 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 187 | * Propagate event elapsed time into the generic event. |
| 188 | * Can only be executed on the CPU where the event is active. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 189 | * Returns the delta events processed. |
| 190 | */ |
Robert Richter | 4b7bfd0 | 2009-04-29 12:47:22 +0200 | [diff] [blame] | 191 | static u64 |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 192 | x86_perf_event_update(struct perf_event *event, |
| 193 | struct hw_perf_event *hwc, int idx) |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 194 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 195 | int shift = 64 - x86_pmu.event_bits; |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 196 | u64 prev_raw_count, new_raw_count; |
| 197 | s64 delta; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 198 | |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 199 | if (idx == X86_PMC_IDX_FIXED_BTS) |
| 200 | return 0; |
| 201 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 202 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 203 | * Careful: an NMI might modify the previous event value. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 204 | * |
| 205 | * Our tactic to handle this is to first atomically read and |
| 206 | * exchange a new raw count - then add that new-prev delta |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 207 | * count to the generic event atomically: |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 208 | */ |
| 209 | again: |
| 210 | prev_raw_count = atomic64_read(&hwc->prev_count); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 211 | rdmsrl(hwc->event_base + idx, new_raw_count); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 212 | |
| 213 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, |
| 214 | new_raw_count) != prev_raw_count) |
| 215 | goto again; |
| 216 | |
| 217 | /* |
| 218 | * Now we have the new raw value and have updated the prev |
| 219 | * timestamp already. We can now calculate the elapsed delta |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 220 | * (event-)time and add that to the generic event. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 221 | * |
| 222 | * Careful, not all hw sign-extends above the physical width |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 223 | * of the count. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 224 | */ |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 225 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
| 226 | delta >>= shift; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 227 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 228 | atomic64_add(delta, &event->count); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 229 | atomic64_sub(delta, &hwc->period_left); |
Robert Richter | 4b7bfd0 | 2009-04-29 12:47:22 +0200 | [diff] [blame] | 230 | |
| 231 | return new_raw_count; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 232 | } |
| 233 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 234 | static atomic_t active_events; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 235 | static DEFINE_MUTEX(pmc_reserve_mutex); |
| 236 | |
| 237 | static bool reserve_pmc_hardware(void) |
| 238 | { |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 239 | #ifdef CONFIG_X86_LOCAL_APIC |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 240 | int i; |
| 241 | |
| 242 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 243 | disable_lapic_nmi_watchdog(); |
| 244 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 245 | for (i = 0; i < x86_pmu.num_events; i++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 246 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 247 | goto perfctr_fail; |
| 248 | } |
| 249 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 250 | for (i = 0; i < x86_pmu.num_events; i++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 251 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 252 | goto eventsel_fail; |
| 253 | } |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 254 | #endif |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 255 | |
| 256 | return true; |
| 257 | |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 258 | #ifdef CONFIG_X86_LOCAL_APIC |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 259 | eventsel_fail: |
| 260 | for (i--; i >= 0; i--) |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 261 | release_evntsel_nmi(x86_pmu.eventsel + i); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 262 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 263 | i = x86_pmu.num_events; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 264 | |
| 265 | perfctr_fail: |
| 266 | for (i--; i >= 0; i--) |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 267 | release_perfctr_nmi(x86_pmu.perfctr + i); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 268 | |
| 269 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 270 | enable_lapic_nmi_watchdog(); |
| 271 | |
| 272 | return false; |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 273 | #endif |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 274 | } |
| 275 | |
| 276 | static void release_pmc_hardware(void) |
| 277 | { |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 278 | #ifdef CONFIG_X86_LOCAL_APIC |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 279 | int i; |
| 280 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 281 | for (i = 0; i < x86_pmu.num_events; i++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 282 | release_perfctr_nmi(x86_pmu.perfctr + i); |
| 283 | release_evntsel_nmi(x86_pmu.eventsel + i); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 284 | } |
| 285 | |
| 286 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 287 | enable_lapic_nmi_watchdog(); |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 288 | #endif |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 289 | } |
| 290 | |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 291 | static inline bool bts_available(void) |
| 292 | { |
| 293 | return x86_pmu.enable_bts != NULL; |
| 294 | } |
| 295 | |
| 296 | static inline void init_debug_store_on_cpu(int cpu) |
| 297 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 298 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 299 | |
| 300 | if (!ds) |
| 301 | return; |
| 302 | |
| 303 | wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, |
markus.t.metzger@intel.com | 596da17 | 2009-09-02 16:04:47 +0200 | [diff] [blame] | 304 | (u32)((u64)(unsigned long)ds), |
| 305 | (u32)((u64)(unsigned long)ds >> 32)); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 306 | } |
| 307 | |
| 308 | static inline void fini_debug_store_on_cpu(int cpu) |
| 309 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 310 | if (!per_cpu(cpu_hw_events, cpu).ds) |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 311 | return; |
| 312 | |
| 313 | wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0); |
| 314 | } |
| 315 | |
| 316 | static void release_bts_hardware(void) |
| 317 | { |
| 318 | int cpu; |
| 319 | |
| 320 | if (!bts_available()) |
| 321 | return; |
| 322 | |
| 323 | get_online_cpus(); |
| 324 | |
| 325 | for_each_online_cpu(cpu) |
| 326 | fini_debug_store_on_cpu(cpu); |
| 327 | |
| 328 | for_each_possible_cpu(cpu) { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 329 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 330 | |
| 331 | if (!ds) |
| 332 | continue; |
| 333 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 334 | per_cpu(cpu_hw_events, cpu).ds = NULL; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 335 | |
markus.t.metzger@intel.com | 596da17 | 2009-09-02 16:04:47 +0200 | [diff] [blame] | 336 | kfree((void *)(unsigned long)ds->bts_buffer_base); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 337 | kfree(ds); |
| 338 | } |
| 339 | |
| 340 | put_online_cpus(); |
| 341 | } |
| 342 | |
| 343 | static int reserve_bts_hardware(void) |
| 344 | { |
| 345 | int cpu, err = 0; |
| 346 | |
| 347 | if (!bts_available()) |
markus.t.metzger@intel.com | 747b50a | 2009-09-02 16:04:46 +0200 | [diff] [blame] | 348 | return 0; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 349 | |
| 350 | get_online_cpus(); |
| 351 | |
| 352 | for_each_possible_cpu(cpu) { |
| 353 | struct debug_store *ds; |
| 354 | void *buffer; |
| 355 | |
| 356 | err = -ENOMEM; |
| 357 | buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL); |
| 358 | if (unlikely(!buffer)) |
| 359 | break; |
| 360 | |
| 361 | ds = kzalloc(sizeof(*ds), GFP_KERNEL); |
| 362 | if (unlikely(!ds)) { |
| 363 | kfree(buffer); |
| 364 | break; |
| 365 | } |
| 366 | |
markus.t.metzger@intel.com | 596da17 | 2009-09-02 16:04:47 +0200 | [diff] [blame] | 367 | ds->bts_buffer_base = (u64)(unsigned long)buffer; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 368 | ds->bts_index = ds->bts_buffer_base; |
| 369 | ds->bts_absolute_maximum = |
| 370 | ds->bts_buffer_base + BTS_BUFFER_SIZE; |
| 371 | ds->bts_interrupt_threshold = |
| 372 | ds->bts_absolute_maximum - BTS_OVFL_TH; |
| 373 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 374 | per_cpu(cpu_hw_events, cpu).ds = ds; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 375 | err = 0; |
| 376 | } |
| 377 | |
| 378 | if (err) |
| 379 | release_bts_hardware(); |
| 380 | else { |
| 381 | for_each_online_cpu(cpu) |
| 382 | init_debug_store_on_cpu(cpu); |
| 383 | } |
| 384 | |
| 385 | put_online_cpus(); |
| 386 | |
| 387 | return err; |
| 388 | } |
| 389 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 390 | static void hw_perf_event_destroy(struct perf_event *event) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 391 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 392 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 393 | release_pmc_hardware(); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 394 | release_bts_hardware(); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 395 | mutex_unlock(&pmc_reserve_mutex); |
| 396 | } |
| 397 | } |
| 398 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 399 | static inline int x86_pmu_initialized(void) |
| 400 | { |
| 401 | return x86_pmu.handle_irq != NULL; |
| 402 | } |
| 403 | |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 404 | static inline int |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 405 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr) |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 406 | { |
| 407 | unsigned int cache_type, cache_op, cache_result; |
| 408 | u64 config, val; |
| 409 | |
| 410 | config = attr->config; |
| 411 | |
| 412 | cache_type = (config >> 0) & 0xff; |
| 413 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) |
| 414 | return -EINVAL; |
| 415 | |
| 416 | cache_op = (config >> 8) & 0xff; |
| 417 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) |
| 418 | return -EINVAL; |
| 419 | |
| 420 | cache_result = (config >> 16) & 0xff; |
| 421 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) |
| 422 | return -EINVAL; |
| 423 | |
| 424 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; |
| 425 | |
| 426 | if (val == 0) |
| 427 | return -ENOENT; |
| 428 | |
| 429 | if (val == -1) |
| 430 | return -EINVAL; |
| 431 | |
| 432 | hwc->config |= val; |
| 433 | |
| 434 | return 0; |
| 435 | } |
| 436 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 437 | /* |
Peter Zijlstra | 0d48696 | 2009-06-02 19:22:16 +0200 | [diff] [blame] | 438 | * Setup the hardware configuration for a given attr_type |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 439 | */ |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 440 | static int __hw_perf_event_init(struct perf_event *event) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 441 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 442 | struct perf_event_attr *attr = &event->attr; |
| 443 | struct hw_perf_event *hwc = &event->hw; |
Peter Zijlstra | 9c74fb5 | 2009-07-08 10:21:41 +0200 | [diff] [blame] | 444 | u64 config; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 445 | int err; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 446 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 447 | if (!x86_pmu_initialized()) |
| 448 | return -ENODEV; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 449 | |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 450 | err = 0; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 451 | if (!atomic_inc_not_zero(&active_events)) { |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 452 | mutex_lock(&pmc_reserve_mutex); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 453 | if (atomic_read(&active_events) == 0) { |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 454 | if (!reserve_pmc_hardware()) |
| 455 | err = -EBUSY; |
| 456 | else |
markus.t.metzger@intel.com | 747b50a | 2009-09-02 16:04:46 +0200 | [diff] [blame] | 457 | err = reserve_bts_hardware(); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 458 | } |
| 459 | if (!err) |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 460 | atomic_inc(&active_events); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 461 | mutex_unlock(&pmc_reserve_mutex); |
| 462 | } |
| 463 | if (err) |
| 464 | return err; |
| 465 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 466 | event->destroy = hw_perf_event_destroy; |
Peter Zijlstra | a1792cdac | 2009-09-09 10:04:47 +0200 | [diff] [blame] | 467 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 468 | /* |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 469 | * Generate PMC IRQs: |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 470 | * (keep 'enabled' bit clear for now) |
| 471 | */ |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 472 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 473 | |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 474 | hwc->idx = -1; |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 475 | hwc->last_cpu = -1; |
| 476 | hwc->last_tag = ~0ULL; |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 477 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 478 | /* |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 479 | * Count user and OS events unless requested not to. |
| 480 | */ |
Peter Zijlstra | 0d48696 | 2009-06-02 19:22:16 +0200 | [diff] [blame] | 481 | if (!attr->exclude_user) |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 482 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; |
Peter Zijlstra | 0d48696 | 2009-06-02 19:22:16 +0200 | [diff] [blame] | 483 | if (!attr->exclude_kernel) |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 484 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; |
| 485 | |
Peter Zijlstra | bd2b5b1 | 2009-06-10 13:40:57 +0200 | [diff] [blame] | 486 | if (!hwc->sample_period) { |
Peter Zijlstra | b23f332 | 2009-06-02 15:13:03 +0200 | [diff] [blame] | 487 | hwc->sample_period = x86_pmu.max_period; |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 488 | hwc->last_period = hwc->sample_period; |
Peter Zijlstra | bd2b5b1 | 2009-06-10 13:40:57 +0200 | [diff] [blame] | 489 | atomic64_set(&hwc->period_left, hwc->sample_period); |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 490 | } else { |
| 491 | /* |
| 492 | * If we have a PMU initialized but no APIC |
| 493 | * interrupts, we cannot sample hardware |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 494 | * events (user-space has to fall back and |
| 495 | * sample via a hrtimer based software event): |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 496 | */ |
| 497 | if (!x86_pmu.apic) |
| 498 | return -EOPNOTSUPP; |
Peter Zijlstra | bd2b5b1 | 2009-06-10 13:40:57 +0200 | [diff] [blame] | 499 | } |
Ingo Molnar | d2517a4 | 2009-05-17 10:04:45 +0200 | [diff] [blame] | 500 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 501 | /* |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 502 | * Raw hw_event type provide the config in the hw_event structure |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 503 | */ |
Ingo Molnar | a21ca2c | 2009-06-06 09:58:57 +0200 | [diff] [blame] | 504 | if (attr->type == PERF_TYPE_RAW) { |
| 505 | hwc->config |= x86_pmu.raw_event(attr->config); |
Peter Zijlstra | 320ebf0 | 2010-03-02 12:35:37 +0100 | [diff] [blame^] | 506 | if ((hwc->config & ARCH_PERFMON_EVENTSEL_ANY) && |
| 507 | perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN)) |
| 508 | return -EACCES; |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 509 | return 0; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 510 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 511 | |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 512 | if (attr->type == PERF_TYPE_HW_CACHE) |
| 513 | return set_ext_hw_attr(hwc, attr); |
| 514 | |
| 515 | if (attr->config >= x86_pmu.max_events) |
| 516 | return -EINVAL; |
Peter Zijlstra | 9c74fb5 | 2009-07-08 10:21:41 +0200 | [diff] [blame] | 517 | |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 518 | /* |
| 519 | * The generic map: |
| 520 | */ |
Peter Zijlstra | 9c74fb5 | 2009-07-08 10:21:41 +0200 | [diff] [blame] | 521 | config = x86_pmu.event_map(attr->config); |
| 522 | |
| 523 | if (config == 0) |
| 524 | return -ENOENT; |
| 525 | |
| 526 | if (config == -1LL) |
| 527 | return -EINVAL; |
| 528 | |
markus.t.metzger@intel.com | 747b50a | 2009-09-02 16:04:46 +0200 | [diff] [blame] | 529 | /* |
| 530 | * Branch tracing: |
| 531 | */ |
| 532 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && |
markus.t.metzger@intel.com | 1653192 | 2009-09-02 16:04:48 +0200 | [diff] [blame] | 533 | (hwc->sample_period == 1)) { |
| 534 | /* BTS is not supported by this architecture. */ |
| 535 | if (!bts_available()) |
| 536 | return -EOPNOTSUPP; |
| 537 | |
| 538 | /* BTS is currently only allowed for user-mode. */ |
| 539 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
| 540 | return -EOPNOTSUPP; |
| 541 | } |
markus.t.metzger@intel.com | 747b50a | 2009-09-02 16:04:46 +0200 | [diff] [blame] | 542 | |
Peter Zijlstra | 9c74fb5 | 2009-07-08 10:21:41 +0200 | [diff] [blame] | 543 | hwc->config |= config; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 544 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 545 | return 0; |
| 546 | } |
| 547 | |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 548 | static void x86_pmu_disable_all(void) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 549 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 550 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 551 | int idx; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 552 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 553 | for (idx = 0; idx < x86_pmu.num_events; idx++) { |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 554 | u64 val; |
| 555 | |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 556 | if (!test_bit(idx, cpuc->active_mask)) |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 557 | continue; |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 558 | rdmsrl(x86_pmu.eventsel + idx, val); |
Robert Richter | bb1165d | 2010-03-01 14:21:23 +0100 | [diff] [blame] | 559 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 560 | continue; |
Robert Richter | bb1165d | 2010-03-01 14:21:23 +0100 | [diff] [blame] | 561 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 562 | wrmsrl(x86_pmu.eventsel + idx, val); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 563 | } |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 564 | } |
| 565 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 566 | void hw_perf_disable(void) |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 567 | { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 568 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 569 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 570 | if (!x86_pmu_initialized()) |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 571 | return; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 572 | |
Peter Zijlstra | 1a6e21f | 2010-01-27 23:07:47 +0100 | [diff] [blame] | 573 | if (!cpuc->enabled) |
| 574 | return; |
| 575 | |
| 576 | cpuc->n_added = 0; |
| 577 | cpuc->enabled = 0; |
| 578 | barrier(); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 579 | |
| 580 | x86_pmu.disable_all(); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 581 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 582 | |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 583 | static void x86_pmu_enable_all(void) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 584 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 585 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 586 | int idx; |
| 587 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 588 | for (idx = 0; idx < x86_pmu.num_events; idx++) { |
| 589 | struct perf_event *event = cpuc->events[idx]; |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 590 | u64 val; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 591 | |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 592 | if (!test_bit(idx, cpuc->active_mask)) |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 593 | continue; |
Peter Zijlstra | 984b838 | 2009-07-10 09:59:56 +0200 | [diff] [blame] | 594 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 595 | val = event->hw.config; |
Robert Richter | bb1165d | 2010-03-01 14:21:23 +0100 | [diff] [blame] | 596 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 597 | wrmsrl(x86_pmu.eventsel + idx, val); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 598 | } |
| 599 | } |
| 600 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 601 | static const struct pmu pmu; |
| 602 | |
| 603 | static inline int is_x86_event(struct perf_event *event) |
| 604 | { |
| 605 | return event->pmu == &pmu; |
| 606 | } |
| 607 | |
| 608 | static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
| 609 | { |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 610 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 611 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
Peter Zijlstra | c933c1a | 2010-01-22 16:40:12 +0100 | [diff] [blame] | 612 | int i, j, w, wmax, num = 0; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 613 | struct hw_perf_event *hwc; |
| 614 | |
| 615 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); |
| 616 | |
| 617 | for (i = 0; i < n; i++) { |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 618 | constraints[i] = |
| 619 | x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 620 | } |
| 621 | |
| 622 | /* |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 623 | * fastpath, try to reuse previous register |
| 624 | */ |
Peter Zijlstra | c933c1a | 2010-01-22 16:40:12 +0100 | [diff] [blame] | 625 | for (i = 0; i < n; i++) { |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 626 | hwc = &cpuc->event_list[i]->hw; |
Peter Zijlstra | 81269a0 | 2010-01-22 14:55:22 +0100 | [diff] [blame] | 627 | c = constraints[i]; |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 628 | |
| 629 | /* never assigned */ |
| 630 | if (hwc->idx == -1) |
| 631 | break; |
| 632 | |
| 633 | /* constraint still honored */ |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 634 | if (!test_bit(hwc->idx, c->idxmsk)) |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 635 | break; |
| 636 | |
| 637 | /* not already used */ |
| 638 | if (test_bit(hwc->idx, used_mask)) |
| 639 | break; |
| 640 | |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 641 | set_bit(hwc->idx, used_mask); |
| 642 | if (assign) |
| 643 | assign[i] = hwc->idx; |
| 644 | } |
Peter Zijlstra | c933c1a | 2010-01-22 16:40:12 +0100 | [diff] [blame] | 645 | if (i == n) |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 646 | goto done; |
| 647 | |
| 648 | /* |
| 649 | * begin slow path |
| 650 | */ |
| 651 | |
| 652 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); |
| 653 | |
| 654 | /* |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 655 | * weight = number of possible counters |
| 656 | * |
| 657 | * 1 = most constrained, only works on one counter |
| 658 | * wmax = least constrained, works on any counter |
| 659 | * |
| 660 | * assign events to counters starting with most |
| 661 | * constrained events. |
| 662 | */ |
| 663 | wmax = x86_pmu.num_events; |
| 664 | |
| 665 | /* |
| 666 | * when fixed event counters are present, |
| 667 | * wmax is incremented by 1 to account |
| 668 | * for one more choice |
| 669 | */ |
| 670 | if (x86_pmu.num_events_fixed) |
| 671 | wmax++; |
| 672 | |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 673 | for (w = 1, num = n; num && w <= wmax; w++) { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 674 | /* for each event */ |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 675 | for (i = 0; num && i < n; i++) { |
Peter Zijlstra | 81269a0 | 2010-01-22 14:55:22 +0100 | [diff] [blame] | 676 | c = constraints[i]; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 677 | hwc = &cpuc->event_list[i]->hw; |
| 678 | |
Peter Zijlstra | 272d30b | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 679 | if (c->weight != w) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 680 | continue; |
| 681 | |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 682 | for_each_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 683 | if (!test_bit(j, used_mask)) |
| 684 | break; |
| 685 | } |
| 686 | |
| 687 | if (j == X86_PMC_IDX_MAX) |
| 688 | break; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 689 | |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 690 | set_bit(j, used_mask); |
| 691 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 692 | if (assign) |
| 693 | assign[i] = j; |
| 694 | num--; |
| 695 | } |
| 696 | } |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 697 | done: |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 698 | /* |
| 699 | * scheduling failed or is just a simulation, |
| 700 | * free resources if necessary |
| 701 | */ |
| 702 | if (!assign || num) { |
| 703 | for (i = 0; i < n; i++) { |
| 704 | if (x86_pmu.put_event_constraints) |
| 705 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); |
| 706 | } |
| 707 | } |
| 708 | return num ? -ENOSPC : 0; |
| 709 | } |
| 710 | |
| 711 | /* |
| 712 | * dogrp: true if must collect siblings events (group) |
| 713 | * returns total number of events and error code |
| 714 | */ |
| 715 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) |
| 716 | { |
| 717 | struct perf_event *event; |
| 718 | int n, max_count; |
| 719 | |
| 720 | max_count = x86_pmu.num_events + x86_pmu.num_events_fixed; |
| 721 | |
| 722 | /* current number of events already accepted */ |
| 723 | n = cpuc->n_events; |
| 724 | |
| 725 | if (is_x86_event(leader)) { |
| 726 | if (n >= max_count) |
| 727 | return -ENOSPC; |
| 728 | cpuc->event_list[n] = leader; |
| 729 | n++; |
| 730 | } |
| 731 | if (!dogrp) |
| 732 | return n; |
| 733 | |
| 734 | list_for_each_entry(event, &leader->sibling_list, group_entry) { |
| 735 | if (!is_x86_event(event) || |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 736 | event->state <= PERF_EVENT_STATE_OFF) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 737 | continue; |
| 738 | |
| 739 | if (n >= max_count) |
| 740 | return -ENOSPC; |
| 741 | |
| 742 | cpuc->event_list[n] = event; |
| 743 | n++; |
| 744 | } |
| 745 | return n; |
| 746 | } |
| 747 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 748 | static inline void x86_assign_hw_event(struct perf_event *event, |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 749 | struct cpu_hw_events *cpuc, int i) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 750 | { |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 751 | struct hw_perf_event *hwc = &event->hw; |
| 752 | |
| 753 | hwc->idx = cpuc->assign[i]; |
| 754 | hwc->last_cpu = smp_processor_id(); |
| 755 | hwc->last_tag = ++cpuc->tags[i]; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 756 | |
| 757 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { |
| 758 | hwc->config_base = 0; |
| 759 | hwc->event_base = 0; |
| 760 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { |
| 761 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
| 762 | /* |
| 763 | * We set it so that event_base + idx in wrmsr/rdmsr maps to |
| 764 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: |
| 765 | */ |
| 766 | hwc->event_base = |
| 767 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; |
| 768 | } else { |
| 769 | hwc->config_base = x86_pmu.eventsel; |
| 770 | hwc->event_base = x86_pmu.perfctr; |
| 771 | } |
| 772 | } |
| 773 | |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 774 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
| 775 | struct cpu_hw_events *cpuc, |
| 776 | int i) |
| 777 | { |
| 778 | return hwc->idx == cpuc->assign[i] && |
| 779 | hwc->last_cpu == smp_processor_id() && |
| 780 | hwc->last_tag == cpuc->tags[i]; |
| 781 | } |
| 782 | |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 783 | static void x86_pmu_stop(struct perf_event *event); |
Peter Zijlstra | 2e84187 | 2010-01-25 15:58:43 +0100 | [diff] [blame] | 784 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 785 | void hw_perf_enable(void) |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 786 | { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 787 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 788 | struct perf_event *event; |
| 789 | struct hw_perf_event *hwc; |
| 790 | int i; |
| 791 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 792 | if (!x86_pmu_initialized()) |
Ingo Molnar | 2b9ff0d | 2008-12-14 18:36:30 +0100 | [diff] [blame] | 793 | return; |
Peter Zijlstra | 1a6e21f | 2010-01-27 23:07:47 +0100 | [diff] [blame] | 794 | |
| 795 | if (cpuc->enabled) |
| 796 | return; |
| 797 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 798 | if (cpuc->n_added) { |
| 799 | /* |
| 800 | * apply assignment obtained either from |
| 801 | * hw_perf_group_sched_in() or x86_pmu_enable() |
| 802 | * |
| 803 | * step1: save events moving to new counters |
| 804 | * step2: reprogram moved events into new counters |
| 805 | */ |
| 806 | for (i = 0; i < cpuc->n_events; i++) { |
| 807 | |
| 808 | event = cpuc->event_list[i]; |
| 809 | hwc = &event->hw; |
| 810 | |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 811 | /* |
| 812 | * we can avoid reprogramming counter if: |
| 813 | * - assigned same counter as last time |
| 814 | * - running on same CPU as last time |
| 815 | * - no other event has used the counter since |
| 816 | */ |
| 817 | if (hwc->idx == -1 || |
| 818 | match_prev_assignment(hwc, cpuc, i)) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 819 | continue; |
| 820 | |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 821 | x86_pmu_stop(event); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 822 | |
| 823 | hwc->idx = -1; |
| 824 | } |
| 825 | |
| 826 | for (i = 0; i < cpuc->n_events; i++) { |
| 827 | |
| 828 | event = cpuc->event_list[i]; |
| 829 | hwc = &event->hw; |
| 830 | |
| 831 | if (hwc->idx == -1) { |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 832 | x86_assign_hw_event(event, cpuc, i); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 833 | x86_perf_event_set_period(event, hwc, hwc->idx); |
| 834 | } |
| 835 | /* |
| 836 | * need to mark as active because x86_pmu_disable() |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 837 | * clear active_mask and events[] yet it preserves |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 838 | * idx |
| 839 | */ |
| 840 | set_bit(hwc->idx, cpuc->active_mask); |
| 841 | cpuc->events[hwc->idx] = event; |
| 842 | |
| 843 | x86_pmu.enable(hwc, hwc->idx); |
| 844 | perf_event_update_userpage(event); |
| 845 | } |
| 846 | cpuc->n_added = 0; |
| 847 | perf_events_lapic_init(); |
| 848 | } |
Peter Zijlstra | 1a6e21f | 2010-01-27 23:07:47 +0100 | [diff] [blame] | 849 | |
| 850 | cpuc->enabled = 1; |
| 851 | barrier(); |
| 852 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 853 | x86_pmu.enable_all(); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 854 | } |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 855 | |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 856 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, int idx) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 857 | { |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 858 | (void)checking_wrmsrl(hwc->config_base + idx, |
Robert Richter | bb1165d | 2010-03-01 14:21:23 +0100 | [diff] [blame] | 859 | hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE); |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 860 | } |
| 861 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 862 | static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 863 | { |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 864 | (void)checking_wrmsrl(hwc->config_base + idx, hwc->config); |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 865 | } |
| 866 | |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 867 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 868 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 869 | /* |
| 870 | * Set the next IRQ period, based on the hwc->period_left value. |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 871 | * To be called with the event disabled in hw: |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 872 | */ |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 873 | static int |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 874 | x86_perf_event_set_period(struct perf_event *event, |
| 875 | struct hw_perf_event *hwc, int idx) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 876 | { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 877 | s64 left = atomic64_read(&hwc->period_left); |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 878 | s64 period = hwc->sample_period; |
| 879 | int err, ret = 0; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 880 | |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 881 | if (idx == X86_PMC_IDX_FIXED_BTS) |
| 882 | return 0; |
| 883 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 884 | /* |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 885 | * If we are way outside a reasonable range then just skip forward: |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 886 | */ |
| 887 | if (unlikely(left <= -period)) { |
| 888 | left = period; |
| 889 | atomic64_set(&hwc->period_left, left); |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 890 | hwc->last_period = period; |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 891 | ret = 1; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 892 | } |
| 893 | |
| 894 | if (unlikely(left <= 0)) { |
| 895 | left += period; |
| 896 | atomic64_set(&hwc->period_left, left); |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 897 | hwc->last_period = period; |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 898 | ret = 1; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 899 | } |
Ingo Molnar | 1c80f4b | 2009-05-15 08:25:22 +0200 | [diff] [blame] | 900 | /* |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 901 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
Ingo Molnar | 1c80f4b | 2009-05-15 08:25:22 +0200 | [diff] [blame] | 902 | */ |
| 903 | if (unlikely(left < 2)) |
| 904 | left = 2; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 905 | |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 906 | if (left > x86_pmu.max_period) |
| 907 | left = x86_pmu.max_period; |
| 908 | |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 909 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 910 | |
| 911 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 912 | * The hw event starts counting from this event offset, |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 913 | * mark it to be able to extra future deltas: |
| 914 | */ |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 915 | atomic64_set(&hwc->prev_count, (u64)-left); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 916 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 917 | err = checking_wrmsrl(hwc->event_base + idx, |
| 918 | (u64)(-left) & x86_pmu.event_mask); |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 919 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 920 | perf_event_update_userpage(event); |
Peter Zijlstra | 194002b | 2009-06-22 16:35:24 +0200 | [diff] [blame] | 921 | |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 922 | return ret; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 923 | } |
| 924 | |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 925 | static void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx) |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 926 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 927 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 928 | if (cpuc->enabled) |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 929 | __x86_pmu_enable_event(hwc, idx); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 930 | } |
| 931 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 932 | /* |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 933 | * activate a single event |
| 934 | * |
| 935 | * The event is added to the group of enabled events |
| 936 | * but only if it can be scehduled with existing events. |
| 937 | * |
| 938 | * Called with PMU disabled. If successful and return value 1, |
| 939 | * then guaranteed to call perf_enable() and hw_perf_enable() |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 940 | */ |
| 941 | static int x86_pmu_enable(struct perf_event *event) |
| 942 | { |
| 943 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 944 | struct hw_perf_event *hwc; |
| 945 | int assign[X86_PMC_IDX_MAX]; |
| 946 | int n, n0, ret; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 947 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 948 | hwc = &event->hw; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 949 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 950 | n0 = cpuc->n_events; |
| 951 | n = collect_events(cpuc, event, false); |
| 952 | if (n < 0) |
| 953 | return n; |
Ingo Molnar | 53b441a | 2009-05-25 21:41:28 +0200 | [diff] [blame] | 954 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 955 | ret = x86_schedule_events(cpuc, n, assign); |
| 956 | if (ret) |
| 957 | return ret; |
| 958 | /* |
| 959 | * copy new assignment, now we know it is possible |
| 960 | * will be used by hw_perf_enable() |
| 961 | */ |
| 962 | memcpy(cpuc->assign, assign, n*sizeof(int)); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 963 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 964 | cpuc->n_events = n; |
| 965 | cpuc->n_added = n - n0; |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 966 | |
Ingo Molnar | 95cdd2e | 2008-12-21 13:50:42 +0100 | [diff] [blame] | 967 | return 0; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 968 | } |
| 969 | |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 970 | static int x86_pmu_start(struct perf_event *event) |
| 971 | { |
| 972 | struct hw_perf_event *hwc = &event->hw; |
| 973 | |
| 974 | if (hwc->idx == -1) |
| 975 | return -EAGAIN; |
| 976 | |
| 977 | x86_perf_event_set_period(event, hwc, hwc->idx); |
| 978 | x86_pmu.enable(hwc, hwc->idx); |
| 979 | |
| 980 | return 0; |
| 981 | } |
| 982 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 983 | static void x86_pmu_unthrottle(struct perf_event *event) |
Peter Zijlstra | a78ac32 | 2009-05-25 17:39:05 +0200 | [diff] [blame] | 984 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 985 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 986 | struct hw_perf_event *hwc = &event->hw; |
Peter Zijlstra | a78ac32 | 2009-05-25 17:39:05 +0200 | [diff] [blame] | 987 | |
| 988 | if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX || |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 989 | cpuc->events[hwc->idx] != event)) |
Peter Zijlstra | a78ac32 | 2009-05-25 17:39:05 +0200 | [diff] [blame] | 990 | return; |
| 991 | |
| 992 | x86_pmu.enable(hwc, hwc->idx); |
| 993 | } |
| 994 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 995 | void perf_event_print_debug(void) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 996 | { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 997 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 998 | struct cpu_hw_events *cpuc; |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 999 | unsigned long flags; |
Ingo Molnar | 1e12567 | 2008-12-09 12:18:18 +0100 | [diff] [blame] | 1000 | int cpu, idx; |
| 1001 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1002 | if (!x86_pmu.num_events) |
Ingo Molnar | 1e12567 | 2008-12-09 12:18:18 +0100 | [diff] [blame] | 1003 | return; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1004 | |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 1005 | local_irq_save(flags); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1006 | |
| 1007 | cpu = smp_processor_id(); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1008 | cpuc = &per_cpu(cpu_hw_events, cpu); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1009 | |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 1010 | if (x86_pmu.version >= 2) { |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1011 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
| 1012 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
| 1013 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); |
| 1014 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1015 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1016 | pr_info("\n"); |
| 1017 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); |
| 1018 | pr_info("CPU#%d: status: %016llx\n", cpu, status); |
| 1019 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); |
| 1020 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1021 | } |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1022 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1023 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1024 | for (idx = 0; idx < x86_pmu.num_events; idx++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 1025 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
| 1026 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1027 | |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1028 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1029 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1030 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1031 | cpu, idx, pmc_ctrl); |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1032 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1033 | cpu, idx, pmc_count); |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1034 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1035 | cpu, idx, prev_left); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1036 | } |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1037 | for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1038 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
| 1039 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1040 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1041 | cpu, idx, pmc_count); |
| 1042 | } |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 1043 | local_irq_restore(flags); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1044 | } |
| 1045 | |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 1046 | static void x86_pmu_stop(struct perf_event *event) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1047 | { |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 1048 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1049 | struct hw_perf_event *hwc = &event->hw; |
Peter Zijlstra | 2e84187 | 2010-01-25 15:58:43 +0100 | [diff] [blame] | 1050 | int idx = hwc->idx; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1051 | |
Robert Richter | 0953423 | 2009-04-29 12:47:16 +0200 | [diff] [blame] | 1052 | /* |
| 1053 | * Must be done before we disable, otherwise the nmi handler |
| 1054 | * could reenable again: |
| 1055 | */ |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 1056 | clear_bit(idx, cpuc->active_mask); |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 1057 | x86_pmu.disable(hwc, idx); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1058 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1059 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1060 | * Drain the remaining delta count out of a event |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1061 | * that we are disabling: |
| 1062 | */ |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1063 | x86_perf_event_update(event, hwc, idx); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1064 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1065 | cpuc->events[idx] = NULL; |
Peter Zijlstra | 2e84187 | 2010-01-25 15:58:43 +0100 | [diff] [blame] | 1066 | } |
| 1067 | |
| 1068 | static void x86_pmu_disable(struct perf_event *event) |
| 1069 | { |
| 1070 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 1071 | int i; |
| 1072 | |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 1073 | x86_pmu_stop(event); |
Peter Zijlstra | 194002b | 2009-06-22 16:35:24 +0200 | [diff] [blame] | 1074 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1075 | for (i = 0; i < cpuc->n_events; i++) { |
| 1076 | if (event == cpuc->event_list[i]) { |
| 1077 | |
| 1078 | if (x86_pmu.put_event_constraints) |
| 1079 | x86_pmu.put_event_constraints(cpuc, event); |
| 1080 | |
| 1081 | while (++i < cpuc->n_events) |
| 1082 | cpuc->event_list[i-1] = cpuc->event_list[i]; |
| 1083 | |
| 1084 | --cpuc->n_events; |
Peter Zijlstra | 6c9687a | 2010-01-25 11:57:25 +0100 | [diff] [blame] | 1085 | break; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1086 | } |
| 1087 | } |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1088 | perf_event_update_userpage(event); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1089 | } |
| 1090 | |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 1091 | static int x86_pmu_handle_irq(struct pt_regs *regs) |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1092 | { |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 1093 | struct perf_sample_data data; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1094 | struct cpu_hw_events *cpuc; |
| 1095 | struct perf_event *event; |
| 1096 | struct hw_perf_event *hwc; |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1097 | int idx, handled = 0; |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 1098 | u64 val; |
| 1099 | |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 1100 | data.addr = 0; |
Xiao Guangrong | 5e855db | 2009-12-10 17:08:54 +0800 | [diff] [blame] | 1101 | data.raw = NULL; |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 1102 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1103 | cpuc = &__get_cpu_var(cpu_hw_events); |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1104 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1105 | for (idx = 0; idx < x86_pmu.num_events; idx++) { |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 1106 | if (!test_bit(idx, cpuc->active_mask)) |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1107 | continue; |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 1108 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1109 | event = cpuc->events[idx]; |
| 1110 | hwc = &event->hw; |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame] | 1111 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1112 | val = x86_perf_event_update(event, hwc, idx); |
| 1113 | if (val & (1ULL << (x86_pmu.event_bits - 1))) |
Peter Zijlstra | 48e22d5 | 2009-05-25 17:39:04 +0200 | [diff] [blame] | 1114 | continue; |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 1115 | |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1116 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1117 | * event overflow |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1118 | */ |
| 1119 | handled = 1; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1120 | data.period = event->hw.last_period; |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1121 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1122 | if (!x86_perf_event_set_period(event, hwc, idx)) |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1123 | continue; |
| 1124 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1125 | if (perf_event_overflow(event, 1, &data, regs)) |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 1126 | x86_pmu.disable(hwc, idx); |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1127 | } |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 1128 | |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1129 | if (handled) |
| 1130 | inc_irq_stat(apic_perf_irqs); |
| 1131 | |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 1132 | return handled; |
| 1133 | } |
Robert Richter | 39d81ea | 2009-04-29 12:47:05 +0200 | [diff] [blame] | 1134 | |
Peter Zijlstra | b6276f3 | 2009-04-06 11:45:03 +0200 | [diff] [blame] | 1135 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
| 1136 | { |
| 1137 | irq_enter(); |
| 1138 | ack_APIC_irq(); |
| 1139 | inc_irq_stat(apic_pending_irqs); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1140 | perf_event_do_pending(); |
Peter Zijlstra | b6276f3 | 2009-04-06 11:45:03 +0200 | [diff] [blame] | 1141 | irq_exit(); |
| 1142 | } |
| 1143 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1144 | void set_perf_event_pending(void) |
Peter Zijlstra | b6276f3 | 2009-04-06 11:45:03 +0200 | [diff] [blame] | 1145 | { |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 1146 | #ifdef CONFIG_X86_LOCAL_APIC |
Peter Zijlstra | 7d42896 | 2009-09-23 11:03:37 +0200 | [diff] [blame] | 1147 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
| 1148 | return; |
| 1149 | |
Peter Zijlstra | b6276f3 | 2009-04-06 11:45:03 +0200 | [diff] [blame] | 1150 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 1151 | #endif |
Peter Zijlstra | b6276f3 | 2009-04-06 11:45:03 +0200 | [diff] [blame] | 1152 | } |
| 1153 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1154 | void perf_events_lapic_init(void) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1155 | { |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 1156 | #ifdef CONFIG_X86_LOCAL_APIC |
| 1157 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1158 | return; |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 1159 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1160 | /* |
Yong Wang | c323d95 | 2009-05-29 13:28:35 +0800 | [diff] [blame] | 1161 | * Always use NMI for PMU |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1162 | */ |
Yong Wang | c323d95 | 2009-05-29 13:28:35 +0800 | [diff] [blame] | 1163 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 1164 | #endif |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1165 | } |
| 1166 | |
| 1167 | static int __kprobes |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1168 | perf_event_nmi_handler(struct notifier_block *self, |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1169 | unsigned long cmd, void *__args) |
| 1170 | { |
| 1171 | struct die_args *args = __args; |
| 1172 | struct pt_regs *regs; |
| 1173 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1174 | if (!atomic_read(&active_events)) |
Peter Zijlstra | 63a809a | 2009-05-01 12:23:17 +0200 | [diff] [blame] | 1175 | return NOTIFY_DONE; |
| 1176 | |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 1177 | switch (cmd) { |
| 1178 | case DIE_NMI: |
| 1179 | case DIE_NMI_IPI: |
| 1180 | break; |
| 1181 | |
| 1182 | default: |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1183 | return NOTIFY_DONE; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 1184 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1185 | |
| 1186 | regs = args->regs; |
| 1187 | |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 1188 | #ifdef CONFIG_X86_LOCAL_APIC |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1189 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 1190 | #endif |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame] | 1191 | /* |
| 1192 | * Can't rely on the handled return value to say it was our NMI, two |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1193 | * events could trigger 'simultaneously' raising two back-to-back NMIs. |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame] | 1194 | * |
| 1195 | * If the first NMI handles both, the latter will be empty and daze |
| 1196 | * the CPU. |
| 1197 | */ |
Yong Wang | a328810 | 2009-06-03 13:12:55 +0800 | [diff] [blame] | 1198 | x86_pmu.handle_irq(regs); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1199 | |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame] | 1200 | return NOTIFY_STOP; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1201 | } |
| 1202 | |
Peter Zijlstra | f22f54f | 2010-02-26 12:05:05 +0100 | [diff] [blame] | 1203 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
| 1204 | .notifier_call = perf_event_nmi_handler, |
| 1205 | .next = NULL, |
| 1206 | .priority = 1 |
| 1207 | }; |
| 1208 | |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1209 | static struct event_constraint unconstrained; |
Stephane Eranian | 38331f6 | 2010-02-08 17:17:01 +0200 | [diff] [blame] | 1210 | static struct event_constraint emptyconstraint; |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1211 | |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1212 | static struct event_constraint * |
Peter Zijlstra | f22f54f | 2010-02-26 12:05:05 +0100 | [diff] [blame] | 1213 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1214 | { |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1215 | struct event_constraint *c; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1216 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1217 | if (x86_pmu.event_constraints) { |
| 1218 | for_each_event_constraint(c, x86_pmu.event_constraints) { |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1219 | if ((event->hw.config & c->cmask) == c->code) |
| 1220 | return c; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1221 | } |
| 1222 | } |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1223 | |
| 1224 | return &unconstrained; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1225 | } |
| 1226 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1227 | static int x86_event_sched_in(struct perf_event *event, |
Peter Zijlstra | 6e37738 | 2010-02-11 13:21:58 +0100 | [diff] [blame] | 1228 | struct perf_cpu_context *cpuctx) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1229 | { |
| 1230 | int ret = 0; |
| 1231 | |
| 1232 | event->state = PERF_EVENT_STATE_ACTIVE; |
Peter Zijlstra | 6e37738 | 2010-02-11 13:21:58 +0100 | [diff] [blame] | 1233 | event->oncpu = smp_processor_id(); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1234 | event->tstamp_running += event->ctx->time - event->tstamp_stopped; |
| 1235 | |
| 1236 | if (!is_x86_event(event)) |
| 1237 | ret = event->pmu->enable(event); |
| 1238 | |
| 1239 | if (!ret && !is_software_event(event)) |
| 1240 | cpuctx->active_oncpu++; |
| 1241 | |
| 1242 | if (!ret && event->attr.exclusive) |
| 1243 | cpuctx->exclusive = 1; |
| 1244 | |
| 1245 | return ret; |
| 1246 | } |
| 1247 | |
| 1248 | static void x86_event_sched_out(struct perf_event *event, |
Peter Zijlstra | 6e37738 | 2010-02-11 13:21:58 +0100 | [diff] [blame] | 1249 | struct perf_cpu_context *cpuctx) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1250 | { |
| 1251 | event->state = PERF_EVENT_STATE_INACTIVE; |
| 1252 | event->oncpu = -1; |
| 1253 | |
| 1254 | if (!is_x86_event(event)) |
| 1255 | event->pmu->disable(event); |
| 1256 | |
| 1257 | event->tstamp_running -= event->ctx->time - event->tstamp_stopped; |
| 1258 | |
| 1259 | if (!is_software_event(event)) |
| 1260 | cpuctx->active_oncpu--; |
| 1261 | |
| 1262 | if (event->attr.exclusive || !cpuctx->active_oncpu) |
| 1263 | cpuctx->exclusive = 0; |
| 1264 | } |
| 1265 | |
| 1266 | /* |
| 1267 | * Called to enable a whole group of events. |
| 1268 | * Returns 1 if the group was enabled, or -EAGAIN if it could not be. |
| 1269 | * Assumes the caller has disabled interrupts and has |
| 1270 | * frozen the PMU with hw_perf_save_disable. |
| 1271 | * |
| 1272 | * called with PMU disabled. If successful and return value 1, |
| 1273 | * then guaranteed to call perf_enable() and hw_perf_enable() |
| 1274 | */ |
| 1275 | int hw_perf_group_sched_in(struct perf_event *leader, |
| 1276 | struct perf_cpu_context *cpuctx, |
Peter Zijlstra | 6e37738 | 2010-02-11 13:21:58 +0100 | [diff] [blame] | 1277 | struct perf_event_context *ctx) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1278 | { |
Peter Zijlstra | 6e37738 | 2010-02-11 13:21:58 +0100 | [diff] [blame] | 1279 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1280 | struct perf_event *sub; |
| 1281 | int assign[X86_PMC_IDX_MAX]; |
| 1282 | int n0, n1, ret; |
| 1283 | |
| 1284 | /* n0 = total number of events */ |
| 1285 | n0 = collect_events(cpuc, leader, true); |
| 1286 | if (n0 < 0) |
| 1287 | return n0; |
| 1288 | |
| 1289 | ret = x86_schedule_events(cpuc, n0, assign); |
| 1290 | if (ret) |
| 1291 | return ret; |
| 1292 | |
Peter Zijlstra | 6e37738 | 2010-02-11 13:21:58 +0100 | [diff] [blame] | 1293 | ret = x86_event_sched_in(leader, cpuctx); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1294 | if (ret) |
| 1295 | return ret; |
| 1296 | |
| 1297 | n1 = 1; |
| 1298 | list_for_each_entry(sub, &leader->sibling_list, group_entry) { |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1299 | if (sub->state > PERF_EVENT_STATE_OFF) { |
Peter Zijlstra | 6e37738 | 2010-02-11 13:21:58 +0100 | [diff] [blame] | 1300 | ret = x86_event_sched_in(sub, cpuctx); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1301 | if (ret) |
| 1302 | goto undo; |
| 1303 | ++n1; |
| 1304 | } |
| 1305 | } |
| 1306 | /* |
| 1307 | * copy new assignment, now we know it is possible |
| 1308 | * will be used by hw_perf_enable() |
| 1309 | */ |
| 1310 | memcpy(cpuc->assign, assign, n0*sizeof(int)); |
| 1311 | |
| 1312 | cpuc->n_events = n0; |
| 1313 | cpuc->n_added = n1; |
| 1314 | ctx->nr_active += n1; |
| 1315 | |
| 1316 | /* |
| 1317 | * 1 means successful and events are active |
| 1318 | * This is not quite true because we defer |
| 1319 | * actual activation until hw_perf_enable() but |
| 1320 | * this way we* ensure caller won't try to enable |
| 1321 | * individual events |
| 1322 | */ |
| 1323 | return 1; |
| 1324 | undo: |
Peter Zijlstra | 6e37738 | 2010-02-11 13:21:58 +0100 | [diff] [blame] | 1325 | x86_event_sched_out(leader, cpuctx); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1326 | n0 = 1; |
| 1327 | list_for_each_entry(sub, &leader->sibling_list, group_entry) { |
| 1328 | if (sub->state == PERF_EVENT_STATE_ACTIVE) { |
Peter Zijlstra | 6e37738 | 2010-02-11 13:21:58 +0100 | [diff] [blame] | 1329 | x86_event_sched_out(sub, cpuctx); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1330 | if (++n0 == n1) |
| 1331 | break; |
| 1332 | } |
| 1333 | } |
| 1334 | return ret; |
| 1335 | } |
| 1336 | |
Peter Zijlstra | f22f54f | 2010-02-26 12:05:05 +0100 | [diff] [blame] | 1337 | #include "perf_event_amd.c" |
| 1338 | #include "perf_event_p6.c" |
| 1339 | #include "perf_event_intel.c" |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1340 | |
Cyrill Gorcunov | 1255803 | 2009-12-10 19:56:34 +0300 | [diff] [blame] | 1341 | static void __init pmu_check_apic(void) |
| 1342 | { |
| 1343 | if (cpu_has_apic) |
| 1344 | return; |
| 1345 | |
| 1346 | x86_pmu.apic = 0; |
| 1347 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); |
| 1348 | pr_info("no hardware sampling interrupt available.\n"); |
| 1349 | } |
| 1350 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1351 | void __init init_hw_perf_events(void) |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1352 | { |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1353 | int err; |
| 1354 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1355 | pr_info("Performance Events: "); |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1356 | |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1357 | switch (boot_cpu_data.x86_vendor) { |
| 1358 | case X86_VENDOR_INTEL: |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1359 | err = intel_pmu_init(); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1360 | break; |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1361 | case X86_VENDOR_AMD: |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 1362 | err = amd_pmu_init(); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1363 | break; |
Robert Richter | 4138960 | 2009-04-29 12:47:00 +0200 | [diff] [blame] | 1364 | default: |
| 1365 | return; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1366 | } |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1367 | if (err != 0) { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1368 | pr_cont("no PMU driver, software events only.\n"); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1369 | return; |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1370 | } |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1371 | |
Cyrill Gorcunov | 1255803 | 2009-12-10 19:56:34 +0300 | [diff] [blame] | 1372 | pmu_check_apic(); |
| 1373 | |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1374 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 1375 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1376 | if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) { |
| 1377 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
| 1378 | x86_pmu.num_events, X86_PMC_MAX_GENERIC); |
| 1379 | x86_pmu.num_events = X86_PMC_MAX_GENERIC; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1380 | } |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1381 | perf_event_mask = (1 << x86_pmu.num_events) - 1; |
| 1382 | perf_max_events = x86_pmu.num_events; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1383 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1384 | if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) { |
| 1385 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
| 1386 | x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED); |
| 1387 | x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED; |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 1388 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1389 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1390 | perf_event_mask |= |
| 1391 | ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED; |
| 1392 | x86_pmu.intel_ctrl = perf_event_mask; |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 1393 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1394 | perf_events_lapic_init(); |
| 1395 | register_die_notifier(&perf_event_nmi_notifier); |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1396 | |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1397 | unconstrained = (struct event_constraint) |
Peter Zijlstra | fce877e | 2010-01-29 13:25:12 +0100 | [diff] [blame] | 1398 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1, |
| 1399 | 0, x86_pmu.num_events); |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1400 | |
Ingo Molnar | 57c0c15 | 2009-09-21 12:20:38 +0200 | [diff] [blame] | 1401 | pr_info("... version: %d\n", x86_pmu.version); |
| 1402 | pr_info("... bit width: %d\n", x86_pmu.event_bits); |
| 1403 | pr_info("... generic registers: %d\n", x86_pmu.num_events); |
| 1404 | pr_info("... value mask: %016Lx\n", x86_pmu.event_mask); |
| 1405 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
| 1406 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_events_fixed); |
| 1407 | pr_info("... event mask: %016Lx\n", perf_event_mask); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1408 | } |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1409 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1410 | static inline void x86_pmu_read(struct perf_event *event) |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1411 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1412 | x86_perf_event_update(event, &event->hw, event->hw.idx); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1413 | } |
| 1414 | |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 1415 | static const struct pmu pmu = { |
| 1416 | .enable = x86_pmu_enable, |
| 1417 | .disable = x86_pmu_disable, |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame] | 1418 | .start = x86_pmu_start, |
| 1419 | .stop = x86_pmu_stop, |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 1420 | .read = x86_pmu_read, |
Peter Zijlstra | a78ac32 | 2009-05-25 17:39:05 +0200 | [diff] [blame] | 1421 | .unthrottle = x86_pmu_unthrottle, |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1422 | }; |
| 1423 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1424 | /* |
| 1425 | * validate a single event group |
| 1426 | * |
| 1427 | * validation include: |
Ingo Molnar | 184f412 | 2010-01-27 08:39:39 +0100 | [diff] [blame] | 1428 | * - check events are compatible which each other |
| 1429 | * - events do not compete for the same counter |
| 1430 | * - number of events <= number of counters |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1431 | * |
| 1432 | * validation ensures the group can be loaded onto the |
| 1433 | * PMU if it was the only group available. |
| 1434 | */ |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1435 | static int validate_group(struct perf_event *event) |
| 1436 | { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1437 | struct perf_event *leader = event->group_leader; |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1438 | struct cpu_hw_events *fake_cpuc; |
| 1439 | int ret, n; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1440 | |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1441 | ret = -ENOMEM; |
| 1442 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); |
| 1443 | if (!fake_cpuc) |
| 1444 | goto out; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1445 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1446 | /* |
| 1447 | * the event is not yet connected with its |
| 1448 | * siblings therefore we must first collect |
| 1449 | * existing siblings, then add the new event |
| 1450 | * before we can simulate the scheduling |
| 1451 | */ |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1452 | ret = -ENOSPC; |
| 1453 | n = collect_events(fake_cpuc, leader, true); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1454 | if (n < 0) |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1455 | goto out_free; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1456 | |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1457 | fake_cpuc->n_events = n; |
| 1458 | n = collect_events(fake_cpuc, event, false); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1459 | if (n < 0) |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1460 | goto out_free; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1461 | |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1462 | fake_cpuc->n_events = n; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1463 | |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 1464 | ret = x86_schedule_events(fake_cpuc, n, NULL); |
| 1465 | |
| 1466 | out_free: |
| 1467 | kfree(fake_cpuc); |
| 1468 | out: |
| 1469 | return ret; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1470 | } |
| 1471 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1472 | const struct pmu *hw_perf_event_init(struct perf_event *event) |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1473 | { |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1474 | const struct pmu *tmp; |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1475 | int err; |
| 1476 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1477 | err = __hw_perf_event_init(event); |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1478 | if (!err) { |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1479 | /* |
| 1480 | * we temporarily connect event to its pmu |
| 1481 | * such that validate_group() can classify |
| 1482 | * it as an x86 event using is_x86_event() |
| 1483 | */ |
| 1484 | tmp = event->pmu; |
| 1485 | event->pmu = &pmu; |
| 1486 | |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1487 | if (event->group_leader != event) |
| 1488 | err = validate_group(event); |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1489 | |
| 1490 | event->pmu = tmp; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1491 | } |
Peter Zijlstra | a1792cdac | 2009-09-09 10:04:47 +0200 | [diff] [blame] | 1492 | if (err) { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1493 | if (event->destroy) |
| 1494 | event->destroy(event); |
Peter Zijlstra | 9ea98e1 | 2009-03-30 19:07:09 +0200 | [diff] [blame] | 1495 | return ERR_PTR(err); |
Peter Zijlstra | a1792cdac | 2009-09-09 10:04:47 +0200 | [diff] [blame] | 1496 | } |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1497 | |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 1498 | return &pmu; |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 1499 | } |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1500 | |
| 1501 | /* |
| 1502 | * callchain support |
| 1503 | */ |
| 1504 | |
| 1505 | static inline |
Peter Zijlstra | f9188e0 | 2009-06-18 22:20:52 +0200 | [diff] [blame] | 1506 | void callchain_store(struct perf_callchain_entry *entry, u64 ip) |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1507 | { |
Peter Zijlstra | f9188e0 | 2009-06-18 22:20:52 +0200 | [diff] [blame] | 1508 | if (entry->nr < PERF_MAX_STACK_DEPTH) |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1509 | entry->ip[entry->nr++] = ip; |
| 1510 | } |
| 1511 | |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1512 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry); |
| 1513 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1514 | |
| 1515 | |
| 1516 | static void |
| 1517 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) |
| 1518 | { |
| 1519 | /* Ignore warnings */ |
| 1520 | } |
| 1521 | |
| 1522 | static void backtrace_warning(void *data, char *msg) |
| 1523 | { |
| 1524 | /* Ignore warnings */ |
| 1525 | } |
| 1526 | |
| 1527 | static int backtrace_stack(void *data, char *name) |
| 1528 | { |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame] | 1529 | return 0; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1530 | } |
| 1531 | |
| 1532 | static void backtrace_address(void *data, unsigned long addr, int reliable) |
| 1533 | { |
| 1534 | struct perf_callchain_entry *entry = data; |
| 1535 | |
| 1536 | if (reliable) |
| 1537 | callchain_store(entry, addr); |
| 1538 | } |
| 1539 | |
| 1540 | static const struct stacktrace_ops backtrace_ops = { |
| 1541 | .warning = backtrace_warning, |
| 1542 | .warning_symbol = backtrace_warning_symbol, |
| 1543 | .stack = backtrace_stack, |
| 1544 | .address = backtrace_address, |
Frederic Weisbecker | 06d65bd | 2009-12-17 05:40:34 +0100 | [diff] [blame] | 1545 | .walk_stack = print_context_stack_bp, |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1546 | }; |
| 1547 | |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame] | 1548 | #include "../dumpstack.h" |
| 1549 | |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1550 | static void |
| 1551 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 1552 | { |
Peter Zijlstra | f9188e0 | 2009-06-18 22:20:52 +0200 | [diff] [blame] | 1553 | callchain_store(entry, PERF_CONTEXT_KERNEL); |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame] | 1554 | callchain_store(entry, regs->ip); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1555 | |
Frederic Weisbecker | 48b5ba9 | 2009-12-31 05:53:02 +0100 | [diff] [blame] | 1556 | dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1557 | } |
| 1558 | |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 1559 | /* |
| 1560 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context |
| 1561 | */ |
| 1562 | static unsigned long |
| 1563 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1564 | { |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 1565 | unsigned long offset, addr = (unsigned long)from; |
| 1566 | int type = in_nmi() ? KM_NMI : KM_IRQ0; |
| 1567 | unsigned long size, len = 0; |
| 1568 | struct page *page; |
| 1569 | void *map; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1570 | int ret; |
| 1571 | |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 1572 | do { |
| 1573 | ret = __get_user_pages_fast(addr, 1, 0, &page); |
| 1574 | if (!ret) |
| 1575 | break; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1576 | |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 1577 | offset = addr & (PAGE_SIZE - 1); |
| 1578 | size = min(PAGE_SIZE - offset, n - len); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1579 | |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 1580 | map = kmap_atomic(page, type); |
| 1581 | memcpy(to, map+offset, size); |
| 1582 | kunmap_atomic(map, type); |
| 1583 | put_page(page); |
| 1584 | |
| 1585 | len += size; |
| 1586 | to += size; |
| 1587 | addr += size; |
| 1588 | |
| 1589 | } while (len < n); |
| 1590 | |
| 1591 | return len; |
| 1592 | } |
| 1593 | |
| 1594 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) |
| 1595 | { |
| 1596 | unsigned long bytes; |
| 1597 | |
| 1598 | bytes = copy_from_user_nmi(frame, fp, sizeof(*frame)); |
| 1599 | |
| 1600 | return bytes == sizeof(*frame); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1601 | } |
| 1602 | |
| 1603 | static void |
| 1604 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 1605 | { |
| 1606 | struct stack_frame frame; |
| 1607 | const void __user *fp; |
| 1608 | |
Ingo Molnar | 5a6cec3 | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1609 | if (!user_mode(regs)) |
| 1610 | regs = task_pt_regs(current); |
| 1611 | |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 1612 | fp = (void __user *)regs->bp; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1613 | |
Peter Zijlstra | f9188e0 | 2009-06-18 22:20:52 +0200 | [diff] [blame] | 1614 | callchain_store(entry, PERF_CONTEXT_USER); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1615 | callchain_store(entry, regs->ip); |
| 1616 | |
Peter Zijlstra | f9188e0 | 2009-06-18 22:20:52 +0200 | [diff] [blame] | 1617 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame] | 1618 | frame.next_frame = NULL; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1619 | frame.return_address = 0; |
| 1620 | |
| 1621 | if (!copy_stack_frame(fp, &frame)) |
| 1622 | break; |
| 1623 | |
Ingo Molnar | 5a6cec3 | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 1624 | if ((unsigned long)fp < regs->sp) |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1625 | break; |
| 1626 | |
| 1627 | callchain_store(entry, frame.return_address); |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame] | 1628 | fp = frame.next_frame; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1629 | } |
| 1630 | } |
| 1631 | |
| 1632 | static void |
| 1633 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 1634 | { |
| 1635 | int is_user; |
| 1636 | |
| 1637 | if (!regs) |
| 1638 | return; |
| 1639 | |
| 1640 | is_user = user_mode(regs); |
| 1641 | |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1642 | if (is_user && current->state != TASK_RUNNING) |
| 1643 | return; |
| 1644 | |
| 1645 | if (!is_user) |
| 1646 | perf_callchain_kernel(regs, entry); |
| 1647 | |
| 1648 | if (current->mm) |
| 1649 | perf_callchain_user(regs, entry); |
| 1650 | } |
| 1651 | |
| 1652 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) |
| 1653 | { |
| 1654 | struct perf_callchain_entry *entry; |
| 1655 | |
| 1656 | if (in_nmi()) |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1657 | entry = &__get_cpu_var(pmc_nmi_entry); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1658 | else |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1659 | entry = &__get_cpu_var(pmc_irq_entry); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 1660 | |
| 1661 | entry->nr = 0; |
| 1662 | |
| 1663 | perf_do_callchain(regs, entry); |
| 1664 | |
| 1665 | return entry; |
| 1666 | } |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1667 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1668 | void hw_perf_event_setup_online(int cpu) |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1669 | { |
| 1670 | init_debug_store_on_cpu(cpu); |
Stephane Eranian | 38331f6 | 2010-02-08 17:17:01 +0200 | [diff] [blame] | 1671 | |
| 1672 | switch (boot_cpu_data.x86_vendor) { |
| 1673 | case X86_VENDOR_AMD: |
| 1674 | amd_pmu_cpu_online(cpu); |
| 1675 | break; |
| 1676 | default: |
| 1677 | return; |
| 1678 | } |
| 1679 | } |
| 1680 | |
| 1681 | void hw_perf_event_setup_offline(int cpu) |
| 1682 | { |
| 1683 | init_debug_store_on_cpu(cpu); |
| 1684 | |
| 1685 | switch (boot_cpu_data.x86_vendor) { |
| 1686 | case X86_VENDOR_AMD: |
| 1687 | amd_pmu_cpu_offline(cpu); |
| 1688 | break; |
| 1689 | default: |
| 1690 | return; |
| 1691 | } |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1692 | } |