Hongzhou Yang | a6df410 | 2015-01-21 13:28:15 +0800 | [diff] [blame] | 1 | /* |
| 2 | * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver. |
| 3 | * Copyright (c) 2014 MediaTek Inc. |
| 4 | * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/io.h> |
| 17 | #include <linux/gpio.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/of.h> |
| 20 | #include <linux/of_address.h> |
| 21 | #include <linux/of_device.h> |
| 22 | #include <linux/of_irq.h> |
| 23 | #include <linux/pinctrl/consumer.h> |
| 24 | #include <linux/pinctrl/machine.h> |
| 25 | #include <linux/pinctrl/pinconf.h> |
| 26 | #include <linux/pinctrl/pinconf-generic.h> |
| 27 | #include <linux/pinctrl/pinctrl.h> |
| 28 | #include <linux/pinctrl/pinmux.h> |
| 29 | #include <linux/platform_device.h> |
| 30 | #include <linux/slab.h> |
| 31 | #include <linux/bitops.h> |
| 32 | #include <linux/regmap.h> |
| 33 | #include <linux/mfd/syscon.h> |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 34 | #include <linux/delay.h> |
Hongzhou Yang | 30f010f | 2015-01-27 15:13:55 +0800 | [diff] [blame] | 35 | #include <linux/interrupt.h> |
Hongzhou Yang | a6df410 | 2015-01-21 13:28:15 +0800 | [diff] [blame] | 36 | #include <dt-bindings/pinctrl/mt65xx.h> |
| 37 | |
| 38 | #include "../core.h" |
| 39 | #include "../pinconf.h" |
| 40 | #include "../pinctrl-utils.h" |
| 41 | #include "pinctrl-mtk-common.h" |
| 42 | |
| 43 | #define MAX_GPIO_MODE_PER_REG 5 |
| 44 | #define GPIO_MODE_BITS 3 |
| 45 | |
| 46 | static const char * const mtk_gpio_functions[] = { |
| 47 | "func0", "func1", "func2", "func3", |
| 48 | "func4", "func5", "func6", "func7", |
| 49 | }; |
| 50 | |
| 51 | /* |
| 52 | * There are two base address for pull related configuration |
| 53 | * in mt8135, and different GPIO pins use different base address. |
| 54 | * When pin number greater than type1_start and less than type1_end, |
| 55 | * should use the second base address. |
| 56 | */ |
| 57 | static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl, |
| 58 | unsigned long pin) |
| 59 | { |
| 60 | if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) |
| 61 | return pctl->regmap2; |
| 62 | return pctl->regmap1; |
| 63 | } |
| 64 | |
| 65 | static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin) |
| 66 | { |
| 67 | /* Different SoC has different mask and port shift. */ |
| 68 | return ((pin >> 4) & pctl->devdata->port_mask) |
| 69 | << pctl->devdata->port_shf; |
| 70 | } |
| 71 | |
| 72 | static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, |
| 73 | struct pinctrl_gpio_range *range, unsigned offset, |
| 74 | bool input) |
| 75 | { |
| 76 | unsigned int reg_addr; |
| 77 | unsigned int bit; |
| 78 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 79 | |
| 80 | reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; |
| 81 | bit = BIT(offset & 0xf); |
| 82 | |
| 83 | if (input) |
| 84 | /* Different SoC has different alignment offset. */ |
| 85 | reg_addr = CLR_ADDR(reg_addr, pctl); |
| 86 | else |
| 87 | reg_addr = SET_ADDR(reg_addr, pctl); |
| 88 | |
| 89 | regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); |
| 90 | return 0; |
| 91 | } |
| 92 | |
| 93 | static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 94 | { |
| 95 | unsigned int reg_addr; |
| 96 | unsigned int bit; |
| 97 | struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); |
| 98 | |
| 99 | reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset; |
| 100 | bit = BIT(offset & 0xf); |
| 101 | |
| 102 | if (value) |
| 103 | reg_addr = SET_ADDR(reg_addr, pctl); |
| 104 | else |
| 105 | reg_addr = CLR_ADDR(reg_addr, pctl); |
| 106 | |
| 107 | regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); |
| 108 | } |
| 109 | |
| 110 | static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, |
| 111 | int value, enum pin_config_param param) |
| 112 | { |
| 113 | unsigned int reg_addr, offset; |
| 114 | unsigned int bit; |
Hongzhou Yang | 30f010f | 2015-01-27 15:13:55 +0800 | [diff] [blame] | 115 | int ret; |
| 116 | |
| 117 | /* |
| 118 | * Due to some pins are irregular, their input enable and smt |
| 119 | * control register are discontinuous, but they are mapping together. |
| 120 | * So we need this special handle. |
| 121 | */ |
| 122 | if (pctl->devdata->spec_ies_smt_set) { |
| 123 | ret = pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), |
| 124 | pin, pctl->devdata->port_align, value); |
| 125 | if (!ret) |
| 126 | return; |
| 127 | } |
Hongzhou Yang | a6df410 | 2015-01-21 13:28:15 +0800 | [diff] [blame] | 128 | |
| 129 | bit = BIT(pin & 0xf); |
| 130 | |
| 131 | if (param == PIN_CONFIG_INPUT_ENABLE) |
| 132 | offset = pctl->devdata->ies_offset; |
| 133 | else |
| 134 | offset = pctl->devdata->smt_offset; |
| 135 | |
| 136 | if (value) |
| 137 | reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl); |
| 138 | else |
| 139 | reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); |
| 140 | |
| 141 | regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit); |
| 142 | } |
| 143 | |
| 144 | static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin( |
| 145 | struct mtk_pinctrl *pctl, unsigned long pin) { |
| 146 | int i; |
| 147 | |
| 148 | for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) { |
| 149 | const struct mtk_pin_drv_grp *pin_drv = |
| 150 | pctl->devdata->pin_drv_grp + i; |
| 151 | if (pin == pin_drv->pin) |
| 152 | return pin_drv; |
| 153 | } |
| 154 | |
| 155 | return NULL; |
| 156 | } |
| 157 | |
| 158 | static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl, |
| 159 | unsigned int pin, unsigned char driving) |
| 160 | { |
| 161 | const struct mtk_pin_drv_grp *pin_drv; |
| 162 | unsigned int val; |
| 163 | unsigned int bits, mask, shift; |
| 164 | const struct mtk_drv_group_desc *drv_grp; |
| 165 | |
| 166 | if (pin >= pctl->devdata->npins) |
| 167 | return -EINVAL; |
| 168 | |
| 169 | pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin); |
| 170 | if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls) |
| 171 | return -EINVAL; |
| 172 | |
| 173 | drv_grp = pctl->devdata->grp_desc + pin_drv->grp; |
| 174 | if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv |
| 175 | && !(driving % drv_grp->step)) { |
| 176 | val = driving / drv_grp->step - 1; |
| 177 | bits = drv_grp->high_bit - drv_grp->low_bit + 1; |
| 178 | mask = BIT(bits) - 1; |
| 179 | shift = pin_drv->bit + drv_grp->low_bit; |
| 180 | mask <<= shift; |
| 181 | val <<= shift; |
| 182 | return regmap_update_bits(mtk_get_regmap(pctl, pin), |
| 183 | pin_drv->offset, mask, val); |
| 184 | } |
| 185 | |
| 186 | return -EINVAL; |
| 187 | } |
| 188 | |
| 189 | static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, |
| 190 | unsigned int pin, bool enable, bool isup, unsigned int arg) |
| 191 | { |
| 192 | unsigned int bit; |
| 193 | unsigned int reg_pullen, reg_pullsel; |
| 194 | int ret; |
| 195 | |
| 196 | /* Some pins' pull setting are very different, |
| 197 | * they have separate pull up/down bit, R0 and R1 |
| 198 | * resistor bit, so we need this special handle. |
| 199 | */ |
| 200 | if (pctl->devdata->spec_pull_set) { |
| 201 | ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin), |
| 202 | pin, pctl->devdata->port_align, isup, arg); |
| 203 | if (!ret) |
| 204 | return 0; |
| 205 | } |
| 206 | |
| 207 | /* For generic pull config, default arg value should be 0 or 1. */ |
| 208 | if (arg != 0 && arg != 1) { |
| 209 | dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n", |
| 210 | arg, pin); |
| 211 | return -EINVAL; |
| 212 | } |
| 213 | |
| 214 | bit = BIT(pin & 0xf); |
| 215 | if (enable) |
| 216 | reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) + |
| 217 | pctl->devdata->pullen_offset, pctl); |
| 218 | else |
| 219 | reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) + |
| 220 | pctl->devdata->pullen_offset, pctl); |
| 221 | |
| 222 | if (isup) |
| 223 | reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) + |
| 224 | pctl->devdata->pullsel_offset, pctl); |
| 225 | else |
| 226 | reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) + |
| 227 | pctl->devdata->pullsel_offset, pctl); |
| 228 | |
| 229 | regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit); |
| 230 | regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit); |
| 231 | return 0; |
| 232 | } |
| 233 | |
| 234 | static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev, |
| 235 | unsigned int pin, enum pin_config_param param, |
| 236 | enum pin_config_param arg) |
| 237 | { |
| 238 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 239 | |
| 240 | switch (param) { |
| 241 | case PIN_CONFIG_BIAS_DISABLE: |
| 242 | mtk_pconf_set_pull_select(pctl, pin, false, false, arg); |
| 243 | break; |
| 244 | case PIN_CONFIG_BIAS_PULL_UP: |
| 245 | mtk_pconf_set_pull_select(pctl, pin, true, true, arg); |
| 246 | break; |
| 247 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 248 | mtk_pconf_set_pull_select(pctl, pin, true, false, arg); |
| 249 | break; |
| 250 | case PIN_CONFIG_INPUT_ENABLE: |
| 251 | mtk_pconf_set_ies_smt(pctl, pin, arg, param); |
| 252 | break; |
| 253 | case PIN_CONFIG_OUTPUT: |
| 254 | mtk_gpio_set(pctl->chip, pin, arg); |
| 255 | mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); |
| 256 | break; |
| 257 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: |
| 258 | mtk_pconf_set_ies_smt(pctl, pin, arg, param); |
| 259 | break; |
| 260 | case PIN_CONFIG_DRIVE_STRENGTH: |
| 261 | mtk_pconf_set_driving(pctl, pin, arg); |
| 262 | break; |
| 263 | default: |
| 264 | return -EINVAL; |
| 265 | } |
| 266 | |
| 267 | return 0; |
| 268 | } |
| 269 | |
| 270 | static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, |
| 271 | unsigned group, |
| 272 | unsigned long *config) |
| 273 | { |
| 274 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 275 | |
| 276 | *config = pctl->groups[group].config; |
| 277 | |
| 278 | return 0; |
| 279 | } |
| 280 | |
| 281 | static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, |
| 282 | unsigned long *configs, unsigned num_configs) |
| 283 | { |
| 284 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 285 | struct mtk_pinctrl_group *g = &pctl->groups[group]; |
| 286 | int i; |
| 287 | |
| 288 | for (i = 0; i < num_configs; i++) { |
| 289 | mtk_pconf_parse_conf(pctldev, g->pin, |
| 290 | pinconf_to_config_param(configs[i]), |
| 291 | pinconf_to_config_argument(configs[i])); |
| 292 | |
| 293 | g->config = configs[i]; |
| 294 | } |
| 295 | |
| 296 | return 0; |
| 297 | } |
| 298 | |
| 299 | static const struct pinconf_ops mtk_pconf_ops = { |
| 300 | .pin_config_group_get = mtk_pconf_group_get, |
| 301 | .pin_config_group_set = mtk_pconf_group_set, |
| 302 | }; |
| 303 | |
| 304 | static struct mtk_pinctrl_group * |
| 305 | mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin) |
| 306 | { |
| 307 | int i; |
| 308 | |
| 309 | for (i = 0; i < pctl->ngroups; i++) { |
| 310 | struct mtk_pinctrl_group *grp = pctl->groups + i; |
| 311 | |
| 312 | if (grp->pin == pin) |
| 313 | return grp; |
| 314 | } |
| 315 | |
| 316 | return NULL; |
| 317 | } |
| 318 | |
| 319 | static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin( |
| 320 | struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum) |
| 321 | { |
| 322 | const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num; |
| 323 | const struct mtk_desc_function *func = pin->functions; |
| 324 | |
| 325 | while (func && func->name) { |
| 326 | if (func->muxval == fnum) |
| 327 | return func; |
| 328 | func++; |
| 329 | } |
| 330 | |
| 331 | return NULL; |
| 332 | } |
| 333 | |
| 334 | static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl, |
| 335 | u32 pin_num, u32 fnum) |
| 336 | { |
| 337 | int i; |
| 338 | |
| 339 | for (i = 0; i < pctl->devdata->npins; i++) { |
| 340 | const struct mtk_desc_pin *pin = pctl->devdata->pins + i; |
| 341 | |
| 342 | if (pin->pin.number == pin_num) { |
| 343 | const struct mtk_desc_function *func = |
| 344 | pin->functions; |
| 345 | |
| 346 | while (func && func->name) { |
| 347 | if (func->muxval == fnum) |
| 348 | return true; |
| 349 | func++; |
| 350 | } |
| 351 | |
| 352 | break; |
| 353 | } |
| 354 | } |
| 355 | |
| 356 | return false; |
| 357 | } |
| 358 | |
| 359 | static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl, |
| 360 | u32 pin, u32 fnum, struct mtk_pinctrl_group *grp, |
| 361 | struct pinctrl_map **map, unsigned *reserved_maps, |
| 362 | unsigned *num_maps) |
| 363 | { |
| 364 | bool ret; |
| 365 | |
| 366 | if (*num_maps == *reserved_maps) |
| 367 | return -ENOSPC; |
| 368 | |
| 369 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; |
| 370 | (*map)[*num_maps].data.mux.group = grp->name; |
| 371 | |
| 372 | ret = mtk_pctrl_is_function_valid(pctl, pin, fnum); |
| 373 | if (!ret) { |
| 374 | dev_err(pctl->dev, "invalid function %d on pin %d .\n", |
| 375 | fnum, pin); |
| 376 | return -EINVAL; |
| 377 | } |
| 378 | |
| 379 | (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum]; |
| 380 | (*num_maps)++; |
| 381 | |
| 382 | return 0; |
| 383 | } |
| 384 | |
| 385 | static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, |
| 386 | struct device_node *node, |
| 387 | struct pinctrl_map **map, |
| 388 | unsigned *reserved_maps, |
| 389 | unsigned *num_maps) |
| 390 | { |
| 391 | struct property *pins; |
| 392 | u32 pinfunc, pin, func; |
| 393 | int num_pins, num_funcs, maps_per_pin; |
| 394 | unsigned long *configs; |
| 395 | unsigned int num_configs; |
| 396 | bool has_config = 0; |
| 397 | int i, err; |
| 398 | unsigned reserve = 0; |
| 399 | struct mtk_pinctrl_group *grp; |
| 400 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 401 | |
| 402 | pins = of_find_property(node, "pinmux", NULL); |
| 403 | if (!pins) { |
| 404 | dev_err(pctl->dev, "missing pins property in node %s .\n", |
| 405 | node->name); |
| 406 | return -EINVAL; |
| 407 | } |
| 408 | |
| 409 | err = pinconf_generic_parse_dt_config(node, &configs, &num_configs); |
| 410 | if (num_configs) |
| 411 | has_config = 1; |
| 412 | |
| 413 | num_pins = pins->length / sizeof(u32); |
| 414 | num_funcs = num_pins; |
| 415 | maps_per_pin = 0; |
| 416 | if (num_funcs) |
| 417 | maps_per_pin++; |
| 418 | if (has_config && num_pins >= 1) |
| 419 | maps_per_pin++; |
| 420 | |
| 421 | if (!num_pins || !maps_per_pin) |
| 422 | return -EINVAL; |
| 423 | |
| 424 | reserve = num_pins * maps_per_pin; |
| 425 | |
| 426 | err = pinctrl_utils_reserve_map(pctldev, map, |
| 427 | reserved_maps, num_maps, reserve); |
| 428 | if (err < 0) |
| 429 | goto fail; |
| 430 | |
| 431 | for (i = 0; i < num_pins; i++) { |
| 432 | err = of_property_read_u32_index(node, "pinmux", |
| 433 | i, &pinfunc); |
| 434 | if (err) |
| 435 | goto fail; |
| 436 | |
| 437 | pin = MTK_GET_PIN_NO(pinfunc); |
| 438 | func = MTK_GET_PIN_FUNC(pinfunc); |
| 439 | |
| 440 | if (pin >= pctl->devdata->npins || |
| 441 | func >= ARRAY_SIZE(mtk_gpio_functions)) { |
| 442 | dev_err(pctl->dev, "invalid pins value.\n"); |
| 443 | err = -EINVAL; |
| 444 | goto fail; |
| 445 | } |
| 446 | |
| 447 | grp = mtk_pctrl_find_group_by_pin(pctl, pin); |
| 448 | if (!grp) { |
| 449 | dev_err(pctl->dev, "unable to match pin %d to group\n", |
| 450 | pin); |
| 451 | return -EINVAL; |
| 452 | } |
| 453 | |
| 454 | err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, |
| 455 | reserved_maps, num_maps); |
| 456 | if (err < 0) |
| 457 | goto fail; |
| 458 | |
| 459 | if (has_config) { |
| 460 | err = pinctrl_utils_add_map_configs(pctldev, map, |
| 461 | reserved_maps, num_maps, grp->name, |
| 462 | configs, num_configs, |
| 463 | PIN_MAP_TYPE_CONFIGS_GROUP); |
| 464 | if (err < 0) |
| 465 | goto fail; |
| 466 | } |
| 467 | } |
| 468 | |
| 469 | return 0; |
| 470 | |
| 471 | fail: |
| 472 | return err; |
| 473 | } |
| 474 | |
| 475 | static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, |
| 476 | struct device_node *np_config, |
| 477 | struct pinctrl_map **map, unsigned *num_maps) |
| 478 | { |
| 479 | struct device_node *np; |
| 480 | unsigned reserved_maps; |
| 481 | int ret; |
| 482 | |
| 483 | *map = NULL; |
| 484 | *num_maps = 0; |
| 485 | reserved_maps = 0; |
| 486 | |
| 487 | for_each_child_of_node(np_config, np) { |
| 488 | ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map, |
| 489 | &reserved_maps, num_maps); |
| 490 | if (ret < 0) { |
| 491 | pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); |
| 492 | return ret; |
| 493 | } |
| 494 | } |
| 495 | |
| 496 | return 0; |
| 497 | } |
| 498 | |
| 499 | static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev) |
| 500 | { |
| 501 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 502 | |
| 503 | return pctl->ngroups; |
| 504 | } |
| 505 | |
| 506 | static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev, |
| 507 | unsigned group) |
| 508 | { |
| 509 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 510 | |
| 511 | return pctl->groups[group].name; |
| 512 | } |
| 513 | |
| 514 | static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev, |
| 515 | unsigned group, |
| 516 | const unsigned **pins, |
| 517 | unsigned *num_pins) |
| 518 | { |
| 519 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 520 | |
| 521 | *pins = (unsigned *)&pctl->groups[group].pin; |
| 522 | *num_pins = 1; |
| 523 | |
| 524 | return 0; |
| 525 | } |
| 526 | |
| 527 | static const struct pinctrl_ops mtk_pctrl_ops = { |
| 528 | .dt_node_to_map = mtk_pctrl_dt_node_to_map, |
| 529 | .dt_free_map = pinctrl_utils_dt_free_map, |
| 530 | .get_groups_count = mtk_pctrl_get_groups_count, |
| 531 | .get_group_name = mtk_pctrl_get_group_name, |
| 532 | .get_group_pins = mtk_pctrl_get_group_pins, |
| 533 | }; |
| 534 | |
| 535 | static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
| 536 | { |
| 537 | return ARRAY_SIZE(mtk_gpio_functions); |
| 538 | } |
| 539 | |
| 540 | static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev, |
| 541 | unsigned selector) |
| 542 | { |
| 543 | return mtk_gpio_functions[selector]; |
| 544 | } |
| 545 | |
| 546 | static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev, |
| 547 | unsigned function, |
| 548 | const char * const **groups, |
| 549 | unsigned * const num_groups) |
| 550 | { |
| 551 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 552 | |
| 553 | *groups = pctl->grp_names; |
| 554 | *num_groups = pctl->ngroups; |
| 555 | |
| 556 | return 0; |
| 557 | } |
| 558 | |
| 559 | static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev, |
| 560 | unsigned long pin, unsigned long mode) |
| 561 | { |
| 562 | unsigned int reg_addr; |
| 563 | unsigned char bit; |
| 564 | unsigned int val; |
| 565 | unsigned int mask = (1L << GPIO_MODE_BITS) - 1; |
| 566 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 567 | |
| 568 | reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf) |
| 569 | + pctl->devdata->pinmux_offset; |
| 570 | |
| 571 | bit = pin % MAX_GPIO_MODE_PER_REG; |
| 572 | mask <<= (GPIO_MODE_BITS * bit); |
| 573 | val = (mode << (GPIO_MODE_BITS * bit)); |
| 574 | return regmap_update_bits(mtk_get_regmap(pctl, pin), |
| 575 | reg_addr, mask, val); |
| 576 | } |
| 577 | |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 578 | static const struct mtk_desc_pin * |
| 579 | mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num) |
| 580 | { |
| 581 | int i; |
| 582 | const struct mtk_desc_pin *pin; |
| 583 | |
| 584 | for (i = 0; i < pctl->devdata->npins; i++) { |
| 585 | pin = pctl->devdata->pins + i; |
| 586 | if (pin->eint.eintnum == eint_num) |
| 587 | return pin; |
| 588 | } |
| 589 | |
| 590 | return NULL; |
| 591 | } |
| 592 | |
Hongzhou Yang | a6df410 | 2015-01-21 13:28:15 +0800 | [diff] [blame] | 593 | static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev, |
| 594 | unsigned function, |
| 595 | unsigned group) |
| 596 | { |
| 597 | bool ret; |
| 598 | const struct mtk_desc_function *desc; |
| 599 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
| 600 | struct mtk_pinctrl_group *g = pctl->groups + group; |
| 601 | |
| 602 | ret = mtk_pctrl_is_function_valid(pctl, g->pin, function); |
| 603 | if (!ret) { |
| 604 | dev_err(pctl->dev, "invaild function %d on group %d .\n", |
| 605 | function, group); |
| 606 | return -EINVAL; |
| 607 | } |
| 608 | |
| 609 | desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function); |
| 610 | if (!desc) |
| 611 | return -EINVAL; |
| 612 | mtk_pmx_set_mode(pctldev, g->pin, desc->muxval); |
| 613 | return 0; |
| 614 | } |
| 615 | |
| 616 | static const struct pinmux_ops mtk_pmx_ops = { |
| 617 | .get_functions_count = mtk_pmx_get_funcs_cnt, |
| 618 | .get_function_name = mtk_pmx_get_func_name, |
| 619 | .get_function_groups = mtk_pmx_get_func_groups, |
| 620 | .set_mux = mtk_pmx_set_mux, |
| 621 | .gpio_set_direction = mtk_pmx_gpio_set_direction, |
| 622 | }; |
| 623 | |
| 624 | static int mtk_gpio_request(struct gpio_chip *chip, unsigned offset) |
| 625 | { |
| 626 | return pinctrl_request_gpio(chip->base + offset); |
| 627 | } |
| 628 | |
| 629 | static void mtk_gpio_free(struct gpio_chip *chip, unsigned offset) |
| 630 | { |
| 631 | pinctrl_free_gpio(chip->base + offset); |
| 632 | } |
| 633 | |
| 634 | static int mtk_gpio_direction_input(struct gpio_chip *chip, |
| 635 | unsigned offset) |
| 636 | { |
| 637 | return pinctrl_gpio_direction_input(chip->base + offset); |
| 638 | } |
| 639 | |
| 640 | static int mtk_gpio_direction_output(struct gpio_chip *chip, |
| 641 | unsigned offset, int value) |
| 642 | { |
| 643 | mtk_gpio_set(chip, offset, value); |
| 644 | return pinctrl_gpio_direction_output(chip->base + offset); |
| 645 | } |
| 646 | |
| 647 | static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
| 648 | { |
| 649 | unsigned int reg_addr; |
| 650 | unsigned int bit; |
| 651 | unsigned int read_val = 0; |
| 652 | |
| 653 | struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); |
| 654 | |
| 655 | reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; |
| 656 | bit = BIT(offset & 0xf); |
| 657 | regmap_read(pctl->regmap1, reg_addr, &read_val); |
| 658 | return !!(read_val & bit); |
| 659 | } |
| 660 | |
| 661 | static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 662 | { |
| 663 | unsigned int reg_addr; |
| 664 | unsigned int bit; |
| 665 | unsigned int read_val = 0; |
| 666 | struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); |
| 667 | |
| 668 | if (mtk_gpio_get_direction(chip, offset)) |
| 669 | reg_addr = mtk_get_port(pctl, offset) + |
| 670 | pctl->devdata->dout_offset; |
| 671 | else |
| 672 | reg_addr = mtk_get_port(pctl, offset) + |
| 673 | pctl->devdata->din_offset; |
| 674 | |
| 675 | bit = BIT(offset & 0xf); |
| 676 | regmap_read(pctl->regmap1, reg_addr, &read_val); |
| 677 | return !!(read_val & bit); |
| 678 | } |
| 679 | |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 680 | static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
| 681 | { |
| 682 | const struct mtk_desc_pin *pin; |
| 683 | struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); |
| 684 | int irq; |
| 685 | |
| 686 | pin = pctl->devdata->pins + offset; |
| 687 | if (pin->eint.eintnum == NO_EINT_SUPPORT) |
| 688 | return -EINVAL; |
| 689 | |
| 690 | irq = irq_find_mapping(pctl->domain, pin->eint.eintnum); |
| 691 | if (!irq) |
| 692 | return -EINVAL; |
| 693 | |
| 694 | return irq; |
| 695 | } |
| 696 | |
| 697 | static int mtk_pinctrl_irq_request_resources(struct irq_data *d) |
| 698 | { |
| 699 | struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); |
| 700 | const struct mtk_desc_pin *pin; |
| 701 | int ret; |
| 702 | |
| 703 | pin = mtk_find_pin_by_eint_num(pctl, d->hwirq); |
| 704 | |
| 705 | if (!pin) { |
| 706 | dev_err(pctl->dev, "Can not find pin\n"); |
| 707 | return -EINVAL; |
| 708 | } |
| 709 | |
| 710 | ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number); |
| 711 | if (ret) { |
| 712 | dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", |
| 713 | irqd_to_hwirq(d)); |
| 714 | return ret; |
| 715 | } |
| 716 | |
| 717 | /* set mux to INT mode */ |
| 718 | mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux); |
| 719 | |
| 720 | return 0; |
| 721 | } |
| 722 | |
| 723 | static void mtk_pinctrl_irq_release_resources(struct irq_data *d) |
| 724 | { |
| 725 | struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); |
| 726 | const struct mtk_desc_pin *pin; |
| 727 | |
| 728 | pin = mtk_find_pin_by_eint_num(pctl, d->hwirq); |
| 729 | |
| 730 | if (!pin) { |
| 731 | dev_err(pctl->dev, "Can not find pin\n"); |
| 732 | return; |
| 733 | } |
| 734 | |
| 735 | gpiochip_unlock_as_irq(pctl->chip, pin->pin.number); |
| 736 | } |
| 737 | |
| 738 | static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl, |
| 739 | unsigned int eint_num, unsigned int offset) |
| 740 | { |
| 741 | unsigned int eint_base = 0; |
| 742 | void __iomem *reg; |
| 743 | |
| 744 | if (eint_num >= pctl->devdata->ap_num) |
| 745 | eint_base = pctl->devdata->ap_num; |
| 746 | |
| 747 | reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4; |
| 748 | |
| 749 | return reg; |
| 750 | } |
| 751 | |
| 752 | /* |
| 753 | * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not |
| 754 | * @eint_num: the EINT number to setmtk_pinctrl |
| 755 | */ |
| 756 | static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl, |
| 757 | unsigned int eint_num) |
| 758 | { |
| 759 | unsigned int sens; |
| 760 | unsigned int bit = BIT(eint_num % 32); |
| 761 | const struct mtk_eint_offsets *eint_offsets = |
| 762 | &pctl->devdata->eint_offsets; |
| 763 | |
| 764 | void __iomem *reg = mtk_eint_get_offset(pctl, eint_num, |
| 765 | eint_offsets->sens); |
| 766 | |
| 767 | if (readl(reg) & bit) |
| 768 | sens = MT_LEVEL_SENSITIVE; |
| 769 | else |
| 770 | sens = MT_EDGE_SENSITIVE; |
| 771 | |
| 772 | if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE)) |
| 773 | return 1; |
| 774 | else |
| 775 | return 0; |
| 776 | } |
| 777 | |
| 778 | /* |
| 779 | * mtk_eint_get_mask: To get the eint mask |
| 780 | * @eint_num: the EINT number to get |
| 781 | */ |
| 782 | static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl, |
| 783 | unsigned int eint_num) |
| 784 | { |
| 785 | unsigned int bit = BIT(eint_num % 32); |
| 786 | const struct mtk_eint_offsets *eint_offsets = |
| 787 | &pctl->devdata->eint_offsets; |
| 788 | |
| 789 | void __iomem *reg = mtk_eint_get_offset(pctl, eint_num, |
| 790 | eint_offsets->mask); |
| 791 | |
| 792 | return !!(readl(reg) & bit); |
| 793 | } |
| 794 | |
Yingjoe Chen | 3221f40 | 2015-01-27 14:15:26 +0800 | [diff] [blame^] | 795 | static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq) |
| 796 | { |
| 797 | int start_level, curr_level; |
| 798 | unsigned int reg_offset; |
| 799 | const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets); |
| 800 | u32 mask = 1 << (hwirq & 0x1f); |
| 801 | u32 port = (hwirq >> 5) & eint_offsets->port_mask; |
| 802 | void __iomem *reg = pctl->eint_reg_base + (port << 2); |
| 803 | const struct mtk_desc_pin *pin; |
| 804 | |
| 805 | pin = mtk_find_pin_by_eint_num(pctl, hwirq); |
| 806 | curr_level = mtk_gpio_get(pctl->chip, pin->pin.number); |
| 807 | do { |
| 808 | start_level = curr_level; |
| 809 | if (start_level) |
| 810 | reg_offset = eint_offsets->pol_clr; |
| 811 | else |
| 812 | reg_offset = eint_offsets->pol_set; |
| 813 | writel(mask, reg + reg_offset); |
| 814 | |
| 815 | curr_level = mtk_gpio_get(pctl->chip, pin->pin.number); |
| 816 | } while (start_level != curr_level); |
| 817 | |
| 818 | return start_level; |
| 819 | } |
| 820 | |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 821 | static void mtk_eint_mask(struct irq_data *d) |
| 822 | { |
| 823 | struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); |
| 824 | const struct mtk_eint_offsets *eint_offsets = |
| 825 | &pctl->devdata->eint_offsets; |
| 826 | u32 mask = BIT(d->hwirq & 0x1f); |
| 827 | void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, |
| 828 | eint_offsets->mask_set); |
| 829 | |
| 830 | writel(mask, reg); |
| 831 | } |
| 832 | |
| 833 | static void mtk_eint_unmask(struct irq_data *d) |
| 834 | { |
| 835 | struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); |
| 836 | const struct mtk_eint_offsets *eint_offsets = |
| 837 | &pctl->devdata->eint_offsets; |
| 838 | u32 mask = BIT(d->hwirq & 0x1f); |
| 839 | void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, |
| 840 | eint_offsets->mask_clr); |
| 841 | |
| 842 | writel(mask, reg); |
Yingjoe Chen | 3221f40 | 2015-01-27 14:15:26 +0800 | [diff] [blame^] | 843 | |
| 844 | if (pctl->eint_dual_edges[d->hwirq]) |
| 845 | mtk_eint_flip_edge(pctl, d->hwirq); |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 846 | } |
| 847 | |
| 848 | static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset, |
| 849 | unsigned debounce) |
| 850 | { |
| 851 | struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); |
| 852 | int eint_num, virq, eint_offset; |
| 853 | unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc; |
| 854 | static const unsigned int dbnc_arr[] = {0 , 1, 16, 32, 64, 128, 256}; |
| 855 | const struct mtk_desc_pin *pin; |
| 856 | struct irq_data *d; |
| 857 | |
| 858 | pin = pctl->devdata->pins + offset; |
| 859 | if (pin->eint.eintnum == NO_EINT_SUPPORT) |
| 860 | return -EINVAL; |
| 861 | |
| 862 | eint_num = pin->eint.eintnum; |
| 863 | virq = irq_find_mapping(pctl->domain, eint_num); |
| 864 | eint_offset = (eint_num % 4) * 8; |
| 865 | d = irq_get_irq_data(virq); |
| 866 | |
| 867 | set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set; |
| 868 | clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr; |
| 869 | if (!mtk_eint_can_en_debounce(pctl, eint_num)) |
| 870 | return -ENOSYS; |
| 871 | |
| 872 | dbnc = ARRAY_SIZE(dbnc_arr); |
| 873 | for (i = 0; i < ARRAY_SIZE(dbnc_arr); i++) { |
| 874 | if (debounce <= dbnc_arr[i]) { |
| 875 | dbnc = i; |
| 876 | break; |
| 877 | } |
| 878 | } |
| 879 | |
| 880 | if (!mtk_eint_get_mask(pctl, eint_num)) { |
| 881 | mtk_eint_mask(d); |
| 882 | unmask = 1; |
| 883 | } |
| 884 | |
| 885 | clr_bit = 0xff << eint_offset; |
| 886 | writel(clr_bit, pctl->eint_reg_base + clr_offset); |
| 887 | |
| 888 | bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) << |
| 889 | eint_offset; |
| 890 | rst = EINT_DBNC_RST_BIT << eint_offset; |
| 891 | writel(rst | bit, pctl->eint_reg_base + set_offset); |
| 892 | |
| 893 | /* Delay a while (more than 2T) to wait for hw debounce counter reset |
| 894 | work correctly */ |
| 895 | udelay(1); |
| 896 | if (unmask == 1) |
| 897 | mtk_eint_unmask(d); |
| 898 | |
| 899 | return 0; |
| 900 | } |
| 901 | |
Hongzhou Yang | a6df410 | 2015-01-21 13:28:15 +0800 | [diff] [blame] | 902 | static struct gpio_chip mtk_gpio_chip = { |
| 903 | .owner = THIS_MODULE, |
| 904 | .request = mtk_gpio_request, |
| 905 | .free = mtk_gpio_free, |
| 906 | .direction_input = mtk_gpio_direction_input, |
| 907 | .direction_output = mtk_gpio_direction_output, |
| 908 | .get = mtk_gpio_get, |
| 909 | .set = mtk_gpio_set, |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 910 | .to_irq = mtk_gpio_to_irq, |
| 911 | .set_debounce = mtk_gpio_set_debounce, |
Hongzhou Yang | a6df410 | 2015-01-21 13:28:15 +0800 | [diff] [blame] | 912 | .of_gpio_n_cells = 2, |
| 913 | }; |
| 914 | |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 915 | static int mtk_eint_set_type(struct irq_data *d, |
| 916 | unsigned int type) |
| 917 | { |
| 918 | struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); |
| 919 | const struct mtk_eint_offsets *eint_offsets = |
| 920 | &pctl->devdata->eint_offsets; |
| 921 | u32 mask = BIT(d->hwirq & 0x1f); |
| 922 | void __iomem *reg; |
| 923 | |
| 924 | if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) || |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 925 | ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) { |
| 926 | dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n", |
| 927 | d->irq, d->hwirq, type); |
| 928 | return -EINVAL; |
| 929 | } |
| 930 | |
Yingjoe Chen | 3221f40 | 2015-01-27 14:15:26 +0800 | [diff] [blame^] | 931 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) |
| 932 | pctl->eint_dual_edges[d->hwirq] = 1; |
| 933 | else |
| 934 | pctl->eint_dual_edges[d->hwirq] = 0; |
| 935 | |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 936 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) { |
| 937 | reg = mtk_eint_get_offset(pctl, d->hwirq, |
| 938 | eint_offsets->pol_clr); |
| 939 | writel(mask, reg); |
| 940 | } else { |
| 941 | reg = mtk_eint_get_offset(pctl, d->hwirq, |
| 942 | eint_offsets->pol_set); |
| 943 | writel(mask, reg); |
| 944 | } |
| 945 | |
| 946 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
| 947 | reg = mtk_eint_get_offset(pctl, d->hwirq, |
| 948 | eint_offsets->sens_clr); |
| 949 | writel(mask, reg); |
| 950 | } else { |
| 951 | reg = mtk_eint_get_offset(pctl, d->hwirq, |
| 952 | eint_offsets->sens_set); |
| 953 | writel(mask, reg); |
| 954 | } |
| 955 | |
Yingjoe Chen | 3221f40 | 2015-01-27 14:15:26 +0800 | [diff] [blame^] | 956 | if (pctl->eint_dual_edges[d->hwirq]) |
| 957 | mtk_eint_flip_edge(pctl, d->hwirq); |
| 958 | |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 959 | return 0; |
| 960 | } |
| 961 | |
| 962 | static void mtk_eint_ack(struct irq_data *d) |
| 963 | { |
| 964 | struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); |
| 965 | const struct mtk_eint_offsets *eint_offsets = |
| 966 | &pctl->devdata->eint_offsets; |
| 967 | u32 mask = BIT(d->hwirq & 0x1f); |
| 968 | void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, |
| 969 | eint_offsets->ack); |
| 970 | |
| 971 | writel(mask, reg); |
| 972 | } |
| 973 | |
| 974 | static struct irq_chip mtk_pinctrl_irq_chip = { |
| 975 | .name = "mt-eint", |
| 976 | .irq_mask = mtk_eint_mask, |
| 977 | .irq_unmask = mtk_eint_unmask, |
| 978 | .irq_ack = mtk_eint_ack, |
| 979 | .irq_set_type = mtk_eint_set_type, |
| 980 | .irq_request_resources = mtk_pinctrl_irq_request_resources, |
| 981 | .irq_release_resources = mtk_pinctrl_irq_release_resources, |
| 982 | }; |
| 983 | |
| 984 | static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl) |
| 985 | { |
| 986 | const struct mtk_eint_offsets *eint_offsets = |
| 987 | &pctl->devdata->eint_offsets; |
| 988 | void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en; |
| 989 | unsigned int i; |
| 990 | |
| 991 | for (i = 0; i < pctl->devdata->ap_num; i += 32) { |
| 992 | writel(0xffffffff, reg); |
| 993 | reg += 4; |
| 994 | } |
| 995 | return 0; |
| 996 | } |
| 997 | |
| 998 | static inline void |
| 999 | mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index) |
| 1000 | { |
| 1001 | unsigned int rst, ctrl_offset; |
| 1002 | unsigned int bit, dbnc; |
| 1003 | const struct mtk_eint_offsets *eint_offsets = |
| 1004 | &pctl->devdata->eint_offsets; |
| 1005 | |
| 1006 | ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl; |
| 1007 | dbnc = readl(pctl->eint_reg_base + ctrl_offset); |
| 1008 | bit = EINT_DBNC_SET_EN << ((index % 4) * 8); |
| 1009 | if ((bit & dbnc) > 0) { |
| 1010 | ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set; |
| 1011 | rst = EINT_DBNC_RST_BIT << ((index % 4) * 8); |
| 1012 | writel(rst, pctl->eint_reg_base + ctrl_offset); |
| 1013 | } |
| 1014 | } |
| 1015 | |
| 1016 | static void mtk_eint_irq_handler(unsigned irq, struct irq_desc *desc) |
| 1017 | { |
| 1018 | struct irq_chip *chip = irq_get_chip(irq); |
| 1019 | struct mtk_pinctrl *pctl = irq_get_handler_data(irq); |
| 1020 | unsigned int status, eint_num; |
| 1021 | int offset, index, virq; |
| 1022 | const struct mtk_eint_offsets *eint_offsets = |
| 1023 | &pctl->devdata->eint_offsets; |
| 1024 | void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat); |
Yingjoe Chen | 3221f40 | 2015-01-27 14:15:26 +0800 | [diff] [blame^] | 1025 | int dual_edges, start_level, curr_level; |
| 1026 | const struct mtk_desc_pin *pin; |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 1027 | |
| 1028 | chained_irq_enter(chip, desc); |
| 1029 | for (eint_num = 0; eint_num < pctl->devdata->ap_num; eint_num += 32) { |
| 1030 | status = readl(reg); |
| 1031 | reg += 4; |
| 1032 | while (status) { |
| 1033 | offset = __ffs(status); |
| 1034 | index = eint_num + offset; |
| 1035 | virq = irq_find_mapping(pctl->domain, index); |
| 1036 | status &= ~BIT(offset); |
| 1037 | |
Yingjoe Chen | 3221f40 | 2015-01-27 14:15:26 +0800 | [diff] [blame^] | 1038 | dual_edges = pctl->eint_dual_edges[index]; |
| 1039 | if (dual_edges) { |
| 1040 | /* Clear soft-irq in case we raised it |
| 1041 | last time */ |
| 1042 | writel(BIT(offset), reg - eint_offsets->stat + |
| 1043 | eint_offsets->soft_clr); |
| 1044 | |
| 1045 | pin = mtk_find_pin_by_eint_num(pctl, index); |
| 1046 | start_level = mtk_gpio_get(pctl->chip, |
| 1047 | pin->pin.number); |
| 1048 | } |
| 1049 | |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 1050 | generic_handle_irq(virq); |
| 1051 | |
Yingjoe Chen | 3221f40 | 2015-01-27 14:15:26 +0800 | [diff] [blame^] | 1052 | if (dual_edges) { |
| 1053 | curr_level = mtk_eint_flip_edge(pctl, index); |
| 1054 | |
| 1055 | /* If level changed, we might lost one edge |
| 1056 | interrupt, raised it through soft-irq */ |
| 1057 | if (start_level != curr_level) |
| 1058 | writel(BIT(offset), reg - |
| 1059 | eint_offsets->stat + |
| 1060 | eint_offsets->soft_set); |
| 1061 | } |
| 1062 | |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 1063 | if (index < pctl->devdata->db_cnt) |
| 1064 | mtk_eint_debounce_process(pctl , index); |
| 1065 | } |
| 1066 | } |
| 1067 | chained_irq_exit(chip, desc); |
| 1068 | } |
| 1069 | |
Hongzhou Yang | a6df410 | 2015-01-21 13:28:15 +0800 | [diff] [blame] | 1070 | static int mtk_pctrl_build_state(struct platform_device *pdev) |
| 1071 | { |
| 1072 | struct mtk_pinctrl *pctl = platform_get_drvdata(pdev); |
| 1073 | int i; |
| 1074 | |
| 1075 | pctl->ngroups = pctl->devdata->npins; |
| 1076 | |
| 1077 | /* Allocate groups */ |
| 1078 | pctl->groups = devm_kzalloc(&pdev->dev, |
| 1079 | pctl->ngroups * sizeof(*pctl->groups), |
| 1080 | GFP_KERNEL); |
| 1081 | if (!pctl->groups) |
| 1082 | return -ENOMEM; |
| 1083 | |
| 1084 | /* We assume that one pin is one group, use pin name as group name. */ |
| 1085 | pctl->grp_names = devm_kzalloc(&pdev->dev, |
| 1086 | pctl->ngroups * sizeof(*pctl->grp_names), |
| 1087 | GFP_KERNEL); |
| 1088 | if (!pctl->grp_names) |
| 1089 | return -ENOMEM; |
| 1090 | |
| 1091 | for (i = 0; i < pctl->devdata->npins; i++) { |
| 1092 | const struct mtk_desc_pin *pin = pctl->devdata->pins + i; |
| 1093 | struct mtk_pinctrl_group *group = pctl->groups + i; |
| 1094 | |
| 1095 | group->name = pin->pin.name; |
| 1096 | group->pin = pin->pin.number; |
| 1097 | |
| 1098 | pctl->grp_names[i] = pin->pin.name; |
| 1099 | } |
| 1100 | |
| 1101 | return 0; |
| 1102 | } |
| 1103 | |
| 1104 | static struct pinctrl_desc mtk_pctrl_desc = { |
| 1105 | .confops = &mtk_pconf_ops, |
| 1106 | .pctlops = &mtk_pctrl_ops, |
| 1107 | .pmxops = &mtk_pmx_ops, |
| 1108 | }; |
| 1109 | |
| 1110 | int mtk_pctrl_init(struct platform_device *pdev, |
| 1111 | const struct mtk_pinctrl_devdata *data) |
| 1112 | { |
| 1113 | struct pinctrl_pin_desc *pins; |
| 1114 | struct mtk_pinctrl *pctl; |
| 1115 | struct device_node *np = pdev->dev.of_node, *node; |
| 1116 | struct property *prop; |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 1117 | struct resource *res; |
| 1118 | int i, ret, irq; |
Hongzhou Yang | a6df410 | 2015-01-21 13:28:15 +0800 | [diff] [blame] | 1119 | |
| 1120 | pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); |
| 1121 | if (!pctl) |
| 1122 | return -ENOMEM; |
| 1123 | |
| 1124 | platform_set_drvdata(pdev, pctl); |
| 1125 | |
| 1126 | prop = of_find_property(np, "pins-are-numbered", NULL); |
| 1127 | if (!prop) { |
| 1128 | dev_err(&pdev->dev, "only support pins-are-numbered format\n", ret); |
| 1129 | return -EINVAL; |
| 1130 | } |
| 1131 | |
| 1132 | node = of_parse_phandle(np, "mediatek,pctl-regmap", 0); |
| 1133 | if (node) { |
| 1134 | pctl->regmap1 = syscon_node_to_regmap(node); |
| 1135 | if (IS_ERR(pctl->regmap1)) |
| 1136 | return PTR_ERR(pctl->regmap1); |
| 1137 | } |
| 1138 | |
| 1139 | /* Only 8135 has two base addr, other SoCs have only one. */ |
| 1140 | node = of_parse_phandle(np, "mediatek,pctl-regmap", 1); |
| 1141 | if (node) { |
| 1142 | pctl->regmap2 = syscon_node_to_regmap(node); |
| 1143 | if (IS_ERR(pctl->regmap2)) |
| 1144 | return PTR_ERR(pctl->regmap2); |
| 1145 | } |
| 1146 | |
| 1147 | pctl->devdata = data; |
| 1148 | ret = mtk_pctrl_build_state(pdev); |
| 1149 | if (ret) { |
| 1150 | dev_err(&pdev->dev, "build state failed: %d\n", ret); |
| 1151 | return -EINVAL; |
| 1152 | } |
| 1153 | |
| 1154 | pins = devm_kzalloc(&pdev->dev, |
| 1155 | pctl->devdata->npins * sizeof(*pins), |
| 1156 | GFP_KERNEL); |
| 1157 | if (!pins) |
| 1158 | return -ENOMEM; |
| 1159 | |
| 1160 | for (i = 0; i < pctl->devdata->npins; i++) |
| 1161 | pins[i] = pctl->devdata->pins[i].pin; |
| 1162 | mtk_pctrl_desc.name = dev_name(&pdev->dev); |
| 1163 | mtk_pctrl_desc.owner = THIS_MODULE; |
| 1164 | mtk_pctrl_desc.pins = pins; |
| 1165 | mtk_pctrl_desc.npins = pctl->devdata->npins; |
| 1166 | pctl->dev = &pdev->dev; |
| 1167 | pctl->pctl_dev = pinctrl_register(&mtk_pctrl_desc, &pdev->dev, pctl); |
| 1168 | if (!pctl->pctl_dev) { |
| 1169 | dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); |
| 1170 | return -EINVAL; |
| 1171 | } |
| 1172 | |
| 1173 | pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); |
| 1174 | if (!pctl->chip) { |
| 1175 | ret = -ENOMEM; |
| 1176 | goto pctrl_error; |
| 1177 | } |
| 1178 | |
| 1179 | pctl->chip = &mtk_gpio_chip; |
| 1180 | pctl->chip->ngpio = pctl->devdata->npins; |
| 1181 | pctl->chip->label = dev_name(&pdev->dev); |
| 1182 | pctl->chip->dev = &pdev->dev; |
| 1183 | pctl->chip->base = 0; |
| 1184 | |
| 1185 | ret = gpiochip_add(pctl->chip); |
| 1186 | if (ret) { |
| 1187 | ret = -EINVAL; |
| 1188 | goto pctrl_error; |
| 1189 | } |
| 1190 | |
| 1191 | /* Register the GPIO to pin mappings. */ |
| 1192 | ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), |
| 1193 | 0, 0, pctl->devdata->npins); |
| 1194 | if (ret) { |
| 1195 | ret = -EINVAL; |
| 1196 | goto chip_error; |
| 1197 | } |
| 1198 | |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 1199 | /* Get EINT register base from dts. */ |
| 1200 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1201 | if (!res) { |
| 1202 | dev_err(&pdev->dev, "Unable to get Pinctrl resource\n"); |
| 1203 | ret = -EINVAL; |
| 1204 | goto chip_error; |
| 1205 | } |
| 1206 | |
| 1207 | pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res); |
| 1208 | if (IS_ERR(pctl->eint_reg_base)) { |
| 1209 | ret = -EINVAL; |
| 1210 | goto chip_error; |
| 1211 | } |
| 1212 | |
Yingjoe Chen | 3221f40 | 2015-01-27 14:15:26 +0800 | [diff] [blame^] | 1213 | pctl->eint_dual_edges = devm_kzalloc(&pdev->dev, |
| 1214 | sizeof(int) * pctl->devdata->ap_num, GFP_KERNEL); |
| 1215 | if (!pctl->eint_dual_edges) { |
| 1216 | ret = -ENOMEM; |
| 1217 | goto chip_error; |
| 1218 | } |
| 1219 | |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 1220 | irq = irq_of_parse_and_map(np, 0); |
| 1221 | if (!irq) { |
| 1222 | dev_err(&pdev->dev, "couldn't parse and map irq\n"); |
| 1223 | ret = -EINVAL; |
Yingjoe Chen | 3221f40 | 2015-01-27 14:15:26 +0800 | [diff] [blame^] | 1224 | goto free_edges; |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 1225 | } |
| 1226 | |
| 1227 | pctl->domain = irq_domain_add_linear(np, |
| 1228 | pctl->devdata->ap_num, &irq_domain_simple_ops, NULL); |
| 1229 | if (!pctl->domain) { |
| 1230 | dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); |
| 1231 | ret = -ENOMEM; |
Yingjoe Chen | 3221f40 | 2015-01-27 14:15:26 +0800 | [diff] [blame^] | 1232 | goto free_edges; |
Maoguang Meng | d9819eb | 2015-01-21 13:28:16 +0800 | [diff] [blame] | 1233 | } |
| 1234 | |
| 1235 | mtk_eint_init(pctl); |
| 1236 | for (i = 0; i < pctl->devdata->ap_num; i++) { |
| 1237 | int virq = irq_create_mapping(pctl->domain, i); |
| 1238 | |
| 1239 | irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip, |
| 1240 | handle_level_irq); |
| 1241 | irq_set_chip_data(virq, pctl); |
| 1242 | set_irq_flags(virq, IRQF_VALID); |
| 1243 | }; |
| 1244 | |
| 1245 | irq_set_chained_handler(irq, mtk_eint_irq_handler); |
| 1246 | irq_set_handler_data(irq, pctl); |
| 1247 | set_irq_flags(irq, IRQF_VALID); |
Hongzhou Yang | a6df410 | 2015-01-21 13:28:15 +0800 | [diff] [blame] | 1248 | return 0; |
| 1249 | |
Yingjoe Chen | 3221f40 | 2015-01-27 14:15:26 +0800 | [diff] [blame^] | 1250 | free_edges: |
| 1251 | kfree(pctl->eint_dual_edges); |
Hongzhou Yang | a6df410 | 2015-01-21 13:28:15 +0800 | [diff] [blame] | 1252 | chip_error: |
| 1253 | gpiochip_remove(pctl->chip); |
| 1254 | pctrl_error: |
| 1255 | pinctrl_unregister(pctl->pctl_dev); |
| 1256 | return ret; |
| 1257 | } |
| 1258 | |
| 1259 | MODULE_LICENSE("GPL"); |
| 1260 | MODULE_DESCRIPTION("MediaTek Pinctrl Driver"); |
| 1261 | MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>"); |