Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 2 | * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 4 | * Based on linux/arch/mips/pci/ops-tx4938.c, |
| 5 | * linux/arch/mips/pci/fixup-rbtx4938.c, |
| 6 | * linux/arch/mips/txx9/rbtx4938/setup.c, |
| 7 | * and RBTX49xx patch from CELF patch archive. |
| 8 | * |
| 9 | * 2003-2005 (c) MontaVista Software, Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 11 | * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | * |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 13 | * This program is free software; you can redistribute it and/or modify it |
| 14 | * under the terms of the GNU General Public License as published by the |
| 15 | * Free Software Foundation; either version 2 of the License, or (at your |
| 16 | * option) any later version. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #include <linux/kernel.h> |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 19 | #include <asm/txx9/tx4927pcic.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 21 | static struct { |
| 22 | struct pci_controller *channel; |
| 23 | struct tx4927_pcic_reg __iomem *pcicptr; |
| 24 | } pcicptrs[2]; /* TX4938 has 2 pcic */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 26 | static void __init set_tx4927_pcicptr(struct pci_controller *channel, |
| 27 | struct tx4927_pcic_reg __iomem *pcicptr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | { |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 29 | int i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 31 | for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { |
| 32 | if (pcicptrs[i].channel == channel) { |
| 33 | pcicptrs[i].pcicptr = pcicptr; |
| 34 | return; |
| 35 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | } |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 37 | for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { |
| 38 | if (!pcicptrs[i].channel) { |
| 39 | pcicptrs[i].channel = channel; |
| 40 | pcicptrs[i].pcicptr = pcicptr; |
| 41 | return; |
| 42 | } |
| 43 | } |
| 44 | BUG(); |
| 45 | } |
| 46 | |
| 47 | struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr( |
| 48 | struct pci_controller *channel) |
| 49 | { |
| 50 | int i; |
| 51 | |
| 52 | for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { |
| 53 | if (pcicptrs[i].channel == channel) |
| 54 | return pcicptrs[i].pcicptr; |
| 55 | } |
| 56 | return NULL; |
| 57 | } |
| 58 | |
| 59 | static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where, |
| 60 | struct tx4927_pcic_reg __iomem *pcicptr) |
| 61 | { |
| 62 | if (bus->parent == NULL && |
| 63 | devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0)) |
| 64 | return -1; |
| 65 | __raw_writel(((bus->number & 0xff) << 0x10) |
| 66 | | ((devfn & 0xff) << 0x08) | (where & 0xfc) |
| 67 | | (bus->parent ? 1 : 0), |
| 68 | &pcicptr->g2pcfgadrs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 69 | /* clear M_ABORT and Disable M_ABORT Int. */ |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 70 | __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) |
| 71 | | (PCI_STATUS_REC_MASTER_ABORT << 16), |
| 72 | &pcicptr->pcistatus); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 73 | return 0; |
| 74 | } |
| 75 | |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 76 | static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 77 | { |
| 78 | int code = PCIBIOS_SUCCESSFUL; |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 79 | |
| 80 | /* wait write cycle completion before checking error status */ |
| 81 | while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB) |
| 82 | ; |
| 83 | if (__raw_readl(&pcicptr->pcistatus) |
| 84 | & (PCI_STATUS_REC_MASTER_ABORT << 16)) { |
| 85 | __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) |
| 86 | | (PCI_STATUS_REC_MASTER_ABORT << 16), |
| 87 | &pcicptr->pcistatus); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 88 | code = PCIBIOS_DEVICE_NOT_FOUND; |
| 89 | } |
| 90 | return code; |
| 91 | } |
| 92 | |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 93 | static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 94 | { |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 95 | #ifdef __BIG_ENDIAN |
| 96 | offset ^= 3; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 97 | #endif |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 98 | return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset); |
| 99 | } |
| 100 | static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr) |
| 101 | { |
| 102 | #ifdef __BIG_ENDIAN |
| 103 | offset ^= 2; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 104 | #endif |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 105 | return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset); |
| 106 | } |
| 107 | static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr) |
| 108 | { |
| 109 | return __raw_readl(&pcicptr->g2pcfgdata); |
| 110 | } |
| 111 | static void icd_writeb(u8 val, int offset, |
| 112 | struct tx4927_pcic_reg __iomem *pcicptr) |
| 113 | { |
| 114 | #ifdef __BIG_ENDIAN |
| 115 | offset ^= 3; |
| 116 | #endif |
| 117 | __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset); |
| 118 | } |
| 119 | static void icd_writew(u16 val, int offset, |
| 120 | struct tx4927_pcic_reg __iomem *pcicptr) |
| 121 | { |
| 122 | #ifdef __BIG_ENDIAN |
| 123 | offset ^= 2; |
| 124 | #endif |
| 125 | __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset); |
| 126 | } |
| 127 | static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr) |
| 128 | { |
| 129 | __raw_writel(val, &pcicptr->g2pcfgdata); |
| 130 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 131 | |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 132 | static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus) |
| 133 | { |
| 134 | struct pci_controller *channel = bus->sysdata; |
| 135 | return get_tx4927_pcicptr(channel); |
| 136 | } |
| 137 | |
| 138 | static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn, |
| 139 | int where, int size, u32 *val) |
| 140 | { |
| 141 | struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus); |
| 142 | |
| 143 | if (mkaddr(bus, devfn, where, pcicptr)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 144 | *val = 0xffffffff; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 145 | return -1; |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 146 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | switch (size) { |
| 148 | case 1: |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 149 | *val = icd_readb(where & 3, pcicptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 150 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 151 | case 2: |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 152 | *val = icd_readw(where & 3, pcicptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 153 | break; |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 154 | default: |
| 155 | *val = icd_readl(pcicptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | } |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 157 | return check_abort(pcicptr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | } |
| 159 | |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 160 | static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn, |
| 161 | int where, int size, u32 val) |
| 162 | { |
| 163 | struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus); |
| 164 | |
| 165 | if (mkaddr(bus, devfn, where, pcicptr)) |
| 166 | return -1; |
| 167 | switch (size) { |
| 168 | case 1: |
| 169 | icd_writeb(val, where & 3, pcicptr); |
| 170 | break; |
| 171 | case 2: |
| 172 | icd_writew(val, where & 3, pcicptr); |
| 173 | break; |
| 174 | default: |
| 175 | icd_writel(val, pcicptr); |
| 176 | } |
| 177 | return check_abort(pcicptr); |
| 178 | } |
| 179 | |
| 180 | static struct pci_ops tx4927_pci_ops = { |
| 181 | .read = tx4927_pci_config_read, |
| 182 | .write = tx4927_pci_config_write, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 183 | }; |
| 184 | |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 185 | static struct { |
| 186 | u8 trdyto; |
| 187 | u8 retryto; |
| 188 | u16 gbwc; |
| 189 | } tx4927_pci_opts __devinitdata = { |
| 190 | .trdyto = 0, |
| 191 | .retryto = 0, |
| 192 | .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 193 | }; |
Atsushi Nemoto | 89d63fe | 2008-07-11 00:33:08 +0900 | [diff] [blame] | 194 | |
| 195 | void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, |
| 196 | struct pci_controller *channel, int extarb) |
| 197 | { |
| 198 | int i; |
| 199 | unsigned long flags; |
| 200 | |
| 201 | set_tx4927_pcicptr(channel, pcicptr); |
| 202 | |
| 203 | if (!channel->pci_ops) |
| 204 | printk(KERN_INFO |
| 205 | "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n", |
| 206 | __raw_readl(&pcicptr->pciid) >> 16, |
| 207 | __raw_readl(&pcicptr->pciid) & 0xffff, |
| 208 | __raw_readl(&pcicptr->pciccrev) & 0xff, |
| 209 | extarb ? "External" : "Internal"); |
| 210 | channel->pci_ops = &tx4927_pci_ops; |
| 211 | |
| 212 | local_irq_save(flags); |
| 213 | |
| 214 | /* Disable All Initiator Space */ |
| 215 | __raw_writel(__raw_readl(&pcicptr->pciccfg) |
| 216 | & ~(TX4927_PCIC_PCICCFG_G2PMEN(0) |
| 217 | | TX4927_PCIC_PCICCFG_G2PMEN(1) |
| 218 | | TX4927_PCIC_PCICCFG_G2PMEN(2) |
| 219 | | TX4927_PCIC_PCICCFG_G2PIOEN), |
| 220 | &pcicptr->pciccfg); |
| 221 | |
| 222 | /* GB->PCI mappings */ |
| 223 | __raw_writel((channel->io_resource->end - channel->io_resource->start) |
| 224 | >> 4, |
| 225 | &pcicptr->g2piomask); |
| 226 | ____raw_writeq((channel->io_resource->start + |
| 227 | channel->io_map_base - IO_BASE) | |
| 228 | #ifdef __BIG_ENDIAN |
| 229 | TX4927_PCIC_G2PIOGBASE_ECHG |
| 230 | #else |
| 231 | TX4927_PCIC_G2PIOGBASE_BSDIS |
| 232 | #endif |
| 233 | , &pcicptr->g2piogbase); |
| 234 | ____raw_writeq(channel->io_resource->start - channel->io_offset, |
| 235 | &pcicptr->g2piopbase); |
| 236 | for (i = 0; i < 3; i++) { |
| 237 | __raw_writel(0, &pcicptr->g2pmmask[i]); |
| 238 | ____raw_writeq(0, &pcicptr->g2pmgbase[i]); |
| 239 | ____raw_writeq(0, &pcicptr->g2pmpbase[i]); |
| 240 | } |
| 241 | if (channel->mem_resource->end) { |
| 242 | __raw_writel((channel->mem_resource->end |
| 243 | - channel->mem_resource->start) >> 4, |
| 244 | &pcicptr->g2pmmask[0]); |
| 245 | ____raw_writeq(channel->mem_resource->start | |
| 246 | #ifdef __BIG_ENDIAN |
| 247 | TX4927_PCIC_G2PMnGBASE_ECHG |
| 248 | #else |
| 249 | TX4927_PCIC_G2PMnGBASE_BSDIS |
| 250 | #endif |
| 251 | , &pcicptr->g2pmgbase[0]); |
| 252 | ____raw_writeq(channel->mem_resource->start - |
| 253 | channel->mem_offset, |
| 254 | &pcicptr->g2pmpbase[0]); |
| 255 | } |
| 256 | /* PCI->GB mappings (I/O 256B) */ |
| 257 | __raw_writel(0, &pcicptr->p2giopbase); /* 256B */ |
| 258 | ____raw_writeq(0, &pcicptr->p2giogbase); |
| 259 | /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */ |
| 260 | __raw_writel(0, &pcicptr->p2gm0plbase); |
| 261 | __raw_writel(0, &pcicptr->p2gm0pubase); |
| 262 | ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN | |
| 263 | #ifdef __BIG_ENDIAN |
| 264 | TX4927_PCIC_P2GMnGBASE_TECHG |
| 265 | #else |
| 266 | TX4927_PCIC_P2GMnGBASE_TBSDIS |
| 267 | #endif |
| 268 | , &pcicptr->p2gmgbase[0]); |
| 269 | /* PCI->GB mappings (MEM 16MB) */ |
| 270 | __raw_writel(0xffffffff, &pcicptr->p2gm1plbase); |
| 271 | __raw_writel(0xffffffff, &pcicptr->p2gm1pubase); |
| 272 | ____raw_writeq(0, &pcicptr->p2gmgbase[1]); |
| 273 | /* PCI->GB mappings (MEM 1MB) */ |
| 274 | __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */ |
| 275 | ____raw_writeq(0, &pcicptr->p2gmgbase[2]); |
| 276 | |
| 277 | /* Clear all (including IRBER) except for GBWC */ |
| 278 | __raw_writel((tx4927_pci_opts.gbwc << 16) |
| 279 | & TX4927_PCIC_PCICCFG_GBWC_MASK, |
| 280 | &pcicptr->pciccfg); |
| 281 | /* Enable Initiator Memory Space */ |
| 282 | if (channel->mem_resource->end) |
| 283 | __raw_writel(__raw_readl(&pcicptr->pciccfg) |
| 284 | | TX4927_PCIC_PCICCFG_G2PMEN(0), |
| 285 | &pcicptr->pciccfg); |
| 286 | /* Enable Initiator I/O Space */ |
| 287 | if (channel->io_resource->end) |
| 288 | __raw_writel(__raw_readl(&pcicptr->pciccfg) |
| 289 | | TX4927_PCIC_PCICCFG_G2PIOEN, |
| 290 | &pcicptr->pciccfg); |
| 291 | /* Enable Initiator Config */ |
| 292 | __raw_writel(__raw_readl(&pcicptr->pciccfg) |
| 293 | | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR, |
| 294 | &pcicptr->pciccfg); |
| 295 | |
| 296 | /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */ |
| 297 | __raw_writel(0, &pcicptr->pcicfg1); |
| 298 | |
| 299 | __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff) |
| 300 | | (tx4927_pci_opts.trdyto & 0xff) |
| 301 | | ((tx4927_pci_opts.retryto & 0xff) << 8), |
| 302 | &pcicptr->g2ptocnt); |
| 303 | |
| 304 | /* Clear All Local Bus Status */ |
| 305 | __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus); |
| 306 | /* Enable All Local Bus Interrupts */ |
| 307 | __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask); |
| 308 | /* Clear All Initiator Status */ |
| 309 | __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus); |
| 310 | /* Enable All Initiator Interrupts */ |
| 311 | __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask); |
| 312 | /* Clear All PCI Status Error */ |
| 313 | __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) |
| 314 | | (TX4927_PCIC_PCISTATUS_ALL << 16), |
| 315 | &pcicptr->pcistatus); |
| 316 | /* Enable All PCI Status Error Interrupts */ |
| 317 | __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask); |
| 318 | |
| 319 | if (!extarb) { |
| 320 | /* Reset Bus Arbiter */ |
| 321 | __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg); |
| 322 | __raw_writel(0, &pcicptr->pbabm); |
| 323 | /* Enable Bus Arbiter */ |
| 324 | __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg); |
| 325 | } |
| 326 | |
| 327 | __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
| 328 | | PCI_COMMAND_PARITY | PCI_COMMAND_SERR, |
| 329 | &pcicptr->pcistatus); |
| 330 | local_irq_restore(flags); |
| 331 | |
| 332 | printk(KERN_DEBUG |
| 333 | "PCI: COMMAND=%04x,PCIMASK=%04x," |
| 334 | "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n", |
| 335 | __raw_readl(&pcicptr->pcistatus) & 0xffff, |
| 336 | __raw_readl(&pcicptr->pcimask) & 0xffff, |
| 337 | __raw_readl(&pcicptr->g2ptocnt) & 0xff, |
| 338 | (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8, |
| 339 | (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff); |
| 340 | } |
| 341 | |
| 342 | static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr) |
| 343 | { |
| 344 | __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16); |
| 345 | __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus); |
| 346 | __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus); |
| 347 | static struct { |
| 348 | __u32 flag; |
| 349 | const char *str; |
| 350 | } pcistat_tbl[] = { |
| 351 | { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" }, |
| 352 | { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" }, |
| 353 | { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" }, |
| 354 | { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" }, |
| 355 | { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" }, |
| 356 | { PCI_STATUS_PARITY, "MasterParityError" }, |
| 357 | }, g2pstat_tbl[] = { |
| 358 | { TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" }, |
| 359 | { TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" }, |
| 360 | }, pcicstat_tbl[] = { |
| 361 | { TX4927_PCIC_PCICSTATUS_PME, "PME" }, |
| 362 | { TX4927_PCIC_PCICSTATUS_TLB, "TLB" }, |
| 363 | { TX4927_PCIC_PCICSTATUS_NIB, "NIB" }, |
| 364 | { TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" }, |
| 365 | { TX4927_PCIC_PCICSTATUS_PERR, "PERR" }, |
| 366 | { TX4927_PCIC_PCICSTATUS_SERR, "SERR" }, |
| 367 | { TX4927_PCIC_PCICSTATUS_GBE, "GBE" }, |
| 368 | { TX4927_PCIC_PCICSTATUS_IWB, "IWB" }, |
| 369 | }; |
| 370 | int i, cont; |
| 371 | |
| 372 | printk(KERN_ERR ""); |
| 373 | if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) { |
| 374 | printk(KERN_CONT "pcistat:%04x(", pcistatus); |
| 375 | for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++) |
| 376 | if (pcistatus & pcistat_tbl[i].flag) |
| 377 | printk(KERN_CONT "%s%s", |
| 378 | cont++ ? " " : "", pcistat_tbl[i].str); |
| 379 | printk(KERN_CONT ") "); |
| 380 | } |
| 381 | if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) { |
| 382 | printk(KERN_CONT "g2pstatus:%08x(", g2pstatus); |
| 383 | for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++) |
| 384 | if (g2pstatus & g2pstat_tbl[i].flag) |
| 385 | printk(KERN_CONT "%s%s", |
| 386 | cont++ ? " " : "", g2pstat_tbl[i].str); |
| 387 | printk(KERN_CONT ") "); |
| 388 | } |
| 389 | if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) { |
| 390 | printk(KERN_CONT "pcicstatus:%08x(", pcicstatus); |
| 391 | for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++) |
| 392 | if (pcicstatus & pcicstat_tbl[i].flag) |
| 393 | printk(KERN_CONT "%s%s", |
| 394 | cont++ ? " " : "", pcicstat_tbl[i].str); |
| 395 | printk(KERN_CONT ")"); |
| 396 | } |
| 397 | printk(KERN_CONT "\n"); |
| 398 | } |
| 399 | |
| 400 | void tx4927_report_pcic_status(void) |
| 401 | { |
| 402 | int i; |
| 403 | |
| 404 | for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) { |
| 405 | if (pcicptrs[i].pcicptr) |
| 406 | tx4927_report_pcic_status1(pcicptrs[i].pcicptr); |
| 407 | } |
| 408 | } |