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Vimal Singh67ce04b2009-05-12 13:47:03 -07001/*
2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
Russell King763e7352012-04-25 00:16:00 +010012#include <linux/dmaengine.h>
Vimal Singh67ce04b2009-05-12 13:47:03 -070013#include <linux/dma-mapping.h>
14#include <linux/delay.h>
Paul Gortmakera0e5cc52011-07-03 15:17:31 -040015#include <linux/module.h>
Sukumar Ghorai4e070372011-01-28 15:42:06 +053016#include <linux/interrupt.h>
vimal singhc276aca2009-06-27 11:07:06 +053017#include <linux/jiffies.h>
18#include <linux/sched.h>
Vimal Singh67ce04b2009-05-12 13:47:03 -070019#include <linux/mtd/mtd.h>
20#include <linux/mtd/nand.h>
21#include <linux/mtd/partitions.h>
Russell King763e7352012-04-25 00:16:00 +010022#include <linux/omap-dma.h>
Vimal Singh67ce04b2009-05-12 13:47:03 -070023#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090024#include <linux/slab.h>
Philip Avinash62116e52013-01-04 13:26:51 +053025#include <linux/of.h>
26#include <linux/of_device.h>
Vimal Singh67ce04b2009-05-12 13:47:03 -070027
Pekon Gupta32d42a82013-10-24 18:20:23 +053028#include <linux/mtd/nand_bch.h>
Philip Avinash62116e52013-01-04 13:26:51 +053029#include <linux/platform_data/elm.h>
Ivan Djelic0e618ef2012-04-30 12:17:18 +020030
Arnd Bergmann22037472012-08-24 15:21:06 +020031#include <linux/platform_data/mtd-nand-omap2.h>
Vimal Singh67ce04b2009-05-12 13:47:03 -070032
Vimal Singh67ce04b2009-05-12 13:47:03 -070033#define DRIVER_NAME "omap2-nand"
Sukumar Ghorai4e070372011-01-28 15:42:06 +053034#define OMAP_NAND_TIMEOUT_MS 5000
Vimal Singh67ce04b2009-05-12 13:47:03 -070035
Vimal Singh67ce04b2009-05-12 13:47:03 -070036#define NAND_Ecc_P1e (1 << 0)
37#define NAND_Ecc_P2e (1 << 1)
38#define NAND_Ecc_P4e (1 << 2)
39#define NAND_Ecc_P8e (1 << 3)
40#define NAND_Ecc_P16e (1 << 4)
41#define NAND_Ecc_P32e (1 << 5)
42#define NAND_Ecc_P64e (1 << 6)
43#define NAND_Ecc_P128e (1 << 7)
44#define NAND_Ecc_P256e (1 << 8)
45#define NAND_Ecc_P512e (1 << 9)
46#define NAND_Ecc_P1024e (1 << 10)
47#define NAND_Ecc_P2048e (1 << 11)
48
49#define NAND_Ecc_P1o (1 << 16)
50#define NAND_Ecc_P2o (1 << 17)
51#define NAND_Ecc_P4o (1 << 18)
52#define NAND_Ecc_P8o (1 << 19)
53#define NAND_Ecc_P16o (1 << 20)
54#define NAND_Ecc_P32o (1 << 21)
55#define NAND_Ecc_P64o (1 << 22)
56#define NAND_Ecc_P128o (1 << 23)
57#define NAND_Ecc_P256o (1 << 24)
58#define NAND_Ecc_P512o (1 << 25)
59#define NAND_Ecc_P1024o (1 << 26)
60#define NAND_Ecc_P2048o (1 << 27)
61
62#define TF(value) (value ? 1 : 0)
63
64#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
65#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
66#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
67#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
68#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
69#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
70#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
71#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
72
73#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
74#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
75#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
76#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
77#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
78#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
79#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
80#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
81
82#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
83#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
84#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
85#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
86#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
87#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
88#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
89#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
90
91#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
92#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
93#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
94#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
95#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
96#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
97#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
98#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
99
100#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
101#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
102
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700103#define PREFETCH_CONFIG1_CS_SHIFT 24
104#define ECC_CONFIG_CS_SHIFT 1
105#define CS_MASK 0x7
106#define ENABLE_PREFETCH (0x1 << 7)
107#define DMA_MPU_MODE_SHIFT 2
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +0530108#define ECCSIZE0_SHIFT 12
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700109#define ECCSIZE1_SHIFT 22
110#define ECC1RESULTSIZE 0x1
111#define ECCCLEAR 0x100
112#define ECC1 0x1
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530113#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
114#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
115#define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
116#define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
117#define STATUS_BUFF_EMPTY 0x00000001
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700118
Lokesh Vutlad5e7c862012-10-15 14:03:51 -0700119#define OMAP24XX_DMA_GPMC 4
120
Philip Avinashc3e4b992013-01-04 13:26:49 +0530121#define BCH8_MAX_ERROR 8 /* upto 8 bit correctable */
122#define BCH4_MAX_ERROR 4 /* upto 4 bit correctable */
123
Philip Avinash62116e52013-01-04 13:26:51 +0530124#define SECTOR_BYTES 512
125/* 4 bit padding to make byte aligned, 56 = 52 + 4 */
126#define BCH4_BIT_PAD 4
127#define BCH8_ECC_MAX ((SECTOR_BYTES + BCH8_ECC_OOB_BYTES) * 8)
128#define BCH4_ECC_MAX ((SECTOR_BYTES + BCH4_ECC_OOB_BYTES) * 8)
129
130/* GPMC ecc engine settings for read */
131#define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
132#define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */
133#define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */
134#define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */
135#define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */
136
137/* GPMC ecc engine settings for write */
138#define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
139#define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
140#define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */
141
Pekon Guptab491da72013-10-24 18:20:22 +0530142#define BADBLOCK_MARKER_LENGTH 2
Pekon Guptaa919e512013-10-24 18:20:21 +0530143
Philip Avinash62116e52013-01-04 13:26:51 +0530144#ifdef CONFIG_MTD_NAND_OMAP_BCH
145static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
146 0xac, 0x6b, 0xff, 0x99, 0x7b};
147static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
148#endif
149
Sukumar Ghoraif040d332011-01-28 15:42:09 +0530150/* oob info generated runtime depending on ecc algorithm and layout selected */
151static struct nand_ecclayout omap_oobinfo;
vimal singh59e9c5a2009-07-13 16:26:24 +0530152
Vimal Singh67ce04b2009-05-12 13:47:03 -0700153struct omap_nand_info {
154 struct nand_hw_control controller;
155 struct omap_nand_platform_data *pdata;
156 struct mtd_info mtd;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700157 struct nand_chip nand;
158 struct platform_device *pdev;
159
160 int gpmc_cs;
161 unsigned long phys_base;
Afzal Mohammed9c4c2f82012-08-30 12:53:23 -0700162 unsigned long mem_size;
vimal singhdfe32892009-07-13 16:29:16 +0530163 struct completion comp;
Russell King763e7352012-04-25 00:16:00 +0100164 struct dma_chan *dma;
Afzal Mohammed5c468452012-08-30 12:53:24 -0700165 int gpmc_irq_fifo;
166 int gpmc_irq_count;
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530167 enum {
168 OMAP_NAND_IO_READ = 0, /* read */
169 OMAP_NAND_IO_WRITE, /* write */
170 } iomode;
171 u_char *buf;
172 int buf_len;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700173 struct gpmc_nand_regs reg;
Pekon Guptaa919e512013-10-24 18:20:21 +0530174 /* fields specific for BCHx_HW ECC scheme */
Philip Avinash62116e52013-01-04 13:26:51 +0530175 bool is_elm_used;
176 struct device *elm_dev;
177 struct device_node *of_node;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700178};
179
180/**
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700181 * omap_prefetch_enable - configures and starts prefetch transfer
182 * @cs: cs (chip select) number
183 * @fifo_th: fifo threshold to be used for read/ write
184 * @dma_mode: dma mode enable (1) or disable (0)
185 * @u32_count: number of bytes to be transferred
186 * @is_write: prefetch read(0) or write post(1) mode
187 */
188static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
189 unsigned int u32_count, int is_write, struct omap_nand_info *info)
190{
191 u32 val;
192
193 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
194 return -1;
195
196 if (readl(info->reg.gpmc_prefetch_control))
197 return -EBUSY;
198
199 /* Set the amount of bytes to be prefetched */
200 writel(u32_count, info->reg.gpmc_prefetch_config2);
201
202 /* Set dma/mpu mode, the prefetch read / post write and
203 * enable the engine. Set which cs is has requested for.
204 */
205 val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
206 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
207 (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
208 writel(val, info->reg.gpmc_prefetch_config1);
209
210 /* Start the prefetch engine */
211 writel(0x1, info->reg.gpmc_prefetch_control);
212
213 return 0;
214}
215
216/**
217 * omap_prefetch_reset - disables and stops the prefetch engine
218 */
219static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
220{
221 u32 config1;
222
223 /* check if the same module/cs is trying to reset */
224 config1 = readl(info->reg.gpmc_prefetch_config1);
225 if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
226 return -EINVAL;
227
228 /* Stop the PFPW engine */
229 writel(0x0, info->reg.gpmc_prefetch_control);
230
231 /* Reset/disable the PFPW engine */
232 writel(0x0, info->reg.gpmc_prefetch_config1);
233
234 return 0;
235}
236
237/**
Vimal Singh67ce04b2009-05-12 13:47:03 -0700238 * omap_hwcontrol - hardware specific access to control-lines
239 * @mtd: MTD device structure
240 * @cmd: command to device
241 * @ctrl:
242 * NAND_NCE: bit 0 -> don't care
243 * NAND_CLE: bit 1 -> Command Latch
244 * NAND_ALE: bit 2 -> Address Latch
245 *
246 * NOTE: boards may use different bits for these!!
247 */
248static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
249{
250 struct omap_nand_info *info = container_of(mtd,
251 struct omap_nand_info, mtd);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700252
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000253 if (cmd != NAND_CMD_NONE) {
254 if (ctrl & NAND_CLE)
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700255 writeb(cmd, info->reg.gpmc_nand_command);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700256
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000257 else if (ctrl & NAND_ALE)
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700258 writeb(cmd, info->reg.gpmc_nand_address);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000259
260 else /* NAND_NCE */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700261 writeb(cmd, info->reg.gpmc_nand_data);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700262 }
Vimal Singh67ce04b2009-05-12 13:47:03 -0700263}
264
265/**
vimal singh59e9c5a2009-07-13 16:26:24 +0530266 * omap_read_buf8 - read data from NAND controller into buffer
267 * @mtd: MTD device structure
268 * @buf: buffer to store date
269 * @len: number of bytes to read
270 */
271static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
272{
273 struct nand_chip *nand = mtd->priv;
274
275 ioread8_rep(nand->IO_ADDR_R, buf, len);
276}
277
278/**
279 * omap_write_buf8 - write buffer to NAND controller
280 * @mtd: MTD device structure
281 * @buf: data buffer
282 * @len: number of bytes to write
283 */
284static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
285{
286 struct omap_nand_info *info = container_of(mtd,
287 struct omap_nand_info, mtd);
288 u_char *p = (u_char *)buf;
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000289 u32 status = 0;
vimal singh59e9c5a2009-07-13 16:26:24 +0530290
291 while (len--) {
292 iowrite8(*p++, info->nand.IO_ADDR_W);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000293 /* wait until buffer is available for write */
294 do {
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700295 status = readl(info->reg.gpmc_status) &
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530296 STATUS_BUFF_EMPTY;
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000297 } while (!status);
vimal singh59e9c5a2009-07-13 16:26:24 +0530298 }
299}
300
301/**
Vimal Singh67ce04b2009-05-12 13:47:03 -0700302 * omap_read_buf16 - read data from NAND controller into buffer
303 * @mtd: MTD device structure
304 * @buf: buffer to store date
305 * @len: number of bytes to read
306 */
307static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
308{
309 struct nand_chip *nand = mtd->priv;
310
vimal singh59e9c5a2009-07-13 16:26:24 +0530311 ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700312}
313
314/**
315 * omap_write_buf16 - write buffer to NAND controller
316 * @mtd: MTD device structure
317 * @buf: data buffer
318 * @len: number of bytes to write
319 */
320static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
321{
322 struct omap_nand_info *info = container_of(mtd,
323 struct omap_nand_info, mtd);
324 u16 *p = (u16 *) buf;
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000325 u32 status = 0;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700326 /* FIXME try bursts of writesw() or DMA ... */
327 len >>= 1;
328
329 while (len--) {
vimal singh59e9c5a2009-07-13 16:26:24 +0530330 iowrite16(*p++, info->nand.IO_ADDR_W);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000331 /* wait until buffer is available for write */
332 do {
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700333 status = readl(info->reg.gpmc_status) &
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530334 STATUS_BUFF_EMPTY;
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000335 } while (!status);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700336 }
337}
vimal singh59e9c5a2009-07-13 16:26:24 +0530338
339/**
340 * omap_read_buf_pref - read data from NAND controller into buffer
341 * @mtd: MTD device structure
342 * @buf: buffer to store date
343 * @len: number of bytes to read
344 */
345static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
346{
347 struct omap_nand_info *info = container_of(mtd,
348 struct omap_nand_info, mtd);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000349 uint32_t r_count = 0;
vimal singh59e9c5a2009-07-13 16:26:24 +0530350 int ret = 0;
351 u32 *p = (u32 *)buf;
352
353 /* take care of subpage reads */
Vimal Singhc3341d02010-01-07 12:16:26 +0530354 if (len % 4) {
355 if (info->nand.options & NAND_BUSWIDTH_16)
356 omap_read_buf16(mtd, buf, len % 4);
357 else
358 omap_read_buf8(mtd, buf, len % 4);
359 p = (u32 *) (buf + len % 4);
360 len -= len % 4;
vimal singh59e9c5a2009-07-13 16:26:24 +0530361 }
vimal singh59e9c5a2009-07-13 16:26:24 +0530362
363 /* configure and start prefetch transfer */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700364 ret = omap_prefetch_enable(info->gpmc_cs,
365 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
vimal singh59e9c5a2009-07-13 16:26:24 +0530366 if (ret) {
367 /* PFPW engine is busy, use cpu copy method */
368 if (info->nand.options & NAND_BUSWIDTH_16)
Kishore Kadiyalac5d8c0c2011-05-11 21:17:27 +0530369 omap_read_buf16(mtd, (u_char *)p, len);
vimal singh59e9c5a2009-07-13 16:26:24 +0530370 else
Kishore Kadiyalac5d8c0c2011-05-11 21:17:27 +0530371 omap_read_buf8(mtd, (u_char *)p, len);
vimal singh59e9c5a2009-07-13 16:26:24 +0530372 } else {
373 do {
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700374 r_count = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530375 r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000376 r_count = r_count >> 2;
377 ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
vimal singh59e9c5a2009-07-13 16:26:24 +0530378 p += r_count;
379 len -= r_count << 2;
380 } while (len);
vimal singh59e9c5a2009-07-13 16:26:24 +0530381 /* disable and stop the PFPW engine */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700382 omap_prefetch_reset(info->gpmc_cs, info);
vimal singh59e9c5a2009-07-13 16:26:24 +0530383 }
384}
385
386/**
387 * omap_write_buf_pref - write buffer to NAND controller
388 * @mtd: MTD device structure
389 * @buf: data buffer
390 * @len: number of bytes to write
391 */
392static void omap_write_buf_pref(struct mtd_info *mtd,
393 const u_char *buf, int len)
394{
395 struct omap_nand_info *info = container_of(mtd,
396 struct omap_nand_info, mtd);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530397 uint32_t w_count = 0;
vimal singh59e9c5a2009-07-13 16:26:24 +0530398 int i = 0, ret = 0;
Kishore Kadiyalac5d8c0c2011-05-11 21:17:27 +0530399 u16 *p = (u16 *)buf;
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530400 unsigned long tim, limit;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700401 u32 val;
vimal singh59e9c5a2009-07-13 16:26:24 +0530402
403 /* take care of subpage writes */
404 if (len % 2 != 0) {
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000405 writeb(*buf, info->nand.IO_ADDR_W);
vimal singh59e9c5a2009-07-13 16:26:24 +0530406 p = (u16 *)(buf + 1);
407 len--;
408 }
409
410 /* configure and start prefetch transfer */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700411 ret = omap_prefetch_enable(info->gpmc_cs,
412 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
vimal singh59e9c5a2009-07-13 16:26:24 +0530413 if (ret) {
414 /* PFPW engine is busy, use cpu copy method */
415 if (info->nand.options & NAND_BUSWIDTH_16)
Kishore Kadiyalac5d8c0c2011-05-11 21:17:27 +0530416 omap_write_buf16(mtd, (u_char *)p, len);
vimal singh59e9c5a2009-07-13 16:26:24 +0530417 else
Kishore Kadiyalac5d8c0c2011-05-11 21:17:27 +0530418 omap_write_buf8(mtd, (u_char *)p, len);
vimal singh59e9c5a2009-07-13 16:26:24 +0530419 } else {
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000420 while (len) {
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700421 w_count = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530422 w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000423 w_count = w_count >> 1;
vimal singh59e9c5a2009-07-13 16:26:24 +0530424 for (i = 0; (i < w_count) && len; i++, len -= 2)
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000425 iowrite16(*p++, info->nand.IO_ADDR_W);
vimal singh59e9c5a2009-07-13 16:26:24 +0530426 }
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000427 /* wait for data to flushed-out before reset the prefetch */
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530428 tim = 0;
429 limit = (loops_per_jiffy *
430 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700431 do {
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530432 cpu_relax();
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700433 val = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530434 val = PREFETCH_STATUS_COUNT(val);
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700435 } while (val && (tim++ < limit));
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530436
vimal singh59e9c5a2009-07-13 16:26:24 +0530437 /* disable and stop the PFPW engine */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700438 omap_prefetch_reset(info->gpmc_cs, info);
vimal singh59e9c5a2009-07-13 16:26:24 +0530439 }
440}
441
vimal singhdfe32892009-07-13 16:29:16 +0530442/*
Russell King2df41d02012-04-25 00:19:39 +0100443 * omap_nand_dma_callback: callback on the completion of dma transfer
vimal singhdfe32892009-07-13 16:29:16 +0530444 * @data: pointer to completion data structure
445 */
Russell King763e7352012-04-25 00:16:00 +0100446static void omap_nand_dma_callback(void *data)
447{
448 complete((struct completion *) data);
449}
vimal singhdfe32892009-07-13 16:29:16 +0530450
451/*
Peter Meerwald4cacbe22012-07-19 13:21:04 +0200452 * omap_nand_dma_transfer: configure and start dma transfer
vimal singhdfe32892009-07-13 16:29:16 +0530453 * @mtd: MTD device structure
454 * @addr: virtual address in RAM of source/destination
455 * @len: number of data bytes to be transferred
456 * @is_write: flag for read/write operation
457 */
458static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
459 unsigned int len, int is_write)
460{
461 struct omap_nand_info *info = container_of(mtd,
462 struct omap_nand_info, mtd);
Russell King2df41d02012-04-25 00:19:39 +0100463 struct dma_async_tx_descriptor *tx;
vimal singhdfe32892009-07-13 16:29:16 +0530464 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
465 DMA_FROM_DEVICE;
Russell King2df41d02012-04-25 00:19:39 +0100466 struct scatterlist sg;
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530467 unsigned long tim, limit;
Russell King2df41d02012-04-25 00:19:39 +0100468 unsigned n;
469 int ret;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700470 u32 val;
vimal singhdfe32892009-07-13 16:29:16 +0530471
472 if (addr >= high_memory) {
473 struct page *p1;
474
475 if (((size_t)addr & PAGE_MASK) !=
476 ((size_t)(addr + len - 1) & PAGE_MASK))
477 goto out_copy;
478 p1 = vmalloc_to_page(addr);
479 if (!p1)
480 goto out_copy;
481 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
482 }
483
Russell King2df41d02012-04-25 00:19:39 +0100484 sg_init_one(&sg, addr, len);
485 n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
486 if (n == 0) {
vimal singhdfe32892009-07-13 16:29:16 +0530487 dev_err(&info->pdev->dev,
488 "Couldn't DMA map a %d byte buffer\n", len);
489 goto out_copy;
490 }
491
Russell King2df41d02012-04-25 00:19:39 +0100492 tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
493 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
494 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
495 if (!tx)
496 goto out_copy_unmap;
497
498 tx->callback = omap_nand_dma_callback;
499 tx->callback_param = &info->comp;
500 dmaengine_submit(tx);
501
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700502 /* configure and start prefetch transfer */
503 ret = omap_prefetch_enable(info->gpmc_cs,
504 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
vimal singhdfe32892009-07-13 16:29:16 +0530505 if (ret)
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530506 /* PFPW engine is busy, use cpu copy method */
Grazvydas Ignotasd7efe222012-04-11 04:04:34 +0300507 goto out_copy_unmap;
vimal singhdfe32892009-07-13 16:29:16 +0530508
509 init_completion(&info->comp);
Russell King2df41d02012-04-25 00:19:39 +0100510 dma_async_issue_pending(info->dma);
vimal singhdfe32892009-07-13 16:29:16 +0530511
512 /* setup and start DMA using dma_addr */
513 wait_for_completion(&info->comp);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530514 tim = 0;
515 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700516
517 do {
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530518 cpu_relax();
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700519 val = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530520 val = PREFETCH_STATUS_COUNT(val);
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700521 } while (val && (tim++ < limit));
vimal singhdfe32892009-07-13 16:29:16 +0530522
vimal singhdfe32892009-07-13 16:29:16 +0530523 /* disable and stop the PFPW engine */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700524 omap_prefetch_reset(info->gpmc_cs, info);
vimal singhdfe32892009-07-13 16:29:16 +0530525
Russell King2df41d02012-04-25 00:19:39 +0100526 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
vimal singhdfe32892009-07-13 16:29:16 +0530527 return 0;
528
Grazvydas Ignotasd7efe222012-04-11 04:04:34 +0300529out_copy_unmap:
Russell King2df41d02012-04-25 00:19:39 +0100530 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
vimal singhdfe32892009-07-13 16:29:16 +0530531out_copy:
532 if (info->nand.options & NAND_BUSWIDTH_16)
533 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
534 : omap_write_buf16(mtd, (u_char *) addr, len);
535 else
536 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
537 : omap_write_buf8(mtd, (u_char *) addr, len);
538 return 0;
539}
vimal singhdfe32892009-07-13 16:29:16 +0530540
541/**
542 * omap_read_buf_dma_pref - read data from NAND controller into buffer
543 * @mtd: MTD device structure
544 * @buf: buffer to store date
545 * @len: number of bytes to read
546 */
547static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
548{
549 if (len <= mtd->oobsize)
550 omap_read_buf_pref(mtd, buf, len);
551 else
552 /* start transfer in DMA mode */
553 omap_nand_dma_transfer(mtd, buf, len, 0x0);
554}
555
556/**
557 * omap_write_buf_dma_pref - write buffer to NAND controller
558 * @mtd: MTD device structure
559 * @buf: data buffer
560 * @len: number of bytes to write
561 */
562static void omap_write_buf_dma_pref(struct mtd_info *mtd,
563 const u_char *buf, int len)
564{
565 if (len <= mtd->oobsize)
566 omap_write_buf_pref(mtd, buf, len);
567 else
568 /* start transfer in DMA mode */
Vimal Singhbdaefc42010-01-05 12:49:24 +0530569 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
vimal singhdfe32892009-07-13 16:29:16 +0530570}
571
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530572/*
Peter Meerwald4cacbe22012-07-19 13:21:04 +0200573 * omap_nand_irq - GPMC irq handler
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530574 * @this_irq: gpmc irq number
575 * @dev: omap_nand_info structure pointer is passed here
576 */
577static irqreturn_t omap_nand_irq(int this_irq, void *dev)
578{
579 struct omap_nand_info *info = (struct omap_nand_info *) dev;
580 u32 bytes;
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530581
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700582 bytes = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530583 bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530584 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
585 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
Afzal Mohammed5c468452012-08-30 12:53:24 -0700586 if (this_irq == info->gpmc_irq_count)
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530587 goto done;
588
589 if (info->buf_len && (info->buf_len < bytes))
590 bytes = info->buf_len;
591 else if (!info->buf_len)
592 bytes = 0;
593 iowrite32_rep(info->nand.IO_ADDR_W,
594 (u32 *)info->buf, bytes >> 2);
595 info->buf = info->buf + bytes;
596 info->buf_len -= bytes;
597
598 } else {
599 ioread32_rep(info->nand.IO_ADDR_R,
600 (u32 *)info->buf, bytes >> 2);
601 info->buf = info->buf + bytes;
602
Afzal Mohammed5c468452012-08-30 12:53:24 -0700603 if (this_irq == info->gpmc_irq_count)
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530604 goto done;
605 }
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530606
607 return IRQ_HANDLED;
608
609done:
610 complete(&info->comp);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530611
Afzal Mohammed5c468452012-08-30 12:53:24 -0700612 disable_irq_nosync(info->gpmc_irq_fifo);
613 disable_irq_nosync(info->gpmc_irq_count);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530614
615 return IRQ_HANDLED;
616}
617
618/*
619 * omap_read_buf_irq_pref - read data from NAND controller into buffer
620 * @mtd: MTD device structure
621 * @buf: buffer to store date
622 * @len: number of bytes to read
623 */
624static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
625{
626 struct omap_nand_info *info = container_of(mtd,
627 struct omap_nand_info, mtd);
628 int ret = 0;
629
630 if (len <= mtd->oobsize) {
631 omap_read_buf_pref(mtd, buf, len);
632 return;
633 }
634
635 info->iomode = OMAP_NAND_IO_READ;
636 info->buf = buf;
637 init_completion(&info->comp);
638
639 /* configure and start prefetch transfer */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700640 ret = omap_prefetch_enable(info->gpmc_cs,
641 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530642 if (ret)
643 /* PFPW engine is busy, use cpu copy method */
644 goto out_copy;
645
646 info->buf_len = len;
Afzal Mohammed5c468452012-08-30 12:53:24 -0700647
648 enable_irq(info->gpmc_irq_count);
649 enable_irq(info->gpmc_irq_fifo);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530650
651 /* waiting for read to complete */
652 wait_for_completion(&info->comp);
653
654 /* disable and stop the PFPW engine */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700655 omap_prefetch_reset(info->gpmc_cs, info);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530656 return;
657
658out_copy:
659 if (info->nand.options & NAND_BUSWIDTH_16)
660 omap_read_buf16(mtd, buf, len);
661 else
662 omap_read_buf8(mtd, buf, len);
663}
664
665/*
666 * omap_write_buf_irq_pref - write buffer to NAND controller
667 * @mtd: MTD device structure
668 * @buf: data buffer
669 * @len: number of bytes to write
670 */
671static void omap_write_buf_irq_pref(struct mtd_info *mtd,
672 const u_char *buf, int len)
673{
674 struct omap_nand_info *info = container_of(mtd,
675 struct omap_nand_info, mtd);
676 int ret = 0;
677 unsigned long tim, limit;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700678 u32 val;
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530679
680 if (len <= mtd->oobsize) {
681 omap_write_buf_pref(mtd, buf, len);
682 return;
683 }
684
685 info->iomode = OMAP_NAND_IO_WRITE;
686 info->buf = (u_char *) buf;
687 init_completion(&info->comp);
688
Sukumar Ghorai317379a2011-01-28 15:42:07 +0530689 /* configure and start prefetch transfer : size=24 */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700690 ret = omap_prefetch_enable(info->gpmc_cs,
691 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530692 if (ret)
693 /* PFPW engine is busy, use cpu copy method */
694 goto out_copy;
695
696 info->buf_len = len;
Afzal Mohammed5c468452012-08-30 12:53:24 -0700697
698 enable_irq(info->gpmc_irq_count);
699 enable_irq(info->gpmc_irq_fifo);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530700
701 /* waiting for write to complete */
702 wait_for_completion(&info->comp);
Afzal Mohammed5c468452012-08-30 12:53:24 -0700703
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530704 /* wait for data to flushed-out before reset the prefetch */
705 tim = 0;
706 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700707 do {
708 val = readl(info->reg.gpmc_prefetch_status);
Afzal Mohammed47f88af42012-09-29 18:20:11 +0530709 val = PREFETCH_STATUS_COUNT(val);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530710 cpu_relax();
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700711 } while (val && (tim++ < limit));
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530712
713 /* disable and stop the PFPW engine */
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700714 omap_prefetch_reset(info->gpmc_cs, info);
Sukumar Ghorai4e070372011-01-28 15:42:06 +0530715 return;
716
717out_copy:
718 if (info->nand.options & NAND_BUSWIDTH_16)
719 omap_write_buf16(mtd, buf, len);
720 else
721 omap_write_buf8(mtd, buf, len);
722}
723
Vimal Singh67ce04b2009-05-12 13:47:03 -0700724/**
Vimal Singh67ce04b2009-05-12 13:47:03 -0700725 * gen_true_ecc - This function will generate true ECC value
726 * @ecc_buf: buffer to store ecc code
727 *
728 * This generated true ECC value can be used when correcting
729 * data read from NAND flash memory core
730 */
731static void gen_true_ecc(u8 *ecc_buf)
732{
733 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
734 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
735
736 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
737 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
738 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
739 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
740 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
741 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
742}
743
744/**
745 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
746 * @ecc_data1: ecc code from nand spare area
747 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
748 * @page_data: page data
749 *
750 * This function compares two ECC's and indicates if there is an error.
751 * If the error can be corrected it will be corrected to the buffer.
John Ogness74f1b722011-02-28 13:12:46 +0100752 * If there is no error, %0 is returned. If there is an error but it
753 * was corrected, %1 is returned. Otherwise, %-1 is returned.
Vimal Singh67ce04b2009-05-12 13:47:03 -0700754 */
755static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
756 u8 *ecc_data2, /* read from register */
757 u8 *page_data)
758{
759 uint i;
760 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
761 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
762 u8 ecc_bit[24];
763 u8 ecc_sum = 0;
764 u8 find_bit = 0;
765 uint find_byte = 0;
766 int isEccFF;
767
768 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
769
770 gen_true_ecc(ecc_data1);
771 gen_true_ecc(ecc_data2);
772
773 for (i = 0; i <= 2; i++) {
774 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
775 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
776 }
777
778 for (i = 0; i < 8; i++) {
779 tmp0_bit[i] = *ecc_data1 % 2;
780 *ecc_data1 = *ecc_data1 / 2;
781 }
782
783 for (i = 0; i < 8; i++) {
784 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
785 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
786 }
787
788 for (i = 0; i < 8; i++) {
789 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
790 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
791 }
792
793 for (i = 0; i < 8; i++) {
794 comp0_bit[i] = *ecc_data2 % 2;
795 *ecc_data2 = *ecc_data2 / 2;
796 }
797
798 for (i = 0; i < 8; i++) {
799 comp1_bit[i] = *(ecc_data2 + 1) % 2;
800 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
801 }
802
803 for (i = 0; i < 8; i++) {
804 comp2_bit[i] = *(ecc_data2 + 2) % 2;
805 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
806 }
807
808 for (i = 0; i < 6; i++)
809 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
810
811 for (i = 0; i < 8; i++)
812 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
813
814 for (i = 0; i < 8; i++)
815 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
816
817 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
818 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
819
820 for (i = 0; i < 24; i++)
821 ecc_sum += ecc_bit[i];
822
823 switch (ecc_sum) {
824 case 0:
825 /* Not reached because this function is not called if
826 * ECC values are equal
827 */
828 return 0;
829
830 case 1:
831 /* Uncorrectable error */
Brian Norris289c0522011-07-19 10:06:09 -0700832 pr_debug("ECC UNCORRECTED_ERROR 1\n");
Vimal Singh67ce04b2009-05-12 13:47:03 -0700833 return -1;
834
835 case 11:
836 /* UN-Correctable error */
Brian Norris289c0522011-07-19 10:06:09 -0700837 pr_debug("ECC UNCORRECTED_ERROR B\n");
Vimal Singh67ce04b2009-05-12 13:47:03 -0700838 return -1;
839
840 case 12:
841 /* Correctable error */
842 find_byte = (ecc_bit[23] << 8) +
843 (ecc_bit[21] << 7) +
844 (ecc_bit[19] << 6) +
845 (ecc_bit[17] << 5) +
846 (ecc_bit[15] << 4) +
847 (ecc_bit[13] << 3) +
848 (ecc_bit[11] << 2) +
849 (ecc_bit[9] << 1) +
850 ecc_bit[7];
851
852 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
853
Brian Norris0a32a102011-07-19 10:06:10 -0700854 pr_debug("Correcting single bit ECC error at offset: "
855 "%d, bit: %d\n", find_byte, find_bit);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700856
857 page_data[find_byte] ^= (1 << find_bit);
858
John Ogness74f1b722011-02-28 13:12:46 +0100859 return 1;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700860 default:
861 if (isEccFF) {
862 if (ecc_data2[0] == 0 &&
863 ecc_data2[1] == 0 &&
864 ecc_data2[2] == 0)
865 return 0;
866 }
Brian Norris289c0522011-07-19 10:06:09 -0700867 pr_debug("UNCORRECTED_ERROR default\n");
Vimal Singh67ce04b2009-05-12 13:47:03 -0700868 return -1;
869 }
870}
871
872/**
873 * omap_correct_data - Compares the ECC read with HW generated ECC
874 * @mtd: MTD device structure
875 * @dat: page data
876 * @read_ecc: ecc read from nand flash
877 * @calc_ecc: ecc read from HW ECC registers
878 *
879 * Compares the ecc read from nand spare area with ECC registers values
John Ogness74f1b722011-02-28 13:12:46 +0100880 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
881 * detection and correction. If there are no errors, %0 is returned. If
882 * there were errors and all of the errors were corrected, the number of
883 * corrected errors is returned. If uncorrectable errors exist, %-1 is
884 * returned.
Vimal Singh67ce04b2009-05-12 13:47:03 -0700885 */
886static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
887 u_char *read_ecc, u_char *calc_ecc)
888{
889 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
890 mtd);
891 int blockCnt = 0, i = 0, ret = 0;
John Ogness74f1b722011-02-28 13:12:46 +0100892 int stat = 0;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700893
894 /* Ex NAND_ECC_HW12_2048 */
895 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
896 (info->nand.ecc.size == 2048))
897 blockCnt = 4;
898 else
899 blockCnt = 1;
900
901 for (i = 0; i < blockCnt; i++) {
902 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
903 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
904 if (ret < 0)
905 return ret;
John Ogness74f1b722011-02-28 13:12:46 +0100906 /* keep track of the number of corrected errors */
907 stat += ret;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700908 }
909 read_ecc += 3;
910 calc_ecc += 3;
911 dat += 512;
912 }
John Ogness74f1b722011-02-28 13:12:46 +0100913 return stat;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700914}
915
916/**
917 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
918 * @mtd: MTD device structure
919 * @dat: The pointer to data on which ecc is computed
920 * @ecc_code: The ecc_code buffer
921 *
922 * Using noninverted ECC can be considered ugly since writing a blank
923 * page ie. padding will clear the ECC bytes. This is no problem as long
924 * nobody is trying to write data on the seemingly unused page. Reading
925 * an erased page will produce an ECC mismatch between generated and read
926 * ECC bytes that has to be dealt with separately.
927 */
928static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
929 u_char *ecc_code)
930{
931 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
932 mtd);
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700933 u32 val;
934
935 val = readl(info->reg.gpmc_ecc_config);
936 if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs)
937 return -EINVAL;
938
939 /* read ecc result */
940 val = readl(info->reg.gpmc_ecc1_result);
941 *ecc_code++ = val; /* P128e, ..., P1e */
942 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
943 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
944 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
945
946 return 0;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700947}
948
949/**
950 * omap_enable_hwecc - This function enables the hardware ecc functionality
951 * @mtd: MTD device structure
952 * @mode: Read/Write mode
953 */
954static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
955{
956 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
957 mtd);
958 struct nand_chip *chip = mtd->priv;
959 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700960 u32 val;
Vimal Singh67ce04b2009-05-12 13:47:03 -0700961
Afzal Mohammed65b97cf2012-08-30 12:53:22 -0700962 /* clear ecc and enable bits */
963 val = ECCCLEAR | ECC1;
964 writel(val, info->reg.gpmc_ecc_control);
965
966 /* program ecc and result sizes */
967 val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
968 ECC1RESULTSIZE);
969 writel(val, info->reg.gpmc_ecc_size_config);
970
971 switch (mode) {
972 case NAND_ECC_READ:
973 case NAND_ECC_WRITE:
974 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
975 break;
976 case NAND_ECC_READSYN:
977 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
978 break;
979 default:
980 dev_info(&info->pdev->dev,
981 "error: unrecognized Mode[%d]!\n", mode);
982 break;
983 }
984
985 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
986 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
987 writel(val, info->reg.gpmc_ecc_config);
Vimal Singh67ce04b2009-05-12 13:47:03 -0700988}
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +0000989
Vimal Singh67ce04b2009-05-12 13:47:03 -0700990/**
991 * omap_wait - wait until the command is done
992 * @mtd: MTD device structure
993 * @chip: NAND Chip structure
994 *
995 * Wait function is called during Program and erase operations and
996 * the way it is called from MTD layer, we should wait till the NAND
997 * chip is ready after the programming/erase operation has completed.
998 *
999 * Erase can take up to 400ms and program up to 20ms according to
1000 * general NAND and SmartMedia specs
1001 */
1002static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
1003{
1004 struct nand_chip *this = mtd->priv;
1005 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1006 mtd);
1007 unsigned long timeo = jiffies;
Ivan Djelica9c465f2012-04-17 13:11:53 +02001008 int status, state = this->state;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001009
1010 if (state == FL_ERASING)
Toan Pham4ff67722013-03-15 10:44:59 -07001011 timeo += msecs_to_jiffies(400);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001012 else
Toan Pham4ff67722013-03-15 10:44:59 -07001013 timeo += msecs_to_jiffies(20);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001014
Afzal Mohammed65b97cf2012-08-30 12:53:22 -07001015 writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001016 while (time_before(jiffies, timeo)) {
Afzal Mohammed65b97cf2012-08-30 12:53:22 -07001017 status = readb(info->reg.gpmc_nand_data);
vimal singhc276aca2009-06-27 11:07:06 +05301018 if (status & NAND_STATUS_READY)
Vimal Singh67ce04b2009-05-12 13:47:03 -07001019 break;
vimal singhc276aca2009-06-27 11:07:06 +05301020 cond_resched();
Vimal Singh67ce04b2009-05-12 13:47:03 -07001021 }
Ivan Djelica9c465f2012-04-17 13:11:53 +02001022
Afzal Mohammed4ea1e4b2012-09-29 11:22:21 +05301023 status = readb(info->reg.gpmc_nand_data);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001024 return status;
1025}
1026
1027/**
1028 * omap_dev_ready - calls the platform specific dev_ready function
1029 * @mtd: MTD device structure
1030 */
1031static int omap_dev_ready(struct mtd_info *mtd)
1032{
Sukumar Ghorai2c01946c2010-07-09 09:14:45 +00001033 unsigned int val = 0;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001034 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1035 mtd);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001036
Afzal Mohammed65b97cf2012-08-30 12:53:22 -07001037 val = readl(info->reg.gpmc_status);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001038
Afzal Mohammed65b97cf2012-08-30 12:53:22 -07001039 if ((val & 0x100) == 0x100) {
1040 return 1;
1041 } else {
1042 return 0;
1043 }
Vimal Singh67ce04b2009-05-12 13:47:03 -07001044}
1045
Pekon Guptaa919e512013-10-24 18:20:21 +05301046#if defined(CONFIG_MTD_NAND_ECC_BCH) || defined(CONFIG_MTD_NAND_OMAP_BCH)
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001047/**
1048 * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction
1049 * @mtd: MTD device structure
1050 * @mode: Read/Write mode
Philip Avinash62116e52013-01-04 13:26:51 +05301051 *
1052 * When using BCH, sector size is hardcoded to 512 bytes.
1053 * Using wrapping mode 6 both for reading and writing if ELM module not uses
1054 * for error correction.
1055 * On writing,
1056 * eccsize0 = 0 (no additional protected byte in spare area)
1057 * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001058 */
1059static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode)
1060{
1061 int nerrors;
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301062 unsigned int dev_width, nsectors;
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001063 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1064 mtd);
1065 struct nand_chip *chip = mtd->priv;
Philip Avinash62116e52013-01-04 13:26:51 +05301066 u32 val, wr_mode;
1067 unsigned int ecc_size1, ecc_size0;
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001068
Philip Avinash62116e52013-01-04 13:26:51 +05301069 /* Using wrapping mode 6 for writing */
1070 wr_mode = BCH_WRAPMODE_6;
1071
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001072 /*
Philip Avinash62116e52013-01-04 13:26:51 +05301073 * ECC engine enabled for valid ecc_size0 nibbles
1074 * and disabled for ecc_size1 nibbles.
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001075 */
Philip Avinash62116e52013-01-04 13:26:51 +05301076 ecc_size0 = BCH_ECC_SIZE0;
1077 ecc_size1 = BCH_ECC_SIZE1;
1078
1079 /* Perform ecc calculation on 512-byte sector */
1080 nsectors = 1;
1081
1082 /* Update number of error correction */
1083 nerrors = info->nand.ecc.strength;
1084
1085 /* Multi sector reading/writing for NAND flash with page size < 4096 */
1086 if (info->is_elm_used && (mtd->writesize <= 4096)) {
1087 if (mode == NAND_ECC_READ) {
1088 /* Using wrapping mode 1 for reading */
1089 wr_mode = BCH_WRAPMODE_1;
1090
1091 /*
1092 * ECC engine enabled for ecc_size0 nibbles
1093 * and disabled for ecc_size1 nibbles.
1094 */
1095 ecc_size0 = (nerrors == 8) ?
1096 BCH8R_ECC_SIZE0 : BCH4R_ECC_SIZE0;
1097 ecc_size1 = (nerrors == 8) ?
1098 BCH8R_ECC_SIZE1 : BCH4R_ECC_SIZE1;
1099 }
1100
1101 /* Perform ecc calculation for one page (< 4096) */
1102 nsectors = info->nand.ecc.steps;
1103 }
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301104
1105 writel(ECC1, info->reg.gpmc_ecc_control);
1106
Philip Avinash62116e52013-01-04 13:26:51 +05301107 /* Configure ecc size for BCH */
1108 val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301109 writel(val, info->reg.gpmc_ecc_size_config);
1110
Philip Avinash62116e52013-01-04 13:26:51 +05301111 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1112
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301113 /* BCH configuration */
1114 val = ((1 << 16) | /* enable BCH */
1115 (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
Philip Avinash62116e52013-01-04 13:26:51 +05301116 (wr_mode << 8) | /* wrap mode */
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301117 (dev_width << 7) | /* bus width */
1118 (((nsectors-1) & 0x7) << 4) | /* number of sectors */
1119 (info->gpmc_cs << 1) | /* ECC CS */
1120 (0x1)); /* enable ECC */
1121
1122 writel(val, info->reg.gpmc_ecc_config);
1123
Philip Avinash62116e52013-01-04 13:26:51 +05301124 /* Clear ecc and enable bits */
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301125 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001126}
Pekon Guptaa919e512013-10-24 18:20:21 +05301127#endif
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001128
Pekon Guptaa919e512013-10-24 18:20:21 +05301129#ifdef CONFIG_MTD_NAND_ECC_BCH
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001130/**
1131 * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes
1132 * @mtd: MTD device structure
1133 * @dat: The pointer to data on which ecc is computed
1134 * @ecc_code: The ecc_code buffer
1135 */
1136static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat,
1137 u_char *ecc_code)
1138{
1139 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1140 mtd);
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301141 unsigned long nsectors, val1, val2;
1142 int i;
1143
1144 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1145
1146 for (i = 0; i < nsectors; i++) {
1147
1148 /* Read hw-computed remainder */
1149 val1 = readl(info->reg.gpmc_bch_result0[i]);
1150 val2 = readl(info->reg.gpmc_bch_result1[i]);
1151
1152 /*
1153 * Add constant polynomial to remainder, in order to get an ecc
1154 * sequence of 0xFFs for a buffer filled with 0xFFs; and
1155 * left-justify the resulting polynomial.
1156 */
1157 *ecc_code++ = 0x28 ^ ((val2 >> 12) & 0xFF);
1158 *ecc_code++ = 0x13 ^ ((val2 >> 4) & 0xFF);
1159 *ecc_code++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
1160 *ecc_code++ = 0x39 ^ ((val1 >> 20) & 0xFF);
1161 *ecc_code++ = 0x96 ^ ((val1 >> 12) & 0xFF);
1162 *ecc_code++ = 0xac ^ ((val1 >> 4) & 0xFF);
1163 *ecc_code++ = 0x7f ^ ((val1 & 0xF) << 4);
1164 }
1165
1166 return 0;
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001167}
1168
1169/**
1170 * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes
1171 * @mtd: MTD device structure
1172 * @dat: The pointer to data on which ecc is computed
1173 * @ecc_code: The ecc_code buffer
1174 */
1175static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat,
1176 u_char *ecc_code)
1177{
1178 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1179 mtd);
Afzal Mohammed2ef9f3d2012-10-04 19:03:06 +05301180 unsigned long nsectors, val1, val2, val3, val4;
1181 int i;
1182
1183 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1184
1185 for (i = 0; i < nsectors; i++) {
1186
1187 /* Read hw-computed remainder */
1188 val1 = readl(info->reg.gpmc_bch_result0[i]);
1189 val2 = readl(info->reg.gpmc_bch_result1[i]);
1190 val3 = readl(info->reg.gpmc_bch_result2[i]);
1191 val4 = readl(info->reg.gpmc_bch_result3[i]);
1192
1193 /*
1194 * Add constant polynomial to remainder, in order to get an ecc
1195 * sequence of 0xFFs for a buffer filled with 0xFFs.
1196 */
1197 *ecc_code++ = 0xef ^ (val4 & 0xFF);
1198 *ecc_code++ = 0x51 ^ ((val3 >> 24) & 0xFF);
1199 *ecc_code++ = 0x2e ^ ((val3 >> 16) & 0xFF);
1200 *ecc_code++ = 0x09 ^ ((val3 >> 8) & 0xFF);
1201 *ecc_code++ = 0xed ^ (val3 & 0xFF);
1202 *ecc_code++ = 0x93 ^ ((val2 >> 24) & 0xFF);
1203 *ecc_code++ = 0x9a ^ ((val2 >> 16) & 0xFF);
1204 *ecc_code++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
1205 *ecc_code++ = 0x97 ^ (val2 & 0xFF);
1206 *ecc_code++ = 0x79 ^ ((val1 >> 24) & 0xFF);
1207 *ecc_code++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
1208 *ecc_code++ = 0x24 ^ ((val1 >> 8) & 0xFF);
1209 *ecc_code++ = 0xb5 ^ (val1 & 0xFF);
1210 }
1211
1212 return 0;
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001213}
Pekon Guptaa919e512013-10-24 18:20:21 +05301214#endif /* CONFIG_MTD_NAND_ECC_BCH */
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001215
Pekon Guptaa919e512013-10-24 18:20:21 +05301216#ifdef CONFIG_MTD_NAND_OMAP_BCH
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001217/**
Philip Avinash62116e52013-01-04 13:26:51 +05301218 * omap3_calculate_ecc_bch - Generate bytes of ECC bytes
1219 * @mtd: MTD device structure
1220 * @dat: The pointer to data on which ecc is computed
1221 * @ecc_code: The ecc_code buffer
1222 *
1223 * Support calculating of BCH4/8 ecc vectors for the page
1224 */
1225static int omap3_calculate_ecc_bch(struct mtd_info *mtd, const u_char *dat,
1226 u_char *ecc_code)
1227{
1228 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1229 mtd);
1230 unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
1231 int i, eccbchtsel;
1232
1233 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1234 /*
1235 * find BCH scheme used
1236 * 0 -> BCH4
1237 * 1 -> BCH8
1238 */
1239 eccbchtsel = ((readl(info->reg.gpmc_ecc_config) >> 12) & 0x3);
1240
1241 for (i = 0; i < nsectors; i++) {
1242
1243 /* Read hw-computed remainder */
1244 bch_val1 = readl(info->reg.gpmc_bch_result0[i]);
1245 bch_val2 = readl(info->reg.gpmc_bch_result1[i]);
1246 if (eccbchtsel) {
1247 bch_val3 = readl(info->reg.gpmc_bch_result2[i]);
1248 bch_val4 = readl(info->reg.gpmc_bch_result3[i]);
1249 }
1250
1251 if (eccbchtsel) {
1252 /* BCH8 ecc scheme */
1253 *ecc_code++ = (bch_val4 & 0xFF);
1254 *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1255 *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1256 *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1257 *ecc_code++ = (bch_val3 & 0xFF);
1258 *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1259 *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1260 *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1261 *ecc_code++ = (bch_val2 & 0xFF);
1262 *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1263 *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1264 *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1265 *ecc_code++ = (bch_val1 & 0xFF);
1266 /*
1267 * Setting 14th byte to zero to handle
1268 * erased page & maintain compatibility
1269 * with RBL
1270 */
1271 *ecc_code++ = 0x0;
1272 } else {
1273 /* BCH4 ecc scheme */
1274 *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1275 *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1276 *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1277 ((bch_val1 >> 28) & 0xF);
1278 *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1279 *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1280 *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1281 *ecc_code++ = ((bch_val1 & 0xF) << 4);
1282 /*
1283 * Setting 8th byte to zero to handle
1284 * erased page
1285 */
1286 *ecc_code++ = 0x0;
1287 }
1288 }
1289
1290 return 0;
1291}
1292
1293/**
1294 * erased_sector_bitflips - count bit flips
1295 * @data: data sector buffer
1296 * @oob: oob buffer
1297 * @info: omap_nand_info
1298 *
1299 * Check the bit flips in erased page falls below correctable level.
1300 * If falls below, report the page as erased with correctable bit
1301 * flip, else report as uncorrectable page.
1302 */
1303static int erased_sector_bitflips(u_char *data, u_char *oob,
1304 struct omap_nand_info *info)
1305{
1306 int flip_bits = 0, i;
1307
1308 for (i = 0; i < info->nand.ecc.size; i++) {
1309 flip_bits += hweight8(~data[i]);
1310 if (flip_bits > info->nand.ecc.strength)
1311 return 0;
1312 }
1313
1314 for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1315 flip_bits += hweight8(~oob[i]);
1316 if (flip_bits > info->nand.ecc.strength)
1317 return 0;
1318 }
1319
1320 /*
1321 * Bit flips falls in correctable level.
1322 * Fill data area with 0xFF
1323 */
1324 if (flip_bits) {
1325 memset(data, 0xFF, info->nand.ecc.size);
1326 memset(oob, 0xFF, info->nand.ecc.bytes);
1327 }
1328
1329 return flip_bits;
1330}
1331
1332/**
1333 * omap_elm_correct_data - corrects page data area in case error reported
1334 * @mtd: MTD device structure
1335 * @data: page data
1336 * @read_ecc: ecc read from nand flash
1337 * @calc_ecc: ecc read from HW ECC registers
1338 *
1339 * Calculated ecc vector reported as zero in case of non-error pages.
1340 * In case of error/erased pages non-zero error vector is reported.
1341 * In case of non-zero ecc vector, check read_ecc at fixed offset
1342 * (x = 13/7 in case of BCH8/4 == 0) to find page programmed or not.
1343 * To handle bit flips in this data, count the number of 0's in
1344 * read_ecc[x] and check if it greater than 4. If it is less, it is
1345 * programmed page, else erased page.
1346 *
1347 * 1. If page is erased, check with standard ecc vector (ecc vector
1348 * for erased page to find any bit flip). If check fails, bit flip
1349 * is present in erased page. Count the bit flips in erased page and
1350 * if it falls under correctable level, report page with 0xFF and
1351 * update the correctable bit information.
1352 * 2. If error is reported on programmed page, update elm error
1353 * vector and correct the page with ELM error correction routine.
1354 *
1355 */
1356static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data,
1357 u_char *read_ecc, u_char *calc_ecc)
1358{
1359 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1360 mtd);
1361 int eccsteps = info->nand.ecc.steps;
1362 int i , j, stat = 0;
1363 int eccsize, eccflag, ecc_vector_size;
1364 struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1365 u_char *ecc_vec = calc_ecc;
1366 u_char *spare_ecc = read_ecc;
1367 u_char *erased_ecc_vec;
1368 enum bch_ecc type;
1369 bool is_error_reported = false;
1370
1371 /* Initialize elm error vector to zero */
1372 memset(err_vec, 0, sizeof(err_vec));
1373
1374 if (info->nand.ecc.strength == BCH8_MAX_ERROR) {
1375 type = BCH8_ECC;
1376 erased_ecc_vec = bch8_vector;
1377 } else {
1378 type = BCH4_ECC;
1379 erased_ecc_vec = bch4_vector;
1380 }
1381
1382 ecc_vector_size = info->nand.ecc.bytes;
1383
1384 /*
1385 * Remove extra byte padding for BCH8 RBL
1386 * compatibility and erased page handling
1387 */
1388 eccsize = ecc_vector_size - 1;
1389
1390 for (i = 0; i < eccsteps ; i++) {
1391 eccflag = 0; /* initialize eccflag */
1392
1393 /*
1394 * Check any error reported,
1395 * In case of error, non zero ecc reported.
1396 */
1397
1398 for (j = 0; (j < eccsize); j++) {
1399 if (calc_ecc[j] != 0) {
1400 eccflag = 1; /* non zero ecc, error present */
1401 break;
1402 }
1403 }
1404
1405 if (eccflag == 1) {
1406 /*
1407 * Set threshold to minimum of 4, half of ecc.strength/2
1408 * to allow max bit flip in byte to 4
1409 */
1410 unsigned int threshold = min_t(unsigned int, 4,
1411 info->nand.ecc.strength / 2);
1412
1413 /*
1414 * Check data area is programmed by counting
1415 * number of 0's at fixed offset in spare area.
1416 * Checking count of 0's against threshold.
1417 * In case programmed page expects at least threshold
1418 * zeros in byte.
1419 * If zeros are less than threshold for programmed page/
1420 * zeros are more than threshold erased page, either
1421 * case page reported as uncorrectable.
1422 */
1423 if (hweight8(~read_ecc[eccsize]) >= threshold) {
1424 /*
1425 * Update elm error vector as
1426 * data area is programmed
1427 */
1428 err_vec[i].error_reported = true;
1429 is_error_reported = true;
1430 } else {
1431 /* Error reported in erased page */
1432 int bitflip_count;
1433 u_char *buf = &data[info->nand.ecc.size * i];
1434
1435 if (memcmp(calc_ecc, erased_ecc_vec, eccsize)) {
1436 bitflip_count = erased_sector_bitflips(
1437 buf, read_ecc, info);
1438
1439 if (bitflip_count)
1440 stat += bitflip_count;
1441 else
1442 return -EINVAL;
1443 }
1444 }
1445 }
1446
1447 /* Update the ecc vector */
1448 calc_ecc += ecc_vector_size;
1449 read_ecc += ecc_vector_size;
1450 }
1451
1452 /* Check if any error reported */
1453 if (!is_error_reported)
1454 return 0;
1455
1456 /* Decode BCH error using ELM module */
1457 elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1458
1459 for (i = 0; i < eccsteps; i++) {
1460 if (err_vec[i].error_reported) {
1461 for (j = 0; j < err_vec[i].error_count; j++) {
1462 u32 bit_pos, byte_pos, error_max, pos;
1463
1464 if (type == BCH8_ECC)
1465 error_max = BCH8_ECC_MAX;
1466 else
1467 error_max = BCH4_ECC_MAX;
1468
1469 if (info->nand.ecc.strength == BCH8_MAX_ERROR)
1470 pos = err_vec[i].error_loc[j];
1471 else
1472 /* Add 4 to take care 4 bit padding */
1473 pos = err_vec[i].error_loc[j] +
1474 BCH4_BIT_PAD;
1475
1476 /* Calculate bit position of error */
1477 bit_pos = pos % 8;
1478
1479 /* Calculate byte position of error */
1480 byte_pos = (error_max - pos - 1) / 8;
1481
1482 if (pos < error_max) {
1483 if (byte_pos < 512)
1484 data[byte_pos] ^= 1 << bit_pos;
1485 else
1486 spare_ecc[byte_pos - 512] ^=
1487 1 << bit_pos;
1488 }
1489 /* else, not interested to correct ecc */
1490 }
1491 }
1492
1493 /* Update number of correctable errors */
1494 stat += err_vec[i].error_count;
1495
1496 /* Update page data with sector size */
1497 data += info->nand.ecc.size;
1498 spare_ecc += ecc_vector_size;
1499 }
1500
1501 for (i = 0; i < eccsteps; i++)
1502 /* Return error if uncorrectable error present */
1503 if (err_vec[i].error_uncorrectable)
1504 return -EINVAL;
1505
1506 return stat;
1507}
1508
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001509/**
Philip Avinash62116e52013-01-04 13:26:51 +05301510 * omap_write_page_bch - BCH ecc based write page function for entire page
1511 * @mtd: mtd info structure
1512 * @chip: nand chip info structure
1513 * @buf: data buffer
1514 * @oob_required: must write chip->oob_poi to OOB
1515 *
1516 * Custom write page method evolved to support multi sector writing in one shot
1517 */
1518static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1519 const uint8_t *buf, int oob_required)
1520{
1521 int i;
1522 uint8_t *ecc_calc = chip->buffers->ecccalc;
1523 uint32_t *eccpos = chip->ecc.layout->eccpos;
1524
1525 /* Enable GPMC ecc engine */
1526 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1527
1528 /* Write data */
1529 chip->write_buf(mtd, buf, mtd->writesize);
1530
1531 /* Update ecc vector from GPMC result registers */
1532 chip->ecc.calculate(mtd, buf, &ecc_calc[0]);
1533
1534 for (i = 0; i < chip->ecc.total; i++)
1535 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1536
1537 /* Write ecc vector to OOB area */
1538 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1539 return 0;
1540}
1541
1542/**
1543 * omap_read_page_bch - BCH ecc based page read function for entire page
1544 * @mtd: mtd info structure
1545 * @chip: nand chip info structure
1546 * @buf: buffer to store read data
1547 * @oob_required: caller requires OOB data read to chip->oob_poi
1548 * @page: page number to read
1549 *
1550 * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1551 * used for error correction.
1552 * Custom method evolved to support ELM error correction & multi sector
1553 * reading. On reading page data area is read along with OOB data with
1554 * ecc engine enabled. ecc vector updated after read of OOB data.
1555 * For non error pages ecc vector reported as zero.
1556 */
1557static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1558 uint8_t *buf, int oob_required, int page)
1559{
1560 uint8_t *ecc_calc = chip->buffers->ecccalc;
1561 uint8_t *ecc_code = chip->buffers->ecccode;
1562 uint32_t *eccpos = chip->ecc.layout->eccpos;
1563 uint8_t *oob = &chip->oob_poi[eccpos[0]];
1564 uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0];
1565 int stat;
1566 unsigned int max_bitflips = 0;
1567
1568 /* Enable GPMC ecc engine */
1569 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1570
1571 /* Read data */
1572 chip->read_buf(mtd, buf, mtd->writesize);
1573
1574 /* Read oob bytes */
1575 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
1576 chip->read_buf(mtd, oob, chip->ecc.total);
1577
1578 /* Calculate ecc bytes */
1579 chip->ecc.calculate(mtd, buf, ecc_calc);
1580
1581 memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total);
1582
1583 stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc);
1584
1585 if (stat < 0) {
1586 mtd->ecc_stats.failed++;
1587 } else {
1588 mtd->ecc_stats.corrected += stat;
1589 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1590 }
1591
1592 return max_bitflips;
1593}
1594
1595/**
Pekon Guptaa919e512013-10-24 18:20:21 +05301596 * is_elm_present - checks for presence of ELM module by scanning DT nodes
1597 * @omap_nand_info: NAND device structure containing platform data
1598 * @bch_type: 0x0=BCH4, 0x1=BCH8, 0x2=BCH16
1599 */
1600static int is_elm_present(struct omap_nand_info *info,
1601 struct device_node *elm_node, enum bch_ecc bch_type)
1602{
1603 struct platform_device *pdev;
1604 info->is_elm_used = false;
1605 /* check whether elm-id is passed via DT */
1606 if (!elm_node) {
1607 pr_err("nand: error: ELM DT node not found\n");
1608 return -ENODEV;
1609 }
1610 pdev = of_find_device_by_node(elm_node);
1611 /* check whether ELM device is registered */
1612 if (!pdev) {
1613 pr_err("nand: error: ELM device not found\n");
1614 return -ENODEV;
1615 }
1616 /* ELM module available, now configure it */
1617 info->elm_dev = &pdev->dev;
1618 if (elm_config(info->elm_dev, bch_type))
1619 return -ENODEV;
1620 info->is_elm_used = true;
1621 return 0;
1622}
1623#endif /* CONFIG_MTD_NAND_ECC_BCH */
1624
Bill Pemberton06f25512012-11-19 13:23:07 -05001625static int omap_nand_probe(struct platform_device *pdev)
Vimal Singh67ce04b2009-05-12 13:47:03 -07001626{
1627 struct omap_nand_info *info;
1628 struct omap_nand_platform_data *pdata;
Pekon Gupta633deb52013-10-24 18:20:19 +05301629 struct mtd_info *mtd;
1630 struct nand_chip *nand_chip;
Pekon Guptab491da72013-10-24 18:20:22 +05301631 struct nand_ecclayout *ecclayout;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001632 int err;
Pekon Guptab491da72013-10-24 18:20:22 +05301633 int i;
Pekon Gupta633deb52013-10-24 18:20:19 +05301634 dma_cap_mask_t mask;
1635 unsigned sig;
Afzal Mohammed9c4c2f82012-08-30 12:53:23 -07001636 struct resource *res;
Daniel Mackccf04c52012-12-14 11:36:41 +01001637 struct mtd_part_parser_data ppdata = {};
Vimal Singh67ce04b2009-05-12 13:47:03 -07001638
Jingoo Han453810b2013-07-30 17:18:33 +09001639 pdata = dev_get_platdata(&pdev->dev);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001640 if (pdata == NULL) {
1641 dev_err(&pdev->dev, "platform data missing\n");
1642 return -ENODEV;
1643 }
1644
1645 info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
1646 if (!info)
1647 return -ENOMEM;
1648
1649 platform_set_drvdata(pdev, info);
1650
1651 spin_lock_init(&info->controller.lock);
1652 init_waitqueue_head(&info->controller.wq);
1653
Pekon Gupta633deb52013-10-24 18:20:19 +05301654 info->pdev = pdev;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001655 info->gpmc_cs = pdata->cs;
Afzal Mohammed65b97cf2012-08-30 12:53:22 -07001656 info->reg = pdata->reg;
Pekon Guptaa919e512013-10-24 18:20:21 +05301657 info->of_node = pdata->of_node;
Pekon Gupta633deb52013-10-24 18:20:19 +05301658 mtd = &info->mtd;
1659 mtd->priv = &info->nand;
1660 mtd->name = dev_name(&pdev->dev);
1661 mtd->owner = THIS_MODULE;
1662 nand_chip = &info->nand;
Pekon Gupta32d42a82013-10-24 18:20:23 +05301663 nand_chip->ecc.priv = NULL;
Pekon Gupta633deb52013-10-24 18:20:19 +05301664 nand_chip->options |= NAND_SKIP_BBTSCAN;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001665
Afzal Mohammed9c4c2f82012-08-30 12:53:23 -07001666 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1667 if (res == NULL) {
1668 err = -EINVAL;
1669 dev_err(&pdev->dev, "error getting memory resource\n");
1670 goto out_free_info;
1671 }
Vimal Singh67ce04b2009-05-12 13:47:03 -07001672
Afzal Mohammed9c4c2f82012-08-30 12:53:23 -07001673 info->phys_base = res->start;
1674 info->mem_size = resource_size(res);
1675
1676 if (!request_mem_region(info->phys_base, info->mem_size,
Vimal Singh67ce04b2009-05-12 13:47:03 -07001677 pdev->dev.driver->name)) {
1678 err = -EBUSY;
Vimal Singh2f70a1e2010-02-15 10:03:33 -08001679 goto out_free_info;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001680 }
1681
Pekon Gupta633deb52013-10-24 18:20:19 +05301682 nand_chip->IO_ADDR_R = ioremap(info->phys_base, info->mem_size);
1683 if (!nand_chip->IO_ADDR_R) {
Vimal Singh67ce04b2009-05-12 13:47:03 -07001684 err = -ENOMEM;
1685 goto out_release_mem_region;
1686 }
vimal singh59e9c5a2009-07-13 16:26:24 +05301687
Pekon Gupta633deb52013-10-24 18:20:19 +05301688 nand_chip->controller = &info->controller;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001689
Pekon Gupta633deb52013-10-24 18:20:19 +05301690 nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
1691 nand_chip->cmd_ctrl = omap_hwcontrol;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001692
Vimal Singh67ce04b2009-05-12 13:47:03 -07001693 /*
1694 * If RDY/BSY line is connected to OMAP then use the omap ready
Peter Meerwald4cacbe22012-07-19 13:21:04 +02001695 * function and the generic nand_wait function which reads the status
1696 * register after monitoring the RDY/BSY line. Otherwise use a standard
Vimal Singh67ce04b2009-05-12 13:47:03 -07001697 * chip delay which is slightly more than tR (AC Timing) of the NAND
1698 * device and read status register until you get a failure or success
1699 */
1700 if (pdata->dev_ready) {
Pekon Gupta633deb52013-10-24 18:20:19 +05301701 nand_chip->dev_ready = omap_dev_ready;
1702 nand_chip->chip_delay = 0;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001703 } else {
Pekon Gupta633deb52013-10-24 18:20:19 +05301704 nand_chip->waitfunc = omap_wait;
1705 nand_chip->chip_delay = 50;
Vimal Singh67ce04b2009-05-12 13:47:03 -07001706 }
1707
Pekon Guptaf18befb2013-10-24 18:20:20 +05301708 /* scan NAND device connected to chip controller */
1709 nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16;
1710 if (nand_scan_ident(mtd, 1, NULL)) {
1711 pr_err("nand device scan failed, may be bus-width mismatch\n");
1712 err = -ENXIO;
1713 goto out_release_mem_region;
1714 }
1715
Pekon Guptab491da72013-10-24 18:20:22 +05301716 /* check for small page devices */
1717 if ((mtd->oobsize < 64) && (pdata->ecc_opt != OMAP_ECC_HAM1_CODE_HW)) {
1718 pr_err("small page devices are not supported\n");
1719 err = -EINVAL;
1720 goto out_release_mem_region;
1721 }
1722
Pekon Guptaf18befb2013-10-24 18:20:20 +05301723 /* re-populate low-level callbacks based on xfer modes */
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301724 switch (pdata->xfer_type) {
1725 case NAND_OMAP_PREFETCH_POLLED:
Pekon Gupta633deb52013-10-24 18:20:19 +05301726 nand_chip->read_buf = omap_read_buf_pref;
1727 nand_chip->write_buf = omap_write_buf_pref;
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301728 break;
vimal singhdfe32892009-07-13 16:29:16 +05301729
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301730 case NAND_OMAP_POLLED:
Pekon Gupta633deb52013-10-24 18:20:19 +05301731 if (nand_chip->options & NAND_BUSWIDTH_16) {
1732 nand_chip->read_buf = omap_read_buf16;
1733 nand_chip->write_buf = omap_write_buf16;
vimal singh59e9c5a2009-07-13 16:26:24 +05301734 } else {
Pekon Gupta633deb52013-10-24 18:20:19 +05301735 nand_chip->read_buf = omap_read_buf8;
1736 nand_chip->write_buf = omap_write_buf8;
vimal singh59e9c5a2009-07-13 16:26:24 +05301737 }
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301738 break;
1739
1740 case NAND_OMAP_PREFETCH_DMA:
Russell King763e7352012-04-25 00:16:00 +01001741 dma_cap_zero(mask);
1742 dma_cap_set(DMA_SLAVE, mask);
1743 sig = OMAP24XX_DMA_GPMC;
1744 info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1745 if (!info->dma) {
Russell King2df41d02012-04-25 00:19:39 +01001746 dev_err(&pdev->dev, "DMA engine request failed\n");
1747 err = -ENXIO;
1748 goto out_release_mem_region;
Russell King763e7352012-04-25 00:16:00 +01001749 } else {
1750 struct dma_slave_config cfg;
Russell King763e7352012-04-25 00:16:00 +01001751
1752 memset(&cfg, 0, sizeof(cfg));
1753 cfg.src_addr = info->phys_base;
1754 cfg.dst_addr = info->phys_base;
1755 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1756 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1757 cfg.src_maxburst = 16;
1758 cfg.dst_maxburst = 16;
Arnd Bergmannd680e2c2012-08-04 11:05:25 +00001759 err = dmaengine_slave_config(info->dma, &cfg);
1760 if (err) {
Russell King763e7352012-04-25 00:16:00 +01001761 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
Arnd Bergmannd680e2c2012-08-04 11:05:25 +00001762 err);
Russell King763e7352012-04-25 00:16:00 +01001763 goto out_release_mem_region;
1764 }
Pekon Gupta633deb52013-10-24 18:20:19 +05301765 nand_chip->read_buf = omap_read_buf_dma_pref;
1766 nand_chip->write_buf = omap_write_buf_dma_pref;
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301767 }
1768 break;
1769
Sukumar Ghorai4e070372011-01-28 15:42:06 +05301770 case NAND_OMAP_PREFETCH_IRQ:
Afzal Mohammed5c468452012-08-30 12:53:24 -07001771 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1772 if (info->gpmc_irq_fifo <= 0) {
1773 dev_err(&pdev->dev, "error getting fifo irq\n");
1774 err = -ENODEV;
1775 goto out_release_mem_region;
1776 }
1777 err = request_irq(info->gpmc_irq_fifo, omap_nand_irq,
1778 IRQF_SHARED, "gpmc-nand-fifo", info);
Sukumar Ghorai4e070372011-01-28 15:42:06 +05301779 if (err) {
1780 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
Afzal Mohammed5c468452012-08-30 12:53:24 -07001781 info->gpmc_irq_fifo, err);
1782 info->gpmc_irq_fifo = 0;
Sukumar Ghorai4e070372011-01-28 15:42:06 +05301783 goto out_release_mem_region;
Sukumar Ghorai4e070372011-01-28 15:42:06 +05301784 }
Afzal Mohammed5c468452012-08-30 12:53:24 -07001785
1786 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1787 if (info->gpmc_irq_count <= 0) {
1788 dev_err(&pdev->dev, "error getting count irq\n");
1789 err = -ENODEV;
1790 goto out_release_mem_region;
1791 }
1792 err = request_irq(info->gpmc_irq_count, omap_nand_irq,
1793 IRQF_SHARED, "gpmc-nand-count", info);
1794 if (err) {
1795 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1796 info->gpmc_irq_count, err);
1797 info->gpmc_irq_count = 0;
1798 goto out_release_mem_region;
1799 }
1800
Pekon Gupta633deb52013-10-24 18:20:19 +05301801 nand_chip->read_buf = omap_read_buf_irq_pref;
1802 nand_chip->write_buf = omap_write_buf_irq_pref;
Afzal Mohammed5c468452012-08-30 12:53:24 -07001803
Sukumar Ghorai4e070372011-01-28 15:42:06 +05301804 break;
1805
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301806 default:
1807 dev_err(&pdev->dev,
1808 "xfer_type(%d) not supported!\n", pdata->xfer_type);
1809 err = -EINVAL;
1810 goto out_release_mem_region;
vimal singh59e9c5a2009-07-13 16:26:24 +05301811 }
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301812
Pekon Guptaa919e512013-10-24 18:20:21 +05301813 /* populate MTD interface based on ECC scheme */
Pekon Guptab491da72013-10-24 18:20:22 +05301814 nand_chip->ecc.layout = &omap_oobinfo;
1815 ecclayout = &omap_oobinfo;
Pekon Guptaa919e512013-10-24 18:20:21 +05301816 switch (pdata->ecc_opt) {
1817 case OMAP_ECC_HAM1_CODE_HW:
1818 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
1819 nand_chip->ecc.mode = NAND_ECC_HW;
Pekon Gupta633deb52013-10-24 18:20:19 +05301820 nand_chip->ecc.bytes = 3;
1821 nand_chip->ecc.size = 512;
1822 nand_chip->ecc.strength = 1;
1823 nand_chip->ecc.calculate = omap_calculate_ecc;
1824 nand_chip->ecc.hwctl = omap_enable_hwecc;
1825 nand_chip->ecc.correct = omap_correct_data;
Pekon Guptab491da72013-10-24 18:20:22 +05301826 /* define ECC layout */
1827 ecclayout->eccbytes = nand_chip->ecc.bytes *
1828 (mtd->writesize /
1829 nand_chip->ecc.size);
1830 if (nand_chip->options & NAND_BUSWIDTH_16)
1831 ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH;
1832 else
1833 ecclayout->eccpos[0] = 1;
1834 ecclayout->oobfree->offset = ecclayout->eccpos[0] +
1835 ecclayout->eccbytes;
Pekon Guptaa919e512013-10-24 18:20:21 +05301836 break;
1837
1838 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1839#ifdef CONFIG_MTD_NAND_ECC_BCH
1840 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
1841 nand_chip->ecc.mode = NAND_ECC_HW;
1842 nand_chip->ecc.size = 512;
1843 nand_chip->ecc.bytes = 7;
1844 nand_chip->ecc.strength = 4;
1845 nand_chip->ecc.hwctl = omap3_enable_hwecc_bch;
Pekon Gupta32d42a82013-10-24 18:20:23 +05301846 nand_chip->ecc.correct = nand_bch_correct_data;
Pekon Guptaa919e512013-10-24 18:20:21 +05301847 nand_chip->ecc.calculate = omap3_calculate_ecc_bch4;
Pekon Guptab491da72013-10-24 18:20:22 +05301848 /* define ECC layout */
1849 ecclayout->eccbytes = nand_chip->ecc.bytes *
1850 (mtd->writesize /
1851 nand_chip->ecc.size);
1852 ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH;
1853 ecclayout->oobfree->offset = ecclayout->eccpos[0] +
1854 ecclayout->eccbytes;
Pekon Guptaa919e512013-10-24 18:20:21 +05301855 /* software bch library is used for locating errors */
Pekon Gupta32d42a82013-10-24 18:20:23 +05301856 nand_chip->ecc.priv = nand_bch_init(mtd,
1857 nand_chip->ecc.size,
1858 nand_chip->ecc.bytes,
1859 &nand_chip->ecc.layout);
1860 if (!nand_chip->ecc.priv) {
Pekon Guptaa919e512013-10-24 18:20:21 +05301861 pr_err("nand: error: unable to use s/w BCH library\n");
1862 err = -EINVAL;
1863 }
1864 break;
1865#else
1866 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1867 err = -EINVAL;
1868 goto out_release_mem_region;
1869#endif
1870
1871 case OMAP_ECC_BCH4_CODE_HW:
1872#ifdef CONFIG_MTD_NAND_OMAP_BCH
1873 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
1874 nand_chip->ecc.mode = NAND_ECC_HW;
1875 nand_chip->ecc.size = 512;
1876 /* 14th bit is kept reserved for ROM-code compatibility */
1877 nand_chip->ecc.bytes = 7 + 1;
1878 nand_chip->ecc.strength = 4;
1879 nand_chip->ecc.hwctl = omap3_enable_hwecc_bch;
1880 nand_chip->ecc.correct = omap_elm_correct_data;
1881 nand_chip->ecc.calculate = omap3_calculate_ecc_bch;
1882 nand_chip->ecc.read_page = omap_read_page_bch;
1883 nand_chip->ecc.write_page = omap_write_page_bch;
Pekon Guptab491da72013-10-24 18:20:22 +05301884 /* define ECC layout */
1885 ecclayout->eccbytes = nand_chip->ecc.bytes *
1886 (mtd->writesize /
1887 nand_chip->ecc.size);
1888 ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH;
1889 ecclayout->oobfree->offset = ecclayout->eccpos[0] +
1890 ecclayout->eccbytes;
Pekon Guptaa919e512013-10-24 18:20:21 +05301891 /* This ECC scheme requires ELM H/W block */
1892 if (is_elm_present(info, pdata->elm_of_node, BCH4_ECC) < 0) {
1893 pr_err("nand: error: could not initialize ELM\n");
1894 err = -ENODEV;
1895 goto out_release_mem_region;
1896 }
1897 break;
1898#else
1899 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1900 err = -EINVAL;
1901 goto out_release_mem_region;
1902#endif
1903
1904 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1905#ifdef CONFIG_MTD_NAND_ECC_BCH
1906 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
1907 nand_chip->ecc.mode = NAND_ECC_HW;
1908 nand_chip->ecc.size = 512;
1909 nand_chip->ecc.bytes = 13;
1910 nand_chip->ecc.strength = 8;
1911 nand_chip->ecc.hwctl = omap3_enable_hwecc_bch;
Pekon Gupta32d42a82013-10-24 18:20:23 +05301912 nand_chip->ecc.correct = nand_bch_correct_data;
Pekon Guptaa919e512013-10-24 18:20:21 +05301913 nand_chip->ecc.calculate = omap3_calculate_ecc_bch8;
Pekon Guptab491da72013-10-24 18:20:22 +05301914 /* define ECC layout */
1915 ecclayout->eccbytes = nand_chip->ecc.bytes *
1916 (mtd->writesize /
1917 nand_chip->ecc.size);
1918 ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH;
1919 ecclayout->oobfree->offset = ecclayout->eccpos[0] +
1920 ecclayout->eccbytes;
Pekon Guptaa919e512013-10-24 18:20:21 +05301921 /* software bch library is used for locating errors */
Pekon Gupta32d42a82013-10-24 18:20:23 +05301922 nand_chip->ecc.priv = nand_bch_init(mtd,
1923 nand_chip->ecc.size,
1924 nand_chip->ecc.bytes,
1925 &nand_chip->ecc.layout);
1926 if (!nand_chip->ecc.priv) {
Pekon Guptaa919e512013-10-24 18:20:21 +05301927 pr_err("nand: error: unable to use s/w BCH library\n");
Ivan Djelic0e618ef2012-04-30 12:17:18 +02001928 err = -EINVAL;
1929 goto out_release_mem_region;
1930 }
Pekon Guptaa919e512013-10-24 18:20:21 +05301931 break;
1932#else
1933 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1934 err = -EINVAL;
1935 goto out_release_mem_region;
1936#endif
1937
1938 case OMAP_ECC_BCH8_CODE_HW:
1939#ifdef CONFIG_MTD_NAND_OMAP_BCH
1940 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
1941 nand_chip->ecc.mode = NAND_ECC_HW;
1942 nand_chip->ecc.size = 512;
1943 /* 14th bit is kept reserved for ROM-code compatibility */
1944 nand_chip->ecc.bytes = 13 + 1;
1945 nand_chip->ecc.strength = 8;
1946 nand_chip->ecc.hwctl = omap3_enable_hwecc_bch;
1947 nand_chip->ecc.correct = omap_elm_correct_data;
1948 nand_chip->ecc.calculate = omap3_calculate_ecc_bch;
1949 nand_chip->ecc.read_page = omap_read_page_bch;
1950 nand_chip->ecc.write_page = omap_write_page_bch;
1951 /* This ECC scheme requires ELM H/W block */
1952 if (is_elm_present(info, pdata->elm_of_node, BCH8_ECC) < 0) {
1953 pr_err("nand: error: could not initialize ELM\n");
1954 goto out_release_mem_region;
1955 }
Pekon Guptab491da72013-10-24 18:20:22 +05301956 /* define ECC layout */
1957 ecclayout->eccbytes = nand_chip->ecc.bytes *
1958 (mtd->writesize /
1959 nand_chip->ecc.size);
1960 ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH;
1961 ecclayout->oobfree->offset = ecclayout->eccpos[0] +
1962 ecclayout->eccbytes;
Pekon Guptaa919e512013-10-24 18:20:21 +05301963 break;
1964#else
1965 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1966 err = -EINVAL;
1967 goto out_release_mem_region;
1968#endif
1969
1970 default:
1971 pr_err("nand: error: invalid or unsupported ECC scheme\n");
1972 err = -EINVAL;
1973 goto out_release_mem_region;
Sukumar Ghoraif3d73f32011-01-28 15:42:08 +05301974 }
Vimal Singh67ce04b2009-05-12 13:47:03 -07001975
Pekon Guptab491da72013-10-24 18:20:22 +05301976 /* populate remaining ECC layout data */
1977 ecclayout->oobfree->length = mtd->oobsize - (BADBLOCK_MARKER_LENGTH +
1978 ecclayout->eccbytes);
1979 for (i = 1; i < ecclayout->eccbytes; i++)
1980 ecclayout->eccpos[i] = ecclayout->eccpos[0] + i;
1981 /* check if NAND device's OOB is enough to store ECC signatures */
1982 if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) {
1983 pr_err("not enough OOB bytes required = %d, available=%d\n",
1984 ecclayout->eccbytes, mtd->oobsize);
1985 err = -EINVAL;
1986 goto out_release_mem_region;
Sukumar Ghoraif040d332011-01-28 15:42:09 +05301987 }
Sukumar Ghorai1b0b323c2011-01-28 15:42:04 +05301988
Jan Weitzela80f1c12011-04-19 16:15:34 +02001989 /* second phase scan */
Pekon Gupta633deb52013-10-24 18:20:19 +05301990 if (nand_scan_tail(mtd)) {
Jan Weitzela80f1c12011-04-19 16:15:34 +02001991 err = -ENXIO;
1992 goto out_release_mem_region;
1993 }
1994
Daniel Mackccf04c52012-12-14 11:36:41 +01001995 ppdata.of_node = pdata->of_node;
Pekon Gupta633deb52013-10-24 18:20:19 +05301996 mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts,
Artem Bityutskiy42d7fbe2012-03-09 19:24:26 +02001997 pdata->nr_parts);
Vimal Singh67ce04b2009-05-12 13:47:03 -07001998
Pekon Gupta633deb52013-10-24 18:20:19 +05301999 platform_set_drvdata(pdev, mtd);
Vimal Singh67ce04b2009-05-12 13:47:03 -07002000
2001 return 0;
2002
2003out_release_mem_region:
Russell King763e7352012-04-25 00:16:00 +01002004 if (info->dma)
2005 dma_release_channel(info->dma);
Afzal Mohammed5c468452012-08-30 12:53:24 -07002006 if (info->gpmc_irq_count > 0)
2007 free_irq(info->gpmc_irq_count, info);
2008 if (info->gpmc_irq_fifo > 0)
2009 free_irq(info->gpmc_irq_fifo, info);
Afzal Mohammed9c4c2f82012-08-30 12:53:23 -07002010 release_mem_region(info->phys_base, info->mem_size);
Vimal Singh67ce04b2009-05-12 13:47:03 -07002011out_free_info:
Pekon Gupta32d42a82013-10-24 18:20:23 +05302012 if (nand_chip->ecc.priv) {
2013 nand_bch_free(nand_chip->ecc.priv);
2014 nand_chip->ecc.priv = NULL;
2015 }
Vimal Singh67ce04b2009-05-12 13:47:03 -07002016 kfree(info);
2017
2018 return err;
2019}
2020
2021static int omap_nand_remove(struct platform_device *pdev)
2022{
2023 struct mtd_info *mtd = platform_get_drvdata(pdev);
Pekon Gupta633deb52013-10-24 18:20:19 +05302024 struct nand_chip *nand_chip = mtd->priv;
Vimal Singhf35b6ed2010-01-05 16:01:08 +05302025 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
2026 mtd);
Pekon Gupta32d42a82013-10-24 18:20:23 +05302027 if (nand_chip->ecc.priv) {
2028 nand_bch_free(nand_chip->ecc.priv);
2029 nand_chip->ecc.priv = NULL;
2030 }
Vimal Singh67ce04b2009-05-12 13:47:03 -07002031
Russell King763e7352012-04-25 00:16:00 +01002032 if (info->dma)
2033 dma_release_channel(info->dma);
2034
Afzal Mohammed5c468452012-08-30 12:53:24 -07002035 if (info->gpmc_irq_count > 0)
2036 free_irq(info->gpmc_irq_count, info);
2037 if (info->gpmc_irq_fifo > 0)
2038 free_irq(info->gpmc_irq_fifo, info);
Sukumar Ghorai4e070372011-01-28 15:42:06 +05302039
Vimal Singh67ce04b2009-05-12 13:47:03 -07002040 /* Release NAND device, its internal structures and partitions */
Pekon Gupta633deb52013-10-24 18:20:19 +05302041 nand_release(mtd);
2042 iounmap(nand_chip->IO_ADDR_R);
Afzal Mohammed48b51d42012-09-29 11:14:47 +05302043 release_mem_region(info->phys_base, info->mem_size);
Andreas Bießmann7d9b1102012-08-31 13:35:41 +02002044 kfree(info);
Vimal Singh67ce04b2009-05-12 13:47:03 -07002045 return 0;
2046}
2047
2048static struct platform_driver omap_nand_driver = {
2049 .probe = omap_nand_probe,
2050 .remove = omap_nand_remove,
2051 .driver = {
2052 .name = DRIVER_NAME,
2053 .owner = THIS_MODULE,
2054 },
2055};
2056
Axel Linf99640d2011-11-27 20:45:03 +08002057module_platform_driver(omap_nand_driver);
Vimal Singh67ce04b2009-05-12 13:47:03 -07002058
Axel Linc804c732011-03-07 11:04:24 +08002059MODULE_ALIAS("platform:" DRIVER_NAME);
Vimal Singh67ce04b2009-05-12 13:47:03 -07002060MODULE_LICENSE("GPL");
2061MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");