Shefali Jain | aeedb24 | 2017-11-27 14:12:28 +0530 | [diff] [blame] | 1 | Qualcomm Technologies MSM Clock controller |
| 2 | |
| 3 | Qualcomm Technologies MSM Clock controller devices contain PLLs, root clock |
| 4 | generators and other clocking hardware blocks that provide stable, low power |
| 5 | clocking to hardware blocks on Qualcomm Technologies SOCs. The clock controller |
| 6 | device node lists the power supplies needed to be scaled using the vdd_*-supply |
| 7 | property. |
| 8 | |
| 9 | Minor differences between hardware revisions are handled in code by re-using |
| 10 | the compatible string to indicate the revision. |
| 11 | |
| 12 | Required properties: |
| 13 | - compatible: Must be one of following, |
| 14 | "qcom,gcc-8953" |
Amit Nischal | 32fef62 | 2018-01-30 12:26:30 +0530 | [diff] [blame^] | 15 | "qcom,gcc-sdm632" |
Shefali Jain | aeedb24 | 2017-11-27 14:12:28 +0530 | [diff] [blame] | 16 | "qcom,cc-debug-8953" |
Amit Nischal | 32fef62 | 2018-01-30 12:26:30 +0530 | [diff] [blame^] | 17 | "qcom,cc-debug-sdm632" |
Shefali Jain | aeedb24 | 2017-11-27 14:12:28 +0530 | [diff] [blame] | 18 | "qcom,gcc-mdss-8953" |
Amit Nischal | 32fef62 | 2018-01-30 12:26:30 +0530 | [diff] [blame^] | 19 | "qcom,gcc-mdss-sdm632" |
Shefali Jain | aeedb24 | 2017-11-27 14:12:28 +0530 | [diff] [blame] | 20 | "qcom,gcc-gfx-8953" |
| 21 | "qcom,gcc-gfx-sdm450" |
Amit Nischal | 32fef62 | 2018-01-30 12:26:30 +0530 | [diff] [blame^] | 22 | "qcom,gcc-gfx-sdm632" |
Shefali Jain | aeedb24 | 2017-11-27 14:12:28 +0530 | [diff] [blame] | 23 | |
| 24 | - reg: Pairs of physical base addresses and region sizes of |
| 25 | memory mapped registers. |
| 26 | - reg-names: Names of the bases for the above registers. Currently, |
| 27 | there is one expected base: "cc_base". Optional |
| 28 | reg-names are "apcs_base", "meas", "mmss_base", |
| 29 | "lpass_base", "apcs_c0_base", "apcs_c1_base", |
| 30 | "apcs_cci_base", "efuse". |
| 31 | |
| 32 | Optional properties: |
| 33 | - vdd_dig-supply: The digital logic rail supply. |
| 34 | - <pll>_dig-supply: Some PLLs might have separate digital supply on some |
| 35 | targets. These properties will be provided on those |
| 36 | targets for specific PLLs. |
| 37 | - <pll>_analog-supply: Some PLLs might have separate analog supply on some |
| 38 | targets. These properties will be provided on those |
| 39 | targets for specific PLLs. |
| 40 | - vdd_gpu_mx-supply: MX rail supply for the GPU core. |
| 41 | - #clock_cells: If this device will also be providing controllable |
| 42 | clocks, the clock_cells property needs to be specified. |
| 43 | This will allow the common clock device tree framework |
| 44 | to recognize _this_ device node as a clock provider. |
| 45 | - qcom,<clk>-corner-<vers>: List of frequency voltage pairs that the clock can |
| 46 | operate at. Drivers can use the OPP library API to |
| 47 | operate on the list of OPPs registered using these |
| 48 | values. |
| 49 | - qcom,<clk>-speedbinX: A table of frequency (Hz) to voltage (corner) mapping |
| 50 | that represents the max frequency possible for each |
| 51 | supported voltage level for the clock. |
| 52 | 'X' is the speed bin into which the device falls into - |
| 53 | a bin will have unique frequency-voltage relationships. |
| 54 | The value 'X' is read from efuse registers, and the right |
| 55 | table is picked from multiple possible tables. |
| 56 | - qcom,<clock-name>-opp-handle: phandle references to the devices for which OPP |
| 57 | table is filled with the clock frequency and voltage |
| 58 | values. |
| 59 | - qcom,<clock-name>-opp-store-vcorner: phandle references to the devices for |
| 60 | which OPP table is filled with the clock frequency |
| 61 | and voltage corner/level. |
| 62 | |
| 63 | Example: |
| 64 | clock_gcc: qcom,gcc@fc400000 { |
| 65 | compatible = "qcom,gcc-8974"; |
| 66 | reg = <0xfc400000 0x4000>; |
| 67 | reg-names = "cc_base"; |
| 68 | vdd_dig-supply = <&pm8841_s2_corner>; |
| 69 | #clock-cells = <1>; |
| 70 | }; |
| 71 | |