Blame - drivers/gpu/drm/radeon/radeon_reg.h - kernel/msm-4.9

2009-06-05 14:42:42 +0200

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/*

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* VA Linux Systems Inc., Fremont, California.

*

*

* Permission is hereby granted, free of charge, to any person obtaining

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* a copy of this software and associated documentation files (the

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* "Software"), to deal in the Software without restriction, including

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* without limitation on the rights to use, copy, modify, merge,

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* publish, distribute, sublicense, and/or sell copies of the Software,

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* and to permit persons to whom the Software is furnished to do so,

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* subject to the following conditions:

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*

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* The above copyright notice and this permission notice (including the

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* next paragraph) shall be included in all copies or substantial

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* portions of the Software.

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*

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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

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* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR

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* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,

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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

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* DEALINGS IN THE SOFTWARE.

*/

/*

* Authors:

* Kevin E. Martin <martin@xfree86.org>

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* Rickard E. Faith <faith@valinux.com>

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* Alan Hourihane <alanh@fairlite.demon.co.uk>

*

* References:

*

* !!!! FIXME !!!!

* RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical

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* Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April

* 1999.

*

* !!!! FIXME !!!!

* RAGE 128 Software Development Manual (Technical Reference Manual P/N

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* SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.

*

*/

/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h

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* AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT

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* ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */

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#ifndef _RADEON_REG_H_

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#define _RADEON_REG_H_

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#include "r300_reg.h"

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#include "r500_reg.h"

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#include "r600_reg.h"

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#include "evergreen_reg.h"

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#include "ni_reg.h"

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#include "si_reg.h"

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#define RADEON_MC_AGP_LOCATION 0x014c

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#define RADEON_MC_AGP_START_MASK 0x0000FFFF

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#define RADEON_MC_AGP_START_SHIFT 0

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#define RADEON_MC_AGP_TOP_MASK 0xFFFF0000

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#define RADEON_MC_AGP_TOP_SHIFT 16

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#define RADEON_MC_FB_LOCATION 0x0148

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#define RADEON_MC_FB_START_MASK 0x0000FFFF

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#define RADEON_MC_FB_START_SHIFT 0

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#define RADEON_MC_FB_TOP_MASK 0xFFFF0000

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#define RADEON_MC_FB_TOP_SHIFT 16

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#define RADEON_AGP_BASE_2 0x015c /* r200+ only */

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#define RADEON_AGP_BASE 0x0170

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#define ATI_DATATYPE_VQ 0

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#define ATI_DATATYPE_CI4 1

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#define ATI_DATATYPE_CI8 2

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#define ATI_DATATYPE_ARGB1555 3

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#define ATI_DATATYPE_RGB565 4

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#define ATI_DATATYPE_RGB888 5

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#define ATI_DATATYPE_ARGB8888 6

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#define ATI_DATATYPE_RGB332 7

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#define ATI_DATATYPE_Y8 8

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#define ATI_DATATYPE_RGB8 9

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#define ATI_DATATYPE_CI16 10

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#define ATI_DATATYPE_VYUY_422 11

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#define ATI_DATATYPE_YVYU_422 12

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#define ATI_DATATYPE_AYUV_444 14

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#define ATI_DATATYPE_ARGB4444 15

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/* Registers for 2D/Video/Overlay */

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#define RADEON_ADAPTER_ID 0x0f2c /* PCI */

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#define RADEON_AGP_BASE 0x0170

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#define RADEON_AGP_CNTL 0x0174

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# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)

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# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)

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# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)

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# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)

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# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)

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# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)

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# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)

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# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)

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#define RADEON_STATUS_PCI_CONFIG 0x06

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# define RADEON_CAP_LIST 0x100000

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#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/

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# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */

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# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */

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# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */

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# define RADEON_CAP_ID_EXP 0x10 /* PCI Express */

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#define RADEON_AGP_COMMAND 0x0f60 /* PCI */

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#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/

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# define RADEON_AGP_ENABLE (1<<8)

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#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */

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#define RADEON_AGP_STATUS 0x0f5c /* PCI */

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# define RADEON_AGP_1X_MODE 0x01

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# define RADEON_AGP_2X_MODE 0x02

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# define RADEON_AGP_4X_MODE 0x04

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# define RADEON_AGP_FW_MODE 0x10

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# define RADEON_AGP_MODE_MASK 0x17

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# define RADEON_AGPv3_MODE 0x08

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# define RADEON_AGPv3_4X_MODE 0x01

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# define RADEON_AGPv3_8X_MODE 0x02

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#define RADEON_ATTRDR 0x03c1 /* VGA */

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#define RADEON_ATTRDW 0x03c0 /* VGA */

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#define RADEON_ATTRX 0x03c0 /* VGA */

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#define RADEON_AUX_SC_CNTL 0x1660

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# define RADEON_AUX1_SC_EN (1 << 0)

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# define RADEON_AUX1_SC_MODE_OR (0 << 1)

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# define RADEON_AUX1_SC_MODE_NAND (1 << 1)

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# define RADEON_AUX2_SC_EN (1 << 2)

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# define RADEON_AUX2_SC_MODE_OR (0 << 3)

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# define RADEON_AUX2_SC_MODE_NAND (1 << 3)

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# define RADEON_AUX3_SC_EN (1 << 4)

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# define RADEON_AUX3_SC_MODE_OR (0 << 5)

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# define RADEON_AUX3_SC_MODE_NAND (1 << 5)

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#define RADEON_AUX1_SC_BOTTOM 0x1670

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#define RADEON_AUX1_SC_LEFT 0x1664

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#define RADEON_AUX1_SC_RIGHT 0x1668

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#define RADEON_AUX1_SC_TOP 0x166c

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#define RADEON_AUX2_SC_BOTTOM 0x1680

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#define RADEON_AUX2_SC_LEFT 0x1674

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#define RADEON_AUX2_SC_RIGHT 0x1678

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#define RADEON_AUX2_SC_TOP 0x167c

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#define RADEON_AUX3_SC_BOTTOM 0x1690

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#define RADEON_AUX3_SC_LEFT 0x1684

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#define RADEON_AUX3_SC_RIGHT 0x1688

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#define RADEON_AUX3_SC_TOP 0x168c

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#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8

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#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc

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#define RADEON_BASE_CODE 0x0f0b

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#define RADEON_BIOS_0_SCRATCH 0x0010

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# define RADEON_FP_PANEL_SCALABLE (1 << 16)

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# define RADEON_FP_PANEL_SCALE_EN (1 << 17)

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# define RADEON_FP_CHIP_SCALE_EN (1 << 18)

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# define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)

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# define RADEON_DISPLAY_ROT_MASK (3 << 28)

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# define RADEON_DISPLAY_ROT_00 (0 << 28)

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# define RADEON_DISPLAY_ROT_90 (1 << 28)

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# define RADEON_DISPLAY_ROT_180 (2 << 28)

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# define RADEON_DISPLAY_ROT_270 (3 << 28)

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#define RADEON_BIOS_1_SCRATCH 0x0014

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#define RADEON_BIOS_2_SCRATCH 0x0018

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#define RADEON_BIOS_3_SCRATCH 0x001c

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#define RADEON_BIOS_4_SCRATCH 0x0020

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# define RADEON_CRT1_ATTACHED_MASK (3 << 0)

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# define RADEON_CRT1_ATTACHED_MONO (1 << 0)

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# define RADEON_CRT1_ATTACHED_COLOR (2 << 0)

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# define RADEON_LCD1_ATTACHED (1 << 2)

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# define RADEON_DFP1_ATTACHED (1 << 3)

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# define RADEON_TV1_ATTACHED_MASK (3 << 4)

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# define RADEON_TV1_ATTACHED_COMP (1 << 4)

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# define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)

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# define RADEON_CRT2_ATTACHED_MASK (3 << 8)

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# define RADEON_CRT2_ATTACHED_MONO (1 << 8)

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# define RADEON_CRT2_ATTACHED_COLOR (2 << 8)

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# define RADEON_DFP2_ATTACHED (1 << 11)

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#define RADEON_BIOS_5_SCRATCH 0x0024

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# define RADEON_LCD1_ON (1 << 0)

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# define RADEON_CRT1_ON (1 << 1)

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# define RADEON_TV1_ON (1 << 2)

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# define RADEON_DFP1_ON (1 << 3)

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# define RADEON_CRT2_ON (1 << 5)

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# define RADEON_CV1_ON (1 << 6)

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# define RADEON_DFP2_ON (1 << 7)

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# define RADEON_LCD1_CRTC_MASK (1 << 8)

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# define RADEON_LCD1_CRTC_SHIFT 8

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# define RADEON_CRT1_CRTC_MASK (1 << 9)

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# define RADEON_CRT1_CRTC_SHIFT 9

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# define RADEON_TV1_CRTC_MASK (1 << 10)

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# define RADEON_TV1_CRTC_SHIFT 10

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# define RADEON_DFP1_CRTC_MASK (1 << 11)

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# define RADEON_DFP1_CRTC_SHIFT 11

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# define RADEON_CRT2_CRTC_MASK (1 << 12)

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# define RADEON_CRT2_CRTC_SHIFT 12

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# define RADEON_CV1_CRTC_MASK (1 << 13)

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# define RADEON_CV1_CRTC_SHIFT 13

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# define RADEON_DFP2_CRTC_MASK (1 << 14)

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# define RADEON_DFP2_CRTC_SHIFT 14

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# define RADEON_ACC_REQ_LCD1 (1 << 16)

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# define RADEON_ACC_REQ_CRT1 (1 << 17)

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# define RADEON_ACC_REQ_TV1 (1 << 18)

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# define RADEON_ACC_REQ_DFP1 (1 << 19)

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# define RADEON_ACC_REQ_CRT2 (1 << 21)

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# define RADEON_ACC_REQ_TV2 (1 << 22)

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# define RADEON_ACC_REQ_DFP2 (1 << 23)

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#define RADEON_BIOS_6_SCRATCH 0x0028

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# define RADEON_ACC_MODE_CHANGE (1 << 2)

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# define RADEON_EXT_DESKTOP_MODE (1 << 3)

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# define RADEON_LCD_DPMS_ON (1 << 20)

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# define RADEON_CRT_DPMS_ON (1 << 21)

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# define RADEON_TV_DPMS_ON (1 << 22)

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# define RADEON_DFP_DPMS_ON (1 << 23)

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# define RADEON_DPMS_MASK (3 << 24)

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# define RADEON_DPMS_ON (0 << 24)

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# define RADEON_DPMS_STANDBY (1 << 24)

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# define RADEON_DPMS_SUSPEND (2 << 24)

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# define RADEON_DPMS_OFF (3 << 24)

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# define RADEON_SCREEN_BLANKING (1 << 26)

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# define RADEON_DRIVER_CRITICAL (1 << 27)

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# define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)

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#define RADEON_BIOS_7_SCRATCH 0x002c

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# define RADEON_SYS_HOTKEY (1 << 10)

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# define RADEON_DRV_LOADED (1 << 12)

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#define RADEON_BIOS_ROM 0x0f30 /* PCI */

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#define RADEON_BIST 0x0f0f /* PCI */

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#define RADEON_BRUSH_DATA0 0x1480

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#define RADEON_BRUSH_DATA1 0x1484

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#define RADEON_BRUSH_DATA10 0x14a8

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#define RADEON_BRUSH_DATA11 0x14ac

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#define RADEON_BRUSH_DATA12 0x14b0

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#define RADEON_BRUSH_DATA13 0x14b4

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#define RADEON_BRUSH_DATA14 0x14b8

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#define RADEON_BRUSH_DATA15 0x14bc

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#define RADEON_BRUSH_DATA16 0x14c0

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#define RADEON_BRUSH_DATA17 0x14c4

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#define RADEON_BRUSH_DATA18 0x14c8

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#define RADEON_BRUSH_DATA19 0x14cc

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#define RADEON_BRUSH_DATA2 0x1488

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#define RADEON_BRUSH_DATA20 0x14d0

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#define RADEON_BRUSH_DATA21 0x14d4

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#define RADEON_BRUSH_DATA22 0x14d8

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#define RADEON_BRUSH_DATA23 0x14dc

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#define RADEON_BRUSH_DATA24 0x14e0

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#define RADEON_BRUSH_DATA25 0x14e4

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#define RADEON_BRUSH_DATA26 0x14e8

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#define RADEON_BRUSH_DATA27 0x14ec

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#define RADEON_BRUSH_DATA28 0x14f0

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#define RADEON_BRUSH_DATA29 0x14f4

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#define RADEON_BRUSH_DATA3 0x148c

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#define RADEON_BRUSH_DATA30 0x14f8

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#define RADEON_BRUSH_DATA31 0x14fc

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#define RADEON_BRUSH_DATA32 0x1500

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#define RADEON_BRUSH_DATA33 0x1504

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#define RADEON_BRUSH_DATA34 0x1508

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#define RADEON_BRUSH_DATA35 0x150c

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#define RADEON_BRUSH_DATA36 0x1510

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#define RADEON_BRUSH_DATA37 0x1514

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#define RADEON_BRUSH_DATA38 0x1518

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#define RADEON_BRUSH_DATA39 0x151c

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#define RADEON_BRUSH_DATA4 0x1490

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#define RADEON_BRUSH_DATA40 0x1520

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#define RADEON_BRUSH_DATA41 0x1524

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#define RADEON_BRUSH_DATA42 0x1528

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#define RADEON_BRUSH_DATA43 0x152c

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#define RADEON_BRUSH_DATA44 0x1530

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#define RADEON_BRUSH_DATA45 0x1534

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#define RADEON_BRUSH_DATA46 0x1538

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#define RADEON_BRUSH_DATA47 0x153c

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#define RADEON_BRUSH_DATA48 0x1540

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#define RADEON_BRUSH_DATA49 0x1544

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#define RADEON_BRUSH_DATA5 0x1494

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#define RADEON_BRUSH_DATA50 0x1548

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#define RADEON_BRUSH_DATA51 0x154c

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#define RADEON_BRUSH_DATA52 0x1550

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#define RADEON_BRUSH_DATA53 0x1554

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#define RADEON_BRUSH_DATA54 0x1558

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#define RADEON_BRUSH_DATA55 0x155c

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#define RADEON_BRUSH_DATA56 0x1560

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#define RADEON_BRUSH_DATA57 0x1564

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#define RADEON_BRUSH_DATA58 0x1568

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#define RADEON_BRUSH_DATA59 0x156c

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#define RADEON_BRUSH_DATA6 0x1498

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#define RADEON_BRUSH_DATA60 0x1570

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#define RADEON_BRUSH_DATA61 0x1574

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#define RADEON_BRUSH_DATA62 0x1578

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#define RADEON_BRUSH_DATA63 0x157c

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#define RADEON_BRUSH_DATA7 0x149c

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#define RADEON_BRUSH_DATA8 0x14a0

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#define RADEON_BRUSH_DATA9 0x14a4

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#define RADEON_BRUSH_SCALE 0x1470

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#define RADEON_BRUSH_Y_X 0x1474

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#define RADEON_BUS_CNTL 0x0030

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# define RADEON_BUS_MASTER_DIS (1 << 6)

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# define RADEON_BUS_BIOS_DIS_ROM (1 << 12)

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# define RS600_BUS_MASTER_DIS (1 << 14)

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# define RS600_MSI_REARM (1 << 20) /* rs600/rs690/rs740 */

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# define RADEON_BUS_RD_DISCARD_EN (1 << 24)

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# define RADEON_BUS_RD_ABORT_EN (1 << 25)

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# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)

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# define RADEON_BUS_WRT_BURST (1 << 29)

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# define RADEON_BUS_READ_BURST (1 << 30)

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#define RADEON_BUS_CNTL1 0x0034

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# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)

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#define RV370_BUS_CNTL 0x004c

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# define RV370_BUS_BIOS_DIS_ROM (1 << 2)

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/* rv370/rv380, rv410, r423/r430/r480, r5xx */

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#define RADEON_MSI_REARM_EN 0x0160

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# define RV370_MSI_REARM_EN (1 << 0)

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/* #define RADEON_PCIE_INDEX 0x0030 */

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/* #define RADEON_PCIE_DATA 0x0034 */

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#define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */

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# define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0

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# define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7

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# define RADEON_PCIE_LC_LINK_WIDTH_X0 0

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# define RADEON_PCIE_LC_LINK_WIDTH_X1 1

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# define RADEON_PCIE_LC_LINK_WIDTH_X2 2

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# define RADEON_PCIE_LC_LINK_WIDTH_X4 3

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# define RADEON_PCIE_LC_LINK_WIDTH_X8 4

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# define RADEON_PCIE_LC_LINK_WIDTH_X12 5

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# define RADEON_PCIE_LC_LINK_WIDTH_X16 6

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# define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4

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# define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70

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# define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)

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# define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)

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# define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)

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# define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)

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# define R600_PCIE_LC_RENEGOTIATION_SUPPORT (1 << 9)

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# define R600_PCIE_LC_RENEGOTIATE_EN (1 << 10)

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# define R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11)

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# define R600_PCIE_LC_UPCONFIGURE_SUPPORT (1 << 12)

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# define R600_PCIE_LC_UPCONFIGURE_DIS (1 << 13)

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#define R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c

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#define R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c

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#define RADEON_CACHE_CNTL 0x1724

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#define RADEON_CACHE_LINE 0x0f0c /* PCI */

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#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */

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#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */

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#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */

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# define RADEON_DONT_USE_XTALIN (1 << 4)

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# define RADEON_SCLK_DYN_START_CNTL (1 << 15)

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#define RADEON_CLOCK_CNTL_DATA 0x000c

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#define RADEON_CLOCK_CNTL_INDEX 0x0008

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# define RADEON_PLL_WR_EN (1 << 7)

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# define RADEON_PLL_DIV_SEL (3 << 8)

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# define RADEON_PLL2_DIV_SEL_MASK (~(3 << 8))

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#define RADEON_CLK_PWRMGT_CNTL 0x0014

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# define RADEON_ENGIN_DYNCLK_MODE (1 << 12)

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# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13)

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# define RADEON_ACTIVE_HILO_LAT_SHIFT 13

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# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)

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# define RADEON_MC_BUSY (1 << 16)

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# define RADEON_DLL_READY (1 << 19)

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# define RADEON_CG_NO1_DEBUG_0 (1 << 24)

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# define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24)

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# define RADEON_DYN_STOP_MODE_MASK (7 << 21)

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# define RADEON_TVPLL_PWRMGT_OFF (1 << 30)

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# define RADEON_TVCLK_TURNOFF (1 << 31)

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#define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */

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# define RADEON_PM_MODE_SEL (1 << 13)

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# define RADEON_TCL_BYPASS_DISABLE (1 << 20)

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#define RADEON_CLR_CMP_CLR_3D 0x1a24

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#define RADEON_CLR_CMP_CLR_DST 0x15c8

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#define RADEON_CLR_CMP_CLR_SRC 0x15c4

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#define RADEON_CLR_CMP_CNTL 0x15c0

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# define RADEON_SRC_CMP_EQ_COLOR (4 << 0)

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# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0)

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# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24)

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#define RADEON_CLR_CMP_MASK 0x15cc

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# define RADEON_CLR_CMP_MSK 0xffffffff

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#define RADEON_CLR_CMP_MASK_3D 0x1A28

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#define RADEON_COMMAND 0x0f04 /* PCI */

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#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c

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#define RADEON_CONFIG_APER_0_BASE 0x0100

377

#define RADEON_CONFIG_APER_1_BASE 0x0104

378

#define RADEON_CONFIG_APER_SIZE 0x0108

379

#define RADEON_CONFIG_BONDS 0x00e8

380

#define RADEON_CONFIG_CNTL 0x00e0

Alex Deucher

d75ee3b

2011-01-24 23:24:59 -0500

[diff] [blame]

381

# define RADEON_CFG_VGA_RAM_EN (1 << 8)

382

# define RADEON_CFG_VGA_IO_DIS (1 << 9)

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

383

# define RADEON_CFG_ATI_REV_A11 (0 << 16)

384

# define RADEON_CFG_ATI_REV_A12 (1 << 16)

385

# define RADEON_CFG_ATI_REV_A13 (2 << 16)

386

# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)

387

#define RADEON_CONFIG_MEMSIZE 0x00f8

388

#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114

389

#define RADEON_CONFIG_REG_1_BASE 0x010c

390

#define RADEON_CONFIG_REG_APER_SIZE 0x0110

391

#define RADEON_CONFIG_XSTRAP 0x00e4

392

#define RADEON_CONSTANT_COLOR_C 0x1d34

393

# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff

394

# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff

395

# define RADEON_CONSTANT_COLOR_ZERO 0x00000000

396

#define RADEON_CRC_CMDFIFO_ADDR 0x0740

397

#define RADEON_CRC_CMDFIFO_DOUT 0x0744

398

#define RADEON_GRPH_BUFFER_CNTL 0x02f0

399

# define RADEON_GRPH_START_REQ_MASK (0x7f)

400

# define RADEON_GRPH_START_REQ_SHIFT 0

401

# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)

402

# define RADEON_GRPH_STOP_REQ_SHIFT 8

403

# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)

404

# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16

405

# define RADEON_GRPH_CRITICAL_CNTL (1<<28)

406

# define RADEON_GRPH_BUFFER_SIZE (1<<29)

407

# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)

408

# define RADEON_GRPH_STOP_CNTL (1<<31)

409

#define RADEON_GRPH2_BUFFER_CNTL 0x03f0

410

# define RADEON_GRPH2_START_REQ_MASK (0x7f)

411

# define RADEON_GRPH2_START_REQ_SHIFT 0

412

# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)

413

# define RADEON_GRPH2_STOP_REQ_SHIFT 8

414

# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)

415

# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16

416

# define RADEON_GRPH2_CRITICAL_CNTL (1<<28)

417

# define RADEON_GRPH2_BUFFER_SIZE (1<<29)

418

# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)

419

# define RADEON_GRPH2_STOP_CNTL (1<<31)

420

#define RADEON_CRTC_CRNT_FRAME 0x0214

421

#define RADEON_CRTC_EXT_CNTL 0x0054

422

# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0)

423

# define RADEON_VGA_ATI_LINEAR (1 << 3)

424

# define RADEON_XCRT_CNT_EN (1 << 6)

425

# define RADEON_CRTC_HSYNC_DIS (1 << 8)

426

# define RADEON_CRTC_VSYNC_DIS (1 << 9)

427

# define RADEON_CRTC_DISPLAY_DIS (1 << 10)

428

# define RADEON_CRTC_SYNC_TRISTAT (1 << 11)

429

# define RADEON_CRTC_CRT_ON (1 << 15)

430

#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055

431

# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0)

432

# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1)

433

# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2)

434

#define RADEON_CRTC_GEN_CNTL 0x0050

435

# define RADEON_CRTC_DBL_SCAN_EN (1 << 0)

436

# define RADEON_CRTC_INTERLACE_EN (1 << 1)

437

# define RADEON_CRTC_CSYNC_EN (1 << 4)

438

# define RADEON_CRTC_ICON_EN (1 << 15)

439

# define RADEON_CRTC_CUR_EN (1 << 16)

Alex Deucher

6f34be5

2010-11-21 10:59:01 -0500

[diff] [blame]

440

# define RADEON_CRTC_VSTAT_MODE_MASK (3 << 17)

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

441

# define RADEON_CRTC_CUR_MODE_MASK (7 << 20)

442

# define RADEON_CRTC_CUR_MODE_SHIFT 20

443

# define RADEON_CRTC_CUR_MODE_MONO 0

444

# define RADEON_CRTC_CUR_MODE_24BPP 2

445

# define RADEON_CRTC_EXT_DISP_EN (1 << 24)

446

# define RADEON_CRTC_EN (1 << 25)

447

# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26)

448

#define RADEON_CRTC2_GEN_CNTL 0x03f8

449

# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0)

450

# define RADEON_CRTC2_INTERLACE_EN (1 << 1)

451

# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4)

452

# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)

453

# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)

454

# define RADEON_CRTC2_CRT2_ON (1 << 7)

455

# define RADEON_CRTC2_PIX_WIDTH_SHIFT 8

456

# define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8)

457

# define RADEON_CRTC2_ICON_EN (1 << 15)

458

# define RADEON_CRTC2_CUR_EN (1 << 16)

459

# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20)

460

# define RADEON_CRTC2_DISP_DIS (1 << 23)

461

# define RADEON_CRTC2_EN (1 << 25)

462

# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26)

463

# define RADEON_CRTC2_CSYNC_EN (1 << 27)

464

# define RADEON_CRTC2_HSYNC_DIS (1 << 28)

465

# define RADEON_CRTC2_VSYNC_DIS (1 << 29)

466

#define RADEON_CRTC_MORE_CNTL 0x27c

467

# define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2)

468

# define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3)

469

# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)

470

# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)

471

#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218

472

#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204

473

# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)

474

# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)

475

# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3

476

# define RADEON_CRTC_H_SYNC_WID (0x3f << 16)

477

# define RADEON_CRTC_H_SYNC_WID_SHIFT 16

478

# define RADEON_CRTC_H_SYNC_POL (1 << 23)

479

#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304

480

# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)

481

# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)

482

# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3

483

# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16)

484

# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16

485

# define RADEON_CRTC2_H_SYNC_POL (1 << 23)

486

#define RADEON_CRTC_H_TOTAL_DISP 0x0200

487

# define RADEON_CRTC_H_TOTAL (0x03ff << 0)

488

# define RADEON_CRTC_H_TOTAL_SHIFT 0

489

# define RADEON_CRTC_H_DISP (0x01ff << 16)

490

# define RADEON_CRTC_H_DISP_SHIFT 16

491

#define RADEON_CRTC2_H_TOTAL_DISP 0x0300

492

# define RADEON_CRTC2_H_TOTAL (0x03ff << 0)

493

# define RADEON_CRTC2_H_TOTAL_SHIFT 0

494

# define RADEON_CRTC2_H_DISP (0x01ff << 16)

495

# define RADEON_CRTC2_H_DISP_SHIFT 16

496

497

#define RADEON_CRTC_OFFSET_RIGHT 0x0220

498

#define RADEON_CRTC_OFFSET 0x0224

499

# define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)

500

# define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31)

501

502

#define RADEON_CRTC2_OFFSET 0x0324

503

# define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)

504

# define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31)

505

#define RADEON_CRTC_OFFSET_CNTL 0x0228

506

# define RADEON_CRTC_TILE_LINE_SHIFT 0

507

# define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4

508

# define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6)

509

# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7)

510

# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7)

511

# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)

512

# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)

513

# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7)

514

# define R300_CRTC_X_Y_MODE_EN (1 << 9)

515

# define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10)

516

# define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10)

517

# define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10)

518

# define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10)

519

# define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10)

520

# define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12)

521

# define R300_CRTC_MICRO_TILE_EN (1 << 13)

522

# define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14)

523

# define R300_CRTC_MACRO_TILE_EN (1 << 15)

524

# define RADEON_CRTC_TILE_EN_RIGHT (1 << 14)

525

# define RADEON_CRTC_TILE_EN (1 << 15)

526

# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)

527

# define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)

Alex Deucher

acb3250

2010-11-23 00:41:00 -0500

[diff] [blame]

528

# define RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN (1 << 28)

529

# define RADEON_CRTC_GUI_TRIG_OFFSET_RIGHT_EN (1 << 29)

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

530

531

#define R300_CRTC_TILE_X0_Y0 0x0350

532

#define R300_CRTC2_TILE_X0_Y0 0x0358

533

534

#define RADEON_CRTC2_OFFSET_CNTL 0x0328

535

# define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16)

536

# define RADEON_CRTC2_TILE_EN (1 << 15)

537

#define RADEON_CRTC_PITCH 0x022c

538

# define RADEON_CRTC_PITCH__SHIFT 0

539

# define RADEON_CRTC_PITCH__RIGHT_SHIFT 16

540

541

#define RADEON_CRTC2_PITCH 0x032c

542

#define RADEON_CRTC_STATUS 0x005c

Alex Deucher

3ae19b7

2012-02-23 17:53:37 -0500

[diff] [blame]

543

# define RADEON_CRTC_VBLANK_CUR (1 << 0)

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

544

# define RADEON_CRTC_VBLANK_SAVE (1 << 1)

545

# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1)

546

#define RADEON_CRTC2_STATUS 0x03fc

Alex Deucher

3ae19b7

2012-02-23 17:53:37 -0500

[diff] [blame]

547

# define RADEON_CRTC2_VBLANK_CUR (1 << 0)

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

548

# define RADEON_CRTC2_VBLANK_SAVE (1 << 1)

549

# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1)

550

#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c

551

# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0)

552

# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0

553

# define RADEON_CRTC_V_SYNC_WID (0x1f << 16)

554

# define RADEON_CRTC_V_SYNC_WID_SHIFT 16

555

# define RADEON_CRTC_V_SYNC_POL (1 << 23)

556

#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c

557

# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0)

558

# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0

559

# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16)

560

# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16

561

# define RADEON_CRTC2_V_SYNC_POL (1 << 23)

562

#define RADEON_CRTC_V_TOTAL_DISP 0x0208

563

# define RADEON_CRTC_V_TOTAL (0x07ff << 0)

564

# define RADEON_CRTC_V_TOTAL_SHIFT 0

565

# define RADEON_CRTC_V_DISP (0x07ff << 16)

566

# define RADEON_CRTC_V_DISP_SHIFT 16

567

#define RADEON_CRTC2_V_TOTAL_DISP 0x0308

568

# define RADEON_CRTC2_V_TOTAL (0x07ff << 0)

569

# define RADEON_CRTC2_V_TOTAL_SHIFT 0

570

# define RADEON_CRTC2_V_DISP (0x07ff << 16)

571

# define RADEON_CRTC2_V_DISP_SHIFT 16

572

#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210

573

# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16)

574

#define RADEON_CRTC2_CRNT_FRAME 0x0314

575

#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

576

#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310

577

#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */

578

#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */

579

#define RADEON_CUR_CLR0 0x026c

580

#define RADEON_CUR_CLR1 0x0270

581

#define RADEON_CUR_HORZ_VERT_OFF 0x0268

582

#define RADEON_CUR_HORZ_VERT_POSN 0x0264

583

#define RADEON_CUR_OFFSET 0x0260

584

# define RADEON_CUR_LOCK (1 << 31)

585

#define RADEON_CUR2_CLR0 0x036c

586

#define RADEON_CUR2_CLR1 0x0370

587

#define RADEON_CUR2_HORZ_VERT_OFF 0x0368

588

#define RADEON_CUR2_HORZ_VERT_POSN 0x0364

589

#define RADEON_CUR2_OFFSET 0x0360

590

# define RADEON_CUR2_LOCK (1 << 31)

591

592

#define RADEON_DAC_CNTL 0x0058

593

# define RADEON_DAC_RANGE_CNTL (3 << 0)

594

# define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0)

595

# define RADEON_DAC_RANGE_CNTL_MASK 0x03

596

# define RADEON_DAC_BLANKING (1 << 2)

597

# define RADEON_DAC_CMP_EN (1 << 3)

598

# define RADEON_DAC_CMP_OUTPUT (1 << 7)

599

# define RADEON_DAC_8BIT_EN (1 << 8)

600

# define RADEON_DAC_TVO_EN (1 << 10)

601

# define RADEON_DAC_VGA_ADR_EN (1 << 13)

602

# define RADEON_DAC_PDWN (1 << 15)

603

# define RADEON_DAC_MASK_ALL (0xff << 24)

604

#define RADEON_DAC_CNTL2 0x007c

605

# define RADEON_DAC2_TV_CLK_SEL (0 << 1)

606

# define RADEON_DAC2_DAC_CLK_SEL (1 << 0)

607

# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1)

608

# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)

609

# define RADEON_DAC2_CMP_EN (1 << 7)

610

# define RADEON_DAC2_CMP_OUT_R (1 << 8)

611

# define RADEON_DAC2_CMP_OUT_G (1 << 9)

612

# define RADEON_DAC2_CMP_OUT_B (1 << 10)

613

# define RADEON_DAC2_CMP_OUTPUT (1 << 11)

614

#define RADEON_DAC_EXT_CNTL 0x0280

615

# define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)

616

# define RADEON_DAC2_FORCE_DATA_EN (1 << 1)

617

# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)

618

# define RADEON_DAC_FORCE_DATA_EN (1 << 5)

619

# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)

620

# define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6)

621

# define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6)

622

# define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6)

623

# define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6)

624

# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00

625

# define RADEON_DAC_FORCE_DATA_SHIFT 8

626

#define RADEON_DAC_MACRO_CNTL 0x0d04

627

# define RADEON_DAC_PDWN_R (1 << 16)

628

# define RADEON_DAC_PDWN_G (1 << 17)

629

# define RADEON_DAC_PDWN_B (1 << 18)

630

#define RADEON_DISP_PWR_MAN 0x0d08

631

# define RADEON_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)

632

# define RADEON_DISP_PWR_MAN_D3_CRTC2_EN (1 << 4)

633

# define RADEON_DISP_PWR_MAN_DPMS_ON (0 << 8)

634

# define RADEON_DISP_PWR_MAN_DPMS_STANDBY (1 << 8)

635

# define RADEON_DISP_PWR_MAN_DPMS_SUSPEND (2 << 8)

636

# define RADEON_DISP_PWR_MAN_DPMS_OFF (3 << 8)

637

# define RADEON_DISP_D3_RST (1 << 16)

638

# define RADEON_DISP_D3_REG_RST (1 << 17)

639

# define RADEON_DISP_D3_GRPH_RST (1 << 18)

640

# define RADEON_DISP_D3_SUBPIC_RST (1 << 19)

641

# define RADEON_DISP_D3_OV0_RST (1 << 20)

642

# define RADEON_DISP_D1D2_GRPH_RST (1 << 21)

643

# define RADEON_DISP_D1D2_SUBPIC_RST (1 << 22)

644

# define RADEON_DISP_D1D2_OV0_RST (1 << 23)

645

# define RADEON_DIG_TMDS_ENABLE_RST (1 << 24)

646

# define RADEON_TV_ENABLE_RST (1 << 25)

647

# define RADEON_AUTO_PWRUP_EN (1 << 26)

648

#define RADEON_TV_DAC_CNTL 0x088c

649

# define RADEON_TV_DAC_NBLANK (1 << 0)

650

# define RADEON_TV_DAC_NHOLD (1 << 1)

651

# define RADEON_TV_DAC_PEDESTAL (1 << 2)

652

# define RADEON_TV_MONITOR_DETECT_EN (1 << 4)

653

# define RADEON_TV_DAC_CMPOUT (1 << 5)

654

# define RADEON_TV_DAC_STD_MASK (3 << 8)

655

# define RADEON_TV_DAC_STD_PAL (0 << 8)

656

# define RADEON_TV_DAC_STD_NTSC (1 << 8)

657

# define RADEON_TV_DAC_STD_PS2 (2 << 8)

658

# define RADEON_TV_DAC_STD_RS343 (3 << 8)

659

# define RADEON_TV_DAC_BGSLEEP (1 << 6)

660

# define RADEON_TV_DAC_BGADJ_MASK (0xf << 16)

661

# define RADEON_TV_DAC_BGADJ_SHIFT 16

662

# define RADEON_TV_DAC_DACADJ_MASK (0xf << 20)

663

# define RADEON_TV_DAC_DACADJ_SHIFT 20

664

# define RADEON_TV_DAC_RDACPD (1 << 24)

665

# define RADEON_TV_DAC_GDACPD (1 << 25)

666

# define RADEON_TV_DAC_BDACPD (1 << 26)

667

# define RADEON_TV_DAC_RDACDET (1 << 29)

668

# define RADEON_TV_DAC_GDACDET (1 << 30)

669

# define RADEON_TV_DAC_BDACDET (1 << 31)

670

# define R420_TV_DAC_DACADJ_MASK (0x1f << 20)

671

# define R420_TV_DAC_RDACPD (1 << 25)

672

# define R420_TV_DAC_GDACPD (1 << 26)

673

# define R420_TV_DAC_BDACPD (1 << 27)

674

# define R420_TV_DAC_TVENABLE (1 << 28)

675

#define RADEON_DISP_HW_DEBUG 0x0d14

676

# define RADEON_CRT2_DISP1_SEL (1 << 5)

677

#define RADEON_DISP_OUTPUT_CNTL 0x0d64

678

# define RADEON_DISP_DAC_SOURCE_MASK 0x03

679

# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c

680

# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01

681

# define RADEON_DISP_DAC_SOURCE_RMX 0x02

682

# define RADEON_DISP_DAC_SOURCE_LTU 0x03

683

# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04

684

# define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2)

685

# define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0

686

# define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2)

687

# define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2)

688

# define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2)

689

# define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4)

690

# define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4)

691

# define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4)

692

# define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4)

693

# define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */

694

# define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */

695

#define RADEON_DISP_TV_OUT_CNTL 0x0d6c

696

# define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16)

697

# define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)

698

#define RADEON_DAC_CRC_SIG 0x02cc

699

#define RADEON_DAC_DATA 0x03c9 /* VGA */

700

#define RADEON_DAC_MASK 0x03c6 /* VGA */

701

#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */

702

#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */

703

#define RADEON_DDA_CONFIG 0x02e0

704

#define RADEON_DDA_ON_OFF 0x02e4

705

#define RADEON_DEFAULT_OFFSET 0x16e0

706

#define RADEON_DEFAULT_PITCH 0x16e4

707

#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8

708

# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)

709

# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)

710

#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820

711

#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824

712

#define RADEON_DEVICE_ID 0x0f02 /* PCI */

713

#define RADEON_DISP_MISC_CNTL 0x0d00

714

# define RADEON_SOFT_RESET_GRPH_PP (1 << 0)

715

#define RADEON_DISP_MERGE_CNTL 0x0d60

716

# define RADEON_DISP_ALPHA_MODE_MASK 0x03

717

# define RADEON_DISP_ALPHA_MODE_KEY 0

718

# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1

719

# define RADEON_DISP_ALPHA_MODE_GLOBAL 2

720

# define RADEON_DISP_RGB_OFFSET_EN (1 << 8)

721

# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)

722

# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)

723

# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)

724

#define RADEON_DISP2_MERGE_CNTL 0x0d68

725

# define RADEON_DISP2_RGB_OFFSET_EN (1 << 8)

726

#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80

727

#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84

728

#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88

729

#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c

730

#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90

731

#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98

732

#define RADEON_DP_BRUSH_BKGD_CLR 0x1478

733

#define RADEON_DP_BRUSH_FRGD_CLR 0x147c

734

#define RADEON_DP_CNTL 0x16c0

735

# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)

736

# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)

737

# define RADEON_DP_DST_TILE_LINEAR (0 << 3)

738

# define RADEON_DP_DST_TILE_MACRO (1 << 3)

739

# define RADEON_DP_DST_TILE_MICRO (2 << 3)

740

# define RADEON_DP_DST_TILE_BOTH (3 << 3)

741

#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0

742

# define RADEON_DST_Y_MAJOR (1 << 2)

743

# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)

744

# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)

745

#define RADEON_DP_DATATYPE 0x16c4

746

# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)

747

#define RADEON_DP_GUI_MASTER_CNTL 0x146c

748

# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)

749

# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)

750

# define RADEON_GMC_SRC_CLIPPING (1 << 2)

751

# define RADEON_GMC_DST_CLIPPING (1 << 3)

752

# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)

753

# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)

754

# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)

755

# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)

756

# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)

757

# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)

758

# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)

759

# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)

760

# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)

761

# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4)

762

# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4)

763

# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)

764

# define RADEON_GMC_BRUSH_NONE (15 << 4)

765

# define RADEON_GMC_DST_8BPP_CI (2 << 8)

766

# define RADEON_GMC_DST_15BPP (3 << 8)

767

# define RADEON_GMC_DST_16BPP (4 << 8)

768

# define RADEON_GMC_DST_24BPP (5 << 8)

769

# define RADEON_GMC_DST_32BPP (6 << 8)

770

# define RADEON_GMC_DST_8BPP_RGB (7 << 8)

771

# define RADEON_GMC_DST_Y8 (8 << 8)

772

# define RADEON_GMC_DST_RGB8 (9 << 8)

773

# define RADEON_GMC_DST_VYUY (11 << 8)

774

# define RADEON_GMC_DST_YVYU (12 << 8)

775

# define RADEON_GMC_DST_AYUV444 (14 << 8)

776

# define RADEON_GMC_DST_ARGB4444 (15 << 8)

777

# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8)

778

# define RADEON_GMC_DST_DATATYPE_SHIFT 8

779

# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12)

780

# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)

781

# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)

782

# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)

783

# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14)

784

# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14)

785

# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14)

786

# define RADEON_GMC_CONVERSION_TEMP (1 << 15)

787

# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15)

788

# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15)

789

# define RADEON_GMC_ROP3_MASK (0xff << 16)

790

# define RADEON_DP_SRC_SOURCE_MASK (7 << 24)

791

# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)

792

# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)

793

# define RADEON_GMC_3D_FCN_EN (1 << 27)

794

# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)

795

# define RADEON_GMC_AUX_CLIP_DIS (1 << 29)

796

# define RADEON_GMC_WR_MSK_DIS (1 << 30)

797

# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31)

798

# define RADEON_ROP3_ZERO 0x00000000

799

# define RADEON_ROP3_DSa 0x00880000

800

# define RADEON_ROP3_SDna 0x00440000

801

# define RADEON_ROP3_S 0x00cc0000

802

# define RADEON_ROP3_DSna 0x00220000

803

# define RADEON_ROP3_D 0x00aa0000

804

# define RADEON_ROP3_DSx 0x00660000

805

# define RADEON_ROP3_DSo 0x00ee0000

806

# define RADEON_ROP3_DSon 0x00110000

807

# define RADEON_ROP3_DSxn 0x00990000

808

# define RADEON_ROP3_Dn 0x00550000

809

# define RADEON_ROP3_SDno 0x00dd0000

810

# define RADEON_ROP3_Sn 0x00330000

811

# define RADEON_ROP3_DSno 0x00bb0000

812

# define RADEON_ROP3_DSan 0x00770000

813

# define RADEON_ROP3_ONE 0x00ff0000

814

# define RADEON_ROP3_DPa 0x00a00000

815

# define RADEON_ROP3_PDna 0x00500000

816

# define RADEON_ROP3_P 0x00f00000

817

# define RADEON_ROP3_DPna 0x000a0000

818

# define RADEON_ROP3_D 0x00aa0000

819

# define RADEON_ROP3_DPx 0x005a0000

820

# define RADEON_ROP3_DPo 0x00fa0000

821

# define RADEON_ROP3_DPon 0x00050000

822

# define RADEON_ROP3_PDxn 0x00a50000

823

# define RADEON_ROP3_PDno 0x00f50000

824

# define RADEON_ROP3_Pn 0x000f0000

825

# define RADEON_ROP3_DPno 0x00af0000

826

# define RADEON_ROP3_DPan 0x005f0000

827

#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84

828

#define RADEON_DP_MIX 0x16c8

829

#define RADEON_DP_SRC_BKGD_CLR 0x15dc

830

#define RADEON_DP_SRC_FRGD_CLR 0x15d8

831

#define RADEON_DP_WRITE_MASK 0x16cc

832

#define RADEON_DST_BRES_DEC 0x1630

833

#define RADEON_DST_BRES_ERR 0x1628

834

#define RADEON_DST_BRES_INC 0x162c

835

#define RADEON_DST_BRES_LNTH 0x1634

836

#define RADEON_DST_BRES_LNTH_SUB 0x1638

837

#define RADEON_DST_HEIGHT 0x1410

838

#define RADEON_DST_HEIGHT_WIDTH 0x143c

839

#define RADEON_DST_HEIGHT_WIDTH_8 0x158c

840

#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4

841

#define RADEON_DST_HEIGHT_Y 0x15a0

842

#define RADEON_DST_LINE_START 0x1600

843

#define RADEON_DST_LINE_END 0x1604

844

#define RADEON_DST_LINE_PATCOUNT 0x1608

845

# define RADEON_BRES_CNTL_SHIFT 8

846

#define RADEON_DST_OFFSET 0x1404

847

#define RADEON_DST_PITCH 0x1408

848

#define RADEON_DST_PITCH_OFFSET 0x142c

849

#define RADEON_DST_PITCH_OFFSET_C 0x1c80

850

# define RADEON_PITCH_SHIFT 21

851

# define RADEON_DST_TILE_LINEAR (0 << 30)

852

# define RADEON_DST_TILE_MACRO (1 << 30)

853

# define RADEON_DST_TILE_MICRO (2 << 30)

854

# define RADEON_DST_TILE_BOTH (3 << 30)

855

#define RADEON_DST_WIDTH 0x140c

856

#define RADEON_DST_WIDTH_HEIGHT 0x1598

857

#define RADEON_DST_WIDTH_X 0x1588

858

#define RADEON_DST_WIDTH_X_INCY 0x159c

859

#define RADEON_DST_X 0x141c

860

#define RADEON_DST_X_SUB 0x15a4

861

#define RADEON_DST_X_Y 0x1594

862

#define RADEON_DST_Y 0x1420

863

#define RADEON_DST_Y_SUB 0x15a8

864

#define RADEON_DST_Y_X 0x1438

865

866

#define RADEON_FCP_CNTL 0x0910

867

# define RADEON_FCP0_SRC_PCICLK 0

868

# define RADEON_FCP0_SRC_PCLK 1

869

# define RADEON_FCP0_SRC_PCLKb 2

870

# define RADEON_FCP0_SRC_HREF 3

871

# define RADEON_FCP0_SRC_GND 4

872

# define RADEON_FCP0_SRC_HREFb 5

873

#define RADEON_FLUSH_1 0x1704

874

#define RADEON_FLUSH_2 0x1708

875

#define RADEON_FLUSH_3 0x170c

876

#define RADEON_FLUSH_4 0x1710

877

#define RADEON_FLUSH_5 0x1714

878

#define RADEON_FLUSH_6 0x1718

879

#define RADEON_FLUSH_7 0x171c

880

#define RADEON_FOG_3D_TABLE_START 0x1810

881

#define RADEON_FOG_3D_TABLE_END 0x1814

882

#define RADEON_FOG_3D_TABLE_DENSITY 0x181c

883

#define RADEON_FOG_TABLE_INDEX 0x1a14

884

#define RADEON_FOG_TABLE_DATA 0x1a18

885

#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250

886

#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254

887

# define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff

888

# define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000

889

# define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff

890

# define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000

891

# define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8

892

# define RADEON_FP_H_SYNC_WID_MASK 0x003f0000

893

# define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff

894

# define RADEON_FP_V_SYNC_WID_MASK 0x001f0000

895

# define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000

896

# define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010

897

# define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000

898

# define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010

899

# define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003

900

# define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010

901

# define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000

902

# define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010

903

#define RADEON_FP_GEN_CNTL 0x0284

904

# define RADEON_FP_FPON (1 << 0)

905

# define RADEON_FP_BLANK_EN (1 << 1)

906

# define RADEON_FP_TMDS_EN (1 << 2)

907

# define RADEON_FP_PANEL_FORMAT (1 << 3)

908

# define RADEON_FP_EN_TMDS (1 << 7)

909

# define RADEON_FP_DETECT_SENSE (1 << 8)

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

910

# define RADEON_FP_DETECT_INT_POL (1 << 9)

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

911

# define R200_FP_SOURCE_SEL_MASK (3 << 10)

912

# define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)

913

# define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)

914

# define R200_FP_SOURCE_SEL_RMX (2 << 10)

915

# define R200_FP_SOURCE_SEL_TRANS (3 << 10)

916

# define RADEON_FP_SEL_CRTC1 (0 << 13)

917

# define RADEON_FP_SEL_CRTC2 (1 << 13)

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

918

# define R300_HPD_SEL(x) ((x) << 13)

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

919

# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)

920

# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)

921

# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)

922

# define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18)

923

# define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)

924

# define RADEON_FP_DFP_SYNC_SEL (1 << 21)

925

# define RADEON_FP_CRTC_LOCK_8DOT (1 << 22)

926

# define RADEON_FP_CRT_SYNC_SEL (1 << 23)

927

# define RADEON_FP_USE_SHADOW_EN (1 << 24)

928

# define RADEON_FP_CRT_SYNC_ALT (1 << 26)

929

#define RADEON_FP2_GEN_CNTL 0x0288

930

# define RADEON_FP2_BLANK_EN (1 << 1)

931

# define RADEON_FP2_ON (1 << 2)

932

# define RADEON_FP2_PANEL_FORMAT (1 << 3)

933

# define RADEON_FP2_DETECT_SENSE (1 << 8)

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

934

# define RADEON_FP2_DETECT_INT_POL (1 << 9)

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

935

# define R200_FP2_SOURCE_SEL_MASK (3 << 10)

936

# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10)

937

# define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10)

938

# define R200_FP2_SOURCE_SEL_RMX (2 << 10)

939

# define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10)

940

# define RADEON_FP2_SRC_SEL_MASK (3 << 13)

941

# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)

942

# define RADEON_FP2_FP_POL (1 << 16)

943

# define RADEON_FP2_LP_POL (1 << 17)

944

# define RADEON_FP2_SCK_POL (1 << 18)

945

# define RADEON_FP2_LCD_CNTL_MASK (7 << 19)

946

# define RADEON_FP2_PAD_FLOP_EN (1 << 22)

947

# define RADEON_FP2_CRC_EN (1 << 23)

948

# define RADEON_FP2_CRC_READ_EN (1 << 24)

949

# define RADEON_FP2_DVO_EN (1 << 25)

950

# define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26)

951

# define R200_FP2_DVO_RATE_SEL_SDR (1 << 27)

952

# define R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28)

953

# define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29)

954

#define RADEON_FP_H_SYNC_STRT_WID 0x02c4

955

#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4

956

#define RADEON_FP_HORZ_STRETCH 0x028c

957

#define RADEON_FP_HORZ2_STRETCH 0x038c

958

# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff

959

# define RADEON_HORZ_STRETCH_RATIO_MAX 4096

960

# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16)

961

# define RADEON_HORZ_PANEL_SHIFT 16

962

# define RADEON_HORZ_STRETCH_PIXREP (0 << 25)

963

# define RADEON_HORZ_STRETCH_BLEND (1 << 26)

964

# define RADEON_HORZ_STRETCH_ENABLE (1 << 25)

965

# define RADEON_HORZ_AUTO_RATIO (1 << 27)

966

# define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28)

967

# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31)

968

#define RADEON_FP_HORZ_VERT_ACTIVE 0x0278

969

#define RADEON_FP_V_SYNC_STRT_WID 0x02c8

970

#define RADEON_FP_VERT_STRETCH 0x0290

971

#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8

972

#define RADEON_FP_VERT2_STRETCH 0x0390

973

# define RADEON_VERT_PANEL_SIZE (0xfff << 12)

974

# define RADEON_VERT_PANEL_SHIFT 12

975

# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff

976

# define RADEON_VERT_STRETCH_RATIO_SHIFT 0

977

# define RADEON_VERT_STRETCH_RATIO_MAX 4096

978

# define RADEON_VERT_STRETCH_ENABLE (1 << 25)

979

# define RADEON_VERT_STRETCH_LINEREP (0 << 26)

980

# define RADEON_VERT_STRETCH_BLEND (1 << 26)

981

# define RADEON_VERT_AUTO_RATIO_EN (1 << 27)

982

# define RADEON_VERT_AUTO_RATIO_INC (1 << 31)

983

# define RADEON_VERT_STRETCH_RESERVED 0x71000000

984

#define RS400_FP_2ND_GEN_CNTL 0x0384

985

# define RS400_FP_2ND_ON (1 << 0)

986

# define RS400_FP_2ND_BLANK_EN (1 << 1)

987

# define RS400_TMDS_2ND_EN (1 << 2)

988

# define RS400_PANEL_FORMAT_2ND (1 << 3)

989

# define RS400_FP_2ND_EN_TMDS (1 << 7)

990

# define RS400_FP_2ND_DETECT_SENSE (1 << 8)

991

# define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10)

992

# define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10)

993

# define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10)

994

# define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10)

995

# define RS400_FP_2ND_DETECT_EN (1 << 12)

996

# define RS400_HPD_2ND_SEL (1 << 13)

997

#define RS400_FP2_2_GEN_CNTL 0x0388

998

# define RS400_FP2_2_BLANK_EN (1 << 1)

999

# define RS400_FP2_2_ON (1 << 2)

1000

# define RS400_FP2_2_PANEL_FORMAT (1 << 3)

1001

# define RS400_FP2_2_DETECT_SENSE (1 << 8)

1002

# define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10)

1003

# define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10)

1004

# define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10)

1005

# define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10)

1006

# define RS400_FP2_2_DVO2_EN (1 << 25)

1007

#define RS400_TMDS2_CNTL 0x0394

1008

#define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4

1009

# define RS400_TMDS2_PLLEN (1 << 0)

1010

# define RS400_TMDS2_PLLRST (1 << 1)

1011

1012

#define RADEON_GEN_INT_CNTL 0x0040

Michel Dänzer

2009-08-13 11:10:51 +0200

[diff] [blame]

1013

# define RADEON_CRTC_VBLANK_MASK (1 << 0)

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

1014

# define RADEON_FP_DETECT_MASK (1 << 4)

Michel Dänzer

2009-08-13 11:10:51 +0200

[diff] [blame]

1015

# define RADEON_CRTC2_VBLANK_MASK (1 << 9)

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

1016

# define RADEON_FP2_DETECT_MASK (1 << 10)

Alex Deucher

2031f77

2010-04-22 12:52:11 -0400

[diff] [blame]

1017

# define RADEON_GUI_IDLE_MASK (1 << 19)

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

1018

# define RADEON_SW_INT_ENABLE (1 << 25)

1019

#define RADEON_GEN_INT_STATUS 0x0044

Michel Dänzer

2009-08-13 11:10:51 +0200

[diff] [blame]

1020

# define AVIVO_DISPLAY_INT_STATUS (1 << 0)

1021

# define RADEON_CRTC_VBLANK_STAT (1 << 0)

1022

# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

1023

# define RADEON_FP_DETECT_STAT (1 << 4)

1024

# define RADEON_FP_DETECT_STAT_ACK (1 << 4)

Michel Dänzer

2009-08-13 11:10:51 +0200

[diff] [blame]

1025

# define RADEON_CRTC2_VBLANK_STAT (1 << 9)

1026

# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

1027

# define RADEON_FP2_DETECT_STAT (1 << 10)

1028

# define RADEON_FP2_DETECT_STAT_ACK (1 << 10)

Alex Deucher

2031f77

2010-04-22 12:52:11 -0400

[diff] [blame]

1029

# define RADEON_GUI_IDLE_STAT (1 << 19)

1030

# define RADEON_GUI_IDLE_STAT_ACK (1 << 19)

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

1031

# define RADEON_SW_INT_FIRE (1 << 26)

1032

# define RADEON_SW_INT_TEST (1 << 25)

1033

# define RADEON_SW_INT_TEST_ACK (1 << 25)

1034

#define RADEON_GENENB 0x03c3 /* VGA */

1035

#define RADEON_GENFC_RD 0x03ca /* VGA */

1036

#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */

1037

#define RADEON_GENMO_RD 0x03cc /* VGA */

1038

#define RADEON_GENMO_WT 0x03c2 /* VGA */

1039

#define RADEON_GENS0 0x03c2 /* VGA */

1040

#define RADEON_GENS1 0x03da /* VGA, 0x03ba */

1041

#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ /* DDC3 */

1042

#define RADEON_GPIO_MONIDB 0x006c

1043

#define RADEON_GPIO_CRT2_DDC 0x006c

1044

#define RADEON_GPIO_DVI_DDC 0x0064 /* DDC2 */

1045

#define RADEON_GPIO_VGA_DDC 0x0060 /* DDC1 */

1046

# define RADEON_GPIO_A_0 (1 << 0)

1047

# define RADEON_GPIO_A_1 (1 << 1)

1048

# define RADEON_GPIO_Y_0 (1 << 8)

1049

# define RADEON_GPIO_Y_1 (1 << 9)

1050

# define RADEON_GPIO_Y_SHIFT_0 8

1051

# define RADEON_GPIO_Y_SHIFT_1 9

1052

# define RADEON_GPIO_EN_0 (1 << 16)

1053

# define RADEON_GPIO_EN_1 (1 << 17)

1054

# define RADEON_GPIO_MASK_0 (1 << 24) /*??*/

1055

# define RADEON_GPIO_MASK_1 (1 << 25) /*??*/

1056

#define RADEON_GRPH8_DATA 0x03cf /* VGA */

1057

#define RADEON_GRPH8_IDX 0x03ce /* VGA */

1058

#define RADEON_GUI_SCRATCH_REG0 0x15e0

1059

#define RADEON_GUI_SCRATCH_REG1 0x15e4

1060

#define RADEON_GUI_SCRATCH_REG2 0x15e8

1061

#define RADEON_GUI_SCRATCH_REG3 0x15ec

1062

#define RADEON_GUI_SCRATCH_REG4 0x15f0

1063

#define RADEON_GUI_SCRATCH_REG5 0x15f4

1064

1065

#define RADEON_HEADER 0x0f0e /* PCI */

1066

#define RADEON_HOST_DATA0 0x17c0

1067

#define RADEON_HOST_DATA1 0x17c4

1068

#define RADEON_HOST_DATA2 0x17c8

1069

#define RADEON_HOST_DATA3 0x17cc

1070

#define RADEON_HOST_DATA4 0x17d0

1071

#define RADEON_HOST_DATA5 0x17d4

1072

#define RADEON_HOST_DATA6 0x17d8

1073

#define RADEON_HOST_DATA7 0x17dc

1074

#define RADEON_HOST_DATA_LAST 0x17e0

1075

#define RADEON_HOST_PATH_CNTL 0x0130

1076

# define RADEON_HP_LIN_RD_CACHE_DIS (1 << 24)

1077

# define RADEON_HDP_READ_BUFFER_INVALIDATE (1 << 27)

1078

# define RADEON_HDP_SOFT_RESET (1 << 26)

1079

# define RADEON_HDP_APER_CNTL (1 << 23)

1080

#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */

1081

# define RADEON_HTOT_CNTL_VGA_EN (1 << 28)

1082

#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */

1083

1084

/* Multimedia I2C bus */

1085

#define RADEON_I2C_CNTL_0 0x0090

Alex Deucher

40bacf1

2009-12-23 03:23:21 -0500

[diff] [blame]

1086

# define RADEON_I2C_DONE (1 << 0)

1087

# define RADEON_I2C_NACK (1 << 1)

1088

# define RADEON_I2C_HALT (1 << 2)

1089

# define RADEON_I2C_SOFT_RST (1 << 5)

1090

# define RADEON_I2C_DRIVE_EN (1 << 6)

1091

# define RADEON_I2C_DRIVE_SEL (1 << 7)

1092

# define RADEON_I2C_START (1 << 8)

1093

# define RADEON_I2C_STOP (1 << 9)

1094

# define RADEON_I2C_RECEIVE (1 << 10)

1095

# define RADEON_I2C_ABORT (1 << 11)

1096

# define RADEON_I2C_GO (1 << 12)

1097

# define RADEON_I2C_PRESCALE_SHIFT 16

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

1098

#define RADEON_I2C_CNTL_1 0x0094

Alex Deucher

40bacf1

2009-12-23 03:23:21 -0500

[diff] [blame]

1099

# define RADEON_I2C_DATA_COUNT_SHIFT 0

1100

# define RADEON_I2C_ADDR_COUNT_SHIFT 4

1101

# define RADEON_I2C_INTRA_BYTE_DELAY_SHIFT 8

1102

# define RADEON_I2C_SEL (1 << 16)

1103

# define RADEON_I2C_EN (1 << 17)

1104

# define RADEON_I2C_TIME_LIMIT_SHIFT 24

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

1105

#define RADEON_I2C_DATA 0x0098

1106

1107

#define RADEON_DVI_I2C_CNTL_0 0x02e0

1108

# define R200_DVI_I2C_PIN_SEL(x) ((x) << 3)

Alex Deucher

40bacf1

2009-12-23 03:23:21 -0500

[diff] [blame]

1109

# define R200_SEL_DDC1 0 /* depends on asic */

1110

# define R200_SEL_DDC2 1 /* depends on asic */

1111

# define R200_SEL_DDC3 2 /* depends on asic */

1112

# define RADEON_SW_WANTS_TO_USE_DVI_I2C (1 << 13)

1113

# define RADEON_SW_CAN_USE_DVI_I2C (1 << 13)

1114

# define RADEON_SW_DONE_USING_DVI_I2C (1 << 14)

1115

# define RADEON_HW_NEEDS_DVI_I2C (1 << 14)

1116

# define RADEON_ABORT_HW_DVI_I2C (1 << 15)

1117

# define RADEON_HW_USING_DVI_I2C (1 << 15)

Alex Deucher

fcec570

2009-11-10 21:25:07 -0500

[diff] [blame]

1118

#define RADEON_DVI_I2C_CNTL_1 0x02e4

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

1119

#define RADEON_DVI_I2C_DATA 0x02e8

1120

1121

#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */

1122

#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */

1123

#define RADEON_IO_BASE 0x0f14 /* PCI */

1124

1125

#define RADEON_LATENCY 0x0f0d /* PCI */

1126

#define RADEON_LEAD_BRES_DEC 0x1608

1127

#define RADEON_LEAD_BRES_LNTH 0x161c

1128

#define RADEON_LEAD_BRES_LNTH_SUB 0x1624

1129

#define RADEON_LVDS_GEN_CNTL 0x02d0

1130

# define RADEON_LVDS_ON (1 << 0)

1131

# define RADEON_LVDS_DISPLAY_DIS (1 << 1)

1132

# define RADEON_LVDS_PANEL_TYPE (1 << 2)

1133

# define RADEON_LVDS_PANEL_FORMAT (1 << 3)

1134

# define RADEON_LVDS_NO_FM (0 << 4)

1135

# define RADEON_LVDS_2_GREY (1 << 4)

1136

# define RADEON_LVDS_4_GREY (2 << 4)

1137

# define RADEON_LVDS_RST_FM (1 << 6)

1138

# define RADEON_LVDS_EN (1 << 7)

1139

# define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8

1140

# define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)

1141

# define RADEON_LVDS_BL_MOD_EN (1 << 16)

1142

# define RADEON_LVDS_BL_CLK_SEL (1 << 17)

1143

# define RADEON_LVDS_DIGON (1 << 18)

1144

# define RADEON_LVDS_BLON (1 << 19)

1145

# define RADEON_LVDS_FP_POL_LOW (1 << 20)

1146

# define RADEON_LVDS_LP_POL_LOW (1 << 21)

1147

# define RADEON_LVDS_DTM_POL_LOW (1 << 22)

1148

# define RADEON_LVDS_SEL_CRTC2 (1 << 23)

1149

# define RADEON_LVDS_FPDI_EN (1 << 27)

1150

# define RADEON_LVDS_HSYNC_DELAY_SHIFT 28

1151

#define RADEON_LVDS_PLL_CNTL 0x02d4

1152

# define RADEON_HSYNC_DELAY_SHIFT 28

1153

# define RADEON_HSYNC_DELAY_MASK (0xf << 28)

1154

# define RADEON_LVDS_PLL_EN (1 << 16)

1155

# define RADEON_LVDS_PLL_RESET (1 << 17)

1156

# define R300_LVDS_SRC_SEL_MASK (3 << 18)

1157

# define R300_LVDS_SRC_SEL_CRTC1 (0 << 18)

1158

# define R300_LVDS_SRC_SEL_CRTC2 (1 << 18)

1159

# define R300_LVDS_SRC_SEL_RMX (2 << 18)

1160

#define RADEON_LVDS_SS_GEN_CNTL 0x02ec

1161

# define RADEON_LVDS_PWRSEQ_DELAY1_SHIFT 16

1162

# define RADEON_LVDS_PWRSEQ_DELAY2_SHIFT 20

1163

1164

#define RADEON_MAX_LATENCY 0x0f3f /* PCI */

1165

#define RADEON_DISPLAY_BASE_ADDR 0x23c

1166

#define RADEON_DISPLAY2_BASE_ADDR 0x33c

1167

#define RADEON_OV0_BASE_ADDR 0x43c

1168

#define RADEON_NB_TOM 0x15c

1169

#define R300_MC_INIT_MISC_LAT_TIMER 0x180

1170

# define R300_MC_DISP0R_INIT_LAT_SHIFT 8

1171

# define R300_MC_DISP0R_INIT_LAT_MASK 0xf

1172

# define R300_MC_DISP1R_INIT_LAT_SHIFT 12

1173

# define R300_MC_DISP1R_INIT_LAT_MASK 0xf

1174

#define RADEON_MCLK_CNTL 0x0012 /* PLL */

1175

# define RADEON_MCLKA_SRC_SEL_MASK 0x7

1176

# define RADEON_FORCEON_MCLKA (1 << 16)

1177

# define RADEON_FORCEON_MCLKB (1 << 17)

1178

# define RADEON_FORCEON_YCLKA (1 << 18)

1179

# define RADEON_FORCEON_YCLKB (1 << 19)

1180

# define RADEON_FORCEON_MC (1 << 20)

1181

# define RADEON_FORCEON_AIC (1 << 21)

1182

# define R300_DISABLE_MC_MCLKA (1 << 21)

1183

# define R300_DISABLE_MC_MCLKB (1 << 21)

1184

#define RADEON_MCLK_MISC 0x001f /* PLL */

1185

# define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12)

1186

# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13)

1187

# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14)

1188

# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15)

Alex Deucher

6a93cb2

2009-11-23 17:39:28 -0500

[diff] [blame]

1189

Alex Deucher

fcec570

2009-11-10 21:25:07 -0500

[diff] [blame]

1190

#define RADEON_GPIOPAD_MASK 0x0198

1191

#define RADEON_GPIOPAD_A 0x019c

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

1192

#define RADEON_GPIOPAD_EN 0x01a0

Alex Deucher

fcec570

2009-11-10 21:25:07 -0500

[diff] [blame]

1193

#define RADEON_GPIOPAD_Y 0x01a4

Alex Deucher

6a93cb2

2009-11-23 17:39:28 -0500

[diff] [blame]

1194

#define RADEON_MDGPIO_MASK 0x01a8

1195

#define RADEON_MDGPIO_A 0x01ac

1196

#define RADEON_MDGPIO_EN 0x01b0

1197

#define RADEON_MDGPIO_Y 0x01b4

1198

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

1199

#define RADEON_MEM_ADDR_CONFIG 0x0148

1200

#define RADEON_MEM_BASE 0x0f10 /* PCI */

1201

#define RADEON_MEM_CNTL 0x0140

1202

# define RADEON_MEM_NUM_CHANNELS_MASK 0x01

1203

# define RADEON_MEM_USE_B_CH_ONLY (1 << 1)

1204

# define RV100_HALF_MODE (1 << 3)

1205

# define R300_MEM_NUM_CHANNELS_MASK 0x03

1206

# define R300_MEM_USE_CD_CH_ONLY (1 << 2)

1207

#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */

1208

#define RADEON_MEM_INIT_LAT_TIMER 0x0154

1209

#define RADEON_MEM_INTF_CNTL 0x014c

1210

#define RADEON_MEM_SDRAM_MODE_REG 0x0158

1211

# define RADEON_SDRAM_MODE_MASK 0xffff0000

1212

# define RADEON_B3MEM_RESET_MASK 0x6fffffff

1213

# define RADEON_MEM_CFG_TYPE_DDR (1 << 30)

1214

#define RADEON_MEM_STR_CNTL 0x0150

1215

# define RADEON_MEM_PWRUP_COMPL_A (1 << 0)

1216

# define RADEON_MEM_PWRUP_COMPL_B (1 << 1)

1217

# define R300_MEM_PWRUP_COMPL_C (1 << 2)

1218

# define R300_MEM_PWRUP_COMPL_D (1 << 3)

1219

# define RADEON_MEM_PWRUP_COMPLETE 0x03

1220

# define R300_MEM_PWRUP_COMPLETE 0x0f

1221

#define RADEON_MC_STATUS 0x0150

1222

# define RADEON_MC_IDLE (1 << 2)

1223

# define R300_MC_IDLE (1 << 4)

1224

#define RADEON_MEM_VGA_RP_SEL 0x003c

1225

#define RADEON_MEM_VGA_WP_SEL 0x0038

1226

#define RADEON_MIN_GRANT 0x0f3e /* PCI */

1227

#define RADEON_MM_DATA 0x0004

1228

#define RADEON_MM_INDEX 0x0000

1229

# define RADEON_MM_APER (1 << 31)

1230

#define RADEON_MPLL_CNTL 0x000e /* PLL */

1231

#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */

1232

#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */

1233

#define RADEON_SEPROM_CNTL1 0x01c0

1234

# define RADEON_SCK_PRESCALE_SHIFT 24

1235

# define RADEON_SCK_PRESCALE_MASK (0xff << 24)

1236

#define R300_MC_IND_INDEX 0x01f8

1237

# define R300_MC_IND_ADDR_MASK 0x3f

1238

# define R300_MC_IND_WR_EN (1 << 8)

1239

#define R300_MC_IND_DATA 0x01fc

1240

#define R300_MC_READ_CNTL_AB 0x017c

1241

# define R300_MEM_RBS_POSITION_A_MASK 0x03

1242

#define R300_MC_READ_CNTL_CD_mcind 0x24

1243

# define R300_MEM_RBS_POSITION_C_MASK 0x03

1244

1245

#define RADEON_N_VIF_COUNT 0x0248

1246

1247

#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470

1248

# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007

1249

# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008

1250

# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010

1251

# define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020

1252

# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040

1253

# define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300

1254

# define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000

1255

# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000

1256

# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000

1257

# define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000

1258

1259

#define RADEON_OV0_COLOUR_CNTL 0x04E0

1260

#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474

1261

#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408

1262

# define RADEON_EXCL_HORZ_START_MASK 0x000000ff

1263

# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00

1264

# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000

1265

# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000

1266

#define RADEON_OV0_EXCLUSIVE_VERT 0x040C

1267

# define RADEON_EXCL_VERT_START_MASK 0x000003ff

1268

# define RADEON_EXCL_VERT_END_MASK 0x03ff0000

1269

#define RADEON_OV0_FILTER_CNTL 0x04A0

1270

# define RADEON_FILTER_PROGRAMMABLE_COEF 0x0

1271

# define RADEON_FILTER_HC_COEF_HORZ_Y 0x1

1272

# define RADEON_FILTER_HC_COEF_HORZ_UV 0x2

1273

# define RADEON_FILTER_HC_COEF_VERT_Y 0x4

1274

# define RADEON_FILTER_HC_COEF_VERT_UV 0x8

1275

# define RADEON_FILTER_HARDCODED_COEF 0xf

1276

# define RADEON_FILTER_COEF_MASK 0xf

1277

1278

#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0

1279

#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4

1280

#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8

1281

#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC

1282

#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0

1283

#define RADEON_OV0_FLAG_CNTL 0x04DC

1284

#define RADEON_OV0_GAMMA_000_00F 0x0d40

1285

#define RADEON_OV0_GAMMA_010_01F 0x0d44

1286

#define RADEON_OV0_GAMMA_020_03F 0x0d48

1287

#define RADEON_OV0_GAMMA_040_07F 0x0d4c

1288

#define RADEON_OV0_GAMMA_080_0BF 0x0e00

1289

#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04

1290

#define RADEON_OV0_GAMMA_100_13F 0x0e08

1291

#define RADEON_OV0_GAMMA_140_17F 0x0e0c

1292

#define RADEON_OV0_GAMMA_180_1BF 0x0e10

1293

#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14

1294

#define RADEON_OV0_GAMMA_200_23F 0x0e18

1295

#define RADEON_OV0_GAMMA_240_27F 0x0e1c

1296

#define RADEON_OV0_GAMMA_280_2BF 0x0e20

1297

#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24

1298

#define RADEON_OV0_GAMMA_300_33F 0x0e28

1299

#define RADEON_OV0_GAMMA_340_37F 0x0e2c

1300

#define RADEON_OV0_GAMMA_380_3BF 0x0d50

1301

#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54

1302

#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC

1303

#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0

1304

#define RADEON_OV0_H_INC 0x0480

1305

#define RADEON_OV0_KEY_CNTL 0x04F4

1306

# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L

1307

# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L

1308

# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L

1309

# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L

1310

# define RADEON_VIDEO_KEY_FN_NE 0x00000003L

1311

# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L

1312

# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L

1313

# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L

1314

# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L

1315

# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L

1316

# define RADEON_CMP_MIX_MASK 0x00000100L

1317

# define RADEON_CMP_MIX_OR 0x00000000L

1318

# define RADEON_CMP_MIX_AND 0x00000100L

1319

#define RADEON_OV0_LIN_TRANS_A 0x0d20

1320

#define RADEON_OV0_LIN_TRANS_B 0x0d24

1321

#define RADEON_OV0_LIN_TRANS_C 0x0d28

1322

#define RADEON_OV0_LIN_TRANS_D 0x0d2c

1323

#define RADEON_OV0_LIN_TRANS_E 0x0d30

1324

#define RADEON_OV0_LIN_TRANS_F 0x0d34

1325

#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430

1326

# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL

1327

# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L

1328

#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488

1329

#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428

1330

# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L

1331

# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L

1332

#define RADEON_OV0_P1_X_START_END 0x0494

1333

#define RADEON_OV0_P2_X_START_END 0x0498

1334

#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434

1335

# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL

1336

# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L

1337

#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C

1338

#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C

1339

#define RADEON_OV0_P3_X_START_END 0x049C

1340

#define RADEON_OV0_REG_LOAD_CNTL 0x0410

1341

# define RADEON_REG_LD_CTL_LOCK 0x00000001L

1342

# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L

1343

# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L

1344

# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L

1345

# define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L

1346

#define RADEON_OV0_SCALE_CNTL 0x0420

1347

# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L

1348

# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L

1349

# define RADEON_SCALER_SIGNED_UV 0x00000010L

1350

# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L

1351

# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L

1352

# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L

1353

# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L

1354

# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L

1355

# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L

1356

# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L

1357

# define RADEON_SCALER_SOURCE_15BPP 0x00000300L

1358

# define RADEON_SCALER_SOURCE_16BPP 0x00000400L

1359

# define RADEON_SCALER_SOURCE_32BPP 0x00000600L

1360

# define RADEON_SCALER_SOURCE_YUV9 0x00000900L

1361

# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L

1362

# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L

1363

# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L

1364

# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L

1365

# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L

1366

# define RADEON_SCALER_CRTC_SEL 0x00004000L

1367

# define RADEON_SCALER_SMART_SWITCH 0x00008000L

1368

# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L

1369

# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L

1370

# define RADEON_SCALER_DIS_LIMIT 0x08000000L

1371

# define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L

1372

# define RADEON_SCALER_INT_EMU 0x20000000L

1373

# define RADEON_SCALER_ENABLE 0x40000000L

1374

# define RADEON_SCALER_SOFT_RESET 0x80000000L

1375

#define RADEON_OV0_STEP_BY 0x0484

1376

#define RADEON_OV0_TEST 0x04F8

1377

#define RADEON_OV0_V_INC 0x0424

1378

#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460

1379

#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464

1380

#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440

1381

# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L

1382

# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L

1383

# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L

1384

# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L

1385

#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444

1386

# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L

1387

# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L

1388

# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L

1389

# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L

1390

#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448

1391

# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L

1392

# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L

1393

# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L

1394

# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L

1395

#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C

1396

#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450

1397

#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454

1398

#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8

1399

#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4

1400

#define RADEON_OV0_Y_X_START 0x0400

1401

#define RADEON_OV0_Y_X_END 0x0404

1402

#define RADEON_OV1_Y_X_START 0x0600

1403

#define RADEON_OV1_Y_X_END 0x0604

1404

#define RADEON_OVR_CLR 0x0230

1405

#define RADEON_OVR_WID_LEFT_RIGHT 0x0234

1406

#define RADEON_OVR_WID_TOP_BOTTOM 0x0238

Alex Deucher

6b02af1

2009-12-04 10:40:41 -0500

[diff] [blame]

1407

#define RADEON_OVR2_CLR 0x0330

1408

#define RADEON_OVR2_WID_LEFT_RIGHT 0x0334

1409

#define RADEON_OVR2_WID_TOP_BOTTOM 0x0338

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

1410

1411

/* first capture unit */

1412

1413

#define RADEON_CAP0_BUF0_OFFSET 0x0920

1414

#define RADEON_CAP0_BUF1_OFFSET 0x0924

1415

#define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928

1416

#define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C

1417

1418

#define RADEON_CAP0_BUF_PITCH 0x0930

1419

#define RADEON_CAP0_V_WINDOW 0x0934

1420

#define RADEON_CAP0_H_WINDOW 0x0938

1421

#define RADEON_CAP0_VBI0_OFFSET 0x093C

1422

#define RADEON_CAP0_VBI1_OFFSET 0x0940

1423

#define RADEON_CAP0_VBI_V_WINDOW 0x0944

1424

#define RADEON_CAP0_VBI_H_WINDOW 0x0948

1425

#define RADEON_CAP0_PORT_MODE_CNTL 0x094C

1426

#define RADEON_CAP0_TRIG_CNTL 0x0950

1427

#define RADEON_CAP0_DEBUG 0x0954

1428

#define RADEON_CAP0_CONFIG 0x0958

1429

# define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001

1430

# define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002

1431

# define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004

1432

# define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008

1433

# define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010

1434

# define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020

1435

# define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040

1436

# define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080

1437

# define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100

1438

# define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200

1439

# define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400

1440

# define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800

1441

# define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000

1442

# define RADEON_CAP0_CONFIG_VBI_EN 0x00002000

1443

# define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000

1444

# define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000

1445

# define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000

1446

# define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000

1447

# define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000

1448

# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000

1449

# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000

1450

# define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000

1451

# define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000

1452

# define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000

1453

# define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000

1454

# define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000

1455

# define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000

1456

# define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000

1457

# define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000

1458

# define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000

1459

# define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000

1460

# define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000

1461

# define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000

1462

#define RADEON_CAP0_ANC_ODD_OFFSET 0x095C

1463

#define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960

1464

#define RADEON_CAP0_ANC_H_WINDOW 0x0964

1465

#define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968

1466

#define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C

1467

#define RADEON_CAP0_BUF_STATUS 0x0970

1468

/* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */

1469

/* #define RADEON_CAP0_XSHARPNESS 0x097C */

1470

#define RADEON_CAP0_VBI2_OFFSET 0x0980

1471

#define RADEON_CAP0_VBI3_OFFSET 0x0984

1472

#define RADEON_CAP0_ANC2_OFFSET 0x0988

1473

#define RADEON_CAP0_ANC3_OFFSET 0x098C

1474

#define RADEON_VID_BUFFER_CONTROL 0x0900

1475

1476

/* second capture unit */

1477

1478

#define RADEON_CAP1_BUF0_OFFSET 0x0990

1479

#define RADEON_CAP1_BUF1_OFFSET 0x0994

1480

#define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998

1481

#define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C

1482

1483

#define RADEON_CAP1_BUF_PITCH 0x09A0

1484

#define RADEON_CAP1_V_WINDOW 0x09A4

1485

#define RADEON_CAP1_H_WINDOW 0x09A8

1486

#define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC

1487

#define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0

1488

#define RADEON_CAP1_VBI_V_WINDOW 0x09B4

1489

#define RADEON_CAP1_VBI_H_WINDOW 0x09B8

1490

#define RADEON_CAP1_PORT_MODE_CNTL 0x09BC

1491

#define RADEON_CAP1_TRIG_CNTL 0x09C0

1492

#define RADEON_CAP1_DEBUG 0x09C4

1493

#define RADEON_CAP1_CONFIG 0x09C8

1494

#define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC

1495

#define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0

1496

#define RADEON_CAP1_ANC_H_WINDOW 0x09D4

1497

#define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8

1498

#define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC

1499

#define RADEON_CAP1_BUF_STATUS 0x09E0

1500

#define RADEON_CAP1_DWNSC_XRATIO 0x09E8

1501

#define RADEON_CAP1_XSHARPNESS 0x09EC

1502

1503

/* misc multimedia registers */

1504

1505

#define RADEON_IDCT_RUNS 0x1F80

1506

#define RADEON_IDCT_LEVELS 0x1F84

1507

#define RADEON_IDCT_CONTROL 0x1FBC

1508

#define RADEON_IDCT_AUTH_CONTROL 0x1F88

1509

#define RADEON_IDCT_AUTH 0x1F8C

1510

1511

#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */

1512

# define RADEON_P2PLL_RESET (1 << 0)

1513

# define RADEON_P2PLL_SLEEP (1 << 1)

1514

# define RADEON_P2PLL_PVG_MASK (7 << 11)

1515

# define RADEON_P2PLL_PVG_SHIFT 11

1516

# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16)

1517

# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)

1518

# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)

1519

#define RADEON_P2PLL_DIV_0 0x002c

1520

# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff

1521

# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000

1522

#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */

1523

# define RADEON_P2PLL_REF_DIV_MASK 0x03ff

1524

# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */

1525

# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */

1526

# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)

1527

# define R300_PPLL_REF_DIV_ACC_SHIFT 18

1528

#define RADEON_PALETTE_DATA 0x00b4

1529

#define RADEON_PALETTE_30_DATA 0x00b8

1530

#define RADEON_PALETTE_INDEX 0x00b0

1531

#define RADEON_PCI_GART_PAGE 0x017c

1532

#define RADEON_PIXCLKS_CNTL 0x002d

1533

# define RADEON_PIX2CLK_SRC_SEL_MASK 0x03

1534

# define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00

1535

# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01

1536

# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02

1537

# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03

1538

# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6)

1539

# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7)

1540

# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8)

1541

# define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)

1542

# define R300_DVOCLK_ALWAYS_ONb (1 << 10)

1543

# define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11)

1544

# define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12)

1545

# define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13)

1546

# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)

1547

# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)

1548

# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15)

1549

# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)

1550

# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)

1551

# define R300_P2G2CLK_ALWAYS_ONb (1 << 18)

1552

# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)

1553

# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)

1554

#define RADEON_PLANE_3D_MASK_C 0x1d44

1555

#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */

1556

# define RADEON_PLL_MASK_READ_B (1 << 9)

1557

#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */

1558

#define RADEON_PMI_DATA 0x0f63 /* PCI */

1559

#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */

1560

#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */

1561

#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */

1562

#define RADEON_PMI_REGISTER 0x0f5c /* PCI */

1563

#define RADEON_PPLL_CNTL 0x0002 /* PLL */

1564

# define RADEON_PPLL_RESET (1 << 0)

1565

# define RADEON_PPLL_SLEEP (1 << 1)

1566

# define RADEON_PPLL_PVG_MASK (7 << 11)

1567

# define RADEON_PPLL_PVG_SHIFT 11

1568

# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16)

1569

# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)

1570

# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)

1571

#define RADEON_PPLL_DIV_0 0x0004 /* PLL */

1572

#define RADEON_PPLL_DIV_1 0x0005 /* PLL */

1573

#define RADEON_PPLL_DIV_2 0x0006 /* PLL */

1574

#define RADEON_PPLL_DIV_3 0x0007 /* PLL */

1575

# define RADEON_PPLL_FB3_DIV_MASK 0x07ff

1576

# define RADEON_PPLL_POST3_DIV_MASK 0x00070000

1577

#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */

1578

# define RADEON_PPLL_REF_DIV_MASK 0x03ff

1579

# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */

1580

# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */

1581

#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */

1582

1583

#define RADEON_RBBM_GUICNTL 0x172c

1584

# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)

1585

# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)

1586

# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)

1587

# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)

1588

#define RADEON_RBBM_SOFT_RESET 0x00f0

1589

# define RADEON_SOFT_RESET_CP (1 << 0)

1590

# define RADEON_SOFT_RESET_HI (1 << 1)

1591

# define RADEON_SOFT_RESET_SE (1 << 2)

1592

# define RADEON_SOFT_RESET_RE (1 << 3)

1593

# define RADEON_SOFT_RESET_PP (1 << 4)

1594

# define RADEON_SOFT_RESET_E2 (1 << 5)

1595

# define RADEON_SOFT_RESET_RB (1 << 6)

1596

# define RADEON_SOFT_RESET_HDP (1 << 7)

1597

#define RADEON_RBBM_STATUS 0x0e40

1598

# define RADEON_RBBM_FIFOCNT_MASK 0x007f

1599

# define RADEON_RBBM_ACTIVE (1 << 31)

1600

#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c

1601

# define RADEON_RB2D_DC_FLUSH (3 << 0)

1602

# define RADEON_RB2D_DC_FREE (3 << 2)

1603

# define RADEON_RB2D_DC_FLUSH_ALL 0xf

1604

# define RADEON_RB2D_DC_BUSY (1 << 31)

1605

#define RADEON_RB2D_DSTCACHE_MODE 0x3428

1606

#define RADEON_DSTCACHE_CTLSTAT 0x1714

1607

1608

#define RADEON_RB3D_ZCACHE_MODE 0x3250

1609

#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254

1610

# define RADEON_RB3D_ZC_FLUSH_ALL 0x5

1611

#define RADEON_RB3D_DSTCACHE_MODE 0x3258

1612

# define RADEON_RB3D_DC_CACHE_ENABLE (0)

1613

# define RADEON_RB3D_DC_2D_CACHE_DISABLE (1)

1614

# define RADEON_RB3D_DC_3D_CACHE_DISABLE (2)

1615

# define RADEON_RB3D_DC_CACHE_DISABLE (3)

1616

# define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2)

1617

# define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2)

1618

# define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8)

1619

# define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8)

1620

# define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10)

1621

# define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10)

1622

# define RADEON_RB3D_DC_FORCE_RMW (1 << 16)

1623

# define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24)

1624

# define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25)

1625

1626

#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C

1627

# define RADEON_RB3D_DC_FLUSH (3 << 0)

1628

# define RADEON_RB3D_DC_FREE (3 << 2)

1629

# define RADEON_RB3D_DC_FLUSH_ALL 0xf

1630

# define RADEON_RB3D_DC_BUSY (1 << 31)

1631

1632

#define RADEON_REG_BASE 0x0f18 /* PCI */

1633

#define RADEON_REGPROG_INF 0x0f09 /* PCI */

1634

#define RADEON_REVISION_ID 0x0f08 /* PCI */

1635

1636

#define RADEON_SC_BOTTOM 0x164c

1637

#define RADEON_SC_BOTTOM_RIGHT 0x16f0

1638

#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c

1639

#define RADEON_SC_LEFT 0x1640

1640

#define RADEON_SC_RIGHT 0x1644

1641

#define RADEON_SC_TOP 0x1648

1642

#define RADEON_SC_TOP_LEFT 0x16ec

1643

#define RADEON_SC_TOP_LEFT_C 0x1c88

1644

# define RADEON_SC_SIGN_MASK_LO 0x8000

1645

# define RADEON_SC_SIGN_MASK_HI 0x80000000

1646

#define RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */

1647

# define RADEON_M_SPLL_REF_DIV_SHIFT 0

1648

# define RADEON_M_SPLL_REF_DIV_MASK 0xff

1649

# define RADEON_MPLL_FB_DIV_SHIFT 8

1650

# define RADEON_MPLL_FB_DIV_MASK 0xff

1651

# define RADEON_SPLL_FB_DIV_SHIFT 16

1652

# define RADEON_SPLL_FB_DIV_MASK 0xff

1653

#define RADEON_SPLL_CNTL 0x000c /* PLL */

1654

# define RADEON_SPLL_SLEEP (1 << 0)

1655

# define RADEON_SPLL_RESET (1 << 1)

1656

# define RADEON_SPLL_PCP_MASK 0x7

1657

# define RADEON_SPLL_PCP_SHIFT 8

1658

# define RADEON_SPLL_PVG_MASK 0x7

1659

# define RADEON_SPLL_PVG_SHIFT 11

1660

# define RADEON_SPLL_PDC_MASK 0x3

1661

# define RADEON_SPLL_PDC_SHIFT 14

1662

#define RADEON_SCLK_CNTL 0x000d /* PLL */

1663

# define RADEON_SCLK_SRC_SEL_MASK 0x0007

1664

# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8

1665

# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008

1666

# define RADEON_SCLK_FORCEON_MASK 0xffff8000

1667

# define RADEON_SCLK_FORCE_DISP2 (1<<15)

1668

# define RADEON_SCLK_FORCE_CP (1<<16)

1669

# define RADEON_SCLK_FORCE_HDP (1<<17)

1670

# define RADEON_SCLK_FORCE_DISP1 (1<<18)

1671

# define RADEON_SCLK_FORCE_TOP (1<<19)

1672

# define RADEON_SCLK_FORCE_E2 (1<<20)

1673

# define RADEON_SCLK_FORCE_SE (1<<21)

1674

# define RADEON_SCLK_FORCE_IDCT (1<<22)

1675

# define RADEON_SCLK_FORCE_VIP (1<<23)

1676

# define RADEON_SCLK_FORCE_RE (1<<24)

1677

# define RADEON_SCLK_FORCE_PB (1<<25)

1678

# define RADEON_SCLK_FORCE_TAM (1<<26)

1679

# define RADEON_SCLK_FORCE_TDM (1<<27)

1680

# define RADEON_SCLK_FORCE_RB (1<<28)

1681

# define RADEON_SCLK_FORCE_TV_SCLK (1<<29)

1682

# define RADEON_SCLK_FORCE_SUBPIC (1<<30)

1683

# define RADEON_SCLK_FORCE_OV0 (1<<31)

1684

# define R300_SCLK_FORCE_VAP (1<<21)

1685

# define R300_SCLK_FORCE_SR (1<<25)

1686

# define R300_SCLK_FORCE_PX (1<<26)

1687

# define R300_SCLK_FORCE_TX (1<<27)

1688

# define R300_SCLK_FORCE_US (1<<28)

1689

# define R300_SCLK_FORCE_SU (1<<30)

1690

#define R300_SCLK_CNTL2 0x1e /* PLL */

1691

# define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10)

1692

# define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11)

1693

# define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12)

1694

# define R300_SCLK_FORCE_TCL (1<<13)

1695

# define R300_SCLK_FORCE_CBA (1<<14)

1696

# define R300_SCLK_FORCE_GA (1<<15)

1697

#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */

1698

# define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007

1699

# define RADEON_SCLK_MORE_FORCEON 0x0700

1700

#define RADEON_SDRAM_MODE_REG 0x0158

1701

#define RADEON_SEQ8_DATA 0x03c5 /* VGA */

1702

#define RADEON_SEQ8_IDX 0x03c4 /* VGA */

1703

#define RADEON_SNAPSHOT_F_COUNT 0x0244

1704

#define RADEON_SNAPSHOT_VH_COUNTS 0x0240

1705

#define RADEON_SNAPSHOT_VIF_COUNT 0x024c

1706

#define RADEON_SRC_OFFSET 0x15ac

1707

#define RADEON_SRC_PITCH 0x15b0

1708

#define RADEON_SRC_PITCH_OFFSET 0x1428

1709

#define RADEON_SRC_SC_BOTTOM 0x165c

1710

#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4

1711

#define RADEON_SRC_SC_RIGHT 0x1654

1712

#define RADEON_SRC_X 0x1414

1713

#define RADEON_SRC_X_Y 0x1590

1714

#define RADEON_SRC_Y 0x1418

1715

#define RADEON_SRC_Y_X 0x1434

1716

#define RADEON_STATUS 0x0f06 /* PCI */

1717

#define RADEON_SUBPIC_CNTL 0x0540 /* ? */

1718

#define RADEON_SUB_CLASS 0x0f0a /* PCI */

1719

#define RADEON_SURFACE_CNTL 0x0b00

1720

# define RADEON_SURF_TRANSLATION_DIS (1 << 8)

1721

# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)

1722

# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)

1723

# define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22)

1724

# define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23)

1725

#define RADEON_SURFACE0_INFO 0x0b0c

1726

# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16)

1727

# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16)

1728

# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16)

1729

# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16)

1730

# define R200_SURF_TILE_NONE (0 << 16)

1731

# define R200_SURF_TILE_COLOR_MACRO (1 << 16)

1732

# define R200_SURF_TILE_COLOR_MICRO (2 << 16)

1733

# define R200_SURF_TILE_COLOR_BOTH (3 << 16)

1734

# define R200_SURF_TILE_DEPTH_32BPP (4 << 16)

1735

# define R200_SURF_TILE_DEPTH_16BPP (5 << 16)

1736

# define R300_SURF_TILE_NONE (0 << 16)

1737

# define R300_SURF_TILE_COLOR_MACRO (1 << 16)

1738

# define R300_SURF_TILE_DEPTH_32BPP (2 << 16)

1739

# define RADEON_SURF_AP0_SWP_16BPP (1 << 20)

1740

# define RADEON_SURF_AP0_SWP_32BPP (1 << 21)

1741

# define RADEON_SURF_AP1_SWP_16BPP (1 << 22)

1742

# define RADEON_SURF_AP1_SWP_32BPP (1 << 23)

1743

#define RADEON_SURFACE0_LOWER_BOUND 0x0b04

1744

#define RADEON_SURFACE0_UPPER_BOUND 0x0b08

1745

#define RADEON_SURFACE1_INFO 0x0b1c

1746

#define RADEON_SURFACE1_LOWER_BOUND 0x0b14

1747

#define RADEON_SURFACE1_UPPER_BOUND 0x0b18

1748

#define RADEON_SURFACE2_INFO 0x0b2c

1749

#define RADEON_SURFACE2_LOWER_BOUND 0x0b24

1750

#define RADEON_SURFACE2_UPPER_BOUND 0x0b28

1751

#define RADEON_SURFACE3_INFO 0x0b3c

1752

#define RADEON_SURFACE3_LOWER_BOUND 0x0b34

1753

#define RADEON_SURFACE3_UPPER_BOUND 0x0b38

1754

#define RADEON_SURFACE4_INFO 0x0b4c

1755

#define RADEON_SURFACE4_LOWER_BOUND 0x0b44

1756

#define RADEON_SURFACE4_UPPER_BOUND 0x0b48

1757

#define RADEON_SURFACE5_INFO 0x0b5c

1758

#define RADEON_SURFACE5_LOWER_BOUND 0x0b54

1759

#define RADEON_SURFACE5_UPPER_BOUND 0x0b58

1760

#define RADEON_SURFACE6_INFO 0x0b6c

1761

#define RADEON_SURFACE6_LOWER_BOUND 0x0b64

1762

#define RADEON_SURFACE6_UPPER_BOUND 0x0b68

1763

#define RADEON_SURFACE7_INFO 0x0b7c

1764

#define RADEON_SURFACE7_LOWER_BOUND 0x0b74

1765

#define RADEON_SURFACE7_UPPER_BOUND 0x0b78

1766

#define RADEON_SW_SEMAPHORE 0x013c

1767

1768

#define RADEON_TEST_DEBUG_CNTL 0x0120

1769

#define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001

1770

1771

#define RADEON_TEST_DEBUG_MUX 0x0124

1772

#define RADEON_TEST_DEBUG_OUT 0x012c

1773

#define RADEON_TMDS_PLL_CNTL 0x02a8

1774

#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4

1775

# define RADEON_TMDS_TRANSMITTER_PLLEN 1

1776

# define RADEON_TMDS_TRANSMITTER_PLLRST 2

1777

#define RADEON_TRAIL_BRES_DEC 0x1614

1778

#define RADEON_TRAIL_BRES_ERR 0x160c

1779

#define RADEON_TRAIL_BRES_INC 0x1610

1780

#define RADEON_TRAIL_X 0x1618

1781

#define RADEON_TRAIL_X_SUB 0x1620

1782

1783

#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */

1784

# define RADEON_VCLK_SRC_SEL_MASK 0x03

1785

# define RADEON_VCLK_SRC_SEL_CPUCLK 0x00

1786

# define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01

1787

# define RADEON_VCLK_SRC_SEL_BYTECLK 0x02

1788

# define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03

1789

# define RADEON_PIXCLK_ALWAYS_ONb (1<<6)

1790

# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)

1791

# define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)

1792

1793

#define RADEON_VENDOR_ID 0x0f00 /* PCI */

1794

#define RADEON_VGA_DDA_CONFIG 0x02e8

1795

#define RADEON_VGA_DDA_ON_OFF 0x02ec

1796

#define RADEON_VID_BUFFER_CONTROL 0x0900

1797

#define RADEON_VIDEOMUX_CNTL 0x0190

1798

1799

/* VIP bus */

1800

#define RADEON_VIPH_CH0_DATA 0x0c00

1801

#define RADEON_VIPH_CH1_DATA 0x0c04

1802

#define RADEON_VIPH_CH2_DATA 0x0c08

1803

#define RADEON_VIPH_CH3_DATA 0x0c0c

1804

#define RADEON_VIPH_CH0_ADDR 0x0c10

1805

#define RADEON_VIPH_CH1_ADDR 0x0c14

1806

#define RADEON_VIPH_CH2_ADDR 0x0c18

1807

#define RADEON_VIPH_CH3_ADDR 0x0c1c

1808

#define RADEON_VIPH_CH0_SBCNT 0x0c20

1809

#define RADEON_VIPH_CH1_SBCNT 0x0c24

1810

#define RADEON_VIPH_CH2_SBCNT 0x0c28

1811

#define RADEON_VIPH_CH3_SBCNT 0x0c2c

1812

#define RADEON_VIPH_CH0_ABCNT 0x0c30

1813

#define RADEON_VIPH_CH1_ABCNT 0x0c34

1814

#define RADEON_VIPH_CH2_ABCNT 0x0c38

1815

#define RADEON_VIPH_CH3_ABCNT 0x0c3c

1816

#define RADEON_VIPH_CONTROL 0x0c40

1817

# define RADEON_VIP_BUSY 0

1818

# define RADEON_VIP_IDLE 1

1819

# define RADEON_VIP_RESET 2

1820

# define RADEON_VIPH_EN (1 << 21)

1821

#define RADEON_VIPH_DV_LAT 0x0c44

1822

#define RADEON_VIPH_BM_CHUNK 0x0c48

1823

#define RADEON_VIPH_DV_INT 0x0c4c

1824

#define RADEON_VIPH_TIMEOUT_STAT 0x0c50

1825

#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010

1826

#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010

1827

#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000

1828

1829

#define RADEON_VIPH_REG_DATA 0x0084

1830

#define RADEON_VIPH_REG_ADDR 0x0080

1831

1832

1833

#define RADEON_WAIT_UNTIL 0x1720

1834

# define RADEON_WAIT_CRTC_PFLIP (1 << 0)

1835

# define RADEON_WAIT_RE_CRTC_VLINE (1 << 1)

1836

# define RADEON_WAIT_FE_CRTC_VLINE (1 << 2)

1837

# define RADEON_WAIT_CRTC_VLINE (1 << 3)

1838

# define RADEON_WAIT_DMA_VID_IDLE (1 << 8)

1839

# define RADEON_WAIT_DMA_GUI_IDLE (1 << 9)

1840

# define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */

1841

# define RADEON_WAIT_OV0_FLIP (1 << 11)

1842

# define RADEON_WAIT_AGP_FLUSH (1 << 13)

1843

# define RADEON_WAIT_2D_IDLE (1 << 14)

1844

# define RADEON_WAIT_3D_IDLE (1 << 15)

1845

# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)

1846

# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)

1847

# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)

1848

# define RADEON_CMDFIFO_ENTRIES_SHIFT 10

1849

# define RADEON_CMDFIFO_ENTRIES_MASK 0x7f

1850

# define RADEON_WAIT_VAP_IDLE (1 << 28)

1851

# define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30)

1852

# define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31)

1853

# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31)

1854

1855

#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */

1856

#define RADEON_XCLK_CNTL 0x000d /* PLL */

1857

#define RADEON_XDLL_CNTL 0x000c /* PLL */

1858

#define RADEON_XPLL_CNTL 0x000b /* PLL */

/* Registers for 3D/TCL */

1863

#define RADEON_PP_BORDER_COLOR_0 0x1d40

1864

#define RADEON_PP_BORDER_COLOR_1 0x1d44

1865

#define RADEON_PP_BORDER_COLOR_2 0x1d48

1866

#define RADEON_PP_CNTL 0x1c38

1867

# define RADEON_STIPPLE_ENABLE (1 << 0)

1868

# define RADEON_SCISSOR_ENABLE (1 << 1)

1869

# define RADEON_PATTERN_ENABLE (1 << 2)

1870

# define RADEON_SHADOW_ENABLE (1 << 3)

1871

# define RADEON_TEX_ENABLE_MASK (0xf << 4)

1872

# define RADEON_TEX_0_ENABLE (1 << 4)

1873

# define RADEON_TEX_1_ENABLE (1 << 5)

1874

# define RADEON_TEX_2_ENABLE (1 << 6)

1875

# define RADEON_TEX_3_ENABLE (1 << 7)

1876

# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)

1877

# define RADEON_TEX_BLEND_0_ENABLE (1 << 12)

1878

# define RADEON_TEX_BLEND_1_ENABLE (1 << 13)

1879

# define RADEON_TEX_BLEND_2_ENABLE (1 << 14)

1880

# define RADEON_TEX_BLEND_3_ENABLE (1 << 15)

1881

# define RADEON_PLANAR_YUV_ENABLE (1 << 20)

1882

# define RADEON_SPECULAR_ENABLE (1 << 21)

1883

# define RADEON_FOG_ENABLE (1 << 22)

1884

# define RADEON_ALPHA_TEST_ENABLE (1 << 23)

1885

# define RADEON_ANTI_ALIAS_NONE (0 << 24)

1886

# define RADEON_ANTI_ALIAS_LINE (1 << 24)

1887

# define RADEON_ANTI_ALIAS_POLY (2 << 24)

1888

# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24)

1889

# define RADEON_BUMP_MAP_ENABLE (1 << 26)

1890

# define RADEON_BUMPED_MAP_T0 (0 << 27)

1891

# define RADEON_BUMPED_MAP_T1 (1 << 27)

1892

# define RADEON_BUMPED_MAP_T2 (2 << 27)

1893

# define RADEON_TEX_3D_ENABLE_0 (1 << 29)

1894

# define RADEON_TEX_3D_ENABLE_1 (1 << 30)

1895

# define RADEON_MC_ENABLE (1 << 31)

1896

#define RADEON_PP_FOG_COLOR 0x1c18

1897

# define RADEON_FOG_COLOR_MASK 0x00ffffff

1898

# define RADEON_FOG_VERTEX (0 << 24)

1899

# define RADEON_FOG_TABLE (1 << 24)

1900

# define RADEON_FOG_USE_DEPTH (0 << 25)

1901

# define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25)

1902

# define RADEON_FOG_USE_SPEC_ALPHA (3 << 25)

1903

#define RADEON_PP_LUM_MATRIX 0x1d00

1904

#define RADEON_PP_MISC 0x1c14

1905

# define RADEON_REF_ALPHA_MASK 0x000000ff

1906

# define RADEON_ALPHA_TEST_FAIL (0 << 8)

1907

# define RADEON_ALPHA_TEST_LESS (1 << 8)

1908

# define RADEON_ALPHA_TEST_LEQUAL (2 << 8)

1909

# define RADEON_ALPHA_TEST_EQUAL (3 << 8)

1910

# define RADEON_ALPHA_TEST_GEQUAL (4 << 8)

1911

# define RADEON_ALPHA_TEST_GREATER (5 << 8)

1912

# define RADEON_ALPHA_TEST_NEQUAL (6 << 8)

1913

# define RADEON_ALPHA_TEST_PASS (7 << 8)

1914

# define RADEON_ALPHA_TEST_OP_MASK (7 << 8)

1915

# define RADEON_CHROMA_FUNC_FAIL (0 << 16)

1916

# define RADEON_CHROMA_FUNC_PASS (1 << 16)

1917

# define RADEON_CHROMA_FUNC_NEQUAL (2 << 16)

1918

# define RADEON_CHROMA_FUNC_EQUAL (3 << 16)

1919

# define RADEON_CHROMA_KEY_NEAREST (0 << 18)

1920

# define RADEON_CHROMA_KEY_ZERO (1 << 18)

1921

# define RADEON_SHADOW_ID_AUTO_INC (1 << 20)

1922

# define RADEON_SHADOW_FUNC_EQUAL (0 << 21)

1923

# define RADEON_SHADOW_FUNC_NEQUAL (1 << 21)

1924

# define RADEON_SHADOW_PASS_1 (0 << 22)

1925

# define RADEON_SHADOW_PASS_2 (1 << 22)

1926

# define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24)

1927

# define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24)

1928

#define RADEON_PP_ROT_MATRIX_0 0x1d58

1929

#define RADEON_PP_ROT_MATRIX_1 0x1d5c

1930

#define RADEON_PP_TXFILTER_0 0x1c54

1931

#define RADEON_PP_TXFILTER_1 0x1c6c

1932

#define RADEON_PP_TXFILTER_2 0x1c84

1933

# define RADEON_MAG_FILTER_NEAREST (0 << 0)

1934

# define RADEON_MAG_FILTER_LINEAR (1 << 0)

1935

# define RADEON_MAG_FILTER_MASK (1 << 0)

1936

# define RADEON_MIN_FILTER_NEAREST (0 << 1)

1937

# define RADEON_MIN_FILTER_LINEAR (1 << 1)

1938

# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)

1939

# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)

1940

# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)

1941

# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)

1942

# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1)

1943

# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1)

1944

# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)

1945

# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)

1946

# define RADEON_MIN_FILTER_MASK (15 << 1)

1947

# define RADEON_MAX_ANISO_1_TO_1 (0 << 5)

1948

# define RADEON_MAX_ANISO_2_TO_1 (1 << 5)

1949

# define RADEON_MAX_ANISO_4_TO_1 (2 << 5)

1950

# define RADEON_MAX_ANISO_8_TO_1 (3 << 5)

1951

# define RADEON_MAX_ANISO_16_TO_1 (4 << 5)

1952

# define RADEON_MAX_ANISO_MASK (7 << 5)

1953

# define RADEON_LOD_BIAS_MASK (0xff << 8)

1954

# define RADEON_LOD_BIAS_SHIFT 8

1955

# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16)

1956

# define RADEON_MAX_MIP_LEVEL_SHIFT 16

1957

# define RADEON_YUV_TO_RGB (1 << 20)

1958

# define RADEON_YUV_TEMPERATURE_COOL (0 << 21)

1959

# define RADEON_YUV_TEMPERATURE_HOT (1 << 21)

1960

# define RADEON_YUV_TEMPERATURE_MASK (1 << 21)

1961

# define RADEON_WRAPEN_S (1 << 22)

1962

# define RADEON_CLAMP_S_WRAP (0 << 23)

1963

# define RADEON_CLAMP_S_MIRROR (1 << 23)

1964

# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23)

1965

# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)

1966

# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23)

1967

# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)

1968

# define RADEON_CLAMP_S_CLAMP_GL (6 << 23)

1969

# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)

1970

# define RADEON_CLAMP_S_MASK (7 << 23)

1971

# define RADEON_WRAPEN_T (1 << 26)

1972

# define RADEON_CLAMP_T_WRAP (0 << 27)

1973

# define RADEON_CLAMP_T_MIRROR (1 << 27)

1974

# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27)

1975

# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)

1976

# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27)

1977

# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)

1978

# define RADEON_CLAMP_T_CLAMP_GL (6 << 27)

1979

# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)

1980

# define RADEON_CLAMP_T_MASK (7 << 27)

1981

# define RADEON_BORDER_MODE_OGL (0 << 31)

1982

# define RADEON_BORDER_MODE_D3D (1 << 31)

1983

#define RADEON_PP_TXFORMAT_0 0x1c58

1984

#define RADEON_PP_TXFORMAT_1 0x1c70

1985

#define RADEON_PP_TXFORMAT_2 0x1c88

1986

# define RADEON_TXFORMAT_I8 (0 << 0)

1987

# define RADEON_TXFORMAT_AI88 (1 << 0)

1988

# define RADEON_TXFORMAT_RGB332 (2 << 0)

1989

# define RADEON_TXFORMAT_ARGB1555 (3 << 0)

1990

# define RADEON_TXFORMAT_RGB565 (4 << 0)

1991

# define RADEON_TXFORMAT_ARGB4444 (5 << 0)

1992

# define RADEON_TXFORMAT_ARGB8888 (6 << 0)

1993

# define RADEON_TXFORMAT_RGBA8888 (7 << 0)

1994

# define RADEON_TXFORMAT_Y8 (8 << 0)

1995

# define RADEON_TXFORMAT_VYUY422 (10 << 0)

1996

# define RADEON_TXFORMAT_YVYU422 (11 << 0)

1997

# define RADEON_TXFORMAT_DXT1 (12 << 0)

1998

# define RADEON_TXFORMAT_DXT23 (14 << 0)

1999

# define RADEON_TXFORMAT_DXT45 (15 << 0)

Dave Airlie

2009-09-01 15:25:57 +1000

[diff] [blame]

2000

# define RADEON_TXFORMAT_SHADOW16 (16 << 0)

2001

# define RADEON_TXFORMAT_SHADOW32 (17 << 0)

2002

# define RADEON_TXFORMAT_DUDV88 (18 << 0)

2003

# define RADEON_TXFORMAT_LDUDV655 (19 << 0)

2004

# define RADEON_TXFORMAT_LDUDUV8888 (20 << 0)

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

2005

# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)

2006

# define RADEON_TXFORMAT_FORMAT_SHIFT 0

2007

# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)

2008

# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6)

2009

# define RADEON_TXFORMAT_NON_POWER2 (1 << 7)

2010

# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8)

2011

# define RADEON_TXFORMAT_WIDTH_SHIFT 8

2012

# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12)

2013

# define RADEON_TXFORMAT_HEIGHT_SHIFT 12

2014

# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16)

2015

# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16

2016

# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20)

2017

# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20

2018

# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)

2019

# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)

2020

# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)

2021

# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)

2022

# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26)

2023

# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26)

2024

# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26)

2025

# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26)

2026

# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)

2027

# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)

2028

# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)

2029

# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31)

2030

#define RADEON_PP_CUBIC_FACES_0 0x1d24

2031

#define RADEON_PP_CUBIC_FACES_1 0x1d28

2032

#define RADEON_PP_CUBIC_FACES_2 0x1d2c

2033

# define RADEON_FACE_WIDTH_1_SHIFT 0

2034

# define RADEON_FACE_HEIGHT_1_SHIFT 4

2035

# define RADEON_FACE_WIDTH_1_MASK (0xf << 0)

2036

# define RADEON_FACE_HEIGHT_1_MASK (0xf << 4)

2037

# define RADEON_FACE_WIDTH_2_SHIFT 8

2038

# define RADEON_FACE_HEIGHT_2_SHIFT 12

2039

# define RADEON_FACE_WIDTH_2_MASK (0xf << 8)

2040

# define RADEON_FACE_HEIGHT_2_MASK (0xf << 12)

2041

# define RADEON_FACE_WIDTH_3_SHIFT 16

2042

# define RADEON_FACE_HEIGHT_3_SHIFT 20

2043

# define RADEON_FACE_WIDTH_3_MASK (0xf << 16)

2044

# define RADEON_FACE_HEIGHT_3_MASK (0xf << 20)

2045

# define RADEON_FACE_WIDTH_4_SHIFT 24

2046

# define RADEON_FACE_HEIGHT_4_SHIFT 28

2047

# define RADEON_FACE_WIDTH_4_MASK (0xf << 24)

2048

# define RADEON_FACE_HEIGHT_4_MASK (0xf << 28)

2049

2050

#define RADEON_PP_TXOFFSET_0 0x1c5c

2051

#define RADEON_PP_TXOFFSET_1 0x1c74

2052

#define RADEON_PP_TXOFFSET_2 0x1c8c

2053

# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0)

2054

# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0)

2055

# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0)

2056

# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)

2057

# define RADEON_TXO_MACRO_LINEAR (0 << 2)

2058

# define RADEON_TXO_MACRO_TILE (1 << 2)

2059

# define RADEON_TXO_MICRO_LINEAR (0 << 3)

2060

# define RADEON_TXO_MICRO_TILE_X2 (1 << 3)

2061

# define RADEON_TXO_MICRO_TILE_OPT (2 << 3)

2062

# define RADEON_TXO_OFFSET_MASK 0xffffffe0

2063

# define RADEON_TXO_OFFSET_SHIFT 5

2064

2065

#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */

2066

#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4

2067

#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8

2068

#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc

2069

#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0

2070

#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00

2071

#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04

2072

#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08

2073

#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c

2074

#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10

2075

#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14

2076

#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18

2077

#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c

2078

#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20

2079

#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24

2080

2081

#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */

2082

#define RADEON_PP_TEX_SIZE_1 0x1d0c

2083

#define RADEON_PP_TEX_SIZE_2 0x1d14

2084

# define RADEON_TEX_USIZE_MASK (0x7ff << 0)

2085

# define RADEON_TEX_USIZE_SHIFT 0

2086

# define RADEON_TEX_VSIZE_MASK (0x7ff << 16)

2087

# define RADEON_TEX_VSIZE_SHIFT 16

2088

# define RADEON_SIGNED_RGB_MASK (1 << 30)

2089

# define RADEON_SIGNED_RGB_SHIFT 30

2090

# define RADEON_SIGNED_ALPHA_MASK (1 << 31)

2091

# define RADEON_SIGNED_ALPHA_SHIFT 31

2092

#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */

2093

#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */

2094

#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */

2095

/* note: bits 13-5: 32 byte aligned stride of texture map */

2096

2097

#define RADEON_PP_TXCBLEND_0 0x1c60

2098

#define RADEON_PP_TXCBLEND_1 0x1c78

2099

#define RADEON_PP_TXCBLEND_2 0x1c90

2100

# define RADEON_COLOR_ARG_A_SHIFT 0

2101

# define RADEON_COLOR_ARG_A_MASK (0x1f << 0)

2102

# define RADEON_COLOR_ARG_A_ZERO (0 << 0)

2103

# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0)

2104

# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0)

2105

# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0)

2106

# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0)

2107

# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0)

2108

# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0)

2109

# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0)

2110

# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0)

2111

# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0)

2112

# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0)

2113

# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0)

2114

# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0)

2115

# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0)

2116

# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0)

2117

# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0)

2118

# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0)

2119

# define RADEON_COLOR_ARG_B_SHIFT 5

2120

# define RADEON_COLOR_ARG_B_MASK (0x1f << 5)

2121

# define RADEON_COLOR_ARG_B_ZERO (0 << 5)

2122

# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5)

2123

# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5)

2124

# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5)

2125

# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5)

2126

# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5)

2127

# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5)

2128

# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5)

2129

# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5)

2130

# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5)

2131

# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5)

2132

# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5)

2133

# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5)

2134

# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5)

2135

# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5)

2136

# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5)

2137

# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5)

2138

# define RADEON_COLOR_ARG_C_SHIFT 10

2139

# define RADEON_COLOR_ARG_C_MASK (0x1f << 10)

2140

# define RADEON_COLOR_ARG_C_ZERO (0 << 10)

2141

# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10)

2142

# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10)

2143

# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10)

2144

# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10)

2145

# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10)

2146

# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10)

2147

# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10)

2148

# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10)

2149

# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10)

2150

# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10)

2151

# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10)

2152

# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10)

2153

# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10)

2154

# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10)

2155

# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10)

2156

# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10)

2157

# define RADEON_COMP_ARG_A (1 << 15)

2158

# define RADEON_COMP_ARG_A_SHIFT 15

2159

# define RADEON_COMP_ARG_B (1 << 16)

2160

# define RADEON_COMP_ARG_B_SHIFT 16

2161

# define RADEON_COMP_ARG_C (1 << 17)

2162

# define RADEON_COMP_ARG_C_SHIFT 17

2163

# define RADEON_BLEND_CTL_MASK (7 << 18)

2164

# define RADEON_BLEND_CTL_ADD (0 << 18)

2165

# define RADEON_BLEND_CTL_SUBTRACT (1 << 18)

2166

# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18)

2167

# define RADEON_BLEND_CTL_BLEND (3 << 18)

2168

# define RADEON_BLEND_CTL_DOT3 (4 << 18)

2169

# define RADEON_SCALE_SHIFT 21

2170

# define RADEON_SCALE_MASK (3 << 21)

2171

# define RADEON_SCALE_1X (0 << 21)

2172

# define RADEON_SCALE_2X (1 << 21)

2173

# define RADEON_SCALE_4X (2 << 21)

2174

# define RADEON_CLAMP_TX (1 << 23)

2175

# define RADEON_T0_EQ_TCUR (1 << 24)

2176

# define RADEON_T1_EQ_TCUR (1 << 25)

2177

# define RADEON_T2_EQ_TCUR (1 << 26)

2178

# define RADEON_T3_EQ_TCUR (1 << 27)

2179

# define RADEON_COLOR_ARG_MASK 0x1f

2180

# define RADEON_COMP_ARG_SHIFT 15

2181

#define RADEON_PP_TXABLEND_0 0x1c64

2182

#define RADEON_PP_TXABLEND_1 0x1c7c

2183

#define RADEON_PP_TXABLEND_2 0x1c94

2184

# define RADEON_ALPHA_ARG_A_SHIFT 0

2185

# define RADEON_ALPHA_ARG_A_MASK (0xf << 0)

2186

# define RADEON_ALPHA_ARG_A_ZERO (0 << 0)

2187

# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0)

2188

# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0)

2189

# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0)

2190

# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0)

2191

# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0)

2192

# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0)

2193

# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0)

2194

# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0)

2195

# define RADEON_ALPHA_ARG_B_SHIFT 4

2196

# define RADEON_ALPHA_ARG_B_MASK (0xf << 4)

2197

# define RADEON_ALPHA_ARG_B_ZERO (0 << 4)

2198

# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4)

2199

# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4)

2200

# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4)

2201

# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4)

2202

# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4)

2203

# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4)

2204

# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4)

2205

# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4)

2206

# define RADEON_ALPHA_ARG_C_SHIFT 8

2207

# define RADEON_ALPHA_ARG_C_MASK (0xf << 8)

2208

# define RADEON_ALPHA_ARG_C_ZERO (0 << 8)

2209

# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8)

2210

# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8)

2211

# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8)

2212

# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8)

2213

# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8)

2214

# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8)

2215

# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8)

2216

# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8)

2217

# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9)

2218

# define RADEON_ALPHA_ARG_MASK 0xf

2219

2220

#define RADEON_PP_TFACTOR_0 0x1c68

2221

#define RADEON_PP_TFACTOR_1 0x1c80

2222

#define RADEON_PP_TFACTOR_2 0x1c98

2223

2224

#define RADEON_RB3D_BLENDCNTL 0x1c20

2225

# define RADEON_COMB_FCN_MASK (3 << 12)

2226

# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12)

2227

# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12)

2228

# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12)

2229

# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12)

2230

# define RADEON_SRC_BLEND_GL_ZERO (32 << 16)

2231

# define RADEON_SRC_BLEND_GL_ONE (33 << 16)

2232

# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16)

2233

# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)

2234

# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16)

2235

# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)

2236

# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16)

2237

# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)

2238

# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16)

2239

# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)

2240

# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)

2241

# define RADEON_SRC_BLEND_MASK (63 << 16)

2242

# define RADEON_DST_BLEND_GL_ZERO (32 << 24)

2243

# define RADEON_DST_BLEND_GL_ONE (33 << 24)

2244

# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24)

2245

# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)

2246

# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24)

2247

# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)

2248

# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24)

2249

# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)

2250

# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24)

2251

# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)

2252

# define RADEON_DST_BLEND_MASK (63 << 24)

2253

#define RADEON_RB3D_CNTL 0x1c3c

2254

# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)

2255

# define RADEON_PLANE_MASK_ENABLE (1 << 1)

2256

# define RADEON_DITHER_ENABLE (1 << 2)

2257

# define RADEON_ROUND_ENABLE (1 << 3)

2258

# define RADEON_SCALE_DITHER_ENABLE (1 << 4)

2259

# define RADEON_DITHER_INIT (1 << 5)

2260

# define RADEON_ROP_ENABLE (1 << 6)

2261

# define RADEON_STENCIL_ENABLE (1 << 7)

2262

# define RADEON_Z_ENABLE (1 << 8)

Dave Airlie

2009-09-01 15:25:57 +1000

[diff] [blame]

2263

# define RADEON_DEPTHXY_OFFSET_ENABLE (1 << 9)

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

2264

# define RADEON_RB3D_COLOR_FORMAT_SHIFT 10

2265

2266

# define RADEON_COLOR_FORMAT_ARGB1555 3

2267

# define RADEON_COLOR_FORMAT_RGB565 4

2268

# define RADEON_COLOR_FORMAT_ARGB8888 6

2269

# define RADEON_COLOR_FORMAT_RGB332 7

2270

# define RADEON_COLOR_FORMAT_Y8 8

2271

# define RADEON_COLOR_FORMAT_RGB8 9

2272

# define RADEON_COLOR_FORMAT_YUV422_VYUY 11

2273

# define RADEON_COLOR_FORMAT_YUV422_YVYU 12

2274

# define RADEON_COLOR_FORMAT_aYUV444 14

2275

# define RADEON_COLOR_FORMAT_ARGB4444 15

2276

2277

# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14)

2278

#define RADEON_RB3D_COLOROFFSET 0x1c40

2279

# define RADEON_COLOROFFSET_MASK 0xfffffff0

2280

#define RADEON_RB3D_COLORPITCH 0x1c48

2281

# define RADEON_COLORPITCH_MASK 0x000001ff8

2282

# define RADEON_COLOR_TILE_ENABLE (1 << 16)

2283

# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17)

2284

# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18)

2285

# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18)

2286

# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18)

2287

#define RADEON_RB3D_DEPTHOFFSET 0x1c24

2288

#define RADEON_RB3D_DEPTHPITCH 0x1c28

2289

# define RADEON_DEPTHPITCH_MASK 0x00001ff8

2290

# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18)

2291

# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18)

2292

# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18)

2293

#define RADEON_RB3D_PLANEMASK 0x1d84

2294

#define RADEON_RB3D_ROPCNTL 0x1d80

2295

# define RADEON_ROP_MASK (15 << 8)

2296

# define RADEON_ROP_CLEAR (0 << 8)

2297

# define RADEON_ROP_NOR (1 << 8)

2298

# define RADEON_ROP_AND_INVERTED (2 << 8)

2299

# define RADEON_ROP_COPY_INVERTED (3 << 8)

2300

# define RADEON_ROP_AND_REVERSE (4 << 8)

2301

# define RADEON_ROP_INVERT (5 << 8)

2302

# define RADEON_ROP_XOR (6 << 8)

2303

# define RADEON_ROP_NAND (7 << 8)

2304

# define RADEON_ROP_AND (8 << 8)

2305

# define RADEON_ROP_EQUIV (9 << 8)

2306

# define RADEON_ROP_NOOP (10 << 8)

2307

# define RADEON_ROP_OR_INVERTED (11 << 8)

2308

# define RADEON_ROP_COPY (12 << 8)

2309

# define RADEON_ROP_OR_REVERSE (13 << 8)

2310

# define RADEON_ROP_OR (14 << 8)

2311

# define RADEON_ROP_SET (15 << 8)

2312

#define RADEON_RB3D_STENCILREFMASK 0x1d7c

2313

# define RADEON_STENCIL_REF_SHIFT 0

2314

# define RADEON_STENCIL_REF_MASK (0xff << 0)

2315

# define RADEON_STENCIL_MASK_SHIFT 16

2316

# define RADEON_STENCIL_VALUE_MASK (0xff << 16)

2317

# define RADEON_STENCIL_WRITEMASK_SHIFT 24

2318

# define RADEON_STENCIL_WRITE_MASK (0xff << 24)

2319

#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c

2320

# define RADEON_DEPTH_FORMAT_MASK (0xf << 0)

2321

# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)

2322

# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)

2323

# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0)

2324

# define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0)

2325

# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0)

2326

# define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0)

2327

# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0)

2328

# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0)

2329

# define RADEON_Z_TEST_NEVER (0 << 4)

2330

# define RADEON_Z_TEST_LESS (1 << 4)

2331

# define RADEON_Z_TEST_LEQUAL (2 << 4)

2332

# define RADEON_Z_TEST_EQUAL (3 << 4)

2333

# define RADEON_Z_TEST_GEQUAL (4 << 4)

2334

# define RADEON_Z_TEST_GREATER (5 << 4)

2335

# define RADEON_Z_TEST_NEQUAL (6 << 4)

2336

# define RADEON_Z_TEST_ALWAYS (7 << 4)

2337

# define RADEON_Z_TEST_MASK (7 << 4)

2338

# define RADEON_STENCIL_TEST_NEVER (0 << 12)

2339

# define RADEON_STENCIL_TEST_LESS (1 << 12)

2340

# define RADEON_STENCIL_TEST_LEQUAL (2 << 12)

2341

# define RADEON_STENCIL_TEST_EQUAL (3 << 12)

2342

# define RADEON_STENCIL_TEST_GEQUAL (4 << 12)

2343

# define RADEON_STENCIL_TEST_GREATER (5 << 12)

2344

# define RADEON_STENCIL_TEST_NEQUAL (6 << 12)

2345

# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)

2346

# define RADEON_STENCIL_TEST_MASK (0x7 << 12)

2347

# define RADEON_STENCIL_FAIL_KEEP (0 << 16)

2348

# define RADEON_STENCIL_FAIL_ZERO (1 << 16)

2349

# define RADEON_STENCIL_FAIL_REPLACE (2 << 16)

2350

# define RADEON_STENCIL_FAIL_INC (3 << 16)

2351

# define RADEON_STENCIL_FAIL_DEC (4 << 16)

2352

# define RADEON_STENCIL_FAIL_INVERT (5 << 16)

2353

# define RADEON_STENCIL_FAIL_MASK (0x7 << 16)

2354

# define RADEON_STENCIL_ZPASS_KEEP (0 << 20)

2355

# define RADEON_STENCIL_ZPASS_ZERO (1 << 20)

2356

# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)

2357

# define RADEON_STENCIL_ZPASS_INC (3 << 20)

2358

# define RADEON_STENCIL_ZPASS_DEC (4 << 20)

2359

# define RADEON_STENCIL_ZPASS_INVERT (5 << 20)

2360

# define RADEON_STENCIL_ZPASS_MASK (0x7 << 20)

2361

# define RADEON_STENCIL_ZFAIL_KEEP (0 << 24)

2362

# define RADEON_STENCIL_ZFAIL_ZERO (1 << 24)

2363

# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)

2364

# define RADEON_STENCIL_ZFAIL_INC (3 << 24)

2365

# define RADEON_STENCIL_ZFAIL_DEC (4 << 24)

2366

# define RADEON_STENCIL_ZFAIL_INVERT (5 << 24)

2367

# define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24)

2368

# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)

2369

# define RADEON_FORCE_Z_DIRTY (1 << 29)

2370

# define RADEON_Z_WRITE_ENABLE (1 << 30)

2371

#define RADEON_RE_LINE_PATTERN 0x1cd0

2372

# define RADEON_LINE_PATTERN_MASK 0x0000ffff

2373

# define RADEON_LINE_REPEAT_COUNT_SHIFT 16

2374

# define RADEON_LINE_PATTERN_START_SHIFT 24

2375

# define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28)

2376

# define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28)

2377

# define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29)

2378

#define RADEON_RE_LINE_STATE 0x1cd4

2379

# define RADEON_LINE_CURRENT_PTR_SHIFT 0

2380

# define RADEON_LINE_CURRENT_COUNT_SHIFT 8

2381

#define RADEON_RE_MISC 0x26c4

2382

# define RADEON_STIPPLE_COORD_MASK 0x1f

2383

# define RADEON_STIPPLE_X_OFFSET_SHIFT 0

2384

# define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0)

2385

# define RADEON_STIPPLE_Y_OFFSET_SHIFT 8

2386

# define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8)

2387

# define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16)

2388

# define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16)

2389

#define RADEON_RE_SOLID_COLOR 0x1c1c

2390

#define RADEON_RE_TOP_LEFT 0x26c0

2391

# define RADEON_RE_LEFT_SHIFT 0

2392

# define RADEON_RE_TOP_SHIFT 16

2393

#define RADEON_RE_WIDTH_HEIGHT 0x1c44

2394

# define RADEON_RE_WIDTH_SHIFT 0

2395

# define RADEON_RE_HEIGHT_SHIFT 16

2396

Dave Airlie

17782d9

2009-08-21 10:07:54 +1000

[diff] [blame]

2397

#define RADEON_RB3D_ZPASS_DATA 0x3290

2398

#define RADEON_RB3D_ZPASS_ADDR 0x3294

2399

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

2400

#define RADEON_SE_CNTL 0x1c4c

2401

# define RADEON_FFACE_CULL_CW (0 << 0)

2402

# define RADEON_FFACE_CULL_CCW (1 << 0)

2403

# define RADEON_FFACE_CULL_DIR_MASK (1 << 0)

2404

# define RADEON_BFACE_CULL (0 << 1)

2405

# define RADEON_BFACE_SOLID (3 << 1)

2406

# define RADEON_FFACE_CULL (0 << 3)

2407

# define RADEON_FFACE_SOLID (3 << 3)

2408

# define RADEON_FFACE_CULL_MASK (3 << 3)

2409

# define RADEON_BADVTX_CULL_DISABLE (1 << 5)

2410

# define RADEON_FLAT_SHADE_VTX_0 (0 << 6)

2411

# define RADEON_FLAT_SHADE_VTX_1 (1 << 6)

2412

# define RADEON_FLAT_SHADE_VTX_2 (2 << 6)

2413

# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)

2414

# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8)

2415

# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)

2416

# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)

2417

# define RADEON_DIFFUSE_SHADE_MASK (3 << 8)

2418

# define RADEON_ALPHA_SHADE_SOLID (0 << 10)

2419

# define RADEON_ALPHA_SHADE_FLAT (1 << 10)

2420

# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)

2421

# define RADEON_ALPHA_SHADE_MASK (3 << 10)

2422

# define RADEON_SPECULAR_SHADE_SOLID (0 << 12)

2423

# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)

2424

# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)

2425

# define RADEON_SPECULAR_SHADE_MASK (3 << 12)

2426

# define RADEON_FOG_SHADE_SOLID (0 << 14)

2427

# define RADEON_FOG_SHADE_FLAT (1 << 14)

2428

# define RADEON_FOG_SHADE_GOURAUD (2 << 14)

2429

# define RADEON_FOG_SHADE_MASK (3 << 14)

2430

# define RADEON_ZBIAS_ENABLE_POINT (1 << 16)

2431

# define RADEON_ZBIAS_ENABLE_LINE (1 << 17)

2432

# define RADEON_ZBIAS_ENABLE_TRI (1 << 18)

2433

# define RADEON_WIDELINE_ENABLE (1 << 20)

2434

# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)

2435

# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)

2436

# define RADEON_VTX_PIX_CENTER_D3D (0 << 27)

2437

# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)

2438

# define RADEON_ROUND_MODE_TRUNC (0 << 28)

2439

# define RADEON_ROUND_MODE_ROUND (1 << 28)

2440

# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28)

2441

# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28)

2442

# define RADEON_ROUND_PREC_16TH_PIX (0 << 30)

2443

# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)

2444

# define RADEON_ROUND_PREC_4TH_PIX (2 << 30)

2445

# define RADEON_ROUND_PREC_HALF_PIX (3 << 30)

2446

#define R200_RE_CNTL 0x1c50

2447

# define R200_STIPPLE_ENABLE 0x1

2448

# define R200_SCISSOR_ENABLE 0x2

2449

# define R200_PATTERN_ENABLE 0x4

2450

# define R200_PERSPECTIVE_ENABLE 0x8

2451

# define R200_POINT_SMOOTH 0x20

2452

# define R200_VTX_STQ0_D3D 0x00010000

2453

# define R200_VTX_STQ1_D3D 0x00040000

2454

# define R200_VTX_STQ2_D3D 0x00100000

2455

# define R200_VTX_STQ3_D3D 0x00400000

2456

# define R200_VTX_STQ4_D3D 0x01000000

2457

# define R200_VTX_STQ5_D3D 0x04000000

2458

#define RADEON_SE_CNTL_STATUS 0x2140

2459

# define RADEON_VC_NO_SWAP (0 << 0)

2460

# define RADEON_VC_16BIT_SWAP (1 << 0)

2461

# define RADEON_VC_32BIT_SWAP (2 << 0)

2462

# define RADEON_VC_HALF_DWORD_SWAP (3 << 0)

2463

# define RADEON_TCL_BYPASS (1 << 8)

2464

#define RADEON_SE_COORD_FMT 0x1c50

2465

# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0)

2466

# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1)

2467

# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8)

2468

# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9)

2469

# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10)

2470

# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11)

2471

# define RADEON_VTX_W0_NORMALIZE (1 << 12)

2472

# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16)

2473

# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17)

2474

# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19)

2475

# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21)

2476

# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23)

2477

# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26)

2478

# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26)

2479

#define RADEON_SE_LINE_WIDTH 0x1db8

2480

#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c

2481

# define RADEON_LIGHTING_ENABLE (1 << 0)

2482

# define RADEON_LIGHT_IN_MODELSPACE (1 << 1)

2483

# define RADEON_LOCAL_VIEWER (1 << 2)

2484

# define RADEON_NORMALIZE_NORMALS (1 << 3)

2485

# define RADEON_RESCALE_NORMALS (1 << 4)

2486

# define RADEON_SPECULAR_LIGHTS (1 << 5)

2487

# define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6)

2488

# define RADEON_LIGHT_ALPHA (1 << 7)

2489

# define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8)

2490

# define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9)

2491

# define RADEON_LM_SOURCE_STATE_PREMULT 0

2492

# define RADEON_LM_SOURCE_STATE_MULT 1

2493

# define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2

2494

# define RADEON_LM_SOURCE_VERTEX_SPECULAR 3

2495

# define RADEON_EMISSIVE_SOURCE_SHIFT 16

2496

# define RADEON_AMBIENT_SOURCE_SHIFT 18

2497

# define RADEON_DIFFUSE_SOURCE_SHIFT 20

2498

# define RADEON_SPECULAR_SOURCE_SHIFT 22

2499

#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220

2500

#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224

2501

#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228

2502

#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c

2503

#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230

2504

#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234

2505

#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238

2506

#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c

2507

#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210

2508

#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214

2509

#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218

2510

#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c

2511

#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240

2512

#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244

2513

#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248

2514

#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c

2515

#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c

2516

# define RADEON_MODELVIEW_0_SHIFT 0

2517

# define RADEON_MODELVIEW_1_SHIFT 4

2518

# define RADEON_MODELVIEW_2_SHIFT 8

2519

# define RADEON_MODELVIEW_3_SHIFT 12

2520

# define RADEON_IT_MODELVIEW_0_SHIFT 16

2521

# define RADEON_IT_MODELVIEW_1_SHIFT 20

2522

# define RADEON_IT_MODELVIEW_2_SHIFT 24

2523

# define RADEON_IT_MODELVIEW_3_SHIFT 28

2524

#define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260

2525

# define RADEON_MODELPROJECT_0_SHIFT 0

2526

# define RADEON_MODELPROJECT_1_SHIFT 4

2527

# define RADEON_MODELPROJECT_2_SHIFT 8

2528

# define RADEON_MODELPROJECT_3_SHIFT 12

2529

# define RADEON_TEXMAT_0_SHIFT 16

2530

# define RADEON_TEXMAT_1_SHIFT 20

2531

# define RADEON_TEXMAT_2_SHIFT 24

2532

# define RADEON_TEXMAT_3_SHIFT 28

2533

2534

2535

#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254

2536

# define RADEON_TCL_VTX_W0 (1 << 0)

2537

# define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1)

2538

# define RADEON_TCL_VTX_FP_ALPHA (1 << 2)

2539

# define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3)

2540

# define RADEON_TCL_VTX_FP_SPEC (1 << 4)

2541

# define RADEON_TCL_VTX_FP_FOG (1 << 5)

2542

# define RADEON_TCL_VTX_PK_SPEC (1 << 6)

2543

# define RADEON_TCL_VTX_ST0 (1 << 7)

2544

# define RADEON_TCL_VTX_ST1 (1 << 8)

2545

# define RADEON_TCL_VTX_Q1 (1 << 9)

2546

# define RADEON_TCL_VTX_ST2 (1 << 10)

2547

# define RADEON_TCL_VTX_Q2 (1 << 11)

2548

# define RADEON_TCL_VTX_ST3 (1 << 12)

2549

# define RADEON_TCL_VTX_Q3 (1 << 13)

2550

# define RADEON_TCL_VTX_Q0 (1 << 14)

2551

# define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15

2552

# define RADEON_TCL_VTX_NORM0 (1 << 18)

2553

# define RADEON_TCL_VTX_XY1 (1 << 27)

2554

# define RADEON_TCL_VTX_Z1 (1 << 28)

2555

# define RADEON_TCL_VTX_W1 (1 << 29)

2556

# define RADEON_TCL_VTX_NORM1 (1 << 30)

2557

# define RADEON_TCL_VTX_Z0 (1 << 31)

2558

2559

#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258

2560

# define RADEON_TCL_COMPUTE_XYZW (1 << 0)

2561

# define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1)

2562

# define RADEON_TCL_COMPUTE_SPECULAR (1 << 2)

2563

# define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3)

2564

# define RADEON_TCL_FORCE_INORDER_PROC (1 << 4)

2565

# define RADEON_TCL_TEX_INPUT_TEX_0 0

2566

# define RADEON_TCL_TEX_INPUT_TEX_1 1

2567

# define RADEON_TCL_TEX_INPUT_TEX_2 2

2568

# define RADEON_TCL_TEX_INPUT_TEX_3 3

2569

# define RADEON_TCL_TEX_COMPUTED_TEX_0 8

2570

# define RADEON_TCL_TEX_COMPUTED_TEX_1 9

2571

# define RADEON_TCL_TEX_COMPUTED_TEX_2 10

2572

# define RADEON_TCL_TEX_COMPUTED_TEX_3 11

2573

# define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16

2574

# define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20

2575

# define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24

2576

# define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28

2577

2578

#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270

2579

# define RADEON_LIGHT_0_ENABLE (1 << 0)

2580

# define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1)

2581

# define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2)

2582

# define RADEON_LIGHT_0_IS_LOCAL (1 << 3)

2583

# define RADEON_LIGHT_0_IS_SPOT (1 << 4)

2584

# define RADEON_LIGHT_0_DUAL_CONE (1 << 5)

2585

# define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6)

2586

# define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7)

2587

# define RADEON_LIGHT_0_SHIFT 0

2588

# define RADEON_LIGHT_1_ENABLE (1 << 16)

2589

# define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17)

2590

# define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18)

2591

# define RADEON_LIGHT_1_IS_LOCAL (1 << 19)

2592

# define RADEON_LIGHT_1_IS_SPOT (1 << 20)

2593

# define RADEON_LIGHT_1_DUAL_CONE (1 << 21)

2594

# define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22)

2595

# define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23)

2596

# define RADEON_LIGHT_1_SHIFT 16

2597

#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274

2598

# define RADEON_LIGHT_2_SHIFT 0

2599

# define RADEON_LIGHT_3_SHIFT 16

2600

#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278

2601

# define RADEON_LIGHT_4_SHIFT 0

2602

# define RADEON_LIGHT_5_SHIFT 16

2603

#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c

2604

# define RADEON_LIGHT_6_SHIFT 0

2605

# define RADEON_LIGHT_7_SHIFT 16

2606

2607

#define RADEON_SE_TCL_SHININESS 0x2250

2608

2609

#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268

2610

# define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0)

2611

# define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1)

2612

# define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2)

2613

# define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3)

2614

# define RADEON_TEXMAT_0_ENABLE (1 << 4)

2615

# define RADEON_TEXMAT_1_ENABLE (1 << 5)

2616

# define RADEON_TEXMAT_2_ENABLE (1 << 6)

2617

# define RADEON_TEXMAT_3_ENABLE (1 << 7)

2618

# define RADEON_TEXGEN_INPUT_MASK 0xf

2619

# define RADEON_TEXGEN_INPUT_TEXCOORD_0 0

2620

# define RADEON_TEXGEN_INPUT_TEXCOORD_1 1

2621

# define RADEON_TEXGEN_INPUT_TEXCOORD_2 2

2622

# define RADEON_TEXGEN_INPUT_TEXCOORD_3 3

2623

# define RADEON_TEXGEN_INPUT_OBJ 4

2624

# define RADEON_TEXGEN_INPUT_EYE 5

2625

# define RADEON_TEXGEN_INPUT_EYE_NORMAL 6

2626

# define RADEON_TEXGEN_INPUT_EYE_REFLECT 7

2627

# define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8

2628

# define RADEON_TEXGEN_0_INPUT_SHIFT 16

2629

# define RADEON_TEXGEN_1_INPUT_SHIFT 20

2630

# define RADEON_TEXGEN_2_INPUT_SHIFT 24

2631

# define RADEON_TEXGEN_3_INPUT_SHIFT 28

2632

2633

#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264

2634

# define RADEON_UCP_IN_CLIP_SPACE (1 << 0)

2635

# define RADEON_UCP_IN_MODEL_SPACE (1 << 1)

2636

# define RADEON_UCP_ENABLE_0 (1 << 2)

2637

# define RADEON_UCP_ENABLE_1 (1 << 3)

2638

# define RADEON_UCP_ENABLE_2 (1 << 4)

2639

# define RADEON_UCP_ENABLE_3 (1 << 5)

2640

# define RADEON_UCP_ENABLE_4 (1 << 6)

2641

# define RADEON_UCP_ENABLE_5 (1 << 7)

2642

# define RADEON_TCL_FOG_MASK (3 << 8)

2643

# define RADEON_TCL_FOG_DISABLE (0 << 8)

2644

# define RADEON_TCL_FOG_EXP (1 << 8)

2645

# define RADEON_TCL_FOG_EXP2 (2 << 8)

2646

# define RADEON_TCL_FOG_LINEAR (3 << 8)

2647

# define RADEON_RNG_BASED_FOG (1 << 10)

2648

# define RADEON_LIGHT_TWOSIDE (1 << 11)

2649

# define RADEON_BLEND_OP_COUNT_MASK (7 << 12)

2650

# define RADEON_BLEND_OP_COUNT_SHIFT 12

2651

# define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16)

2652

# define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17)

2653

# define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18)

2654

# define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18)

2655

# define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19)

2656

# define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19)

2657

# define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20)

2658

# define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20)

2659

# define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21)

2660

# define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21)

2661

# define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22)

2662

# define RADEON_CULL_FRONT_IS_CW (0 << 28)

2663

# define RADEON_CULL_FRONT_IS_CCW (1 << 28)

2664

# define RADEON_CULL_FRONT (1 << 29)

2665

# define RADEON_CULL_BACK (1 << 30)

2666

# define RADEON_FORCE_W_TO_ONE (1 << 31)

2667

2668

#define RADEON_SE_VPORT_XSCALE 0x1d98

2669

#define RADEON_SE_VPORT_XOFFSET 0x1d9c

2670

#define RADEON_SE_VPORT_YSCALE 0x1da0

2671

#define RADEON_SE_VPORT_YOFFSET 0x1da4

2672

#define RADEON_SE_VPORT_ZSCALE 0x1da8

2673

#define RADEON_SE_VPORT_ZOFFSET 0x1dac

2674

#define RADEON_SE_ZBIAS_FACTOR 0x1db0

2675

#define RADEON_SE_ZBIAS_CONSTANT 0x1db4

2676

2677

#define RADEON_SE_VTX_FMT 0x2080

2678

# define RADEON_SE_VTX_FMT_XY 0x00000000

2679

# define RADEON_SE_VTX_FMT_W0 0x00000001

2680

# define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002

2681

# define RADEON_SE_VTX_FMT_FPALPHA 0x00000004

2682

# define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008

2683

# define RADEON_SE_VTX_FMT_FPSPEC 0x00000010

2684

# define RADEON_SE_VTX_FMT_FPFOG 0x00000020

2685

# define RADEON_SE_VTX_FMT_PKSPEC 0x00000040

2686

# define RADEON_SE_VTX_FMT_ST0 0x00000080

2687

# define RADEON_SE_VTX_FMT_ST1 0x00000100

2688

# define RADEON_SE_VTX_FMT_Q1 0x00000200

2689

# define RADEON_SE_VTX_FMT_ST2 0x00000400

2690

# define RADEON_SE_VTX_FMT_Q2 0x00000800

2691

# define RADEON_SE_VTX_FMT_ST3 0x00001000

2692

# define RADEON_SE_VTX_FMT_Q3 0x00002000

2693

# define RADEON_SE_VTX_FMT_Q0 0x00004000

2694

# define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000

2695

# define RADEON_SE_VTX_FMT_N0 0x00040000

2696

# define RADEON_SE_VTX_FMT_XY1 0x08000000

2697

# define RADEON_SE_VTX_FMT_Z1 0x10000000

2698

# define RADEON_SE_VTX_FMT_W1 0x20000000

2699

# define RADEON_SE_VTX_FMT_N1 0x40000000

2700

# define RADEON_SE_VTX_FMT_Z 0x80000000

2701

2702

#define RADEON_SE_VF_CNTL 0x2084

2703

# define RADEON_VF_PRIM_TYPE_POINT_LIST 1

2704

# define RADEON_VF_PRIM_TYPE_LINE_LIST 2

2705

# define RADEON_VF_PRIM_TYPE_LINE_STRIP 3

2706

# define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4

2707

# define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5

2708

# define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6

2709

# define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7

2710

# define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8

2711

# define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9

2712

# define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10

2713

# define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11

2714

# define RADEON_VF_PRIM_TYPE_LINE_LOOP 12

2715

# define RADEON_VF_PRIM_TYPE_QUAD_LIST 13

2716

# define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14

2717

# define RADEON_VF_PRIM_TYPE_POLYGON 15

2718

# define RADEON_VF_PRIM_WALK_STATE (0<<4)

2719

# define RADEON_VF_PRIM_WALK_INDEX (1<<4)

2720

# define RADEON_VF_PRIM_WALK_LIST (2<<4)

2721

# define RADEON_VF_PRIM_WALK_DATA (3<<4)

2722

# define RADEON_VF_COLOR_ORDER_RGBA (1<<6)

2723

# define RADEON_VF_RADEON_MODE (1<<8)

2724

# define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9)

2725

# define RADEON_VF_PROG_STREAM_ENA (1<<10)

2726

# define RADEON_VF_INDEX_SIZE_SHIFT 11

2727

# define RADEON_VF_NUM_VERTICES_SHIFT 16

2728

2729

#define RADEON_SE_PORT_DATA0 0x2000

2730

2731

#define R200_SE_VAP_CNTL 0x2080

2732

# define R200_VAP_TCL_ENABLE 0x00000001

2733

# define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010

2734

# define R200_VAP_FORCE_W_TO_ONE 0x00010000

2735

# define R200_VAP_D3D_TEX_DEFAULT 0x00020000

2736

# define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18

2737

# define R200_VAP_VF_MAX_VTX_NUM (9 << 18)

2738

# define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000

2739

#define R200_VF_MAX_VTX_INDX 0x210c

2740

#define R200_VF_MIN_VTX_INDX 0x2110

2741

#define R200_SE_VTE_CNTL 0x20b0

2742

# define R200_VPORT_X_SCALE_ENA 0x00000001

2743

# define R200_VPORT_X_OFFSET_ENA 0x00000002

2744

# define R200_VPORT_Y_SCALE_ENA 0x00000004

2745

# define R200_VPORT_Y_OFFSET_ENA 0x00000008

2746

# define R200_VPORT_Z_SCALE_ENA 0x00000010

2747

# define R200_VPORT_Z_OFFSET_ENA 0x00000020

2748

# define R200_VTX_XY_FMT 0x00000100

2749

# define R200_VTX_Z_FMT 0x00000200

2750

# define R200_VTX_W0_FMT 0x00000400

2751

# define R200_VTX_W0_NORMALIZE 0x00000800

2752

# define R200_VTX_ST_DENORMALIZED 0x00001000

2753

#define R200_SE_VAP_CNTL_STATUS 0x2140

2754

# define R200_VC_NO_SWAP (0 << 0)

2755

# define R200_VC_16BIT_SWAP (1 << 0)

2756

# define R200_VC_32BIT_SWAP (2 << 0)

2757

#define R200_PP_TXFILTER_0 0x2c00

2758

#define R200_PP_TXFILTER_1 0x2c20

2759

#define R200_PP_TXFILTER_2 0x2c40

2760

#define R200_PP_TXFILTER_3 0x2c60

2761

#define R200_PP_TXFILTER_4 0x2c80

2762

#define R200_PP_TXFILTER_5 0x2ca0

2763

# define R200_MAG_FILTER_NEAREST (0 << 0)

2764

# define R200_MAG_FILTER_LINEAR (1 << 0)

2765

# define R200_MAG_FILTER_MASK (1 << 0)

2766

# define R200_MIN_FILTER_NEAREST (0 << 1)

2767

# define R200_MIN_FILTER_LINEAR (1 << 1)

2768

# define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)

2769

# define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)

2770

# define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)

2771

# define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)

2772

# define R200_MIN_FILTER_ANISO_NEAREST (8 << 1)

2773

# define R200_MIN_FILTER_ANISO_LINEAR (9 << 1)

2774

# define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)

2775

# define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)

2776

# define R200_MIN_FILTER_MASK (15 << 1)

2777

# define R200_MAX_ANISO_1_TO_1 (0 << 5)

2778

# define R200_MAX_ANISO_2_TO_1 (1 << 5)

2779

# define R200_MAX_ANISO_4_TO_1 (2 << 5)

2780

# define R200_MAX_ANISO_8_TO_1 (3 << 5)

2781

# define R200_MAX_ANISO_16_TO_1 (4 << 5)

2782

# define R200_MAX_ANISO_MASK (7 << 5)

2783

# define R200_MAX_MIP_LEVEL_MASK (0x0f << 16)

2784

# define R200_MAX_MIP_LEVEL_SHIFT 16

2785

# define R200_YUV_TO_RGB (1 << 20)

2786

# define R200_YUV_TEMPERATURE_COOL (0 << 21)

2787

# define R200_YUV_TEMPERATURE_HOT (1 << 21)

2788

# define R200_YUV_TEMPERATURE_MASK (1 << 21)

2789

# define R200_WRAPEN_S (1 << 22)

2790

# define R200_CLAMP_S_WRAP (0 << 23)

2791

# define R200_CLAMP_S_MIRROR (1 << 23)

2792

# define R200_CLAMP_S_CLAMP_LAST (2 << 23)

2793

# define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)

2794

# define R200_CLAMP_S_CLAMP_BORDER (4 << 23)

2795

# define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)

2796

# define R200_CLAMP_S_CLAMP_GL (6 << 23)

2797

# define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)

2798

# define R200_CLAMP_S_MASK (7 << 23)

2799

# define R200_WRAPEN_T (1 << 26)

2800

# define R200_CLAMP_T_WRAP (0 << 27)

2801

# define R200_CLAMP_T_MIRROR (1 << 27)

2802

# define R200_CLAMP_T_CLAMP_LAST (2 << 27)

2803

# define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)

2804

# define R200_CLAMP_T_CLAMP_BORDER (4 << 27)

2805

# define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)

2806

# define R200_CLAMP_T_CLAMP_GL (6 << 27)

2807

# define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)

2808

# define R200_CLAMP_T_MASK (7 << 27)

2809

# define R200_KILL_LT_ZERO (1 << 30)

2810

# define R200_BORDER_MODE_OGL (0 << 31)

2811

# define R200_BORDER_MODE_D3D (1 << 31)

2812

#define R200_PP_TXFORMAT_0 0x2c04

2813

#define R200_PP_TXFORMAT_1 0x2c24

2814

#define R200_PP_TXFORMAT_2 0x2c44

2815

#define R200_PP_TXFORMAT_3 0x2c64

2816

#define R200_PP_TXFORMAT_4 0x2c84

2817

#define R200_PP_TXFORMAT_5 0x2ca4

2818

# define R200_TXFORMAT_I8 (0 << 0)

2819

# define R200_TXFORMAT_AI88 (1 << 0)

2820

# define R200_TXFORMAT_RGB332 (2 << 0)

2821

# define R200_TXFORMAT_ARGB1555 (3 << 0)

2822

# define R200_TXFORMAT_RGB565 (4 << 0)

2823

# define R200_TXFORMAT_ARGB4444 (5 << 0)

2824

# define R200_TXFORMAT_ARGB8888 (6 << 0)

2825

# define R200_TXFORMAT_RGBA8888 (7 << 0)

2826

# define R200_TXFORMAT_Y8 (8 << 0)

2827

# define R200_TXFORMAT_AVYU4444 (9 << 0)

2828

# define R200_TXFORMAT_VYUY422 (10 << 0)

2829

# define R200_TXFORMAT_YVYU422 (11 << 0)

2830

# define R200_TXFORMAT_DXT1 (12 << 0)

2831

# define R200_TXFORMAT_DXT23 (14 << 0)

2832

# define R200_TXFORMAT_DXT45 (15 << 0)

Dave Airlie

2009-09-01 15:25:57 +1000

[diff] [blame]

2833

# define R200_TXFORMAT_DVDU88 (18 << 0)

2834

# define R200_TXFORMAT_LDVDU655 (19 << 0)

2835

# define R200_TXFORMAT_LDVDU8888 (20 << 0)

2836

# define R200_TXFORMAT_GR1616 (21 << 0)

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

2837

# define R200_TXFORMAT_ABGR8888 (22 << 0)

Dave Airlie

2009-09-01 15:25:57 +1000

[diff] [blame]

2838

# define R200_TXFORMAT_BGR111110 (23 << 0)

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

2839

# define R200_TXFORMAT_FORMAT_MASK (31 << 0)

2840

# define R200_TXFORMAT_FORMAT_SHIFT 0

2841

# define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6)

2842

# define R200_TXFORMAT_NON_POWER2 (1 << 7)

2843

# define R200_TXFORMAT_WIDTH_MASK (15 << 8)

2844

# define R200_TXFORMAT_WIDTH_SHIFT 8

2845

# define R200_TXFORMAT_HEIGHT_MASK (15 << 12)

2846

# define R200_TXFORMAT_HEIGHT_SHIFT 12

2847

# define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */

2848

# define R200_TXFORMAT_F5_WIDTH_SHIFT 16

2849

# define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20)

2850

# define R200_TXFORMAT_F5_HEIGHT_SHIFT 20

2851

# define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)

2852

# define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)

2853

# define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)

2854

# define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24)

2855

# define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24)

2856

# define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24)

2857

# define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24)

2858

# define R200_TXFORMAT_ST_ROUTE_SHIFT 24

Alex Deucher

43b93fb

2010-10-27 01:02:35 -0400

[diff] [blame]

2859

# define R200_TXFORMAT_LOOKUP_DISABLE (1 << 27)

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

2860

# define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)

2861

# define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)

2862

# define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)

2863

#define R200_PP_TXFORMAT_X_0 0x2c08

2864

#define R200_PP_TXFORMAT_X_1 0x2c28

2865

#define R200_PP_TXFORMAT_X_2 0x2c48

2866

#define R200_PP_TXFORMAT_X_3 0x2c68

2867

#define R200_PP_TXFORMAT_X_4 0x2c88

2868

#define R200_PP_TXFORMAT_X_5 0x2ca8

2869

2870

#define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */

2871

#define R200_PP_TXSIZE_1 0x2c2c /* NPOT only */

2872

#define R200_PP_TXSIZE_2 0x2c4c /* NPOT only */

2873

#define R200_PP_TXSIZE_3 0x2c6c /* NPOT only */

2874

#define R200_PP_TXSIZE_4 0x2c8c /* NPOT only */

2875

#define R200_PP_TXSIZE_5 0x2cac /* NPOT only */

2876

2877

#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */

2878

#define R200_PP_TXPITCH_1 0x2c30 /* NPOT only */

2879

#define R200_PP_TXPITCH_2 0x2c50 /* NPOT only */

2880

#define R200_PP_TXPITCH_3 0x2c70 /* NPOT only */

2881

#define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */

2882

#define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */

2883

Dave Airlie

2009-09-01 15:25:57 +1000

[diff] [blame]

2884

#define R200_PP_CUBIC_FACES_0 0x2c18

2885

#define R200_PP_CUBIC_FACES_1 0x2c38

2886

#define R200_PP_CUBIC_FACES_2 0x2c58

2887

#define R200_PP_CUBIC_FACES_3 0x2c78

2888

#define R200_PP_CUBIC_FACES_4 0x2c98

2889

#define R200_PP_CUBIC_FACES_5 0x2cb8

2890

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

2891

#define R200_PP_TXOFFSET_0 0x2d00

2892

# define R200_TXO_ENDIAN_NO_SWAP (0 << 0)

2893

# define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0)

2894

# define R200_TXO_ENDIAN_WORD_SWAP (2 << 0)

2895

# define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0)

2896

# define R200_TXO_MACRO_LINEAR (0 << 2)

2897

# define R200_TXO_MACRO_TILE (1 << 2)

2898

# define R200_TXO_MICRO_LINEAR (0 << 3)

2899

# define R200_TXO_MICRO_TILE (1 << 3)

2900

# define R200_TXO_OFFSET_MASK 0xffffffe0

2901

# define R200_TXO_OFFSET_SHIFT 5

Dave Airlie

2009-09-01 15:25:57 +1000

[diff] [blame]

2902

#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04

2903

#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08

2904

#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c

2905

#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10

2906

#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14

2907

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

2908

#define R200_PP_TXOFFSET_1 0x2d18

Dave Airlie

2009-09-01 15:25:57 +1000

[diff] [blame]

2909

#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c

2910

#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20

2911

#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24

2912

#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28

2913

#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c

2914

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

2915

#define R200_PP_TXOFFSET_2 0x2d30

Dave Airlie

2009-09-01 15:25:57 +1000

[diff] [blame]

2916

#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34

2917

#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38

2918

#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c

2919

#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40

2920

#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44

2921

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

2922

#define R200_PP_TXOFFSET_3 0x2d48

Dave Airlie

2009-09-01 15:25:57 +1000

[diff] [blame]

2923

#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c

2924

#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50

2925

#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54

2926

#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58

2927

#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

2928

#define R200_PP_TXOFFSET_4 0x2d60

Dave Airlie

2009-09-01 15:25:57 +1000

[diff] [blame]

2929

#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64

2930

#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68

2931

#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c

2932

#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70

2933

#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

2934

#define R200_PP_TXOFFSET_5 0x2d78

Dave Airlie

2009-09-01 15:25:57 +1000

[diff] [blame]

2935

#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c

2936

#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80

2937

#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84

2938

#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88

2939

#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

2940

2941

#define R200_PP_TFACTOR_0 0x2ee0

2942

#define R200_PP_TFACTOR_1 0x2ee4

2943

#define R200_PP_TFACTOR_2 0x2ee8

2944

#define R200_PP_TFACTOR_3 0x2eec

2945

#define R200_PP_TFACTOR_4 0x2ef0

2946

#define R200_PP_TFACTOR_5 0x2ef4

2947

2948

#define R200_PP_TXCBLEND_0 0x2f00

2949

# define R200_TXC_ARG_A_ZERO (0)

2950

# define R200_TXC_ARG_A_CURRENT_COLOR (2)

2951

# define R200_TXC_ARG_A_CURRENT_ALPHA (3)

2952

# define R200_TXC_ARG_A_DIFFUSE_COLOR (4)

2953

# define R200_TXC_ARG_A_DIFFUSE_ALPHA (5)

2954

# define R200_TXC_ARG_A_SPECULAR_COLOR (6)

2955

# define R200_TXC_ARG_A_SPECULAR_ALPHA (7)

2956

# define R200_TXC_ARG_A_TFACTOR_COLOR (8)

2957

# define R200_TXC_ARG_A_TFACTOR_ALPHA (9)

2958

# define R200_TXC_ARG_A_R0_COLOR (10)

2959

# define R200_TXC_ARG_A_R0_ALPHA (11)

2960

# define R200_TXC_ARG_A_R1_COLOR (12)

2961

# define R200_TXC_ARG_A_R1_ALPHA (13)

2962

# define R200_TXC_ARG_A_R2_COLOR (14)

2963

# define R200_TXC_ARG_A_R2_ALPHA (15)

2964

# define R200_TXC_ARG_A_R3_COLOR (16)

2965

# define R200_TXC_ARG_A_R3_ALPHA (17)

2966

# define R200_TXC_ARG_A_R4_COLOR (18)

2967

# define R200_TXC_ARG_A_R4_ALPHA (19)

2968

# define R200_TXC_ARG_A_R5_COLOR (20)

2969

# define R200_TXC_ARG_A_R5_ALPHA (21)

2970

# define R200_TXC_ARG_A_TFACTOR1_COLOR (26)

2971

# define R200_TXC_ARG_A_TFACTOR1_ALPHA (27)

2972

# define R200_TXC_ARG_A_MASK (31 << 0)

2973

# define R200_TXC_ARG_A_SHIFT 0

2974

# define R200_TXC_ARG_B_ZERO (0 << 5)

2975

# define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5)

2976

# define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5)

2977

# define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5)

2978

# define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5)

2979

# define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5)

2980

# define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5)

2981

# define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5)

2982

# define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5)

2983

# define R200_TXC_ARG_B_R0_COLOR (10 << 5)

2984

# define R200_TXC_ARG_B_R0_ALPHA (11 << 5)

2985

# define R200_TXC_ARG_B_R1_COLOR (12 << 5)

2986

# define R200_TXC_ARG_B_R1_ALPHA (13 << 5)

2987

# define R200_TXC_ARG_B_R2_COLOR (14 << 5)

2988

# define R200_TXC_ARG_B_R2_ALPHA (15 << 5)

2989

# define R200_TXC_ARG_B_R3_COLOR (16 << 5)

2990

# define R200_TXC_ARG_B_R3_ALPHA (17 << 5)

2991

# define R200_TXC_ARG_B_R4_COLOR (18 << 5)

2992

# define R200_TXC_ARG_B_R4_ALPHA (19 << 5)

2993

# define R200_TXC_ARG_B_R5_COLOR (20 << 5)

2994

# define R200_TXC_ARG_B_R5_ALPHA (21 << 5)

2995

# define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5)

2996

# define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5)

2997

# define R200_TXC_ARG_B_MASK (31 << 5)

2998

# define R200_TXC_ARG_B_SHIFT 5

2999

# define R200_TXC_ARG_C_ZERO (0 << 10)

3000

# define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10)

3001

# define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10)

3002

# define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10)

3003

# define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10)

3004

# define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10)

3005

# define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10)

3006

# define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10)

3007

# define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10)

3008

# define R200_TXC_ARG_C_R0_COLOR (10 << 10)

3009

# define R200_TXC_ARG_C_R0_ALPHA (11 << 10)

3010

# define R200_TXC_ARG_C_R1_COLOR (12 << 10)

3011

# define R200_TXC_ARG_C_R1_ALPHA (13 << 10)

3012

# define R200_TXC_ARG_C_R2_COLOR (14 << 10)

3013

# define R200_TXC_ARG_C_R2_ALPHA (15 << 10)

3014

# define R200_TXC_ARG_C_R3_COLOR (16 << 10)

3015

# define R200_TXC_ARG_C_R3_ALPHA (17 << 10)

3016

# define R200_TXC_ARG_C_R4_COLOR (18 << 10)

3017

# define R200_TXC_ARG_C_R4_ALPHA (19 << 10)

3018

# define R200_TXC_ARG_C_R5_COLOR (20 << 10)

3019

# define R200_TXC_ARG_C_R5_ALPHA (21 << 10)

3020

# define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10)

3021

# define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10)

3022

# define R200_TXC_ARG_C_MASK (31 << 10)

3023

# define R200_TXC_ARG_C_SHIFT 10

3024

# define R200_TXC_COMP_ARG_A (1 << 16)

3025

# define R200_TXC_COMP_ARG_A_SHIFT (16)

3026

# define R200_TXC_BIAS_ARG_A (1 << 17)

3027

# define R200_TXC_SCALE_ARG_A (1 << 18)

3028

# define R200_TXC_NEG_ARG_A (1 << 19)

3029

# define R200_TXC_COMP_ARG_B (1 << 20)

3030

# define R200_TXC_COMP_ARG_B_SHIFT (20)

3031

# define R200_TXC_BIAS_ARG_B (1 << 21)

3032

# define R200_TXC_SCALE_ARG_B (1 << 22)

3033

# define R200_TXC_NEG_ARG_B (1 << 23)

3034

# define R200_TXC_COMP_ARG_C (1 << 24)

3035

# define R200_TXC_COMP_ARG_C_SHIFT (24)

3036

# define R200_TXC_BIAS_ARG_C (1 << 25)

3037

# define R200_TXC_SCALE_ARG_C (1 << 26)

3038

# define R200_TXC_NEG_ARG_C (1 << 27)

3039

# define R200_TXC_OP_MADD (0 << 28)

3040

# define R200_TXC_OP_CND0 (2 << 28)

3041

# define R200_TXC_OP_LERP (3 << 28)

3042

# define R200_TXC_OP_DOT3 (4 << 28)

3043

# define R200_TXC_OP_DOT4 (5 << 28)

3044

# define R200_TXC_OP_CONDITIONAL (6 << 28)

3045

# define R200_TXC_OP_DOT2_ADD (7 << 28)

3046

# define R200_TXC_OP_MASK (7 << 28)

3047

#define R200_PP_TXCBLEND2_0 0x2f04

3048

# define R200_TXC_TFACTOR_SEL_SHIFT 0

3049

# define R200_TXC_TFACTOR_SEL_MASK 0x7

3050

# define R200_TXC_TFACTOR1_SEL_SHIFT 4

3051

# define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4)

3052

# define R200_TXC_SCALE_SHIFT 8

3053

# define R200_TXC_SCALE_MASK (7 << 8)

3054

# define R200_TXC_SCALE_1X (0 << 8)

3055

# define R200_TXC_SCALE_2X (1 << 8)

3056

# define R200_TXC_SCALE_4X (2 << 8)

3057

# define R200_TXC_SCALE_8X (3 << 8)

3058

# define R200_TXC_SCALE_INV2 (5 << 8)

3059

# define R200_TXC_SCALE_INV4 (6 << 8)

3060

# define R200_TXC_SCALE_INV8 (7 << 8)

3061

# define R200_TXC_CLAMP_SHIFT 12

3062

# define R200_TXC_CLAMP_MASK (3 << 12)

3063

# define R200_TXC_CLAMP_WRAP (0 << 12)

3064

# define R200_TXC_CLAMP_0_1 (1 << 12)

3065

# define R200_TXC_CLAMP_8_8 (2 << 12)

3066

# define R200_TXC_OUTPUT_REG_MASK (7 << 16)

3067

# define R200_TXC_OUTPUT_REG_NONE (0 << 16)

3068

# define R200_TXC_OUTPUT_REG_R0 (1 << 16)

3069

# define R200_TXC_OUTPUT_REG_R1 (2 << 16)

3070

# define R200_TXC_OUTPUT_REG_R2 (3 << 16)

3071

# define R200_TXC_OUTPUT_REG_R3 (4 << 16)

3072

# define R200_TXC_OUTPUT_REG_R4 (5 << 16)

3073

# define R200_TXC_OUTPUT_REG_R5 (6 << 16)

3074

# define R200_TXC_OUTPUT_MASK_MASK (7 << 20)

3075

# define R200_TXC_OUTPUT_MASK_RGB (0 << 20)

3076

# define R200_TXC_OUTPUT_MASK_RG (1 << 20)

3077

# define R200_TXC_OUTPUT_MASK_RB (2 << 20)

3078

# define R200_TXC_OUTPUT_MASK_R (3 << 20)

3079

# define R200_TXC_OUTPUT_MASK_GB (4 << 20)

3080

# define R200_TXC_OUTPUT_MASK_G (5 << 20)

3081

# define R200_TXC_OUTPUT_MASK_B (6 << 20)

3082

# define R200_TXC_OUTPUT_MASK_NONE (7 << 20)

3083

# define R200_TXC_REPL_NORMAL 0

3084

# define R200_TXC_REPL_RED 1

3085

# define R200_TXC_REPL_GREEN 2

3086

# define R200_TXC_REPL_BLUE 3

3087

# define R200_TXC_REPL_ARG_A_SHIFT 26

3088

# define R200_TXC_REPL_ARG_A_MASK (3 << 26)

3089

# define R200_TXC_REPL_ARG_B_SHIFT 28

3090

# define R200_TXC_REPL_ARG_B_MASK (3 << 28)

3091

# define R200_TXC_REPL_ARG_C_SHIFT 30

3092

# define R200_TXC_REPL_ARG_C_MASK (3 << 30)

3093

#define R200_PP_TXABLEND_0 0x2f08

3094

# define R200_TXA_ARG_A_ZERO (0)

3095

# define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */

3096

# define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */

3097

# define R200_TXA_ARG_A_DIFFUSE_ALPHA (4)

3098

# define R200_TXA_ARG_A_DIFFUSE_BLUE (5)

3099

# define R200_TXA_ARG_A_SPECULAR_ALPHA (6)

3100

# define R200_TXA_ARG_A_SPECULAR_BLUE (7)

3101

# define R200_TXA_ARG_A_TFACTOR_ALPHA (8)

3102

# define R200_TXA_ARG_A_TFACTOR_BLUE (9)

3103

# define R200_TXA_ARG_A_R0_ALPHA (10)

3104

# define R200_TXA_ARG_A_R0_BLUE (11)

3105

# define R200_TXA_ARG_A_R1_ALPHA (12)

3106

# define R200_TXA_ARG_A_R1_BLUE (13)

3107

# define R200_TXA_ARG_A_R2_ALPHA (14)

3108

# define R200_TXA_ARG_A_R2_BLUE (15)

3109

# define R200_TXA_ARG_A_R3_ALPHA (16)

3110

# define R200_TXA_ARG_A_R3_BLUE (17)

3111

# define R200_TXA_ARG_A_R4_ALPHA (18)

3112

# define R200_TXA_ARG_A_R4_BLUE (19)

3113

# define R200_TXA_ARG_A_R5_ALPHA (20)

3114

# define R200_TXA_ARG_A_R5_BLUE (21)

3115

# define R200_TXA_ARG_A_TFACTOR1_ALPHA (26)

3116

# define R200_TXA_ARG_A_TFACTOR1_BLUE (27)

3117

# define R200_TXA_ARG_A_MASK (31 << 0)

3118

# define R200_TXA_ARG_A_SHIFT 0

3119

# define R200_TXA_ARG_B_ZERO (0 << 5)

3120

# define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */

3121

# define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */

3122

# define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5)

3123

# define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5)

3124

# define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5)

3125

# define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5)

3126

# define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5)

3127

# define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5)

3128

# define R200_TXA_ARG_B_R0_ALPHA (10 << 5)

3129

# define R200_TXA_ARG_B_R0_BLUE (11 << 5)

3130

# define R200_TXA_ARG_B_R1_ALPHA (12 << 5)

3131

# define R200_TXA_ARG_B_R1_BLUE (13 << 5)

3132

# define R200_TXA_ARG_B_R2_ALPHA (14 << 5)

3133

# define R200_TXA_ARG_B_R2_BLUE (15 << 5)

3134

# define R200_TXA_ARG_B_R3_ALPHA (16 << 5)

3135

# define R200_TXA_ARG_B_R3_BLUE (17 << 5)

3136

# define R200_TXA_ARG_B_R4_ALPHA (18 << 5)

3137

# define R200_TXA_ARG_B_R4_BLUE (19 << 5)

3138

# define R200_TXA_ARG_B_R5_ALPHA (20 << 5)

3139

# define R200_TXA_ARG_B_R5_BLUE (21 << 5)

3140

# define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5)

3141

# define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5)

3142

# define R200_TXA_ARG_B_MASK (31 << 5)

3143

# define R200_TXA_ARG_B_SHIFT 5

3144

# define R200_TXA_ARG_C_ZERO (0 << 10)

3145

# define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */

3146

# define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */

3147

# define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10)

3148

# define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10)

3149

# define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10)

3150

# define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10)

3151

# define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10)

3152

# define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10)

3153

# define R200_TXA_ARG_C_R0_ALPHA (10 << 10)

3154

# define R200_TXA_ARG_C_R0_BLUE (11 << 10)

3155

# define R200_TXA_ARG_C_R1_ALPHA (12 << 10)

3156

# define R200_TXA_ARG_C_R1_BLUE (13 << 10)

3157

# define R200_TXA_ARG_C_R2_ALPHA (14 << 10)

3158

# define R200_TXA_ARG_C_R2_BLUE (15 << 10)

3159

# define R200_TXA_ARG_C_R3_ALPHA (16 << 10)

3160

# define R200_TXA_ARG_C_R3_BLUE (17 << 10)

3161

# define R200_TXA_ARG_C_R4_ALPHA (18 << 10)

3162

# define R200_TXA_ARG_C_R4_BLUE (19 << 10)

3163

# define R200_TXA_ARG_C_R5_ALPHA (20 << 10)

3164

# define R200_TXA_ARG_C_R5_BLUE (21 << 10)

3165

# define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10)

3166

# define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10)

3167

# define R200_TXA_ARG_C_MASK (31 << 10)

3168

# define R200_TXA_ARG_C_SHIFT 10

3169

# define R200_TXA_COMP_ARG_A (1 << 16)

3170

# define R200_TXA_COMP_ARG_A_SHIFT (16)

3171

# define R200_TXA_BIAS_ARG_A (1 << 17)

3172

# define R200_TXA_SCALE_ARG_A (1 << 18)

3173

# define R200_TXA_NEG_ARG_A (1 << 19)

3174

# define R200_TXA_COMP_ARG_B (1 << 20)

3175

# define R200_TXA_COMP_ARG_B_SHIFT (20)

3176

# define R200_TXA_BIAS_ARG_B (1 << 21)

3177

# define R200_TXA_SCALE_ARG_B (1 << 22)

3178

# define R200_TXA_NEG_ARG_B (1 << 23)

3179

# define R200_TXA_COMP_ARG_C (1 << 24)

3180

# define R200_TXA_COMP_ARG_C_SHIFT (24)

3181

# define R200_TXA_BIAS_ARG_C (1 << 25)

3182

# define R200_TXA_SCALE_ARG_C (1 << 26)

3183

# define R200_TXA_NEG_ARG_C (1 << 27)

3184

# define R200_TXA_OP_MADD (0 << 28)

3185

# define R200_TXA_OP_CND0 (2 << 28)

3186

# define R200_TXA_OP_LERP (3 << 28)

3187

# define R200_TXA_OP_CONDITIONAL (6 << 28)

3188

# define R200_TXA_OP_MASK (7 << 28)

3189

#define R200_PP_TXABLEND2_0 0x2f0c

3190

# define R200_TXA_TFACTOR_SEL_SHIFT 0

3191

# define R200_TXA_TFACTOR_SEL_MASK 0x7

3192

# define R200_TXA_TFACTOR1_SEL_SHIFT 4

3193

# define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4)

3194

# define R200_TXA_SCALE_SHIFT 8

3195

# define R200_TXA_SCALE_MASK (7 << 8)

3196

# define R200_TXA_SCALE_1X (0 << 8)

3197

# define R200_TXA_SCALE_2X (1 << 8)

3198

# define R200_TXA_SCALE_4X (2 << 8)

3199

# define R200_TXA_SCALE_8X (3 << 8)

3200

# define R200_TXA_SCALE_INV2 (5 << 8)

3201

# define R200_TXA_SCALE_INV4 (6 << 8)

3202

# define R200_TXA_SCALE_INV8 (7 << 8)

3203

# define R200_TXA_CLAMP_SHIFT 12

3204

# define R200_TXA_CLAMP_MASK (3 << 12)

3205

# define R200_TXA_CLAMP_WRAP (0 << 12)

3206

# define R200_TXA_CLAMP_0_1 (1 << 12)

3207

# define R200_TXA_CLAMP_8_8 (2 << 12)

3208

# define R200_TXA_OUTPUT_REG_MASK (7 << 16)

3209

# define R200_TXA_OUTPUT_REG_NONE (0 << 16)

3210

# define R200_TXA_OUTPUT_REG_R0 (1 << 16)

3211

# define R200_TXA_OUTPUT_REG_R1 (2 << 16)

3212

# define R200_TXA_OUTPUT_REG_R2 (3 << 16)

3213

# define R200_TXA_OUTPUT_REG_R3 (4 << 16)

3214

# define R200_TXA_OUTPUT_REG_R4 (5 << 16)

3215

# define R200_TXA_OUTPUT_REG_R5 (6 << 16)

3216

# define R200_TXA_DOT_ALPHA (1 << 20)

3217

# define R200_TXA_REPL_NORMAL 0

3218

# define R200_TXA_REPL_RED 1

3219

# define R200_TXA_REPL_GREEN 2

3220

# define R200_TXA_REPL_ARG_A_SHIFT 26

3221

# define R200_TXA_REPL_ARG_A_MASK (3 << 26)

3222

# define R200_TXA_REPL_ARG_B_SHIFT 28

3223

# define R200_TXA_REPL_ARG_B_MASK (3 << 28)

3224

# define R200_TXA_REPL_ARG_C_SHIFT 30

3225

# define R200_TXA_REPL_ARG_C_MASK (3 << 30)

3226

3227

#define R200_SE_VTX_FMT_0 0x2088

3228

# define R200_VTX_XY 0 /* always have xy */

3229

# define R200_VTX_Z0 (1<<0)

3230

# define R200_VTX_W0 (1<<1)

3231

# define R200_VTX_WEIGHT_COUNT_SHIFT (2)

3232

# define R200_VTX_PV_MATRIX_SEL (1<<5)

3233

# define R200_VTX_N0 (1<<6)

3234

# define R200_VTX_POINT_SIZE (1<<7)

3235

# define R200_VTX_DISCRETE_FOG (1<<8)

3236

# define R200_VTX_SHININESS_0 (1<<9)

3237

# define R200_VTX_SHININESS_1 (1<<10)

3238

# define R200_VTX_COLOR_NOT_PRESENT 0

3239

# define R200_VTX_PK_RGBA 1

3240

# define R200_VTX_FP_RGB 2

3241

# define R200_VTX_FP_RGBA 3

3242

# define R200_VTX_COLOR_MASK 3

3243

# define R200_VTX_COLOR_0_SHIFT 11

3244

# define R200_VTX_COLOR_1_SHIFT 13

3245

# define R200_VTX_COLOR_2_SHIFT 15

3246

# define R200_VTX_COLOR_3_SHIFT 17

3247

# define R200_VTX_COLOR_4_SHIFT 19

3248

# define R200_VTX_COLOR_5_SHIFT 21

3249

# define R200_VTX_COLOR_6_SHIFT 23

3250

# define R200_VTX_COLOR_7_SHIFT 25

3251

# define R200_VTX_XY1 (1<<28)

3252

# define R200_VTX_Z1 (1<<29)

3253

# define R200_VTX_W1 (1<<30)

3254

# define R200_VTX_N1 (1<<31)

3255

#define R200_SE_VTX_FMT_1 0x208c

3256

# define R200_VTX_TEX0_COMP_CNT_SHIFT 0

3257

# define R200_VTX_TEX1_COMP_CNT_SHIFT 3

3258

# define R200_VTX_TEX2_COMP_CNT_SHIFT 6

3259

# define R200_VTX_TEX3_COMP_CNT_SHIFT 9

3260

# define R200_VTX_TEX4_COMP_CNT_SHIFT 12

3261

# define R200_VTX_TEX5_COMP_CNT_SHIFT 15

3262

3263

#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090

3264

#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094

3265

#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250

3266

# define R200_OUTPUT_XYZW (1<<0)

3267

# define R200_OUTPUT_COLOR_0 (1<<8)

3268

# define R200_OUTPUT_COLOR_1 (1<<9)

3269

# define R200_OUTPUT_TEX_0 (1<<16)

3270

# define R200_OUTPUT_TEX_1 (1<<17)

3271

# define R200_OUTPUT_TEX_2 (1<<18)

3272

# define R200_OUTPUT_TEX_3 (1<<19)

3273

# define R200_OUTPUT_TEX_4 (1<<20)

3274

# define R200_OUTPUT_TEX_5 (1<<21)

3275

# define R200_OUTPUT_TEX_MASK (0x3f<<16)

3276

# define R200_OUTPUT_DISCRETE_FOG (1<<24)

3277

# define R200_OUTPUT_PT_SIZE (1<<25)

3278

# define R200_FORCE_INORDER_PROC (1<<31)

3279

#define R200_PP_CNTL_X 0x2cc4

3280

#define R200_PP_TXMULTI_CTL_0 0x2c1c

Dave Airlie

2009-09-01 15:25:57 +1000

[diff] [blame]

3281

#define R200_PP_TXMULTI_CTL_1 0x2c3c

3282

#define R200_PP_TXMULTI_CTL_2 0x2c5c

3283

#define R200_PP_TXMULTI_CTL_3 0x2c7c

3284

#define R200_PP_TXMULTI_CTL_4 0x2c9c

3285

#define R200_PP_TXMULTI_CTL_5 0x2cbc

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

3286

#define R200_SE_VTX_STATE_CNTL 0x2180

3287

# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16)

3288

3289

/* Registers for CP and Microcode Engine */

3290

#define RADEON_CP_ME_RAM_ADDR 0x07d4

3291

#define RADEON_CP_ME_RAM_RADDR 0x07d8

3292

#define RADEON_CP_ME_RAM_DATAH 0x07dc

3293

#define RADEON_CP_ME_RAM_DATAL 0x07e0

3294

3295

#define RADEON_CP_RB_BASE 0x0700

3296

#define RADEON_CP_RB_CNTL 0x0704

3297

# define RADEON_RB_BUFSZ_SHIFT 0

3298

# define RADEON_RB_BUFSZ_MASK (0x3f << 0)

3299

# define RADEON_RB_BLKSZ_SHIFT 8

3300

# define RADEON_RB_BLKSZ_MASK (0x3f << 8)

Benjamin Herrenschmidt

edc02bf

2011-07-13 06:28:26 +0000

[diff] [blame]

3301

# define RADEON_BUF_SWAP_32BIT (2 << 16)

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

3302

# define RADEON_MAX_FETCH_SHIFT 18

3303

# define RADEON_MAX_FETCH_MASK (0x3 << 18)

3304

# define RADEON_RB_NO_UPDATE (1 << 27)

3305

# define RADEON_RB_RPTR_WR_ENA (1 << 31)

3306

#define RADEON_CP_RB_RPTR_ADDR 0x070c

3307

#define RADEON_CP_RB_RPTR 0x0710

3308

#define RADEON_CP_RB_WPTR 0x0714

3309

#define RADEON_CP_RB_RPTR_WR 0x071c

3310

Jerome Glisse

3ce0a23

2009-09-08 10:10:24 +1000

[diff] [blame]

3311

#define RADEON_SCRATCH_UMSK 0x0770

3312

#define RADEON_SCRATCH_ADDR 0x0774

3313

3314

#define R600_CP_RB_BASE 0xc100

3315

#define R600_CP_RB_CNTL 0xc104

3316

# define R600_RB_BUFSZ(x) ((x) << 0)

3317

# define R600_RB_BLKSZ(x) ((x) << 8)

3318

# define R600_RB_NO_UPDATE (1 << 27)

3319

# define R600_RB_RPTR_WR_ENA (1 << 31)

3320

#define R600_CP_RB_RPTR_WR 0xc108

3321

#define R600_CP_RB_RPTR_ADDR 0xc10c

3322

#define R600_CP_RB_RPTR_ADDR_HI 0xc110

3323

#define R600_CP_RB_WPTR 0xc114

3324

#define R600_CP_RB_WPTR_ADDR 0xc118

3325

#define R600_CP_RB_WPTR_ADDR_HI 0xc11c

3326

#define R600_CP_RB_RPTR 0x8700

3327

#define R600_CP_RB_WPTR_DELAY 0x8704

3328

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

3329

#define RADEON_CP_IB_BASE 0x0738

3330

#define RADEON_CP_IB_BUFSZ 0x073c

3331

3332

#define RADEON_CP_CSQ_CNTL 0x0740

3333

# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)

3334

# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)

3335

# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)

3336

# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)

3337

# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)

3338

# define RADEON_CSQ_PRIBM_INDBM (4 << 28)

3339

# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)

3340

3341

#define R300_CP_RESYNC_ADDR 0x778

3342

#define R300_CP_RESYNC_DATA 0x77c

3343

3344

#define RADEON_CP_CSQ_STAT 0x07f8

3345

# define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0)

3346

# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8)

3347

# define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16)

3348

# define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24)

3349

#define RADEON_CP_CSQ2_STAT 0x07fc

3350

#define RADEON_CP_CSQ_ADDR 0x07f0

3351

#define RADEON_CP_CSQ_DATA 0x07f4

3352

#define RADEON_CP_CSQ_APER_PRIMARY 0x1000

3353

#define RADEON_CP_CSQ_APER_INDIRECT 0x1300

3354

3355

#define RADEON_CP_RB_WPTR_DELAY 0x0718

3356

# define RADEON_PRE_WRITE_TIMER_SHIFT 0

3357

# define RADEON_PRE_WRITE_LIMIT_SHIFT 23

3358

#define RADEON_CP_CSQ_MODE 0x0744

3359

# define RADEON_INDIRECT2_START_SHIFT 0

3360

# define RADEON_INDIRECT2_START_MASK (0x7f << 0)

3361

# define RADEON_INDIRECT1_START_SHIFT 8

3362

# define RADEON_INDIRECT1_START_MASK (0x7f << 8)

3363

3364

#define RADEON_AIC_CNTL 0x01d0

3365

# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)

3366

# define RADEON_DIS_OUT_OF_PCI_GART_ACCESS (1 << 1)

Alex Deucher

3e5cb98

2009-10-16 12:21:24 -0400

[diff] [blame]

3367

# define RS400_MSI_REARM (1 << 3) /* rs400/rs480 */

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

3368

#define RADEON_AIC_LO_ADDR 0x01dc

3369

#define RADEON_AIC_PT_BASE 0x01d8

3370

#define RADEON_AIC_HI_ADDR 0x01e0

/* Constants */

/* #define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 */

3376

/* efine RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 */

/* CP packet types */

3381

#define RADEON_CP_PACKET0 0x00000000

3382

#define RADEON_CP_PACKET1 0x40000000

3383

#define RADEON_CP_PACKET2 0x80000000

3384

#define RADEON_CP_PACKET3 0xC0000000

3385

# define RADEON_CP_PACKET_MASK 0xC0000000

3386

# define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000

3387

# define RADEON_CP_PACKET_MAX_DWORDS (1 << 12)

3388

# define RADEON_CP_PACKET0_REG_MASK 0x000007ff

3389

# define R300_CP_PACKET0_REG_MASK 0x00001fff

Alex Deucher

2f67c6e

2009-09-25 16:35:11 -0400

[diff] [blame]

3390

# define R600_CP_PACKET0_REG_MASK 0x0000ffff

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

3391

# define RADEON_CP_PACKET1_REG0_MASK 0x000007ff

3392

# define RADEON_CP_PACKET1_REG1_MASK 0x003ff800

3393

3394

#define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000

3395

3396

#define RADEON_CP_PACKET3_NOP 0xC0001000

3397

#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900

3398

#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00

3399

#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00

3400

#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300

3401

#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400

3402

#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600

3403

#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800

3404

#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900

3405

#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00

3406

#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00

3407

#define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500

3408

#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00

3409

#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100

3410

#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200

3411

#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300

3412

#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400

3413

#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500

3414

#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800

3415

#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00

3416

#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00

3417

#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00

3418

3419

3420

#define RADEON_CP_VC_FRMT_XY 0x00000000

3421

#define RADEON_CP_VC_FRMT_W0 0x00000001

3422

#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002

3423

#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004

3424

#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008

3425

#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010

3426

#define RADEON_CP_VC_FRMT_FPFOG 0x00000020

3427

#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040

3428

#define RADEON_CP_VC_FRMT_ST0 0x00000080

3429

#define RADEON_CP_VC_FRMT_ST1 0x00000100

3430

#define RADEON_CP_VC_FRMT_Q1 0x00000200

3431

#define RADEON_CP_VC_FRMT_ST2 0x00000400

3432

#define RADEON_CP_VC_FRMT_Q2 0x00000800

3433

#define RADEON_CP_VC_FRMT_ST3 0x00001000

3434

#define RADEON_CP_VC_FRMT_Q3 0x00002000

3435

#define RADEON_CP_VC_FRMT_Q0 0x00004000

3436

#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000

3437

#define RADEON_CP_VC_FRMT_N0 0x00040000

3438

#define RADEON_CP_VC_FRMT_XY1 0x08000000

3439

#define RADEON_CP_VC_FRMT_Z1 0x10000000

3440

#define RADEON_CP_VC_FRMT_W1 0x20000000

3441

#define RADEON_CP_VC_FRMT_N1 0x40000000

3442

#define RADEON_CP_VC_FRMT_Z 0x80000000

3443

3444

#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000

3445

#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001

3446

#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002

3447

#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003

3448

#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004

3449

#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005

3450

#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006

3451

#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007

3452

#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008

3453

#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009

3454

#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a

3455

#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010

3456

#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020

3457

#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030

3458

#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000

3459

#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040

3460

#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080

3461

#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000

3462

#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100

3463

#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000

3464

#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200

3465

#define RADEON_CP_VC_CNTL_NUM_SHIFT 16

3466

3467

#define RADEON_VS_MATRIX_0_ADDR 0

3468

#define RADEON_VS_MATRIX_1_ADDR 4

3469

#define RADEON_VS_MATRIX_2_ADDR 8

3470

#define RADEON_VS_MATRIX_3_ADDR 12

3471

#define RADEON_VS_MATRIX_4_ADDR 16

3472

#define RADEON_VS_MATRIX_5_ADDR 20

3473

#define RADEON_VS_MATRIX_6_ADDR 24

3474

#define RADEON_VS_MATRIX_7_ADDR 28

3475

#define RADEON_VS_MATRIX_8_ADDR 32

3476

#define RADEON_VS_MATRIX_9_ADDR 36

3477

#define RADEON_VS_MATRIX_10_ADDR 40

3478

#define RADEON_VS_MATRIX_11_ADDR 44

3479

#define RADEON_VS_MATRIX_12_ADDR 48

3480

#define RADEON_VS_MATRIX_13_ADDR 52

3481

#define RADEON_VS_MATRIX_14_ADDR 56

3482

#define RADEON_VS_MATRIX_15_ADDR 60

3483

#define RADEON_VS_LIGHT_AMBIENT_ADDR 64

3484

#define RADEON_VS_LIGHT_DIFFUSE_ADDR 72

3485

#define RADEON_VS_LIGHT_SPECULAR_ADDR 80

3486

#define RADEON_VS_LIGHT_DIRPOS_ADDR 88

3487

#define RADEON_VS_LIGHT_HWVSPOT_ADDR 96

3488

#define RADEON_VS_LIGHT_ATTENUATION_ADDR 104

3489

#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112

3490

#define RADEON_VS_UCP_ADDR 116

3491

#define RADEON_VS_GLOBAL_AMBIENT_ADDR 122

3492

#define RADEON_VS_FOG_PARAM_ADDR 123

3493

#define RADEON_VS_EYE_VECTOR_ADDR 124

3494

3495

#define RADEON_SS_LIGHT_DCD_ADDR 0

3496

#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8

3497

#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16

3498

#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24

3499

#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32

3500

#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48

3501

#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49

3502

#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50

3503

#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51

3504

#define RADEON_SS_SHININESS 60

3505

3506

#define RADEON_TV_MASTER_CNTL 0x0800

3507

# define RADEON_TV_ASYNC_RST (1 << 0)

3508

# define RADEON_CRT_ASYNC_RST (1 << 1)

3509

# define RADEON_RESTART_PHASE_FIX (1 << 3)

3510

# define RADEON_TV_FIFO_ASYNC_RST (1 << 4)

3511

# define RADEON_VIN_ASYNC_RST (1 << 5)

3512

# define RADEON_AUD_ASYNC_RST (1 << 6)

3513

# define RADEON_DVS_ASYNC_RST (1 << 7)

3514

# define RADEON_CRT_FIFO_CE_EN (1 << 9)

3515

# define RADEON_TV_FIFO_CE_EN (1 << 10)

3516

# define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14)

3517

# define RADEON_TVCLK_ALWAYS_ONb (1 << 30)

3518

# define RADEON_TV_ON (1 << 31)

3519

#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888

3520

# define RADEON_Y_RED_EN (1 << 0)

3521

# define RADEON_C_GRN_EN (1 << 1)

3522

# define RADEON_CMP_BLU_EN (1 << 2)

3523

# define RADEON_DAC_DITHER_EN (1 << 3)

3524

# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4)

3525

# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8)

3526

# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12)

3527

# define RADEON_TV_FORCE_DAC_DATA_SHIFT 16

3528

#define RADEON_TV_RGB_CNTL 0x0804

3529

# define RADEON_SWITCH_TO_BLUE (1 << 4)

3530

# define RADEON_RGB_DITHER_EN (1 << 5)

3531

# define RADEON_RGB_SRC_SEL_MASK (3 << 8)

3532

# define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8)

3533

# define RADEON_RGB_SRC_SEL_RMX (1 << 8)

3534

# define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8)

3535

# define RADEON_RGB_CONVERT_BY_PASS (1 << 10)

3536

# define RADEON_UVRAM_READ_MARGIN_SHIFT 16

3537

# define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20

Dave Airlie

4ce001a

2009-08-13 16:32:14 +1000

[diff] [blame]

3538

# define RADEON_RGB_ATTEN_SEL(x) ((x) << 24)

3539

# define RADEON_TVOUT_SCALE_EN (1 << 26)

3540

# define RADEON_RGB_ATTEN_VAL(x) ((x) << 28)

Jerome Glisse

2009-06-05 14:42:42 +0200

[diff] [blame]

3541

#define RADEON_TV_SYNC_CNTL 0x0808

3542

# define RADEON_SYNC_OE (1 << 0)

3543

# define RADEON_SYNC_OUT (1 << 1)

3544

# define RADEON_SYNC_IN (1 << 2)

3545

# define RADEON_SYNC_PUB (1 << 3)

3546

# define RADEON_SYNC_PD (1 << 4)

3547

# define RADEON_TV_SYNC_IO_DRIVE (1 << 5)

3548

#define RADEON_TV_HTOTAL 0x080c

3549

#define RADEON_TV_HDISP 0x0810

3550

#define RADEON_TV_HSTART 0x0818

3551

#define RADEON_TV_HCOUNT 0x081C

3552

#define RADEON_TV_VTOTAL 0x0820

3553

#define RADEON_TV_VDISP 0x0824

3554

#define RADEON_TV_VCOUNT 0x0828

3555

#define RADEON_TV_FTOTAL 0x082c

3556

#define RADEON_TV_FCOUNT 0x0830

3557

#define RADEON_TV_FRESTART 0x0834

3558

#define RADEON_TV_HRESTART 0x0838

3559

#define RADEON_TV_VRESTART 0x083c

3560

#define RADEON_TV_HOST_READ_DATA 0x0840

3561

#define RADEON_TV_HOST_WRITE_DATA 0x0844

3562

#define RADEON_TV_HOST_RD_WT_CNTL 0x0848

3563

# define RADEON_HOST_FIFO_RD (1 << 12)

3564

# define RADEON_HOST_FIFO_RD_ACK (1 << 13)

3565

# define RADEON_HOST_FIFO_WT (1 << 14)

3566

# define RADEON_HOST_FIFO_WT_ACK (1 << 15)

3567

#define RADEON_TV_VSCALER_CNTL1 0x084c

3568

# define RADEON_UV_INC_MASK 0xffff

3569

# define RADEON_UV_INC_SHIFT 0

3570

# define RADEON_Y_W_EN (1 << 24)

3571

# define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */

3572

# define RADEON_Y_DEL_W_SIG_SHIFT 26

3573

#define RADEON_TV_TIMING_CNTL 0x0850

3574

# define RADEON_H_INC_MASK 0xfff

3575

# define RADEON_H_INC_SHIFT 0

3576

# define RADEON_REQ_Y_FIRST (1 << 19)

3577

# define RADEON_FORCE_BURST_ALWAYS (1 << 21)

3578

# define RADEON_UV_POST_SCALE_BYPASS (1 << 23)

3579

# define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24

3580

#define RADEON_TV_VSCALER_CNTL2 0x0854

3581

# define RADEON_DITHER_MODE (1 << 0)

3582

# define RADEON_Y_OUTPUT_DITHER_EN (1 << 1)

3583

# define RADEON_UV_OUTPUT_DITHER_EN (1 << 2)

3584

# define RADEON_UV_TO_BUF_DITHER_EN (1 << 3)

3585

#define RADEON_TV_Y_FALL_CNTL 0x0858

3586

# define RADEON_Y_FALL_PING_PONG (1 << 16)

3587

# define RADEON_Y_COEF_EN (1 << 17)

3588

#define RADEON_TV_Y_RISE_CNTL 0x085c

3589

# define RADEON_Y_RISE_PING_PONG (1 << 16)

3590

#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860

3591

#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864

3592

# define RADEON_YUPSAMP_EN (1 << 0)

3593

# define RADEON_UVUPSAMP_EN (1 << 2)

3594

#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868

3595

# define RADEON_Y_GAIN_LIMIT_SHIFT 0

3596

# define RADEON_UV_GAIN_LIMIT_SHIFT 16

3597

#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c

3598

# define RADEON_Y_GAIN_SHIFT 0

3599

# define RADEON_UV_GAIN_SHIFT 16

3600

#define RADEON_TV_MODULATOR_CNTL1 0x0870

3601

# define RADEON_YFLT_EN (1 << 2)

3602

# define RADEON_UVFLT_EN (1 << 3)

3603

# define RADEON_ALT_PHASE_EN (1 << 6)

3604

# define RADEON_SYNC_TIP_LEVEL (1 << 7)

3605

# define RADEON_BLANK_LEVEL_SHIFT 8

3606

# define RADEON_SET_UP_LEVEL_SHIFT 16

3607

# define RADEON_SLEW_RATE_LIMIT (1 << 23)

3608

# define RADEON_CY_FILT_BLEND_SHIFT 28

3609

#define RADEON_TV_MODULATOR_CNTL2 0x0874

3610

# define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff

3611

# define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff

3612

# define RADEON_TV_V_BURST_LEVEL_SHIFT 16

3613

#define RADEON_TV_CRC_CNTL 0x0890

3614

#define RADEON_TV_UV_ADR 0x08ac

3615

# define RADEON_MAX_UV_ADR_MASK 0x000000ff

3616

# define RADEON_MAX_UV_ADR_SHIFT 0

3617

# define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00

3618

# define RADEON_TABLE1_BOT_ADR_SHIFT 8

3619

# define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000

3620

# define RADEON_TABLE3_TOP_ADR_SHIFT 16

3621

# define RADEON_HCODE_TABLE_SEL_MASK 0x06000000

3622

# define RADEON_HCODE_TABLE_SEL_SHIFT 25

3623

# define RADEON_VCODE_TABLE_SEL_MASK 0x18000000

3624

# define RADEON_VCODE_TABLE_SEL_SHIFT 27

3625

# define RADEON_TV_MAX_FIFO_ADDR 0x1a7

3626

# define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff

3627

#define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */

3628

#define RADEON_TV_PLL_CNTL 0x0021 /* PLL */

3629

# define RADEON_TV_M0LO_MASK 0xff

3630

# define RADEON_TV_M0HI_MASK 0x7

3631

# define RADEON_TV_M0HI_SHIFT 18

3632

# define RADEON_TV_N0LO_MASK 0x1ff

3633

# define RADEON_TV_N0LO_SHIFT 8

3634

# define RADEON_TV_N0HI_MASK 0x3

3635

# define RADEON_TV_N0HI_SHIFT 21

3636

# define RADEON_TV_P_MASK 0xf

3637

# define RADEON_TV_P_SHIFT 24

3638

# define RADEON_TV_SLIP_EN (1 << 23)

3639

# define RADEON_TV_DTO_EN (1 << 28)

3640

#define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */

3641

# define RADEON_TVPLL_RESET (1 << 1)

3642

# define RADEON_TVPLL_SLEEP (1 << 3)

3643

# define RADEON_TVPLL_REFCLK_SEL (1 << 4)

3644

# define RADEON_TVPCP_SHIFT 8

3645

# define RADEON_TVPCP_MASK (7 << 8)

3646

# define RADEON_TVPVG_SHIFT 11

3647

# define RADEON_TVPVG_MASK (7 << 11)

3648

# define RADEON_TVPDC_SHIFT 14

3649

# define RADEON_TVPDC_MASK (3 << 14)

3650

# define RADEON_TVPLL_TEST_DIS (1 << 31)

3651

# define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30)

3652

3653

#define RS400_DISP2_REQ_CNTL1 0xe30

3654

# define RS400_DISP2_START_REQ_LEVEL_SHIFT 0

3655

# define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff

3656

# define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12

3657

# define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff

3658

# define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22

3659

# define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff

3660

#define RS400_DISP2_REQ_CNTL2 0xe34

3661

# define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12

3662

# define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff

3663

# define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22

3664

# define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff

3665

#define RS400_DMIF_MEM_CNTL1 0xe38

3666

# define RS400_DISP2_START_ADR_SHIFT 0

3667

# define RS400_DISP2_START_ADR_MASK 0x3ff

3668

# define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12

3669

# define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff

3670

# define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22

3671

# define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff

3672

#define RS400_DISP1_REQ_CNTL1 0xe3c

3673

# define RS400_DISP1_START_REQ_LEVEL_SHIFT 0

3674

# define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff

3675

# define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12

3676

# define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff

3677

# define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22

3678

# define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff

3679

3680

#define RADEON_PCIE_INDEX 0x0030

3681

#define RADEON_PCIE_DATA 0x0034

3682

#define RADEON_PCIE_TX_GART_CNTL 0x10

3683

# define RADEON_PCIE_TX_GART_EN (1 << 0)

3684

# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)

3685

# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)

3686

# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)

3687

# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)

3688

# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)

3689

# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)

3690

# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)

3691

#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11

3692

#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12

3693

#define RADEON_PCIE_TX_GART_BASE 0x13

3694

#define RADEON_PCIE_TX_GART_START_LO 0x14

3695

#define RADEON_PCIE_TX_GART_START_HI 0x15

3696

#define RADEON_PCIE_TX_GART_END_LO 0x16

3697

#define RADEON_PCIE_TX_GART_END_HI 0x17

3698

#define RADEON_PCIE_TX_GART_ERROR 0x18

3699

3700

#define RADEON_SCRATCH_REG0 0x15e0

3701

#define RADEON_SCRATCH_REG1 0x15e4

3702

#define RADEON_SCRATCH_REG2 0x15e8

3703

#define RADEON_SCRATCH_REG3 0x15ec

3704

#define RADEON_SCRATCH_REG4 0x15f0

3705

#define RADEON_SCRATCH_REG5 0x15f4

3706

Alex Deucher

f779b3e

2009-08-19 19:11:39 -0400

[diff] [blame]

3707

#define RV530_GB_PIPE_SELECT2 0x4124

3708

Jerome Glisse