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Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -07001/*
2 * Driver for the Synopsys DesignWare AHB DMA Controller
3 *
4 * Copyright (C) 2005-2007 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/dw_dmac.h>
12
13#define DW_DMA_MAX_NR_CHANNELS 8
14
15/*
16 * Redefine this macro to handle differences between 32- and 64-bit
17 * addressing, big vs. little endian, etc.
18 */
19#define DW_REG(name) u32 name; u32 __pad_##name
20
21/* Hardware register definitions. */
22struct dw_dma_chan_regs {
23 DW_REG(SAR); /* Source Address Register */
24 DW_REG(DAR); /* Destination Address Register */
25 DW_REG(LLP); /* Linked List Pointer */
26 u32 CTL_LO; /* Control Register Low */
27 u32 CTL_HI; /* Control Register High */
28 DW_REG(SSTAT);
29 DW_REG(DSTAT);
30 DW_REG(SSTATAR);
31 DW_REG(DSTATAR);
32 u32 CFG_LO; /* Configuration Register Low */
33 u32 CFG_HI; /* Configuration Register High */
34 DW_REG(SGR);
35 DW_REG(DSR);
36};
37
38struct dw_dma_irq_regs {
39 DW_REG(XFER);
40 DW_REG(BLOCK);
41 DW_REG(SRC_TRAN);
42 DW_REG(DST_TRAN);
43 DW_REG(ERROR);
44};
45
46struct dw_dma_regs {
47 /* per-channel registers */
48 struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
49
50 /* irq handling */
51 struct dw_dma_irq_regs RAW; /* r */
52 struct dw_dma_irq_regs STATUS; /* r (raw & mask) */
53 struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */
54 struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */
55
56 DW_REG(STATUS_INT); /* r */
57
58 /* software handshaking */
59 DW_REG(REQ_SRC);
60 DW_REG(REQ_DST);
61 DW_REG(SGL_REQ_SRC);
62 DW_REG(SGL_REQ_DST);
63 DW_REG(LAST_SRC);
64 DW_REG(LAST_DST);
65
66 /* miscellaneous */
67 DW_REG(CFG);
68 DW_REG(CH_EN);
69 DW_REG(ID);
70 DW_REG(TEST);
71
72 /* optional encoded params, 0x3c8..0x3 */
73};
74
75/* Bitfields in CTL_LO */
76#define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */
77#define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */
78#define DWC_CTLL_SRC_WIDTH(n) ((n)<<4)
79#define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */
80#define DWC_CTLL_DST_DEC (1<<7)
81#define DWC_CTLL_DST_FIX (2<<7)
82#define DWC_CTLL_SRC_INC (0<<7) /* SAR update/not */
83#define DWC_CTLL_SRC_DEC (1<<9)
84#define DWC_CTLL_SRC_FIX (2<<9)
85#define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */
86#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
87#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */
88#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */
Viresh KUMARee665092011-03-04 15:42:51 +053089#define DWC_CTLL_FC(n) ((n) << 20)
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070090#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */
91#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
92#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
93#define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */
94/* plus 4 transfer types for peripheral-as-flow-controller */
95#define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */
96#define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */
97#define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */
98#define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */
99
100/* Bitfields in CTL_HI */
101#define DWC_CTLH_DONE 0x00001000
102#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff
103
104/* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */
Viresh Kumar93317e82011-03-03 15:47:22 +0530105#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */
106#define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700107#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */
108#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */
109#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */
110#define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */
111#define DWC_CFGL_MAX_BURST(x) ((x) << 20)
112#define DWC_CFGL_RELOAD_SAR (1 << 30)
113#define DWC_CFGL_RELOAD_DAR (1 << 31)
114
115/* Bitfields in CFG_HI. Platform-configurable bits are in <linux/dw_dmac.h> */
116#define DWC_CFGH_DS_UPD_EN (1 << 5)
117#define DWC_CFGH_SS_UPD_EN (1 << 6)
118
119/* Bitfields in SGR */
120#define DWC_SGR_SGI(x) ((x) << 0)
121#define DWC_SGR_SGC(x) ((x) << 20)
122
123/* Bitfields in DSR */
124#define DWC_DSR_DSI(x) ((x) << 0)
125#define DWC_DSR_DSC(x) ((x) << 20)
126
127/* Bitfields in CFG */
128#define DW_CFG_DMA_EN (1 << 0)
129
130#define DW_REGLEN 0x400
131
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200132enum dw_dmac_flags {
133 DW_DMA_IS_CYCLIC = 0,
134};
135
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700136struct dw_dma_chan {
137 struct dma_chan chan;
138 void __iomem *ch_regs;
139 u8 mask;
Viresh Kumar93317e82011-03-03 15:47:22 +0530140 u8 priority;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700141
142 spinlock_t lock;
143
144 /* these other elements are all protected by lock */
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200145 unsigned long flags;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700146 dma_cookie_t completed;
147 struct list_head active_list;
148 struct list_head queue;
149 struct list_head free_list;
Hans-Christian Egtvedtd9de4512009-04-01 15:47:02 +0200150 struct dw_cyclic_desc *cdesc;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700151
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700152 unsigned int descs_allocated;
153};
154
155static inline struct dw_dma_chan_regs __iomem *
156__dwc_regs(struct dw_dma_chan *dwc)
157{
158 return dwc->ch_regs;
159}
160
161#define channel_readl(dwc, name) \
Viresh Kumar29782da2011-03-04 14:58:32 +0530162 readl(&(__dwc_regs(dwc)->name))
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700163#define channel_writel(dwc, name, val) \
Viresh Kumar29782da2011-03-04 14:58:32 +0530164 writel((val), &(__dwc_regs(dwc)->name))
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700165
166static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
167{
168 return container_of(chan, struct dw_dma_chan, chan);
169}
170
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700171struct dw_dma {
172 struct dma_device dma;
173 void __iomem *regs;
174 struct tasklet_struct tasklet;
175 struct clk *clk;
176
177 u8 all_chan_mask;
178
179 struct dw_dma_chan chan[0];
180};
181
182static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
183{
184 return dw->regs;
185}
186
187#define dma_readl(dw, name) \
Viresh Kumar29782da2011-03-04 14:58:32 +0530188 readl(&(__dw_regs(dw)->name))
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700189#define dma_writel(dw, name, val) \
Viresh Kumar29782da2011-03-04 14:58:32 +0530190 writel((val), &(__dw_regs(dw)->name))
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700191
192#define channel_set_bit(dw, reg, mask) \
193 dma_writel(dw, reg, ((mask) << 8) | (mask))
194#define channel_clear_bit(dw, reg, mask) \
195 dma_writel(dw, reg, ((mask) << 8) | 0)
196
197static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
198{
199 return container_of(ddev, struct dw_dma, dma);
200}
201
202/* LLI == Linked List Item; a.k.a. DMA block descriptor */
203struct dw_lli {
204 /* values that are not changed by hardware */
205 dma_addr_t sar;
206 dma_addr_t dar;
207 dma_addr_t llp; /* chain to next lli */
208 u32 ctllo;
209 /* values that may get written back: */
210 u32 ctlhi;
211 /* sstat and dstat can snapshot peripheral register state.
212 * silicon config may discard either or both...
213 */
214 u32 sstat;
215 u32 dstat;
216};
217
218struct dw_desc {
219 /* FIRST values the hardware uses */
220 struct dw_lli lli;
221
222 /* THEN values for driver housekeeping */
223 struct list_head desc_node;
Dan Williamse0bd0f82009-09-08 17:53:02 -0700224 struct list_head tx_list;
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -0700225 struct dma_async_tx_descriptor txd;
226 size_t len;
227};
228
229static inline struct dw_desc *
230txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
231{
232 return container_of(txd, struct dw_desc, txd);
233}