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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 NetWinder Floating Point Emulator
3 (c) Rebel.COM, 1998,1999
4 (c) Philip Blundell, 2001
5
6 Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21*/
22
23#ifndef __FPOPCODE_H__
24#define __FPOPCODE_H__
25
26#include <linux/config.h>
27
28/*
29ARM Floating Point Instruction Classes
30| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
31|c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
32|c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|1|0| o f f s e t | CPDT (copro 2)
33| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
34|c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
35|c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
36|c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
37| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
38
39CPDT data transfer instructions
40 LDF, STF, LFM (copro 2), SFM (copro 2)
41
42CPDO dyadic arithmetic instructions
43 ADF, MUF, SUF, RSF, DVF, RDF,
44 POW, RPW, RMF, FML, FDV, FRD, POL
45
46CPDO monadic arithmetic instructions
47 MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
48 SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
49
50CPRT joint arithmetic/data transfer instructions
51 FIX (arithmetic followed by load/store)
52 FLT (load/store followed by arithmetic)
53 CMF, CNF CMFE, CNFE (comparisons)
54 WFS, RFS (write/read floating point status register)
55 WFC, RFC (write/read floating point control register)
56
57cond condition codes
58P pre/post index bit: 0 = postindex, 1 = preindex
59U up/down bit: 0 = stack grows down, 1 = stack grows up
60W write back bit: 1 = update base register (Rn)
61L load/store bit: 0 = store, 1 = load
62Rn base register
63Rd destination/source register
64Fd floating point destination register
65Fn floating point source register
66Fm floating point source register or floating point constant
67
68uv transfer length (TABLE 1)
69wx register count (TABLE 2)
70abcd arithmetic opcode (TABLES 3 & 4)
71ef destination size (rounding precision) (TABLE 5)
72gh rounding mode (TABLE 6)
73j dyadic/monadic bit: 0 = dyadic, 1 = monadic
74i constant bit: 1 = constant (TABLE 6)
75*/
76
77/*
78TABLE 1
79+-------------------------+---+---+---------+---------+
80| Precision | u | v | FPSR.EP | length |
81+-------------------------+---+---+---------+---------+
82| Single | 0 ü 0 | x | 1 words |
83| Double | 1 ü 1 | x | 2 words |
84| Extended | 1 ü 1 | x | 3 words |
85| Packed decimal | 1 ü 1 | 0 | 3 words |
86| Expanded packed decimal | 1 ü 1 | 1 | 4 words |
87+-------------------------+---+---+---------+---------+
88Note: x = don't care
89*/
90
91/*
92TABLE 2
93+---+---+---------------------------------+
94| w | x | Number of registers to transfer |
95+---+---+---------------------------------+
96| 0 ü 1 | 1 |
97| 1 ü 0 | 2 |
98| 1 ü 1 | 3 |
99| 0 ü 0 | 4 |
100+---+---+---------------------------------+
101*/
102
103/*
104TABLE 3: Dyadic Floating Point Opcodes
105+---+---+---+---+----------+-----------------------+-----------------------+
106| a | b | c | d | Mnemonic | Description | Operation |
107+---+---+---+---+----------+-----------------------+-----------------------+
108| 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm |
109| 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm |
110| 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm |
111| 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn |
112| 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm |
113| 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn |
114| 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm |
115| 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn |
116| 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) |
117| 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm |
118| 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm |
119| 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn |
120| 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) |
121| 1 | 1 | 0 | 1 | | undefined instruction | trap |
122| 1 | 1 | 1 | 0 | | undefined instruction | trap |
123| 1 | 1 | 1 | 1 | | undefined instruction | trap |
124+---+---+---+---+----------+-----------------------+-----------------------+
125Note: POW, RPW, POL are deprecated, and are available for backwards
126 compatibility only.
127*/
128
129/*
130TABLE 4: Monadic Floating Point Opcodes
131+---+---+---+---+----------+-----------------------+-----------------------+
132| a | b | c | d | Mnemonic | Description | Operation |
133+---+---+---+---+----------+-----------------------+-----------------------+
134| 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm |
135| 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm |
136| 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) |
137| 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) |
138| 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) |
139| 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) |
140| 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) |
141| 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm |
142| 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) |
143| 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) |
144| 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) |
145| 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) |
146| 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) |
147| 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) |
148| 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) |
149| 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) |
150+---+---+---+---+----------+-----------------------+-----------------------+
151Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are
152 available for backwards compatibility only.
153*/
154
155/*
156TABLE 5
157+-------------------------+---+---+
158| Rounding Precision | e | f |
159+-------------------------+---+---+
160| IEEE Single precision | 0 ü 0 |
161| IEEE Double precision | 0 ü 1 |
162| IEEE Extended precision | 1 ü 0 |
163| undefined (trap) | 1 ü 1 |
164+-------------------------+---+---+
165*/
166
167/*
168TABLE 5
169+---------------------------------+---+---+
170| Rounding Mode | g | h |
171+---------------------------------+---+---+
172| Round to nearest (default) | 0 ü 0 |
173| Round toward plus infinity | 0 ü 1 |
174| Round toward negative infinity | 1 ü 0 |
175| Round toward zero | 1 ü 1 |
176+---------------------------------+---+---+
177*/
178
179/*
180===
181=== Definitions for load and store instructions
182===
183*/
184
185/* bit masks */
186#define BIT_PREINDEX 0x01000000
187#define BIT_UP 0x00800000
188#define BIT_WRITE_BACK 0x00200000
189#define BIT_LOAD 0x00100000
190
191/* masks for load/store */
192#define MASK_CPDT 0x0c000000 /* data processing opcode */
193#define MASK_OFFSET 0x000000ff
194#define MASK_TRANSFER_LENGTH 0x00408000
195#define MASK_REGISTER_COUNT MASK_TRANSFER_LENGTH
196#define MASK_COPROCESSOR 0x00000f00
197
198/* Tests for transfer length */
199#define TRANSFER_SINGLE 0x00000000
200#define TRANSFER_DOUBLE 0x00008000
201#define TRANSFER_EXTENDED 0x00400000
202#define TRANSFER_PACKED MASK_TRANSFER_LENGTH
203
204/* Get the coprocessor number from the opcode. */
205#define getCoprocessorNumber(opcode) ((opcode & MASK_COPROCESSOR) >> 8)
206
207/* Get the offset from the opcode. */
208#define getOffset(opcode) (opcode & MASK_OFFSET)
209
210/* Tests for specific data transfer load/store opcodes. */
211#define TEST_OPCODE(opcode,mask) (((opcode) & (mask)) == (mask))
212
213#define LOAD_OP(opcode) TEST_OPCODE((opcode),MASK_CPDT | BIT_LOAD)
214#define STORE_OP(opcode) ((opcode & (MASK_CPDT | BIT_LOAD)) == MASK_CPDT)
215
216#define LDF_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 1))
217#define LFM_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 2))
218#define STF_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 1))
219#define SFM_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 2))
220
221#define PREINDEXED(opcode) ((opcode & BIT_PREINDEX) != 0)
222#define POSTINDEXED(opcode) ((opcode & BIT_PREINDEX) == 0)
223#define BIT_UP_SET(opcode) ((opcode & BIT_UP) != 0)
224#define BIT_UP_CLEAR(opcode) ((opcode & BIT_DOWN) == 0)
225#define WRITE_BACK(opcode) ((opcode & BIT_WRITE_BACK) != 0)
226#define LOAD(opcode) ((opcode & BIT_LOAD) != 0)
227#define STORE(opcode) ((opcode & BIT_LOAD) == 0)
228
229/*
230===
231=== Definitions for arithmetic instructions
232===
233*/
234/* bit masks */
235#define BIT_MONADIC 0x00008000
236#define BIT_CONSTANT 0x00000008
237
238#define CONSTANT_FM(opcode) ((opcode & BIT_CONSTANT) != 0)
239#define MONADIC_INSTRUCTION(opcode) ((opcode & BIT_MONADIC) != 0)
240
241/* instruction identification masks */
242#define MASK_CPDO 0x0e000000 /* arithmetic opcode */
243#define MASK_ARITHMETIC_OPCODE 0x00f08000
244#define MASK_DESTINATION_SIZE 0x00080080
245
246/* dyadic arithmetic opcodes. */
247#define ADF_CODE 0x00000000
248#define MUF_CODE 0x00100000
249#define SUF_CODE 0x00200000
250#define RSF_CODE 0x00300000
251#define DVF_CODE 0x00400000
252#define RDF_CODE 0x00500000
253#define POW_CODE 0x00600000
254#define RPW_CODE 0x00700000
255#define RMF_CODE 0x00800000
256#define FML_CODE 0x00900000
257#define FDV_CODE 0x00a00000
258#define FRD_CODE 0x00b00000
259#define POL_CODE 0x00c00000
260/* 0x00d00000 is an invalid dyadic arithmetic opcode */
261/* 0x00e00000 is an invalid dyadic arithmetic opcode */
262/* 0x00f00000 is an invalid dyadic arithmetic opcode */
263
264/* monadic arithmetic opcodes. */
265#define MVF_CODE 0x00008000
266#define MNF_CODE 0x00108000
267#define ABS_CODE 0x00208000
268#define RND_CODE 0x00308000
269#define SQT_CODE 0x00408000
270#define LOG_CODE 0x00508000
271#define LGN_CODE 0x00608000
272#define EXP_CODE 0x00708000
273#define SIN_CODE 0x00808000
274#define COS_CODE 0x00908000
275#define TAN_CODE 0x00a08000
276#define ASN_CODE 0x00b08000
277#define ACS_CODE 0x00c08000
278#define ATN_CODE 0x00d08000
279#define URD_CODE 0x00e08000
280#define NRM_CODE 0x00f08000
281
282/*
283===
284=== Definitions for register transfer and comparison instructions
285===
286*/
287
288#define MASK_CPRT 0x0e000010 /* register transfer opcode */
289#define MASK_CPRT_CODE 0x00f00000
290#define FLT_CODE 0x00000000
291#define FIX_CODE 0x00100000
292#define WFS_CODE 0x00200000
293#define RFS_CODE 0x00300000
294#define WFC_CODE 0x00400000
295#define RFC_CODE 0x00500000
296#define CMF_CODE 0x00900000
297#define CNF_CODE 0x00b00000
298#define CMFE_CODE 0x00d00000
299#define CNFE_CODE 0x00f00000
300
301/*
302===
303=== Common definitions
304===
305*/
306
307/* register masks */
308#define MASK_Rd 0x0000f000
309#define MASK_Rn 0x000f0000
310#define MASK_Fd 0x00007000
311#define MASK_Fm 0x00000007
312#define MASK_Fn 0x00070000
313
314/* condition code masks */
315#define CC_MASK 0xf0000000
316#define CC_NEGATIVE 0x80000000
317#define CC_ZERO 0x40000000
318#define CC_CARRY 0x20000000
319#define CC_OVERFLOW 0x10000000
320#define CC_EQ 0x00000000
321#define CC_NE 0x10000000
322#define CC_CS 0x20000000
323#define CC_HS CC_CS
324#define CC_CC 0x30000000
325#define CC_LO CC_CC
326#define CC_MI 0x40000000
327#define CC_PL 0x50000000
328#define CC_VS 0x60000000
329#define CC_VC 0x70000000
330#define CC_HI 0x80000000
331#define CC_LS 0x90000000
332#define CC_GE 0xa0000000
333#define CC_LT 0xb0000000
334#define CC_GT 0xc0000000
335#define CC_LE 0xd0000000
336#define CC_AL 0xe0000000
337#define CC_NV 0xf0000000
338
339/* rounding masks/values */
340#define MASK_ROUNDING_MODE 0x00000060
341#define ROUND_TO_NEAREST 0x00000000
342#define ROUND_TO_PLUS_INFINITY 0x00000020
343#define ROUND_TO_MINUS_INFINITY 0x00000040
344#define ROUND_TO_ZERO 0x00000060
345
346#define MASK_ROUNDING_PRECISION 0x00080080
347#define ROUND_SINGLE 0x00000000
348#define ROUND_DOUBLE 0x00000080
349#define ROUND_EXTENDED 0x00080000
350
351/* Get the condition code from the opcode. */
352#define getCondition(opcode) (opcode >> 28)
353
354/* Get the source register from the opcode. */
355#define getRn(opcode) ((opcode & MASK_Rn) >> 16)
356
357/* Get the destination floating point register from the opcode. */
358#define getFd(opcode) ((opcode & MASK_Fd) >> 12)
359
360/* Get the first source floating point register from the opcode. */
361#define getFn(opcode) ((opcode & MASK_Fn) >> 16)
362
363/* Get the second source floating point register from the opcode. */
364#define getFm(opcode) (opcode & MASK_Fm)
365
366/* Get the destination register from the opcode. */
367#define getRd(opcode) ((opcode & MASK_Rd) >> 12)
368
369/* Get the rounding mode from the opcode. */
370#define getRoundingMode(opcode) ((opcode & MASK_ROUNDING_MODE) >> 5)
371
372#ifdef CONFIG_FPE_NWFPE_XP
Al Viro33215652005-08-23 22:47:52 +0100373static inline __attribute_pure__ floatx80 getExtendedConstant(const unsigned int nIndex)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374{
375 extern const floatx80 floatx80Constant[];
376 return floatx80Constant[nIndex];
377}
378#endif
379
Al Viro33215652005-08-23 22:47:52 +0100380static inline __attribute_pure__ float64 getDoubleConstant(const unsigned int nIndex)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381{
382 extern const float64 float64Constant[];
383 return float64Constant[nIndex];
384}
385
Al Viro33215652005-08-23 22:47:52 +0100386static inline __attribute_pure__ float32 getSingleConstant(const unsigned int nIndex)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387{
388 extern const float32 float32Constant[];
389 return float32Constant[nIndex];
390}
391
392static inline unsigned int getTransferLength(const unsigned int opcode)
393{
394 unsigned int nRc;
395
396 switch (opcode & MASK_TRANSFER_LENGTH) {
397 case 0x00000000:
398 nRc = 1;
399 break; /* single precision */
400 case 0x00008000:
401 nRc = 2;
402 break; /* double precision */
403 case 0x00400000:
404 nRc = 3;
405 break; /* extended precision */
406 default:
407 nRc = 0;
408 }
409
410 return (nRc);
411}
412
413static inline unsigned int getRegisterCount(const unsigned int opcode)
414{
415 unsigned int nRc;
416
417 switch (opcode & MASK_REGISTER_COUNT) {
418 case 0x00000000:
419 nRc = 4;
420 break;
421 case 0x00008000:
422 nRc = 1;
423 break;
424 case 0x00400000:
425 nRc = 2;
426 break;
427 case 0x00408000:
428 nRc = 3;
429 break;
430 default:
431 nRc = 0;
432 }
433
434 return (nRc);
435}
436
437static inline unsigned int getRoundingPrecision(const unsigned int opcode)
438{
439 unsigned int nRc;
440
441 switch (opcode & MASK_ROUNDING_PRECISION) {
442 case 0x00000000:
443 nRc = 1;
444 break;
445 case 0x00000080:
446 nRc = 2;
447 break;
448 case 0x00080000:
449 nRc = 3;
450 break;
451 default:
452 nRc = 0;
453 }
454
455 return (nRc);
456}
457
458static inline unsigned int getDestinationSize(const unsigned int opcode)
459{
460 unsigned int nRc;
461
462 switch (opcode & MASK_DESTINATION_SIZE) {
463 case 0x00000000:
464 nRc = typeSingle;
465 break;
466 case 0x00000080:
467 nRc = typeDouble;
468 break;
469 case 0x00080000:
470 nRc = typeExtended;
471 break;
472 default:
473 nRc = typeNone;
474 }
475
476 return (nRc);
477}
478
Ben Dooks6ec5e7f2005-10-12 19:58:10 +0100479extern unsigned int checkCondition(const unsigned int opcode,
480 const unsigned int ccodes);
481
482extern const float64 float64Constant[];
483extern const float32 float32Constant[];
484
Linus Torvalds1da177e2005-04-16 15:20:36 -0700485#endif