Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
Tang Yuantian | 93a17c0 | 2015-01-15 14:03:41 +0800 | [diff] [blame] | 8 | * clock driver for Freescale QorIQ SoCs. |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 9 | */ |
Emil Medve | c88b2b6 | 2015-01-21 04:03:29 -0600 | [diff] [blame] | 10 | |
| 11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 12 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 13 | #include <linux/clk.h> |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 14 | #include <linux/clk-provider.h> |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 15 | #include <linux/fsl/guts.h> |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 16 | #include <linux/io.h> |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/module.h> |
Rob Herring | c11eede | 2013-11-10 23:19:08 -0600 | [diff] [blame] | 19 | #include <linux/of_address.h> |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 20 | #include <linux/of_platform.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/slab.h> |
| 23 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 24 | #define PLL_DIV1 0 |
| 25 | #define PLL_DIV2 1 |
| 26 | #define PLL_DIV3 2 |
| 27 | #define PLL_DIV4 3 |
| 28 | |
| 29 | #define PLATFORM_PLL 0 |
| 30 | #define CGA_PLL1 1 |
| 31 | #define CGA_PLL2 2 |
| 32 | #define CGA_PLL3 3 |
| 33 | #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */ |
| 34 | #define CGB_PLL1 4 |
| 35 | #define CGB_PLL2 5 |
| 36 | |
| 37 | struct clockgen_pll_div { |
| 38 | struct clk *clk; |
| 39 | char name[32]; |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 40 | }; |
| 41 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 42 | struct clockgen_pll { |
| 43 | struct clockgen_pll_div div[4]; |
| 44 | }; |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 45 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 46 | #define CLKSEL_VALID 1 |
| 47 | #define CLKSEL_80PCT 2 /* Only allowed if PLL <= 80% of max cpu freq */ |
| 48 | |
| 49 | struct clockgen_sourceinfo { |
| 50 | u32 flags; /* CLKSEL_xxx */ |
| 51 | int pll; /* CGx_PLLn */ |
| 52 | int div; /* PLL_DIVn */ |
| 53 | }; |
| 54 | |
| 55 | #define NUM_MUX_PARENTS 16 |
| 56 | |
| 57 | struct clockgen_muxinfo { |
| 58 | struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS]; |
| 59 | }; |
| 60 | |
| 61 | #define NUM_HWACCEL 5 |
| 62 | #define NUM_CMUX 8 |
| 63 | |
| 64 | struct clockgen; |
| 65 | |
| 66 | /* |
| 67 | * cmux freq must be >= platform pll. |
| 68 | * If not set, cmux freq must be >= platform pll/2 |
| 69 | */ |
| 70 | #define CG_CMUX_GE_PLAT 1 |
Scott Wood | 9e19ca2 | 2015-09-19 23:29:55 -0500 | [diff] [blame] | 71 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 72 | #define CG_PLL_8BIT 2 /* PLLCnGSR[CFG] is 8 bits, not 6 */ |
Scott Wood | 9e19ca2 | 2015-09-19 23:29:55 -0500 | [diff] [blame] | 73 | #define CG_VER3 4 /* version 3 cg: reg layout different */ |
| 74 | #define CG_LITTLE_ENDIAN 8 |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 75 | |
| 76 | struct clockgen_chipinfo { |
| 77 | const char *compat, *guts_compat; |
| 78 | const struct clockgen_muxinfo *cmux_groups[2]; |
| 79 | const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL]; |
| 80 | void (*init_periph)(struct clockgen *cg); |
| 81 | int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */ |
| 82 | u32 pll_mask; /* 1 << n bit set if PLL n is valid */ |
| 83 | u32 flags; /* CG_xxx */ |
| 84 | }; |
| 85 | |
| 86 | struct clockgen { |
| 87 | struct device_node *node; |
| 88 | void __iomem *regs; |
| 89 | struct clockgen_chipinfo info; /* mutable copy */ |
| 90 | struct clk *sysclk; |
| 91 | struct clockgen_pll pll[6]; |
| 92 | struct clk *cmux[NUM_CMUX]; |
| 93 | struct clk *hwaccel[NUM_HWACCEL]; |
| 94 | struct clk *fman[2]; |
| 95 | struct ccsr_guts __iomem *guts; |
| 96 | }; |
| 97 | |
| 98 | static struct clockgen clockgen; |
| 99 | |
Scott Wood | 9e19ca2 | 2015-09-19 23:29:55 -0500 | [diff] [blame] | 100 | static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg) |
| 101 | { |
| 102 | if (cg->info.flags & CG_LITTLE_ENDIAN) |
| 103 | iowrite32(val, reg); |
| 104 | else |
| 105 | iowrite32be(val, reg); |
| 106 | } |
| 107 | |
| 108 | static u32 cg_in(struct clockgen *cg, u32 __iomem *reg) |
| 109 | { |
| 110 | u32 val; |
| 111 | |
| 112 | if (cg->info.flags & CG_LITTLE_ENDIAN) |
| 113 | val = ioread32(reg); |
| 114 | else |
| 115 | val = ioread32be(reg); |
| 116 | |
| 117 | return val; |
| 118 | } |
| 119 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 120 | static const struct clockgen_muxinfo p2041_cmux_grp1 = { |
| 121 | { |
| 122 | [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, |
| 123 | [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, |
| 124 | [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, |
| 125 | } |
| 126 | }; |
| 127 | |
| 128 | static const struct clockgen_muxinfo p2041_cmux_grp2 = { |
| 129 | { |
| 130 | [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, |
Scott Wood | 2c7693e | 2015-10-22 23:21:46 -0500 | [diff] [blame] | 131 | [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, |
| 132 | [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 133 | } |
| 134 | }; |
| 135 | |
| 136 | static const struct clockgen_muxinfo p5020_cmux_grp1 = { |
| 137 | { |
| 138 | [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, |
| 139 | [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, |
| 140 | [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 }, |
| 141 | } |
| 142 | }; |
| 143 | |
| 144 | static const struct clockgen_muxinfo p5020_cmux_grp2 = { |
| 145 | { |
| 146 | [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 }, |
| 147 | [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, |
| 148 | [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, |
| 149 | } |
| 150 | }; |
| 151 | |
| 152 | static const struct clockgen_muxinfo p5040_cmux_grp1 = { |
| 153 | { |
| 154 | [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, |
| 155 | [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, |
| 156 | [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 }, |
| 157 | [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 }, |
| 158 | } |
| 159 | }; |
| 160 | |
| 161 | static const struct clockgen_muxinfo p5040_cmux_grp2 = { |
| 162 | { |
| 163 | [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 }, |
| 164 | [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 }, |
| 165 | [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, |
| 166 | [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, |
| 167 | } |
| 168 | }; |
| 169 | |
| 170 | static const struct clockgen_muxinfo p4080_cmux_grp1 = { |
| 171 | { |
| 172 | [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, |
| 173 | [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, |
| 174 | [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, |
| 175 | [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, |
| 176 | [8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 }, |
| 177 | } |
| 178 | }; |
| 179 | |
| 180 | static const struct clockgen_muxinfo p4080_cmux_grp2 = { |
| 181 | { |
| 182 | [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 }, |
| 183 | [8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 }, |
| 184 | [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 }, |
| 185 | [12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 }, |
| 186 | [13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 }, |
| 187 | } |
| 188 | }; |
| 189 | |
| 190 | static const struct clockgen_muxinfo t1023_cmux = { |
| 191 | { |
| 192 | [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, |
| 193 | [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, |
| 194 | } |
| 195 | }; |
| 196 | |
| 197 | static const struct clockgen_muxinfo t1040_cmux = { |
| 198 | { |
| 199 | [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, |
| 200 | [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, |
| 201 | [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, |
| 202 | [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, |
| 203 | } |
| 204 | }; |
| 205 | |
| 206 | |
| 207 | static const struct clockgen_muxinfo clockgen2_cmux_cga = { |
| 208 | { |
| 209 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, |
| 210 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, |
| 211 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, |
| 212 | {}, |
| 213 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, |
| 214 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, |
| 215 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, |
| 216 | {}, |
| 217 | { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 }, |
| 218 | { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 }, |
| 219 | { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 }, |
| 220 | }, |
| 221 | }; |
| 222 | |
| 223 | static const struct clockgen_muxinfo clockgen2_cmux_cga12 = { |
| 224 | { |
| 225 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, |
| 226 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, |
| 227 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, |
| 228 | {}, |
| 229 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, |
| 230 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, |
| 231 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, |
| 232 | }, |
| 233 | }; |
| 234 | |
| 235 | static const struct clockgen_muxinfo clockgen2_cmux_cgb = { |
| 236 | { |
| 237 | { CLKSEL_VALID, CGB_PLL1, PLL_DIV1 }, |
| 238 | { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 }, |
| 239 | { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 }, |
| 240 | {}, |
| 241 | { CLKSEL_VALID, CGB_PLL2, PLL_DIV1 }, |
| 242 | { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 }, |
| 243 | { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 }, |
| 244 | }, |
| 245 | }; |
| 246 | |
Hou Zhiqiang | e994412c | 2015-10-23 16:01:21 +0800 | [diff] [blame] | 247 | static const struct clockgen_muxinfo ls1043a_hwa1 = { |
| 248 | { |
| 249 | {}, |
| 250 | {}, |
| 251 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, |
| 252 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, |
| 253 | {}, |
| 254 | {}, |
| 255 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, |
| 256 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, |
| 257 | }, |
| 258 | }; |
| 259 | |
| 260 | static const struct clockgen_muxinfo ls1043a_hwa2 = { |
| 261 | { |
| 262 | {}, |
| 263 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, |
| 264 | {}, |
| 265 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, |
| 266 | }, |
| 267 | }; |
| 268 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 269 | static const struct clockgen_muxinfo t1023_hwa1 = { |
| 270 | { |
| 271 | {}, |
| 272 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, |
| 273 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, |
| 274 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, |
| 275 | }, |
| 276 | }; |
| 277 | |
| 278 | static const struct clockgen_muxinfo t1023_hwa2 = { |
| 279 | { |
| 280 | [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, |
| 281 | }, |
| 282 | }; |
| 283 | |
| 284 | static const struct clockgen_muxinfo t2080_hwa1 = { |
| 285 | { |
| 286 | {}, |
| 287 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, |
| 288 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, |
| 289 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, |
| 290 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, |
| 291 | { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, |
| 292 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, |
| 293 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, |
| 294 | }, |
| 295 | }; |
| 296 | |
| 297 | static const struct clockgen_muxinfo t2080_hwa2 = { |
| 298 | { |
| 299 | {}, |
| 300 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, |
| 301 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, |
| 302 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, |
| 303 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, |
| 304 | { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, |
| 305 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, |
| 306 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, |
| 307 | }, |
| 308 | }; |
| 309 | |
| 310 | static const struct clockgen_muxinfo t4240_hwa1 = { |
| 311 | { |
| 312 | { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 }, |
| 313 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, |
| 314 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, |
| 315 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, |
| 316 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, |
| 317 | {}, |
| 318 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, |
| 319 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, |
| 320 | }, |
| 321 | }; |
| 322 | |
| 323 | static const struct clockgen_muxinfo t4240_hwa4 = { |
| 324 | { |
| 325 | [2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 }, |
| 326 | [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 }, |
| 327 | [4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 }, |
| 328 | [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, |
| 329 | [6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 }, |
| 330 | }, |
| 331 | }; |
| 332 | |
| 333 | static const struct clockgen_muxinfo t4240_hwa5 = { |
| 334 | { |
| 335 | [2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 }, |
| 336 | [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 }, |
| 337 | [4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 }, |
| 338 | [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, |
| 339 | [6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 }, |
| 340 | [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 }, |
| 341 | }, |
| 342 | }; |
| 343 | |
| 344 | #define RCWSR7_FM1_CLK_SEL 0x40000000 |
| 345 | #define RCWSR7_FM2_CLK_SEL 0x20000000 |
| 346 | #define RCWSR7_HWA_ASYNC_DIV 0x04000000 |
| 347 | |
| 348 | static void __init p2041_init_periph(struct clockgen *cg) |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 349 | { |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 350 | u32 reg; |
| 351 | |
| 352 | reg = ioread32be(&cg->guts->rcwsr[7]); |
| 353 | |
| 354 | if (reg & RCWSR7_FM1_CLK_SEL) |
| 355 | cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; |
| 356 | else |
| 357 | cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; |
| 358 | } |
| 359 | |
| 360 | static void __init p4080_init_periph(struct clockgen *cg) |
| 361 | { |
| 362 | u32 reg; |
| 363 | |
| 364 | reg = ioread32be(&cg->guts->rcwsr[7]); |
| 365 | |
| 366 | if (reg & RCWSR7_FM1_CLK_SEL) |
| 367 | cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; |
| 368 | else |
| 369 | cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; |
| 370 | |
| 371 | if (reg & RCWSR7_FM2_CLK_SEL) |
| 372 | cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; |
| 373 | else |
| 374 | cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; |
| 375 | } |
| 376 | |
| 377 | static void __init p5020_init_periph(struct clockgen *cg) |
| 378 | { |
| 379 | u32 reg; |
| 380 | int div = PLL_DIV2; |
| 381 | |
| 382 | reg = ioread32be(&cg->guts->rcwsr[7]); |
| 383 | if (reg & RCWSR7_HWA_ASYNC_DIV) |
| 384 | div = PLL_DIV4; |
| 385 | |
| 386 | if (reg & RCWSR7_FM1_CLK_SEL) |
| 387 | cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk; |
| 388 | else |
| 389 | cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; |
| 390 | } |
| 391 | |
| 392 | static void __init p5040_init_periph(struct clockgen *cg) |
| 393 | { |
| 394 | u32 reg; |
| 395 | int div = PLL_DIV2; |
| 396 | |
| 397 | reg = ioread32be(&cg->guts->rcwsr[7]); |
| 398 | if (reg & RCWSR7_HWA_ASYNC_DIV) |
| 399 | div = PLL_DIV4; |
| 400 | |
| 401 | if (reg & RCWSR7_FM1_CLK_SEL) |
| 402 | cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk; |
| 403 | else |
| 404 | cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; |
| 405 | |
| 406 | if (reg & RCWSR7_FM2_CLK_SEL) |
| 407 | cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk; |
| 408 | else |
| 409 | cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; |
| 410 | } |
| 411 | |
| 412 | static void __init t1023_init_periph(struct clockgen *cg) |
| 413 | { |
| 414 | cg->fman[0] = cg->hwaccel[1]; |
| 415 | } |
| 416 | |
| 417 | static void __init t1040_init_periph(struct clockgen *cg) |
| 418 | { |
| 419 | cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk; |
| 420 | } |
| 421 | |
| 422 | static void __init t2080_init_periph(struct clockgen *cg) |
| 423 | { |
| 424 | cg->fman[0] = cg->hwaccel[0]; |
| 425 | } |
| 426 | |
| 427 | static void __init t4240_init_periph(struct clockgen *cg) |
| 428 | { |
| 429 | cg->fman[0] = cg->hwaccel[3]; |
| 430 | cg->fman[1] = cg->hwaccel[4]; |
| 431 | } |
| 432 | |
| 433 | static const struct clockgen_chipinfo chipinfo[] = { |
| 434 | { |
| 435 | .compat = "fsl,b4420-clockgen", |
| 436 | .guts_compat = "fsl,b4860-device-config", |
| 437 | .init_periph = t2080_init_periph, |
| 438 | .cmux_groups = { |
| 439 | &clockgen2_cmux_cga12, &clockgen2_cmux_cgb |
| 440 | }, |
| 441 | .hwaccel = { |
| 442 | &t2080_hwa1 |
| 443 | }, |
| 444 | .cmux_to_group = { |
| 445 | 0, 1, 1, 1, -1 |
| 446 | }, |
| 447 | .pll_mask = 0x3f, |
| 448 | .flags = CG_PLL_8BIT, |
| 449 | }, |
| 450 | { |
| 451 | .compat = "fsl,b4860-clockgen", |
| 452 | .guts_compat = "fsl,b4860-device-config", |
| 453 | .init_periph = t2080_init_periph, |
| 454 | .cmux_groups = { |
| 455 | &clockgen2_cmux_cga12, &clockgen2_cmux_cgb |
| 456 | }, |
| 457 | .hwaccel = { |
| 458 | &t2080_hwa1 |
| 459 | }, |
| 460 | .cmux_to_group = { |
| 461 | 0, 1, 1, 1, -1 |
| 462 | }, |
| 463 | .pll_mask = 0x3f, |
| 464 | .flags = CG_PLL_8BIT, |
| 465 | }, |
| 466 | { |
| 467 | .compat = "fsl,ls1021a-clockgen", |
| 468 | .cmux_groups = { |
| 469 | &t1023_cmux |
| 470 | }, |
| 471 | .cmux_to_group = { |
| 472 | 0, -1 |
| 473 | }, |
| 474 | .pll_mask = 0x03, |
| 475 | }, |
| 476 | { |
Hou Zhiqiang | e994412c | 2015-10-23 16:01:21 +0800 | [diff] [blame] | 477 | .compat = "fsl,ls1043a-clockgen", |
| 478 | .init_periph = t2080_init_periph, |
| 479 | .cmux_groups = { |
| 480 | &t1040_cmux |
| 481 | }, |
| 482 | .hwaccel = { |
| 483 | &ls1043a_hwa1, &ls1043a_hwa2 |
| 484 | }, |
| 485 | .cmux_to_group = { |
| 486 | 0, -1 |
| 487 | }, |
| 488 | .pll_mask = 0x07, |
| 489 | .flags = CG_PLL_8BIT, |
| 490 | }, |
| 491 | { |
Scott Wood | 9e19ca2 | 2015-09-19 23:29:55 -0500 | [diff] [blame] | 492 | .compat = "fsl,ls2080a-clockgen", |
| 493 | .cmux_groups = { |
| 494 | &clockgen2_cmux_cga12, &clockgen2_cmux_cgb |
| 495 | }, |
| 496 | .cmux_to_group = { |
| 497 | 0, 0, 1, 1, -1 |
| 498 | }, |
| 499 | .pll_mask = 0x37, |
| 500 | .flags = CG_VER3 | CG_LITTLE_ENDIAN, |
| 501 | }, |
| 502 | { |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 503 | .compat = "fsl,p2041-clockgen", |
| 504 | .guts_compat = "fsl,qoriq-device-config-1.0", |
| 505 | .init_periph = p2041_init_periph, |
| 506 | .cmux_groups = { |
| 507 | &p2041_cmux_grp1, &p2041_cmux_grp2 |
| 508 | }, |
| 509 | .cmux_to_group = { |
| 510 | 0, 0, 1, 1, -1 |
| 511 | }, |
| 512 | .pll_mask = 0x07, |
| 513 | }, |
| 514 | { |
| 515 | .compat = "fsl,p3041-clockgen", |
| 516 | .guts_compat = "fsl,qoriq-device-config-1.0", |
| 517 | .init_periph = p2041_init_periph, |
| 518 | .cmux_groups = { |
| 519 | &p2041_cmux_grp1, &p2041_cmux_grp2 |
| 520 | }, |
| 521 | .cmux_to_group = { |
| 522 | 0, 0, 1, 1, -1 |
| 523 | }, |
| 524 | .pll_mask = 0x07, |
| 525 | }, |
| 526 | { |
| 527 | .compat = "fsl,p4080-clockgen", |
| 528 | .guts_compat = "fsl,qoriq-device-config-1.0", |
| 529 | .init_periph = p4080_init_periph, |
| 530 | .cmux_groups = { |
| 531 | &p4080_cmux_grp1, &p4080_cmux_grp2 |
| 532 | }, |
| 533 | .cmux_to_group = { |
| 534 | 0, 0, 0, 0, 1, 1, 1, 1 |
| 535 | }, |
| 536 | .pll_mask = 0x1f, |
| 537 | }, |
| 538 | { |
| 539 | .compat = "fsl,p5020-clockgen", |
| 540 | .guts_compat = "fsl,qoriq-device-config-1.0", |
| 541 | .init_periph = p5020_init_periph, |
| 542 | .cmux_groups = { |
| 543 | &p2041_cmux_grp1, &p2041_cmux_grp2 |
| 544 | }, |
| 545 | .cmux_to_group = { |
| 546 | 0, 1, -1 |
| 547 | }, |
| 548 | .pll_mask = 0x07, |
| 549 | }, |
| 550 | { |
| 551 | .compat = "fsl,p5040-clockgen", |
| 552 | .guts_compat = "fsl,p5040-device-config", |
| 553 | .init_periph = p5040_init_periph, |
| 554 | .cmux_groups = { |
| 555 | &p5040_cmux_grp1, &p5040_cmux_grp2 |
| 556 | }, |
| 557 | .cmux_to_group = { |
| 558 | 0, 0, 1, 1, -1 |
| 559 | }, |
| 560 | .pll_mask = 0x0f, |
| 561 | }, |
| 562 | { |
| 563 | .compat = "fsl,t1023-clockgen", |
| 564 | .guts_compat = "fsl,t1023-device-config", |
| 565 | .init_periph = t1023_init_periph, |
| 566 | .cmux_groups = { |
| 567 | &t1023_cmux |
| 568 | }, |
| 569 | .hwaccel = { |
| 570 | &t1023_hwa1, &t1023_hwa2 |
| 571 | }, |
| 572 | .cmux_to_group = { |
| 573 | 0, 0, -1 |
| 574 | }, |
| 575 | .pll_mask = 0x03, |
| 576 | .flags = CG_PLL_8BIT, |
| 577 | }, |
| 578 | { |
| 579 | .compat = "fsl,t1040-clockgen", |
| 580 | .guts_compat = "fsl,t1040-device-config", |
| 581 | .init_periph = t1040_init_periph, |
| 582 | .cmux_groups = { |
| 583 | &t1040_cmux |
| 584 | }, |
| 585 | .cmux_to_group = { |
| 586 | 0, 0, 0, 0, -1 |
| 587 | }, |
| 588 | .pll_mask = 0x07, |
| 589 | .flags = CG_PLL_8BIT, |
| 590 | }, |
| 591 | { |
| 592 | .compat = "fsl,t2080-clockgen", |
| 593 | .guts_compat = "fsl,t2080-device-config", |
| 594 | .init_periph = t2080_init_periph, |
| 595 | .cmux_groups = { |
| 596 | &clockgen2_cmux_cga12 |
| 597 | }, |
| 598 | .hwaccel = { |
| 599 | &t2080_hwa1, &t2080_hwa2 |
| 600 | }, |
| 601 | .cmux_to_group = { |
| 602 | 0, -1 |
| 603 | }, |
| 604 | .pll_mask = 0x07, |
| 605 | .flags = CG_PLL_8BIT, |
| 606 | }, |
| 607 | { |
| 608 | .compat = "fsl,t4240-clockgen", |
| 609 | .guts_compat = "fsl,t4240-device-config", |
| 610 | .init_periph = t4240_init_periph, |
| 611 | .cmux_groups = { |
| 612 | &clockgen2_cmux_cga, &clockgen2_cmux_cgb |
| 613 | }, |
| 614 | .hwaccel = { |
| 615 | &t4240_hwa1, NULL, NULL, &t4240_hwa4, &t4240_hwa5 |
| 616 | }, |
| 617 | .cmux_to_group = { |
| 618 | 0, 0, 1, -1 |
| 619 | }, |
| 620 | .pll_mask = 0x3f, |
| 621 | .flags = CG_PLL_8BIT, |
| 622 | }, |
| 623 | {}, |
| 624 | }; |
| 625 | |
| 626 | struct mux_hwclock { |
| 627 | struct clk_hw hw; |
| 628 | struct clockgen *cg; |
| 629 | const struct clockgen_muxinfo *info; |
| 630 | u32 __iomem *reg; |
| 631 | u8 parent_to_clksel[NUM_MUX_PARENTS]; |
| 632 | s8 clksel_to_parent[NUM_MUX_PARENTS]; |
| 633 | int num_parents; |
| 634 | }; |
| 635 | |
| 636 | #define to_mux_hwclock(p) container_of(p, struct mux_hwclock, hw) |
| 637 | #define CLKSEL_MASK 0x78000000 |
| 638 | #define CLKSEL_SHIFT 27 |
| 639 | |
| 640 | static int mux_set_parent(struct clk_hw *hw, u8 idx) |
| 641 | { |
| 642 | struct mux_hwclock *hwc = to_mux_hwclock(hw); |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 643 | u32 clksel; |
| 644 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 645 | if (idx >= hwc->num_parents) |
| 646 | return -EINVAL; |
| 647 | |
| 648 | clksel = hwc->parent_to_clksel[idx]; |
Scott Wood | 9e19ca2 | 2015-09-19 23:29:55 -0500 | [diff] [blame] | 649 | cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 650 | |
| 651 | return 0; |
| 652 | } |
| 653 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 654 | static u8 mux_get_parent(struct clk_hw *hw) |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 655 | { |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 656 | struct mux_hwclock *hwc = to_mux_hwclock(hw); |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 657 | u32 clksel; |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 658 | s8 ret; |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 659 | |
Scott Wood | 9e19ca2 | 2015-09-19 23:29:55 -0500 | [diff] [blame] | 660 | clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 661 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 662 | ret = hwc->clksel_to_parent[clksel]; |
| 663 | if (ret < 0) { |
| 664 | pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg); |
| 665 | return 0; |
| 666 | } |
| 667 | |
| 668 | return ret; |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 669 | } |
| 670 | |
Emil Medve | 334680d | 2015-01-21 04:03:27 -0600 | [diff] [blame] | 671 | static const struct clk_ops cmux_ops = { |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 672 | .get_parent = mux_get_parent, |
| 673 | .set_parent = mux_set_parent, |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 674 | }; |
| 675 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 676 | /* |
| 677 | * Don't allow setting for now, as the clock options haven't been |
| 678 | * sanitized for additional restrictions. |
| 679 | */ |
| 680 | static const struct clk_ops hwaccel_ops = { |
| 681 | .get_parent = mux_get_parent, |
| 682 | }; |
| 683 | |
| 684 | static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg, |
| 685 | struct mux_hwclock *hwc, |
| 686 | int idx) |
| 687 | { |
| 688 | int pll, div; |
| 689 | |
| 690 | if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) |
| 691 | return NULL; |
| 692 | |
| 693 | pll = hwc->info->clksel[idx].pll; |
| 694 | div = hwc->info->clksel[idx].div; |
| 695 | |
| 696 | return &cg->pll[pll].div[div]; |
| 697 | } |
| 698 | |
| 699 | static struct clk * __init create_mux_common(struct clockgen *cg, |
| 700 | struct mux_hwclock *hwc, |
| 701 | const struct clk_ops *ops, |
| 702 | unsigned long min_rate, |
| 703 | unsigned long pct80_rate, |
| 704 | const char *fmt, int idx) |
| 705 | { |
| 706 | struct clk_init_data init = {}; |
| 707 | struct clk *clk; |
| 708 | const struct clockgen_pll_div *div; |
| 709 | const char *parent_names[NUM_MUX_PARENTS]; |
| 710 | char name[32]; |
| 711 | int i, j; |
| 712 | |
| 713 | snprintf(name, sizeof(name), fmt, idx); |
| 714 | |
| 715 | for (i = 0, j = 0; i < NUM_MUX_PARENTS; i++) { |
| 716 | unsigned long rate; |
| 717 | |
| 718 | hwc->clksel_to_parent[i] = -1; |
| 719 | |
| 720 | div = get_pll_div(cg, hwc, i); |
| 721 | if (!div) |
| 722 | continue; |
| 723 | |
| 724 | rate = clk_get_rate(div->clk); |
| 725 | |
| 726 | if (hwc->info->clksel[i].flags & CLKSEL_80PCT && |
| 727 | rate > pct80_rate) |
| 728 | continue; |
| 729 | if (rate < min_rate) |
| 730 | continue; |
| 731 | |
| 732 | parent_names[j] = div->name; |
| 733 | hwc->parent_to_clksel[j] = i; |
| 734 | hwc->clksel_to_parent[i] = j; |
| 735 | j++; |
| 736 | } |
| 737 | |
| 738 | init.name = name; |
| 739 | init.ops = ops; |
| 740 | init.parent_names = parent_names; |
| 741 | init.num_parents = hwc->num_parents = j; |
| 742 | init.flags = 0; |
| 743 | hwc->hw.init = &init; |
| 744 | hwc->cg = cg; |
| 745 | |
| 746 | clk = clk_register(NULL, &hwc->hw); |
| 747 | if (IS_ERR(clk)) { |
| 748 | pr_err("%s: Couldn't register %s: %ld\n", __func__, name, |
| 749 | PTR_ERR(clk)); |
| 750 | kfree(hwc); |
| 751 | return NULL; |
| 752 | } |
| 753 | |
| 754 | return clk; |
| 755 | } |
| 756 | |
| 757 | static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) |
| 758 | { |
| 759 | struct mux_hwclock *hwc; |
| 760 | const struct clockgen_pll_div *div; |
| 761 | unsigned long plat_rate, min_rate; |
| 762 | u64 pct80_rate; |
| 763 | u32 clksel; |
| 764 | |
| 765 | hwc = kzalloc(sizeof(*hwc), GFP_KERNEL); |
| 766 | if (!hwc) |
| 767 | return NULL; |
| 768 | |
| 769 | hwc->reg = cg->regs + 0x20 * idx; |
| 770 | hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]]; |
| 771 | |
| 772 | /* |
| 773 | * Find the rate for the default clksel, and treat it as the |
| 774 | * maximum rated core frequency. If this is an incorrect |
| 775 | * assumption, certain clock options (possibly including the |
| 776 | * default clksel) may be inappropriately excluded on certain |
| 777 | * chips. |
| 778 | */ |
Scott Wood | 9e19ca2 | 2015-09-19 23:29:55 -0500 | [diff] [blame] | 779 | clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 780 | div = get_pll_div(cg, hwc, clksel); |
| 781 | if (!div) |
| 782 | return NULL; |
| 783 | |
| 784 | pct80_rate = clk_get_rate(div->clk); |
| 785 | pct80_rate *= 8; |
| 786 | do_div(pct80_rate, 10); |
| 787 | |
| 788 | plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk); |
| 789 | |
| 790 | if (cg->info.flags & CG_CMUX_GE_PLAT) |
| 791 | min_rate = plat_rate; |
| 792 | else |
| 793 | min_rate = plat_rate / 2; |
| 794 | |
| 795 | return create_mux_common(cg, hwc, &cmux_ops, min_rate, |
| 796 | pct80_rate, "cg-cmux%d", idx); |
| 797 | } |
| 798 | |
| 799 | static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx) |
| 800 | { |
| 801 | struct mux_hwclock *hwc; |
| 802 | |
| 803 | hwc = kzalloc(sizeof(*hwc), GFP_KERNEL); |
| 804 | if (!hwc) |
| 805 | return NULL; |
| 806 | |
| 807 | hwc->reg = cg->regs + 0x20 * idx + 0x10; |
| 808 | hwc->info = cg->info.hwaccel[idx]; |
| 809 | |
| 810 | return create_mux_common(cg, hwc, &hwaccel_ops, 0, 0, |
| 811 | "cg-hwaccel%d", idx); |
| 812 | } |
| 813 | |
| 814 | static void __init create_muxes(struct clockgen *cg) |
| 815 | { |
| 816 | int i; |
| 817 | |
| 818 | for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) { |
| 819 | if (cg->info.cmux_to_group[i] < 0) |
| 820 | break; |
| 821 | if (cg->info.cmux_to_group[i] >= |
| 822 | ARRAY_SIZE(cg->info.cmux_groups)) { |
| 823 | WARN_ON_ONCE(1); |
| 824 | continue; |
| 825 | } |
| 826 | |
| 827 | cg->cmux[i] = create_one_cmux(cg, i); |
| 828 | } |
| 829 | |
| 830 | for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) { |
| 831 | if (!cg->info.hwaccel[i]) |
| 832 | continue; |
| 833 | |
| 834 | cg->hwaccel[i] = create_one_hwaccel(cg, i); |
| 835 | } |
| 836 | } |
| 837 | |
| 838 | static void __init clockgen_init(struct device_node *np); |
| 839 | |
| 840 | /* Legacy nodes may get probed before the parent clockgen node */ |
| 841 | static void __init legacy_init_clockgen(struct device_node *np) |
| 842 | { |
| 843 | if (!clockgen.node) |
| 844 | clockgen_init(of_get_parent(np)); |
| 845 | } |
| 846 | |
| 847 | /* Legacy node */ |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 848 | static void __init core_mux_init(struct device_node *np) |
| 849 | { |
| 850 | struct clk *clk; |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 851 | struct resource res; |
| 852 | int idx, rc; |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 853 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 854 | legacy_init_clockgen(np); |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 855 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 856 | if (of_address_to_resource(np, 0, &res)) |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 857 | return; |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 858 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 859 | idx = (res.start & 0xf0) >> 5; |
| 860 | clk = clockgen.cmux[idx]; |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 861 | |
| 862 | rc = of_clk_add_provider(np, of_clk_src_simple_get, clk); |
| 863 | if (rc) { |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 864 | pr_err("%s: Couldn't register clk provider for node %s: %d\n", |
| 865 | __func__, np->name, rc); |
| 866 | return; |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 867 | } |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 868 | } |
| 869 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 870 | static struct clk *sysclk_from_fixed(struct device_node *node, const char *name) |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 871 | { |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 872 | u32 rate; |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 873 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 874 | if (of_property_read_u32(node, "clock-frequency", &rate)) |
| 875 | return ERR_PTR(-ENODEV); |
| 876 | |
| 877 | return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); |
| 878 | } |
| 879 | |
| 880 | static struct clk *sysclk_from_parent(const char *name) |
| 881 | { |
| 882 | struct clk *clk; |
| 883 | const char *parent_name; |
| 884 | |
| 885 | clk = of_clk_get(clockgen.node, 0); |
| 886 | if (IS_ERR(clk)) |
| 887 | return clk; |
| 888 | |
| 889 | /* Register the input clock under the desired name. */ |
| 890 | parent_name = __clk_get_name(clk); |
| 891 | clk = clk_register_fixed_factor(NULL, name, parent_name, |
| 892 | 0, 1, 1); |
| 893 | if (IS_ERR(clk)) |
| 894 | pr_err("%s: Couldn't register %s: %ld\n", __func__, name, |
| 895 | PTR_ERR(clk)); |
| 896 | |
| 897 | return clk; |
| 898 | } |
| 899 | |
| 900 | static struct clk * __init create_sysclk(const char *name) |
| 901 | { |
| 902 | struct device_node *sysclk; |
| 903 | struct clk *clk; |
| 904 | |
| 905 | clk = sysclk_from_fixed(clockgen.node, name); |
| 906 | if (!IS_ERR(clk)) |
| 907 | return clk; |
| 908 | |
| 909 | clk = sysclk_from_parent(name); |
| 910 | if (!IS_ERR(clk)) |
| 911 | return clk; |
| 912 | |
| 913 | sysclk = of_get_child_by_name(clockgen.node, "sysclk"); |
| 914 | if (sysclk) { |
| 915 | clk = sysclk_from_fixed(sysclk, name); |
| 916 | if (!IS_ERR(clk)) |
| 917 | return clk; |
| 918 | } |
| 919 | |
| 920 | pr_err("%s: No input clock\n", __func__); |
| 921 | return NULL; |
| 922 | } |
| 923 | |
| 924 | /* Legacy node */ |
| 925 | static void __init sysclk_init(struct device_node *node) |
| 926 | { |
| 927 | struct clk *clk; |
| 928 | |
| 929 | legacy_init_clockgen(node); |
| 930 | |
| 931 | clk = clockgen.sysclk; |
| 932 | if (clk) |
| 933 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 934 | } |
| 935 | |
| 936 | #define PLL_KILL BIT(31) |
| 937 | |
| 938 | static void __init create_one_pll(struct clockgen *cg, int idx) |
| 939 | { |
| 940 | u32 __iomem *reg; |
| 941 | u32 mult; |
| 942 | struct clockgen_pll *pll = &cg->pll[idx]; |
| 943 | int i; |
| 944 | |
| 945 | if (!(cg->info.pll_mask & (1 << idx))) |
| 946 | return; |
| 947 | |
Scott Wood | 9e19ca2 | 2015-09-19 23:29:55 -0500 | [diff] [blame] | 948 | if (cg->info.flags & CG_VER3) { |
| 949 | switch (idx) { |
| 950 | case PLATFORM_PLL: |
| 951 | reg = cg->regs + 0x60080; |
| 952 | break; |
| 953 | case CGA_PLL1: |
| 954 | reg = cg->regs + 0x80; |
| 955 | break; |
| 956 | case CGA_PLL2: |
| 957 | reg = cg->regs + 0xa0; |
| 958 | break; |
| 959 | case CGB_PLL1: |
| 960 | reg = cg->regs + 0x10080; |
| 961 | break; |
| 962 | case CGB_PLL2: |
| 963 | reg = cg->regs + 0x100a0; |
| 964 | break; |
| 965 | default: |
| 966 | WARN_ONCE(1, "index %d\n", idx); |
| 967 | return; |
| 968 | } |
| 969 | } else { |
| 970 | if (idx == PLATFORM_PLL) |
| 971 | reg = cg->regs + 0xc00; |
| 972 | else |
| 973 | reg = cg->regs + 0x800 + 0x20 * (idx - 1); |
| 974 | } |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 975 | |
| 976 | /* Get the multiple of PLL */ |
Scott Wood | 9e19ca2 | 2015-09-19 23:29:55 -0500 | [diff] [blame] | 977 | mult = cg_in(cg, reg); |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 978 | |
| 979 | /* Check if this PLL is disabled */ |
| 980 | if (mult & PLL_KILL) { |
| 981 | pr_debug("%s(): pll %p disabled\n", __func__, reg); |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 982 | return; |
| 983 | } |
| 984 | |
Scott Wood | 9e19ca2 | 2015-09-19 23:29:55 -0500 | [diff] [blame] | 985 | if ((cg->info.flags & CG_VER3) || |
| 986 | ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL)) |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 987 | mult = (mult & GENMASK(8, 1)) >> 1; |
| 988 | else |
| 989 | mult = (mult & GENMASK(6, 1)) >> 1; |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 990 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 991 | for (i = 0; i < ARRAY_SIZE(pll->div); i++) { |
| 992 | struct clk *clk; |
| 993 | |
| 994 | snprintf(pll->div[i].name, sizeof(pll->div[i].name), |
| 995 | "cg-pll%d-div%d", idx, i + 1); |
| 996 | |
| 997 | clk = clk_register_fixed_factor(NULL, |
| 998 | pll->div[i].name, "cg-sysclk", 0, mult, i + 1); |
| 999 | if (IS_ERR(clk)) { |
| 1000 | pr_err("%s: %s: register failed %ld\n", |
| 1001 | __func__, pll->div[i].name, PTR_ERR(clk)); |
| 1002 | continue; |
| 1003 | } |
| 1004 | |
| 1005 | pll->div[i].clk = clk; |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 1006 | } |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1007 | } |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 1008 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1009 | static void __init create_plls(struct clockgen *cg) |
| 1010 | { |
| 1011 | int i; |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 1012 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1013 | for (i = 0; i < ARRAY_SIZE(cg->pll); i++) |
| 1014 | create_one_pll(cg, i); |
| 1015 | } |
| 1016 | |
| 1017 | static void __init legacy_pll_init(struct device_node *np, int idx) |
| 1018 | { |
| 1019 | struct clockgen_pll *pll; |
| 1020 | struct clk_onecell_data *onecell_data; |
| 1021 | struct clk **subclks; |
| 1022 | int count, rc; |
| 1023 | |
| 1024 | legacy_init_clockgen(np); |
| 1025 | |
| 1026 | pll = &clockgen.pll[idx]; |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 1027 | count = of_property_count_strings(np, "clock-output-names"); |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 1028 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1029 | BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4); |
| 1030 | subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL); |
Emil Medve | 8002cab | 2015-01-21 04:03:26 -0600 | [diff] [blame] | 1031 | if (!subclks) |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1032 | return; |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 1033 | |
Emil Medve | 6ef1cca | 2015-01-21 04:03:28 -0600 | [diff] [blame] | 1034 | onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL); |
Emil Medve | 8002cab | 2015-01-21 04:03:26 -0600 | [diff] [blame] | 1035 | if (!onecell_data) |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 1036 | goto err_clks; |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 1037 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1038 | if (count <= 3) { |
| 1039 | subclks[0] = pll->div[0].clk; |
| 1040 | subclks[1] = pll->div[1].clk; |
| 1041 | subclks[2] = pll->div[3].clk; |
| 1042 | } else { |
| 1043 | subclks[0] = pll->div[0].clk; |
| 1044 | subclks[1] = pll->div[1].clk; |
| 1045 | subclks[2] = pll->div[2].clk; |
| 1046 | subclks[3] = pll->div[3].clk; |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 1047 | } |
| 1048 | |
| 1049 | onecell_data->clks = subclks; |
| 1050 | onecell_data->clk_num = count; |
| 1051 | |
| 1052 | rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data); |
| 1053 | if (rc) { |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1054 | pr_err("%s: Couldn't register clk provider for node %s: %d\n", |
| 1055 | __func__, np->name, rc); |
Tang Yuantian | 555eae9 | 2013-04-09 16:46:26 +0800 | [diff] [blame] | 1056 | goto err_cell; |
| 1057 | } |
| 1058 | |
| 1059 | return; |
| 1060 | err_cell: |
| 1061 | kfree(onecell_data); |
| 1062 | err_clks: |
| 1063 | kfree(subclks); |
Tang Yuantian | 00fa6e5 | 2014-01-21 09:32:45 +0800 | [diff] [blame] | 1064 | } |
| 1065 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1066 | /* Legacy node */ |
Emil Medve | a513b72 | 2015-01-21 04:03:31 -0600 | [diff] [blame] | 1067 | static void __init pltfrm_pll_init(struct device_node *np) |
| 1068 | { |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1069 | legacy_pll_init(np, PLATFORM_PLL); |
| 1070 | } |
Emil Medve | a513b72 | 2015-01-21 04:03:31 -0600 | [diff] [blame] | 1071 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1072 | /* Legacy node */ |
| 1073 | static void __init core_pll_init(struct device_node *np) |
| 1074 | { |
| 1075 | struct resource res; |
| 1076 | int idx; |
| 1077 | |
| 1078 | if (of_address_to_resource(np, 0, &res)) |
| 1079 | return; |
| 1080 | |
| 1081 | if ((res.start & 0xfff) == 0xc00) { |
| 1082 | /* |
| 1083 | * ls1021a devtree labels the platform PLL |
| 1084 | * with the core PLL compatible |
| 1085 | */ |
| 1086 | pltfrm_pll_init(np); |
| 1087 | } else { |
| 1088 | idx = (res.start & 0xf0) >> 5; |
| 1089 | legacy_pll_init(np, CGA_PLL1 + idx); |
| 1090 | } |
| 1091 | } |
| 1092 | |
| 1093 | static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data) |
| 1094 | { |
| 1095 | struct clockgen *cg = data; |
| 1096 | struct clk *clk; |
| 1097 | struct clockgen_pll *pll; |
| 1098 | u32 type, idx; |
| 1099 | |
| 1100 | if (clkspec->args_count < 2) { |
| 1101 | pr_err("%s: insufficient phandle args\n", __func__); |
| 1102 | return ERR_PTR(-EINVAL); |
| 1103 | } |
| 1104 | |
| 1105 | type = clkspec->args[0]; |
| 1106 | idx = clkspec->args[1]; |
| 1107 | |
| 1108 | switch (type) { |
| 1109 | case 0: |
| 1110 | if (idx != 0) |
| 1111 | goto bad_args; |
| 1112 | clk = cg->sysclk; |
| 1113 | break; |
| 1114 | case 1: |
| 1115 | if (idx >= ARRAY_SIZE(cg->cmux)) |
| 1116 | goto bad_args; |
| 1117 | clk = cg->cmux[idx]; |
| 1118 | break; |
| 1119 | case 2: |
| 1120 | if (idx >= ARRAY_SIZE(cg->hwaccel)) |
| 1121 | goto bad_args; |
| 1122 | clk = cg->hwaccel[idx]; |
| 1123 | break; |
| 1124 | case 3: |
| 1125 | if (idx >= ARRAY_SIZE(cg->fman)) |
| 1126 | goto bad_args; |
| 1127 | clk = cg->fman[idx]; |
| 1128 | break; |
| 1129 | case 4: |
| 1130 | pll = &cg->pll[PLATFORM_PLL]; |
| 1131 | if (idx >= ARRAY_SIZE(pll->div)) |
| 1132 | goto bad_args; |
| 1133 | clk = pll->div[idx].clk; |
| 1134 | break; |
| 1135 | default: |
| 1136 | goto bad_args; |
| 1137 | } |
| 1138 | |
| 1139 | if (!clk) |
| 1140 | return ERR_PTR(-ENOENT); |
| 1141 | return clk; |
| 1142 | |
| 1143 | bad_args: |
| 1144 | pr_err("%s: Bad phandle args %u %u\n", __func__, type, idx); |
| 1145 | return ERR_PTR(-EINVAL); |
| 1146 | } |
| 1147 | |
| 1148 | #ifdef CONFIG_PPC |
| 1149 | #include <asm/mpc85xx.h> |
| 1150 | |
| 1151 | static const u32 a4510_svrs[] __initconst = { |
| 1152 | (SVR_P2040 << 8) | 0x10, /* P2040 1.0 */ |
| 1153 | (SVR_P2040 << 8) | 0x11, /* P2040 1.1 */ |
| 1154 | (SVR_P2041 << 8) | 0x10, /* P2041 1.0 */ |
| 1155 | (SVR_P2041 << 8) | 0x11, /* P2041 1.1 */ |
| 1156 | (SVR_P3041 << 8) | 0x10, /* P3041 1.0 */ |
| 1157 | (SVR_P3041 << 8) | 0x11, /* P3041 1.1 */ |
| 1158 | (SVR_P4040 << 8) | 0x20, /* P4040 2.0 */ |
| 1159 | (SVR_P4080 << 8) | 0x20, /* P4080 2.0 */ |
| 1160 | (SVR_P5010 << 8) | 0x10, /* P5010 1.0 */ |
| 1161 | (SVR_P5010 << 8) | 0x20, /* P5010 2.0 */ |
| 1162 | (SVR_P5020 << 8) | 0x10, /* P5020 1.0 */ |
| 1163 | (SVR_P5021 << 8) | 0x10, /* P5021 1.0 */ |
| 1164 | (SVR_P5040 << 8) | 0x10, /* P5040 1.0 */ |
| 1165 | }; |
| 1166 | |
| 1167 | #define SVR_SECURITY 0x80000 /* The Security (E) bit */ |
| 1168 | |
| 1169 | static bool __init has_erratum_a4510(void) |
| 1170 | { |
| 1171 | u32 svr = mfspr(SPRN_SVR); |
| 1172 | int i; |
| 1173 | |
| 1174 | svr &= ~SVR_SECURITY; |
| 1175 | |
| 1176 | for (i = 0; i < ARRAY_SIZE(a4510_svrs); i++) { |
| 1177 | if (svr == a4510_svrs[i]) |
| 1178 | return true; |
| 1179 | } |
| 1180 | |
| 1181 | return false; |
| 1182 | } |
| 1183 | #else |
| 1184 | static bool __init has_erratum_a4510(void) |
| 1185 | { |
| 1186 | return false; |
| 1187 | } |
| 1188 | #endif |
| 1189 | |
| 1190 | static void __init clockgen_init(struct device_node *np) |
| 1191 | { |
| 1192 | int i, ret; |
| 1193 | bool is_old_ls1021a = false; |
| 1194 | |
| 1195 | /* May have already been called by a legacy probe */ |
| 1196 | if (clockgen.node) |
| 1197 | return; |
| 1198 | |
| 1199 | clockgen.node = np; |
| 1200 | clockgen.regs = of_iomap(np, 0); |
| 1201 | if (!clockgen.regs && |
| 1202 | of_device_is_compatible(of_root, "fsl,ls1021a")) { |
| 1203 | /* Compatibility hack for old, broken device trees */ |
| 1204 | clockgen.regs = ioremap(0x1ee1000, 0x1000); |
| 1205 | is_old_ls1021a = true; |
| 1206 | } |
| 1207 | if (!clockgen.regs) { |
Emil Medve | a513b72 | 2015-01-21 04:03:31 -0600 | [diff] [blame] | 1208 | pr_err("%s(): %s: of_iomap() failed\n", __func__, np->name); |
| 1209 | return; |
| 1210 | } |
| 1211 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1212 | for (i = 0; i < ARRAY_SIZE(chipinfo); i++) { |
| 1213 | if (of_device_is_compatible(np, chipinfo[i].compat)) |
| 1214 | break; |
| 1215 | if (is_old_ls1021a && |
| 1216 | !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen")) |
| 1217 | break; |
Emil Medve | a513b72 | 2015-01-21 04:03:31 -0600 | [diff] [blame] | 1218 | } |
| 1219 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1220 | if (i == ARRAY_SIZE(chipinfo)) { |
| 1221 | pr_err("%s: unknown clockgen node %s\n", __func__, |
| 1222 | np->full_name); |
| 1223 | goto err; |
Emil Medve | a513b72 | 2015-01-21 04:03:31 -0600 | [diff] [blame] | 1224 | } |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1225 | clockgen.info = chipinfo[i]; |
Emil Medve | a513b72 | 2015-01-21 04:03:31 -0600 | [diff] [blame] | 1226 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1227 | if (clockgen.info.guts_compat) { |
| 1228 | struct device_node *guts; |
Emil Medve | a513b72 | 2015-01-21 04:03:31 -0600 | [diff] [blame] | 1229 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1230 | guts = of_find_compatible_node(NULL, NULL, |
| 1231 | clockgen.info.guts_compat); |
| 1232 | if (guts) { |
| 1233 | clockgen.guts = of_iomap(guts, 0); |
| 1234 | if (!clockgen.guts) { |
| 1235 | pr_err("%s: Couldn't map %s regs\n", __func__, |
| 1236 | guts->full_name); |
| 1237 | } |
Emil Medve | a513b72 | 2015-01-21 04:03:31 -0600 | [diff] [blame] | 1238 | } |
| 1239 | |
Emil Medve | a513b72 | 2015-01-21 04:03:31 -0600 | [diff] [blame] | 1240 | } |
| 1241 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1242 | if (has_erratum_a4510()) |
| 1243 | clockgen.info.flags |= CG_CMUX_GE_PLAT; |
| 1244 | |
| 1245 | clockgen.sysclk = create_sysclk("cg-sysclk"); |
| 1246 | create_plls(&clockgen); |
| 1247 | create_muxes(&clockgen); |
| 1248 | |
| 1249 | if (clockgen.info.init_periph) |
| 1250 | clockgen.info.init_periph(&clockgen); |
| 1251 | |
| 1252 | ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen); |
| 1253 | if (ret) { |
| 1254 | pr_err("%s: Couldn't register clk provider for node %s: %d\n", |
| 1255 | __func__, np->name, ret); |
Emil Medve | a513b72 | 2015-01-21 04:03:31 -0600 | [diff] [blame] | 1256 | } |
| 1257 | |
| 1258 | return; |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1259 | err: |
| 1260 | iounmap(clockgen.regs); |
| 1261 | clockgen.regs = NULL; |
Emil Medve | a513b72 | 2015-01-21 04:03:31 -0600 | [diff] [blame] | 1262 | } |
| 1263 | |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1264 | CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init); |
| 1265 | CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init); |
| 1266 | CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init); |
Hou Zhiqiang | e994412c | 2015-10-23 16:01:21 +0800 | [diff] [blame] | 1267 | CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init); |
Scott Wood | 9e19ca2 | 2015-09-19 23:29:55 -0500 | [diff] [blame] | 1268 | CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init); |
Scott Wood | 0dfc86b | 2015-09-19 23:29:54 -0500 | [diff] [blame] | 1269 | |
| 1270 | /* Legacy nodes */ |
Kevin Hao | 66619ac | 2014-12-03 16:53:53 +0800 | [diff] [blame] | 1271 | CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init); |
| 1272 | CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init); |
| 1273 | CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init); |
| 1274 | CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init); |
| 1275 | CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init); |
| 1276 | CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init); |
Emil Medve | a513b72 | 2015-01-21 04:03:31 -0600 | [diff] [blame] | 1277 | CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init); |
| 1278 | CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init); |