blob: 9004c64b169e05c37394bd742ae0f1042b8a2eb1 [file] [log] [blame]
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001/*
2 * Intel 7300 class Memory Controllers kernel module (Clarksboro)
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License version 2 only.
6 *
7 * Copyright (c) 2010 by:
8 * Mauro Carvalho Chehab <mchehab@redhat.com>
9 *
10 * Red Hat Inc. http://www.redhat.com
11 *
12 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
13 * http://www.intel.com/Assets/PDF/datasheet/318082.pdf
14 *
15 * TODO: The chipset allow checking for PCI Express errors also. Currently,
16 * the driver covers only memory error errors
17 *
18 * This driver uses "csrows" EDAC attribute to represent DIMM slot#
19 */
20
21#include <linux/module.h>
22#include <linux/init.h>
23#include <linux/pci.h>
24#include <linux/pci_ids.h>
25#include <linux/slab.h>
26#include <linux/edac.h>
27#include <linux/mmzone.h>
28
29#include "edac_core.h"
30
31/*
32 * Alter this version for the I7300 module when modifications are made
33 */
Michal Marek152ba392011-04-01 12:41:20 +020034#define I7300_REVISION " Ver: 1.0.0"
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -030035
36#define EDAC_MOD_STR "i7300_edac"
37
38#define i7300_printk(level, fmt, arg...) \
39 edac_printk(level, "i7300", fmt, ##arg)
40
41#define i7300_mc_printk(mci, level, fmt, arg...) \
42 edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg)
43
Mauro Carvalho Chehabb4552ac2010-08-27 16:43:01 -030044/***********************************************
45 * i7300 Limit constants Structs and static vars
46 ***********************************************/
47
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -030048/*
49 * Memory topology is organized as:
50 * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
51 * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
52 * Each channel can have to 8 DIMM sets (called as SLOTS)
53 * Slots should generally be filled in pairs
54 * Except on Single Channel mode of operation
55 * just slot 0/channel0 filled on this mode
56 * On normal operation mode, the two channels on a branch should be
Mauro Carvalho Chehabc3af2ea2010-08-26 19:54:51 -030057 * filled together for the same SLOT#
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -030058 * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four
59 * channels on both branches should be filled
60 */
61
62/* Limits for i7300 */
63#define MAX_SLOTS 8
64#define MAX_BRANCHES 2
65#define MAX_CH_PER_BRANCH 2
66#define MAX_CHANNELS (MAX_CH_PER_BRANCH * MAX_BRANCHES)
67#define MAX_MIR 3
68
69#define to_channel(ch, branch) ((((branch)) << 1) | (ch))
70
71#define to_csrow(slot, ch, branch) \
72 (to_channel(ch, branch) | ((slot) << 2))
73
Mauro Carvalho Chehabb4552ac2010-08-27 16:43:01 -030074/* Device name and register DID (Device ID) */
75struct i7300_dev_info {
76 const char *ctl_name; /* name for this device */
77 u16 fsb_mapping_errors; /* DID for the branchmap,control */
78};
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -030079
Mauro Carvalho Chehabb4552ac2010-08-27 16:43:01 -030080/* Table of devices attributes supported by this driver */
81static const struct i7300_dev_info i7300_devs[] = {
82 {
83 .ctl_name = "I7300",
84 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR,
85 },
86};
87
88struct i7300_dimm_info {
89 int megabytes; /* size, 0 means not present */
90};
91
92/* driver private data structure */
93struct i7300_pvt {
94 struct pci_dev *pci_dev_16_0_fsb_ctlr; /* 16.0 */
95 struct pci_dev *pci_dev_16_1_fsb_addr_map; /* 16.1 */
96 struct pci_dev *pci_dev_16_2_fsb_err_regs; /* 16.2 */
97 struct pci_dev *pci_dev_2x_0_fbd_branch[MAX_BRANCHES]; /* 21.0 and 22.0 */
98
99 u16 tolm; /* top of low memory */
100 u64 ambase; /* AMB BAR */
101
102 u32 mc_settings; /* Report several settings */
103 u32 mc_settings_a;
104
105 u16 mir[MAX_MIR]; /* Memory Interleave Reg*/
106
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300107 u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */
Mauro Carvalho Chehabb4552ac2010-08-27 16:43:01 -0300108 u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */
109
110 /* DIMM information matrix, allocating architecture maximums */
111 struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS];
112
113 /* Temporary buffer for use when preparing error messages */
114 char *tmp_prt_buffer;
115};
116
117/* FIXME: Why do we need to have this static? */
118static struct edac_pci_ctl_info *i7300_pci;
119
120/***************************************************
121 * i7300 Register definitions for memory enumeration
122 ***************************************************/
123
124/*
Mauro Carvalho Chehabc3af2ea2010-08-26 19:54:51 -0300125 * Device 16,
126 * Function 0: System Address (not documented)
127 * Function 1: Memory Branch Map, Control, Errors Register
128 */
129
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300130 /* OFFSETS for Function 0 */
Mauro Carvalho Chehabaf3d8832010-08-26 20:58:45 -0300131#define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */
132#define MAXCH 0x56 /* Max Channel Number */
133#define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300134
135 /* OFFSETS for Function 1 */
Mauro Carvalho Chehabaf3d8832010-08-26 20:58:45 -0300136#define MC_SETTINGS 0x40
Mauro Carvalho Chehabbb81a212010-08-27 09:04:11 -0300137 #define IS_MIRRORED(mc) ((mc) & (1 << 16))
138 #define IS_ECC_ENABLED(mc) ((mc) & (1 << 5))
139 #define IS_RETRY_ENABLED(mc) ((mc) & (1 << 31))
140 #define IS_SCRBALGO_ENHANCED(mc) ((mc) & (1 << 8))
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300141
Mauro Carvalho Chehabbb81a212010-08-27 09:04:11 -0300142#define MC_SETTINGS_A 0x58
143 #define IS_SINGLE_MODE(mca) ((mca) & (1 << 14))
Mauro Carvalho Chehabd7de2bd2010-08-27 08:56:48 -0300144
Mauro Carvalho Chehabaf3d8832010-08-26 20:58:45 -0300145#define TOLM 0x6C
Mauro Carvalho Chehabaf3d8832010-08-26 20:58:45 -0300146
147#define MIR0 0x80
148#define MIR1 0x84
149#define MIR2 0x88
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300150
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300151/*
152 * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available
153 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
154 * seems that we cannot use this information directly for the same usage.
155 * Each memory slot may have up to 2 AMB interfaces, one for income and another
156 * for outcome interface to the next slot.
157 * For now, the driver just stores the AMB present registers, but rely only at
158 * the MTR info to detect memory.
159 * Datasheet is also not clear about how to map each AMBPRESENT registers to
160 * one of the 4 available channels.
161 */
162#define AMBPRESENT_0 0x64
163#define AMBPRESENT_1 0x66
164
Jesper Juhl42b16b32011-01-17 00:09:38 +0100165static const u16 mtr_regs[MAX_SLOTS] = {
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300166 0x80, 0x84, 0x88, 0x8c,
167 0x82, 0x86, 0x8a, 0x8e
168};
169
Mauro Carvalho Chehabb4552ac2010-08-27 16:43:01 -0300170/*
171 * Defines to extract the vaious fields from the
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300172 * MTRx - Memory Technology Registers
173 */
174#define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8))
175#define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7))
176#define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4)
177#define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4)
178#define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0)
179#define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
180#define MTR_DRAM_BANKS_ADDR_BITS 2
181#define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
182#define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
183#define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
184
Mauro Carvalho Chehabc3af2ea2010-08-26 19:54:51 -0300185/************************************************
186 * i7300 Register definitions for error detection
187 ************************************************/
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300188
189/*
190 * Device 16.1: FBD Error Registers
191 */
192#define FERR_FAT_FBD 0x98
193static const char *ferr_fat_fbd_name[] = {
194 [22] = "Non-Redundant Fast Reset Timeout",
195 [2] = ">Tmid Thermal event with intelligent throttling disabled",
196 [1] = "Memory or FBD configuration CRC read error",
197 [0] = "Memory Write error on non-redundant retry or "
198 "FBD configuration Write error on retry",
199};
Jean Delvare7e06b7a2012-10-18 15:54:45 +0200200#define GET_FBD_FAT_IDX(fbderr) (((fbderr) >> 28) & 3)
201#define FERR_FAT_FBD_ERR_MASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 22))
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300202
203#define FERR_NF_FBD 0xa0
204static const char *ferr_nf_fbd_name[] = {
205 [24] = "DIMM-Spare Copy Completed",
206 [23] = "DIMM-Spare Copy Initiated",
207 [22] = "Redundant Fast Reset Timeout",
208 [21] = "Memory Write error on redundant retry",
209 [18] = "SPD protocol Error",
210 [17] = "FBD Northbound parity error on FBD Sync Status",
211 [16] = "Correctable Patrol Data ECC",
212 [15] = "Correctable Resilver- or Spare-Copy Data ECC",
213 [14] = "Correctable Mirrored Demand Data ECC",
214 [13] = "Correctable Non-Mirrored Demand Data ECC",
215 [11] = "Memory or FBD configuration CRC read error",
216 [10] = "FBD Configuration Write error on first attempt",
217 [9] = "Memory Write error on first attempt",
218 [8] = "Non-Aliased Uncorrectable Patrol Data ECC",
219 [7] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
220 [6] = "Non-Aliased Uncorrectable Mirrored Demand Data ECC",
221 [5] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC",
222 [4] = "Aliased Uncorrectable Patrol Data ECC",
223 [3] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
224 [2] = "Aliased Uncorrectable Mirrored Demand Data ECC",
225 [1] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC",
226 [0] = "Uncorrectable Data ECC on Replay",
227};
Jean Delvare7e06b7a2012-10-18 15:54:45 +0200228#define GET_FBD_NF_IDX(fbderr) (((fbderr) >> 28) & 3)
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300229#define FERR_NF_FBD_ERR_MASK ((1 << 24) | (1 << 23) | (1 << 22) | (1 << 21) |\
230 (1 << 18) | (1 << 17) | (1 << 16) | (1 << 15) |\
231 (1 << 14) | (1 << 13) | (1 << 11) | (1 << 10) |\
232 (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\
233 (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\
234 (1 << 1) | (1 << 0))
235
236#define EMASK_FBD 0xa8
237#define EMASK_FBD_ERR_MASK ((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24) |\
238 (1 << 22) | (1 << 21) | (1 << 20) | (1 << 19) |\
239 (1 << 18) | (1 << 17) | (1 << 16) | (1 << 14) |\
240 (1 << 13) | (1 << 12) | (1 << 11) | (1 << 10) |\
241 (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\
242 (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\
243 (1 << 1) | (1 << 0))
244
Mauro Carvalho Chehabc3af2ea2010-08-26 19:54:51 -0300245/*
246 * Device 16.2: Global Error Registers
247 */
248
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300249#define FERR_GLOBAL_HI 0x48
250static const char *ferr_global_hi_name[] = {
251 [3] = "FSB 3 Fatal Error",
252 [2] = "FSB 2 Fatal Error",
253 [1] = "FSB 1 Fatal Error",
254 [0] = "FSB 0 Fatal Error",
255};
256#define ferr_global_hi_is_fatal(errno) 1
257
Mauro Carvalho Chehabc3af2ea2010-08-26 19:54:51 -0300258#define FERR_GLOBAL_LO 0x40
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300259static const char *ferr_global_lo_name[] = {
Mauro Carvalho Chehabc3af2ea2010-08-26 19:54:51 -0300260 [31] = "Internal MCH Fatal Error",
261 [30] = "Intel QuickData Technology Device Fatal Error",
262 [29] = "FSB1 Fatal Error",
263 [28] = "FSB0 Fatal Error",
264 [27] = "FBD Channel 3 Fatal Error",
265 [26] = "FBD Channel 2 Fatal Error",
266 [25] = "FBD Channel 1 Fatal Error",
267 [24] = "FBD Channel 0 Fatal Error",
268 [23] = "PCI Express Device 7Fatal Error",
269 [22] = "PCI Express Device 6 Fatal Error",
270 [21] = "PCI Express Device 5 Fatal Error",
271 [20] = "PCI Express Device 4 Fatal Error",
272 [19] = "PCI Express Device 3 Fatal Error",
273 [18] = "PCI Express Device 2 Fatal Error",
274 [17] = "PCI Express Device 1 Fatal Error",
275 [16] = "ESI Fatal Error",
276 [15] = "Internal MCH Non-Fatal Error",
277 [14] = "Intel QuickData Technology Device Non Fatal Error",
278 [13] = "FSB1 Non-Fatal Error",
279 [12] = "FSB 0 Non-Fatal Error",
280 [11] = "FBD Channel 3 Non-Fatal Error",
281 [10] = "FBD Channel 2 Non-Fatal Error",
282 [9] = "FBD Channel 1 Non-Fatal Error",
283 [8] = "FBD Channel 0 Non-Fatal Error",
284 [7] = "PCI Express Device 7 Non-Fatal Error",
285 [6] = "PCI Express Device 6 Non-Fatal Error",
286 [5] = "PCI Express Device 5 Non-Fatal Error",
287 [4] = "PCI Express Device 4 Non-Fatal Error",
288 [3] = "PCI Express Device 3 Non-Fatal Error",
289 [2] = "PCI Express Device 2 Non-Fatal Error",
290 [1] = "PCI Express Device 1 Non-Fatal Error",
291 [0] = "ESI Non-Fatal Error",
292};
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300293#define ferr_global_lo_is_fatal(errno) ((errno < 16) ? 0 : 1)
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300294
Mauro Carvalho Chehab8199d8c2010-08-27 11:51:48 -0300295#define NRECMEMA 0xbe
296 #define NRECMEMA_BANK(v) (((v) >> 12) & 7)
297 #define NRECMEMA_RANK(v) (((v) >> 8) & 15)
298
299#define NRECMEMB 0xc0
300 #define NRECMEMB_IS_WR(v) ((v) & (1 << 31))
301 #define NRECMEMB_CAS(v) (((v) >> 16) & 0x1fff)
302 #define NRECMEMB_RAS(v) ((v) & 0xffff)
303
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300304#define REDMEMA 0xdc
305
Mauro Carvalho Chehab37b69cf2010-08-27 15:44:43 -0300306#define REDMEMB 0x7c
307 #define IS_SECOND_CH(v) ((v) * (1 << 17))
308
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300309#define RECMEMA 0xe0
310 #define RECMEMA_BANK(v) (((v) >> 12) & 7)
311 #define RECMEMA_RANK(v) (((v) >> 8) & 15)
312
313#define RECMEMB 0xe4
314 #define RECMEMB_IS_WR(v) ((v) & (1 << 31))
315 #define RECMEMB_CAS(v) (((v) >> 16) & 0x1fff)
316 #define RECMEMB_RAS(v) ((v) & 0xffff)
317
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300318/********************************************
319 * i7300 Functions related to error detection
320 ********************************************/
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300321
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300322/**
323 * get_err_from_table() - Gets the error message from a table
324 * @table: table name (array of char *)
325 * @size: number of elements at the table
326 * @pos: position of the element to be returned
327 *
328 * This is a small routine that gets the pos-th element of a table. If the
329 * element doesn't exist (or it is empty), it returns "reserved".
330 * Instead of calling it directly, the better is to call via the macro
331 * GET_ERR_FROM_TABLE(), that automatically checks the table size via
332 * ARRAY_SIZE() macro
333 */
334static const char *get_err_from_table(const char *table[], int size, int pos)
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300335{
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300336 if (unlikely(pos >= size))
337 return "Reserved";
338
339 if (unlikely(!table[pos]))
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300340 return "Reserved";
341
342 return table[pos];
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300343}
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300344
345#define GET_ERR_FROM_TABLE(table, pos) \
346 get_err_from_table(table, ARRAY_SIZE(table), pos)
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300347
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300348/**
349 * i7300_process_error_global() - Retrieve the hardware error information from
350 * the hardware global error registers and
351 * sends it to dmesg
352 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300353 */
Mauro Carvalho Chehabf4277422010-08-27 10:33:25 -0300354static void i7300_process_error_global(struct mem_ctl_info *mci)
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300355{
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300356 struct i7300_pvt *pvt;
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300357 u32 errnum, error_reg;
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300358 unsigned long errors;
359 const char *specific;
360 bool is_fatal;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300361
362 pvt = mci->pvt_info;
363
364 /* read in the 1st FATAL error register */
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300365 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300366 FERR_GLOBAL_HI, &error_reg);
367 if (unlikely(error_reg)) {
368 errors = error_reg;
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300369 errnum = find_first_bit(&errors,
370 ARRAY_SIZE(ferr_global_hi_name));
371 specific = GET_ERR_FROM_TABLE(ferr_global_hi_name, errnum);
372 is_fatal = ferr_global_hi_is_fatal(errnum);
Mauro Carvalho Chehab86002322010-08-27 00:46:57 -0300373
374 /* Clear the error bit */
375 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300376 FERR_GLOBAL_HI, error_reg);
Mauro Carvalho Chehab86002322010-08-27 00:46:57 -0300377
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300378 goto error_global;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300379 }
380
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300381 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300382 FERR_GLOBAL_LO, &error_reg);
383 if (unlikely(error_reg)) {
384 errors = error_reg;
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300385 errnum = find_first_bit(&errors,
386 ARRAY_SIZE(ferr_global_lo_name));
387 specific = GET_ERR_FROM_TABLE(ferr_global_lo_name, errnum);
388 is_fatal = ferr_global_lo_is_fatal(errnum);
Mauro Carvalho Chehab86002322010-08-27 00:46:57 -0300389
390 /* Clear the error bit */
391 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300392 FERR_GLOBAL_LO, error_reg);
Mauro Carvalho Chehab86002322010-08-27 00:46:57 -0300393
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300394 goto error_global;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300395 }
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300396 return;
397
398error_global:
399 i7300_mc_printk(mci, KERN_EMERG, "%s misc error: %s\n",
400 is_fatal ? "Fatal" : "NOT fatal", specific);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300401}
402
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300403/**
404 * i7300_process_fbd_error() - Retrieve the hardware error information from
405 * the FBD error registers and sends it via
406 * EDAC error API calls
407 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300408 */
Mauro Carvalho Chehabf4277422010-08-27 10:33:25 -0300409static void i7300_process_fbd_error(struct mem_ctl_info *mci)
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300410{
411 struct i7300_pvt *pvt;
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300412 u32 errnum, value, error_reg;
Mauro Carvalho Chehab8199d8c2010-08-27 11:51:48 -0300413 u16 val16;
Mauro Carvalho Chehab37b69cf2010-08-27 15:44:43 -0300414 unsigned branch, channel, bank, rank, cas, ras;
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300415 u32 syndrome;
416
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300417 unsigned long errors;
418 const char *specific;
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300419 bool is_wr;
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300420
421 pvt = mci->pvt_info;
422
423 /* read in the 1st FATAL error register */
424 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300425 FERR_FAT_FBD, &error_reg);
426 if (unlikely(error_reg & FERR_FAT_FBD_ERR_MASK)) {
427 errors = error_reg & FERR_FAT_FBD_ERR_MASK ;
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300428 errnum = find_first_bit(&errors,
429 ARRAY_SIZE(ferr_fat_fbd_name));
430 specific = GET_ERR_FROM_TABLE(ferr_fat_fbd_name, errnum);
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300431 branch = (GET_FBD_FAT_IDX(error_reg) == 2) ? 1 : 0;
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300432
Mauro Carvalho Chehab8199d8c2010-08-27 11:51:48 -0300433 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map,
434 NRECMEMA, &val16);
435 bank = NRECMEMA_BANK(val16);
436 rank = NRECMEMA_RANK(val16);
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300437
Mauro Carvalho Chehab8199d8c2010-08-27 11:51:48 -0300438 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
439 NRECMEMB, &value);
Mauro Carvalho Chehab8199d8c2010-08-27 11:51:48 -0300440 is_wr = NRECMEMB_IS_WR(value);
441 cas = NRECMEMB_CAS(value);
442 ras = NRECMEMB_RAS(value);
443
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300444 /* Clean the error register */
445 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
446 FERR_FAT_FBD, error_reg);
447
Mauro Carvalho Chehab8199d8c2010-08-27 11:51:48 -0300448 snprintf(pvt->tmp_prt_buffer, PAGE_SIZE,
Mauro Carvalho Chehab70e2a832012-04-16 15:10:05 -0300449 "Bank=%d RAS=%d CAS=%d Err=0x%lx (%s))",
450 bank, ras, cas, errors, specific);
Mauro Carvalho Chehab8199d8c2010-08-27 11:51:48 -0300451
Mauro Carvalho Chehab9eb07a72012-06-04 13:27:43 -0300452 edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 1, 0, 0, 0,
Mauro Carvalho Chehab70e2a832012-04-16 15:10:05 -0300453 branch, -1, rank,
454 is_wr ? "Write error" : "Read error",
Mauro Carvalho Chehab03f7eae2012-06-04 11:29:25 -0300455 pvt->tmp_prt_buffer);
Mauro Carvalho Chehab70e2a832012-04-16 15:10:05 -0300456
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300457 }
458
459 /* read in the 1st NON-FATAL error register */
460 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300461 FERR_NF_FBD, &error_reg);
462 if (unlikely(error_reg & FERR_NF_FBD_ERR_MASK)) {
463 errors = error_reg & FERR_NF_FBD_ERR_MASK;
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300464 errnum = find_first_bit(&errors,
465 ARRAY_SIZE(ferr_nf_fbd_name));
466 specific = GET_ERR_FROM_TABLE(ferr_nf_fbd_name, errnum);
Jean Delvare7e06b7a2012-10-18 15:54:45 +0200467 branch = (GET_FBD_NF_IDX(error_reg) == 2) ? 1 : 0;
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300468
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300469 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
470 REDMEMA, &syndrome);
471
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300472 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map,
473 RECMEMA, &val16);
474 bank = RECMEMA_BANK(val16);
475 rank = RECMEMA_RANK(val16);
476
477 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
478 RECMEMB, &value);
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300479 is_wr = RECMEMB_IS_WR(value);
480 cas = RECMEMB_CAS(value);
481 ras = RECMEMB_RAS(value);
482
Mauro Carvalho Chehab37b69cf2010-08-27 15:44:43 -0300483 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
484 REDMEMB, &value);
Mauro Carvalho Chehab37b69cf2010-08-27 15:44:43 -0300485 channel = (branch << 1);
486 if (IS_SECOND_CH(value))
487 channel++;
488
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300489 /* Clear the error bit */
490 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
491 FERR_NF_FBD, error_reg);
492
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300493 /* Form out message */
494 snprintf(pvt->tmp_prt_buffer, PAGE_SIZE,
Mauro Carvalho Chehab70e2a832012-04-16 15:10:05 -0300495 "DRAM-Bank=%d RAS=%d CAS=%d, Err=0x%lx (%s))",
496 bank, ras, cas, errors, specific);
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300497
Mauro Carvalho Chehab9eb07a72012-06-04 13:27:43 -0300498 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0,
Mauro Carvalho Chehab70e2a832012-04-16 15:10:05 -0300499 syndrome,
500 branch >> 1, channel % 2, rank,
501 is_wr ? "Write error" : "Read error",
Mauro Carvalho Chehab03f7eae2012-06-04 11:29:25 -0300502 pvt->tmp_prt_buffer);
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300503 }
504 return;
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300505}
506
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300507/**
508 * i7300_check_error() - Calls the error checking subroutines
509 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300510 */
Mauro Carvalho Chehabf4277422010-08-27 10:33:25 -0300511static void i7300_check_error(struct mem_ctl_info *mci)
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300512{
Mauro Carvalho Chehabf4277422010-08-27 10:33:25 -0300513 i7300_process_error_global(mci);
514 i7300_process_fbd_error(mci);
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300515};
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300516
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300517/**
518 * i7300_clear_error() - Clears the error registers
519 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300520 */
521static void i7300_clear_error(struct mem_ctl_info *mci)
522{
Mauro Carvalho Chehabe4327602010-08-27 10:30:18 -0300523 struct i7300_pvt *pvt = mci->pvt_info;
524 u32 value;
525 /*
526 * All error values are RWC - we need to read and write 1 to the
527 * bit that we want to cleanup
528 */
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300529
Mauro Carvalho Chehabe4327602010-08-27 10:30:18 -0300530 /* Clear global error registers */
531 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
532 FERR_GLOBAL_HI, &value);
533 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
534 FERR_GLOBAL_HI, value);
535
536 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
537 FERR_GLOBAL_LO, &value);
538 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
539 FERR_GLOBAL_LO, value);
540
541 /* Clear FBD error registers */
542 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
543 FERR_FAT_FBD, &value);
544 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
545 FERR_FAT_FBD, value);
546
547 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
548 FERR_NF_FBD, &value);
549 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
550 FERR_NF_FBD, value);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300551}
552
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300553/**
554 * i7300_enable_error_reporting() - Enable the memory reporting logic at the
555 * hardware
556 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300557 */
558static void i7300_enable_error_reporting(struct mem_ctl_info *mci)
559{
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300560 struct i7300_pvt *pvt = mci->pvt_info;
561 u32 fbd_error_mask;
562
563 /* Read the FBD Error Mask Register */
564 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
565 EMASK_FBD, &fbd_error_mask);
566
567 /* Enable with a '0' */
568 fbd_error_mask &= ~(EMASK_FBD_ERR_MASK);
569
570 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
571 EMASK_FBD, fbd_error_mask);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300572}
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300573
574/************************************************
575 * i7300 Functions related to memory enumberation
576 ************************************************/
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300577
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300578/**
579 * decode_mtr() - Decodes the MTR descriptor, filling the edac structs
580 * @pvt: pointer to the private data struct used by i7300 driver
581 * @slot: DIMM slot (0 to 7)
582 * @ch: Channel number within the branch (0 or 1)
583 * @branch: Branch number (0 or 1)
584 * @dinfo: Pointer to DIMM info where dimm size is stored
585 * @p_csrow: Pointer to the struct csrow_info that corresponds to that element
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300586 */
587static int decode_mtr(struct i7300_pvt *pvt,
588 int slot, int ch, int branch,
589 struct i7300_dimm_info *dinfo,
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300590 struct dimm_info *dimm)
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300591{
592 int mtr, ans, addrBits, channel;
593
594 channel = to_channel(ch, branch);
595
596 mtr = pvt->mtr[slot][branch];
597 ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0;
598
Joe Perches956b9ba2012-04-29 17:08:39 -0300599 edac_dbg(2, "\tMTR%d CH%d: DIMMs are %sPresent (mtr)\n",
600 slot, channel, ans ? "" : "NOT ");
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300601
602 /* Determine if there is a DIMM present in this DIMM slot */
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300603 if (!ans)
604 return 0;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300605
606 /* Start with the number of bits for a Bank
607 * on the DRAM */
608 addrBits = MTR_DRAM_BANKS_ADDR_BITS;
609 /* Add thenumber of ROW bits */
610 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
611 /* add the number of COLUMN bits */
612 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
613 /* add the number of RANK bits */
614 addrBits += MTR_DIMM_RANKS(mtr);
615
616 addrBits += 6; /* add 64 bits per DIMM */
617 addrBits -= 20; /* divide by 2^^20 */
618 addrBits -= 3; /* 8 bits per bytes */
619
620 dinfo->megabytes = 1 << addrBits;
621
Joe Perches956b9ba2012-04-29 17:08:39 -0300622 edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300623
Joe Perches956b9ba2012-04-29 17:08:39 -0300624 edac_dbg(2, "\t\tELECTRICAL THROTTLING is %s\n",
625 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300626
Joe Perches956b9ba2012-04-29 17:08:39 -0300627 edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
628 edac_dbg(2, "\t\tNUMRANK: %s\n",
629 MTR_DIMM_RANKS(mtr) ? "double" : "single");
630 edac_dbg(2, "\t\tNUMROW: %s\n",
631 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" :
632 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" :
633 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" :
634 "65,536 - 16 rows");
635 edac_dbg(2, "\t\tNUMCOL: %s\n",
636 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" :
637 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" :
638 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" :
639 "reserved");
640 edac_dbg(2, "\t\tSIZE: %d MB\n", dinfo->megabytes);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300641
Mauro Carvalho Chehab116389e2010-08-26 23:19:54 -0300642 /*
Mauro Carvalho Chehab15154c52010-08-27 09:16:06 -0300643 * The type of error detection actually depends of the
Mauro Carvalho Chehab116389e2010-08-26 23:19:54 -0300644 * mode of operation. When it is just one single memory chip, at
Mauro Carvalho Chehab15154c52010-08-27 09:16:06 -0300645 * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code.
646 * In normal or mirrored mode, it uses Lockstep mode,
Mauro Carvalho Chehab116389e2010-08-26 23:19:54 -0300647 * with the possibility of using an extended algorithm for x8 memories
648 * See datasheet Sections 7.3.6 to 7.3.8
649 */
Mauro Carvalho Chehab15154c52010-08-27 09:16:06 -0300650
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300651 dimm->nr_pages = MiB_TO_PAGES(dinfo->megabytes);
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300652 dimm->grain = 8;
653 dimm->mtype = MEM_FB_DDR2;
Mauro Carvalho Chehab15154c52010-08-27 09:16:06 -0300654 if (IS_SINGLE_MODE(pvt->mc_settings_a)) {
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300655 dimm->edac_mode = EDAC_SECDED;
Joe Perches956b9ba2012-04-29 17:08:39 -0300656 edac_dbg(2, "\t\tECC code is 8-byte-over-32-byte SECDED+ code\n");
Mauro Carvalho Chehab15154c52010-08-27 09:16:06 -0300657 } else {
Joe Perches956b9ba2012-04-29 17:08:39 -0300658 edac_dbg(2, "\t\tECC code is on Lockstep mode\n");
Mauro Carvalho Chehab28c2ce72010-08-27 11:20:38 -0300659 if (MTR_DRAM_WIDTH(mtr) == 8)
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300660 dimm->edac_mode = EDAC_S8ECD8ED;
Mauro Carvalho Chehab15154c52010-08-27 09:16:06 -0300661 else
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300662 dimm->edac_mode = EDAC_S4ECD4ED;
Mauro Carvalho Chehab15154c52010-08-27 09:16:06 -0300663 }
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300664
665 /* ask what device type on this row */
Mauro Carvalho Chehab28c2ce72010-08-27 11:20:38 -0300666 if (MTR_DRAM_WIDTH(mtr) == 8) {
Joe Perches956b9ba2012-04-29 17:08:39 -0300667 edac_dbg(2, "\t\tScrub algorithm for x8 is on %s mode\n",
668 IS_SCRBALGO_ENHANCED(pvt->mc_settings) ?
669 "enhanced" : "normal");
Mauro Carvalho Chehabd7de2bd2010-08-27 08:56:48 -0300670
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300671 dimm->dtype = DEV_X8;
Mauro Carvalho Chehabd7de2bd2010-08-27 08:56:48 -0300672 } else
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300673 dimm->dtype = DEV_X4;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300674
675 return mtr;
676}
677
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300678/**
679 * print_dimm_size() - Prints dump of the memory organization
680 * @pvt: pointer to the private data struct used by i7300 driver
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300681 *
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300682 * Useful for debug. If debug is disabled, this routine do nothing
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300683 */
684static void print_dimm_size(struct i7300_pvt *pvt)
685{
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300686#ifdef CONFIG_EDAC_DEBUG
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300687 struct i7300_dimm_info *dinfo;
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -0300688 char *p;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300689 int space, n;
690 int channel, slot;
691
692 space = PAGE_SIZE;
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -0300693 p = pvt->tmp_prt_buffer;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300694
695 n = snprintf(p, space, " ");
696 p += n;
697 space -= n;
698 for (channel = 0; channel < MAX_CHANNELS; channel++) {
699 n = snprintf(p, space, "channel %d | ", channel);
700 p += n;
701 space -= n;
702 }
Joe Perches956b9ba2012-04-29 17:08:39 -0300703 edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -0300704 p = pvt->tmp_prt_buffer;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300705 space = PAGE_SIZE;
706 n = snprintf(p, space, "-------------------------------"
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300707 "------------------------------");
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300708 p += n;
709 space -= n;
Joe Perches956b9ba2012-04-29 17:08:39 -0300710 edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -0300711 p = pvt->tmp_prt_buffer;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300712 space = PAGE_SIZE;
713
714 for (slot = 0; slot < MAX_SLOTS; slot++) {
715 n = snprintf(p, space, "csrow/SLOT %d ", slot);
716 p += n;
717 space -= n;
718
719 for (channel = 0; channel < MAX_CHANNELS; channel++) {
720 dinfo = &pvt->dimm_info[slot][channel];
721 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);
722 p += n;
723 space -= n;
724 }
725
Joe Perches956b9ba2012-04-29 17:08:39 -0300726 edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -0300727 p = pvt->tmp_prt_buffer;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300728 space = PAGE_SIZE;
729 }
730
731 n = snprintf(p, space, "-------------------------------"
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300732 "------------------------------");
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300733 p += n;
734 space -= n;
Joe Perches956b9ba2012-04-29 17:08:39 -0300735 edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -0300736 p = pvt->tmp_prt_buffer;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300737 space = PAGE_SIZE;
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300738#endif
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300739}
740
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300741/**
742 * i7300_init_csrows() - Initialize the 'csrows' table within
743 * the mci control structure with the
744 * addressing of memory.
745 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300746 */
747static int i7300_init_csrows(struct mem_ctl_info *mci)
748{
749 struct i7300_pvt *pvt;
750 struct i7300_dimm_info *dinfo;
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300751 int rc = -ENODEV;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300752 int mtr;
Mauro Carvalho Chehab33ad4122013-03-13 22:56:33 -0300753 int ch, branch, slot, channel, max_channel, max_branch;
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300754 struct dimm_info *dimm;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300755
756 pvt = mci->pvt_info;
757
Joe Perches956b9ba2012-04-29 17:08:39 -0300758 edac_dbg(2, "Memory Technology Registers:\n");
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300759
Mauro Carvalho Chehab33ad4122013-03-13 22:56:33 -0300760 if (IS_SINGLE_MODE(pvt->mc_settings_a)) {
761 max_branch = 1;
762 max_channel = 1;
763 } else {
764 max_branch = MAX_BRANCHES;
765 max_channel = MAX_CH_PER_BRANCH;
766 }
767
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300768 /* Get the AMB present registers for the four channels */
Mauro Carvalho Chehab33ad4122013-03-13 22:56:33 -0300769 for (branch = 0; branch < max_branch; branch++) {
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300770 /* Read and dump branch 0's MTRs */
771 channel = to_channel(0, branch);
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300772 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
773 AMBPRESENT_0,
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300774 &pvt->ambpresent[channel]);
Joe Perches956b9ba2012-04-29 17:08:39 -0300775 edac_dbg(2, "\t\tAMB-present CH%d = 0x%x:\n",
776 channel, pvt->ambpresent[channel]);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300777
Mauro Carvalho Chehab33ad4122013-03-13 22:56:33 -0300778 if (max_channel == 1)
779 continue;
780
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300781 channel = to_channel(1, branch);
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300782 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
783 AMBPRESENT_1,
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300784 &pvt->ambpresent[channel]);
Joe Perches956b9ba2012-04-29 17:08:39 -0300785 edac_dbg(2, "\t\tAMB-present CH%d = 0x%x:\n",
786 channel, pvt->ambpresent[channel]);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300787 }
788
789 /* Get the set of MTR[0-7] regs by each branch */
790 for (slot = 0; slot < MAX_SLOTS; slot++) {
791 int where = mtr_regs[slot];
Mauro Carvalho Chehab33ad4122013-03-13 22:56:33 -0300792 for (branch = 0; branch < max_branch; branch++) {
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300793 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300794 where,
795 &pvt->mtr[slot][branch]);
Mauro Carvalho Chehab33ad4122013-03-13 22:56:33 -0300796 for (ch = 0; ch < max_channel; ch++) {
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300797 int channel = to_channel(ch, branch);
798
Mauro Carvalho Chehab70e2a832012-04-16 15:10:05 -0300799 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
800 mci->n_layers, branch, ch, slot);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300801
Mauro Carvalho Chehab70e2a832012-04-16 15:10:05 -0300802 dinfo = &pvt->dimm_info[slot][channel];
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300803
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300804 mtr = decode_mtr(pvt, slot, ch, branch,
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300805 dinfo, dimm);
806
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300807 /* if no DIMMS on this row, continue */
808 if (!MTR_DIMMS_PRESENT(mtr))
809 continue;
810
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300811 rc = 0;
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300812
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300813 }
814 }
815 }
816
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300817 return rc;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300818}
819
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300820/**
821 * decode_mir() - Decodes Memory Interleave Register (MIR) info
822 * @int mir_no: number of the MIR register to decode
823 * @mir: array with the MIR data cached on the driver
824 */
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300825static void decode_mir(int mir_no, u16 mir[MAX_MIR])
826{
827 if (mir[mir_no] & 3)
Joe Perches956b9ba2012-04-29 17:08:39 -0300828 edac_dbg(2, "MIR%d: limit= 0x%x Branch(es) that participate: %s %s\n",
829 mir_no,
830 (mir[mir_no] >> 4) & 0xfff,
831 (mir[mir_no] & 1) ? "B0" : "",
832 (mir[mir_no] & 2) ? "B1" : "");
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300833}
834
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300835/**
836 * i7300_get_mc_regs() - Get the contents of the MC enumeration registers
837 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300838 *
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300839 * Data read is cached internally for its usage when needed
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300840 */
841static int i7300_get_mc_regs(struct mem_ctl_info *mci)
842{
843 struct i7300_pvt *pvt;
844 u32 actual_tolm;
845 int i, rc;
846
847 pvt = mci->pvt_info;
848
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300849 pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE,
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300850 (u32 *) &pvt->ambase);
851
Joe Perches956b9ba2012-04-29 17:08:39 -0300852 edac_dbg(2, "AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300853
854 /* Get the Branch Map regs */
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300855 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300856 pvt->tolm >>= 12;
Joe Perches956b9ba2012-04-29 17:08:39 -0300857 edac_dbg(2, "TOLM (number of 256M regions) =%u (0x%x)\n",
858 pvt->tolm, pvt->tolm);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300859
860 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
Joe Perches956b9ba2012-04-29 17:08:39 -0300861 edac_dbg(2, "Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
862 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300863
Mauro Carvalho Chehabaf3d8832010-08-26 20:58:45 -0300864 /* Get memory controller settings */
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300865 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS,
Mauro Carvalho Chehabaf3d8832010-08-26 20:58:45 -0300866 &pvt->mc_settings);
Mauro Carvalho Chehabbb81a212010-08-27 09:04:11 -0300867 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS_A,
868 &pvt->mc_settings_a);
Mauro Carvalho Chehabd7de2bd2010-08-27 08:56:48 -0300869
Mauro Carvalho Chehabbb81a212010-08-27 09:04:11 -0300870 if (IS_SINGLE_MODE(pvt->mc_settings_a))
Joe Perches956b9ba2012-04-29 17:08:39 -0300871 edac_dbg(0, "Memory controller operating on single mode\n");
Mauro Carvalho Chehabbb81a212010-08-27 09:04:11 -0300872 else
Joe Perches956b9ba2012-04-29 17:08:39 -0300873 edac_dbg(0, "Memory controller operating on %smirrored mode\n",
874 IS_MIRRORED(pvt->mc_settings) ? "" : "non-");
Mauro Carvalho Chehabbb81a212010-08-27 09:04:11 -0300875
Joe Perches956b9ba2012-04-29 17:08:39 -0300876 edac_dbg(0, "Error detection is %s\n",
877 IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
878 edac_dbg(0, "Retry is %s\n",
879 IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
Mauro Carvalho Chehabaf3d8832010-08-26 20:58:45 -0300880
881 /* Get Memory Interleave Range registers */
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300882 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0,
883 &pvt->mir[0]);
884 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR1,
885 &pvt->mir[1]);
886 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR2,
887 &pvt->mir[2]);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300888
889 /* Decode the MIR regs */
890 for (i = 0; i < MAX_MIR; i++)
891 decode_mir(i, pvt->mir);
892
893 rc = i7300_init_csrows(mci);
894 if (rc < 0)
895 return rc;
896
897 /* Go and determine the size of each DIMM and place in an
898 * orderly matrix */
899 print_dimm_size(pvt);
900
901 return 0;
902}
903
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300904/*************************************************
905 * i7300 Functions related to device probe/release
906 *************************************************/
907
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300908/**
909 * i7300_put_devices() - Release the PCI devices
910 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300911 */
912static void i7300_put_devices(struct mem_ctl_info *mci)
913{
914 struct i7300_pvt *pvt;
915 int branch;
916
917 pvt = mci->pvt_info;
918
919 /* Decrement usage count for devices */
920 for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++)
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300921 pci_dev_put(pvt->pci_dev_2x_0_fbd_branch[branch]);
922 pci_dev_put(pvt->pci_dev_16_2_fsb_err_regs);
923 pci_dev_put(pvt->pci_dev_16_1_fsb_addr_map);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300924}
925
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300926/**
927 * i7300_get_devices() - Find and perform 'get' operation on the MCH's
928 * device/functions we want to reference for this driver
929 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300930 *
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300931 * Access and prepare the several devices for usage:
932 * I7300 devices used by this driver:
933 * Device 16, functions 0,1 and 2: PCI_DEVICE_ID_INTEL_I7300_MCH_ERR
934 * Device 21 function 0: PCI_DEVICE_ID_INTEL_I7300_MCH_FB0
935 * Device 22 function 0: PCI_DEVICE_ID_INTEL_I7300_MCH_FB1
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300936 */
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800937static int i7300_get_devices(struct mem_ctl_info *mci)
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300938{
939 struct i7300_pvt *pvt;
940 struct pci_dev *pdev;
941
942 pvt = mci->pvt_info;
943
944 /* Attempt to 'get' the MCH register we want */
945 pdev = NULL;
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300946 while (!pvt->pci_dev_16_1_fsb_addr_map ||
947 !pvt->pci_dev_16_2_fsb_err_regs) {
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300948 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
949 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, pdev);
950 if (!pdev) {
951 /* End of list, leave */
952 i7300_printk(KERN_ERR,
953 "'system address,Process Bus' "
954 "device not found:"
955 "vendor 0x%x device 0x%x ERR funcs "
956 "(broken BIOS?)\n",
957 PCI_VENDOR_ID_INTEL,
958 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR);
959 goto error;
960 }
961
962 /* Store device 16 funcs 1 and 2 */
963 switch (PCI_FUNC(pdev->devfn)) {
964 case 1:
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300965 pvt->pci_dev_16_1_fsb_addr_map = pdev;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300966 break;
967 case 2:
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300968 pvt->pci_dev_16_2_fsb_err_regs = pdev;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300969 break;
970 }
971 }
972
Joe Perches956b9ba2012-04-29 17:08:39 -0300973 edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x\n",
974 pci_name(pvt->pci_dev_16_0_fsb_ctlr),
975 pvt->pci_dev_16_0_fsb_ctlr->vendor,
976 pvt->pci_dev_16_0_fsb_ctlr->device);
977 edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
978 pci_name(pvt->pci_dev_16_1_fsb_addr_map),
979 pvt->pci_dev_16_1_fsb_addr_map->vendor,
980 pvt->pci_dev_16_1_fsb_addr_map->device);
981 edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x\n",
982 pci_name(pvt->pci_dev_16_2_fsb_err_regs),
983 pvt->pci_dev_16_2_fsb_err_regs->vendor,
984 pvt->pci_dev_16_2_fsb_err_regs->device);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300985
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300986 pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL,
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300987 PCI_DEVICE_ID_INTEL_I7300_MCH_FB0,
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300988 NULL);
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300989 if (!pvt->pci_dev_2x_0_fbd_branch[0]) {
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300990 i7300_printk(KERN_ERR,
991 "MC: 'BRANCH 0' device not found:"
992 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
993 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0);
994 goto error;
995 }
996
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300997 pvt->pci_dev_2x_0_fbd_branch[1] = pci_get_device(PCI_VENDOR_ID_INTEL,
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300998 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1,
999 NULL);
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -03001000 if (!pvt->pci_dev_2x_0_fbd_branch[1]) {
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001001 i7300_printk(KERN_ERR,
1002 "MC: 'BRANCH 1' device not found:"
1003 "vendor 0x%x device 0x%x Func 0 "
1004 "(broken BIOS?)\n",
1005 PCI_VENDOR_ID_INTEL,
1006 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1);
1007 goto error;
1008 }
1009
1010 return 0;
1011
1012error:
1013 i7300_put_devices(mci);
1014 return -ENODEV;
1015}
1016
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001017/**
1018 * i7300_init_one() - Probe for one instance of the device
1019 * @pdev: struct pci_dev pointer
1020 * @id: struct pci_device_id pointer - currently unused
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001021 */
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -08001022static int i7300_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001023{
1024 struct mem_ctl_info *mci;
Mauro Carvalho Chehab70e2a832012-04-16 15:10:05 -03001025 struct edac_mc_layer layers[3];
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001026 struct i7300_pvt *pvt;
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001027 int rc;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001028
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001029 /* wake up device */
1030 rc = pci_enable_device(pdev);
1031 if (rc == -EIO)
1032 return rc;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001033
Joe Perches956b9ba2012-04-29 17:08:39 -03001034 edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n",
1035 pdev->bus->number,
1036 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001037
1038 /* We only are looking for func 0 of the set */
1039 if (PCI_FUNC(pdev->devfn) != 0)
1040 return -ENODEV;
1041
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001042 /* allocate a new MC control structure */
Mauro Carvalho Chehab70e2a832012-04-16 15:10:05 -03001043 layers[0].type = EDAC_MC_LAYER_BRANCH;
1044 layers[0].size = MAX_BRANCHES;
1045 layers[0].is_virt_csrow = false;
1046 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1047 layers[1].size = MAX_CH_PER_BRANCH;
1048 layers[1].is_virt_csrow = true;
1049 layers[2].type = EDAC_MC_LAYER_SLOT;
1050 layers[2].size = MAX_SLOTS;
1051 layers[2].is_virt_csrow = true;
Mauro Carvalho Chehabca0907b2012-05-02 14:37:00 -03001052 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001053 if (mci == NULL)
1054 return -ENOMEM;
1055
Joe Perches956b9ba2012-04-29 17:08:39 -03001056 edac_dbg(0, "MC: mci = %p\n", mci);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001057
Mauro Carvalho Chehabfd687502012-03-16 07:44:18 -03001058 mci->pdev = &pdev->dev; /* record ptr to the generic device */
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001059
1060 pvt = mci->pvt_info;
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -03001061 pvt->pci_dev_16_0_fsb_ctlr = pdev; /* Record this device in our private */
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001062
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -03001063 pvt->tmp_prt_buffer = kmalloc(PAGE_SIZE, GFP_KERNEL);
1064 if (!pvt->tmp_prt_buffer) {
1065 edac_mc_free(mci);
1066 return -ENOMEM;
1067 }
1068
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001069 /* 'get' the pci devices we want to reserve for our use */
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001070 if (i7300_get_devices(mci))
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001071 goto fail0;
1072
1073 mci->mc_idx = 0;
1074 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1075 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1076 mci->edac_cap = EDAC_FLAG_NONE;
1077 mci->mod_name = "i7300_edac.c";
1078 mci->mod_ver = I7300_REVISION;
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001079 mci->ctl_name = i7300_devs[0].ctl_name;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001080 mci->dev_name = pci_name(pdev);
1081 mci->ctl_page_to_phys = NULL;
1082
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001083 /* Set the function pointer to an actual operation function */
1084 mci->edac_check = i7300_check_error;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001085
1086 /* initialize the MC control structure 'csrows' table
1087 * with the mapping and control information */
1088 if (i7300_get_mc_regs(mci)) {
Joe Perches956b9ba2012-04-29 17:08:39 -03001089 edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i7300_init_csrows() returned nonzero value\n");
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001090 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1091 } else {
Joe Perches956b9ba2012-04-29 17:08:39 -03001092 edac_dbg(1, "MC: Enable error reporting now\n");
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001093 i7300_enable_error_reporting(mci);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001094 }
1095
1096 /* add this new MC control structure to EDAC's list of MCs */
1097 if (edac_mc_add_mc(mci)) {
Joe Perches956b9ba2012-04-29 17:08:39 -03001098 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001099 /* FIXME: perhaps some code should go here that disables error
1100 * reporting if we just enabled it
1101 */
1102 goto fail1;
1103 }
1104
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001105 i7300_clear_error(mci);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001106
1107 /* allocating generic PCI control info */
1108 i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1109 if (!i7300_pci) {
1110 printk(KERN_WARNING
1111 "%s(): Unable to create PCI control\n",
1112 __func__);
1113 printk(KERN_WARNING
1114 "%s(): PCI error report via EDAC not setup\n",
1115 __func__);
1116 }
1117
1118 return 0;
1119
1120 /* Error exit unwinding stack */
1121fail1:
1122
1123 i7300_put_devices(mci);
1124
1125fail0:
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -03001126 kfree(pvt->tmp_prt_buffer);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001127 edac_mc_free(mci);
1128 return -ENODEV;
1129}
1130
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001131/**
1132 * i7300_remove_one() - Remove the driver
1133 * @pdev: struct pci_dev pointer
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001134 */
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -08001135static void i7300_remove_one(struct pci_dev *pdev)
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001136{
1137 struct mem_ctl_info *mci;
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -03001138 char *tmp;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001139
Joe Perches956b9ba2012-04-29 17:08:39 -03001140 edac_dbg(0, "\n");
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001141
1142 if (i7300_pci)
1143 edac_pci_release_generic_ctl(i7300_pci);
1144
1145 mci = edac_mc_del_mc(&pdev->dev);
1146 if (!mci)
1147 return;
1148
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -03001149 tmp = ((struct i7300_pvt *)mci->pvt_info)->tmp_prt_buffer;
1150
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001151 /* retrieve references to resources, and free those resources */
1152 i7300_put_devices(mci);
1153
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -03001154 kfree(tmp);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001155 edac_mc_free(mci);
1156}
1157
1158/*
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001159 * pci_device_id: table for which devices we are looking for
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001160 *
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001161 * Has only 8086:360c PCI ID
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001162 */
Lionel Debroux36c46f32012-02-27 07:41:47 +01001163static DEFINE_PCI_DEVICE_TABLE(i7300_pci_tbl) = {
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001164 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)},
1165 {0,} /* 0 terminated list. */
1166};
1167
1168MODULE_DEVICE_TABLE(pci, i7300_pci_tbl);
1169
1170/*
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001171 * i7300_driver: pci_driver structure for this module
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001172 */
1173static struct pci_driver i7300_driver = {
1174 .name = "i7300_edac",
1175 .probe = i7300_init_one,
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -08001176 .remove = i7300_remove_one,
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001177 .id_table = i7300_pci_tbl,
1178};
1179
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001180/**
1181 * i7300_init() - Registers the driver
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001182 */
1183static int __init i7300_init(void)
1184{
1185 int pci_rc;
1186
Joe Perches956b9ba2012-04-29 17:08:39 -03001187 edac_dbg(2, "\n");
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001188
1189 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1190 opstate_init();
1191
1192 pci_rc = pci_register_driver(&i7300_driver);
1193
1194 return (pci_rc < 0) ? pci_rc : 0;
1195}
1196
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001197/**
1198 * i7300_init() - Unregisters the driver
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001199 */
1200static void __exit i7300_exit(void)
1201{
Joe Perches956b9ba2012-04-29 17:08:39 -03001202 edac_dbg(2, "\n");
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001203 pci_unregister_driver(&i7300_driver);
1204}
1205
1206module_init(i7300_init);
1207module_exit(i7300_exit);
1208
1209MODULE_LICENSE("GPL");
1210MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1211MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1212MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - "
1213 I7300_REVISION);
1214
1215module_param(edac_op_state, int, 0444);
1216MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");