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Alessandro Rubini28ad94e2009-07-02 19:06:47 +01001/*
Alessandro Rubini28ad94e2009-07-02 19:06:47 +01002 * Copyright (C) 2008 STMicroelectronics
Alessandro Rubinib102c012010-03-05 12:38:51 +01003 * Copyright (C) 2010 Alessandro Rubini
Linus Walleij8fbb97a22010-11-19 10:16:05 +01004 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
Alessandro Rubini28ad94e2009-07-02 19:06:47 +01005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 */
10#include <linux/init.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/io.h>
14#include <linux/clockchips.h>
Linus Walleij694e33a2012-10-18 14:01:25 +020015#include <linux/clocksource.h>
Rabin Vincentc7785ea2013-04-03 13:28:26 +020016#include <linux/of_address.h>
17#include <linux/of_irq.h>
18#include <linux/of_platform.h>
Linus Walleijba327b12010-05-26 07:38:54 +010019#include <linux/clk.h>
Alessandro Rubini28ad94e2009-07-02 19:06:47 +010020#include <linux/jiffies.h>
Fabio Baltieri6f179b72012-12-04 11:10:44 +010021#include <linux/delay.h>
Linus Walleijba327b12010-05-26 07:38:54 +010022#include <linux/err.h>
Linus Walleij694e33a2012-10-18 14:01:25 +020023#include <linux/platform_data/clocksource-nomadik-mtu.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070024#include <linux/sched_clock.h>
Alessandro Rubini28ad94e2009-07-02 19:06:47 +010025#include <asm/mach/time.h>
Alessandro Rubini28ad94e2009-07-02 19:06:47 +010026
Jonas Aaberg05387a92011-09-20 11:18:27 +020027/*
Jonas Aaberg05387a92011-09-20 11:18:27 +020028 * The MTU device hosts four different counters, with 4 set of
29 * registers. These are register names.
30 */
31
32#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
33#define MTU_RIS 0x04 /* Raw interrupt status */
34#define MTU_MIS 0x08 /* Masked interrupt status */
35#define MTU_ICR 0x0C /* Interrupt clear register */
36
37/* per-timer registers take 0..3 as argument */
38#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
39#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
40#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
41#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
42
43/* bits for the control register */
44#define MTU_CRn_ENA 0x80
45#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
46#define MTU_CRn_PRESCALE_MASK 0x0c
47#define MTU_CRn_PRESCALE_1 0x00
48#define MTU_CRn_PRESCALE_16 0x04
49#define MTU_CRn_PRESCALE_256 0x08
50#define MTU_CRn_32BITS 0x02
51#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
52
53/* Other registers are usual amba/primecell registers, currently not used */
54#define MTU_ITCR 0xff0
55#define MTU_ITOP 0xff4
56
57#define MTU_PERIPH_ID0 0xfe0
58#define MTU_PERIPH_ID1 0xfe4
59#define MTU_PERIPH_ID2 0xfe8
60#define MTU_PERIPH_ID3 0xfeC
61
62#define MTU_PCELL0 0xff0
63#define MTU_PCELL1 0xff4
64#define MTU_PCELL2 0xff8
65#define MTU_PCELL3 0xffC
Alessandro Rubini28ad94e2009-07-02 19:06:47 +010066
Linus Walleijb9576622012-01-11 09:46:59 +010067static void __iomem *mtu_base;
Jonas Aaberg2f73a062011-09-14 10:32:51 +020068static bool clkevt_periodic;
69static u32 clk_prescale;
70static u32 nmdk_cycle; /* write-once */
Fabio Baltieri6f179b72012-12-04 11:10:44 +010071static struct delay_timer mtu_delay_timer;
Jonas Aaberg2f73a062011-09-14 10:32:51 +020072
Linus Walleijea7113f2013-04-20 16:09:17 +020073#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
Linus Walleij2a847512010-05-07 10:03:02 +010074/*
Linus Walleij2a847512010-05-07 10:03:02 +010075 * Override the global weak sched_clock symbol with this
76 * local implementation which uses the clocksource to get some
Linus Walleij8fbb97a22010-11-19 10:16:05 +010077 * better resolution when scheduling the kernel.
Linus Walleij2a847512010-05-07 10:03:02 +010078 */
Marc Zyngier2f0778af2011-12-15 12:19:23 +010079static u32 notrace nomadik_read_sched_clock(void)
Linus Walleij2a847512010-05-07 10:03:02 +010080{
Linus Walleij8fbb97a22010-11-19 10:16:05 +010081 if (unlikely(!mtu_base))
82 return 0;
83
Marc Zyngier2f0778af2011-12-15 12:19:23 +010084 return -readl(mtu_base + MTU_VAL(0));
Linus Walleij2a847512010-05-07 10:03:02 +010085}
Mattias Wallincba13832011-05-27 10:29:25 +020086#endif
Jonas Aaberg2f73a062011-09-14 10:32:51 +020087
Fabio Baltieri6f179b72012-12-04 11:10:44 +010088static unsigned long nmdk_timer_read_current_timer(void)
89{
90 return ~readl_relaxed(mtu_base + MTU_VAL(0));
91}
92
Alessandro Rubinib102c012010-03-05 12:38:51 +010093/* Clockevent device: use one-shot mode */
Jonas Aaberg2f73a062011-09-14 10:32:51 +020094static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
95{
96 writel(1 << 1, mtu_base + MTU_IMSC);
97 writel(evt, mtu_base + MTU_LR(1));
98 /* Load highest value, enable device, enable interrupts */
99 writel(MTU_CRn_ONESHOT | clk_prescale |
100 MTU_CRn_32BITS | MTU_CRn_ENA,
101 mtu_base + MTU_CR(1));
102
103 return 0;
104}
105
Jonas Aaberg05387a92011-09-20 11:18:27 +0200106void nmdk_clkevt_reset(void)
Jonas Aaberg2f73a062011-09-14 10:32:51 +0200107{
108 if (clkevt_periodic) {
Jonas Aaberg2f73a062011-09-14 10:32:51 +0200109 /* Timer: configure load and background-load, and fire it up */
110 writel(nmdk_cycle, mtu_base + MTU_LR(1));
111 writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
112
113 writel(MTU_CRn_PERIODIC | clk_prescale |
114 MTU_CRn_32BITS | MTU_CRn_ENA,
115 mtu_base + MTU_CR(1));
116 writel(1 << 1, mtu_base + MTU_IMSC);
117 } else {
118 /* Generate an interrupt to start the clockevent again */
119 (void) nmdk_clkevt_next(nmdk_cycle, NULL);
120 }
121}
122
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100123static void nmdk_clkevt_mode(enum clock_event_mode mode,
124 struct clock_event_device *dev)
125{
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100126 switch (mode) {
127 case CLOCK_EVT_MODE_PERIODIC:
Jonas Aaberg2f73a062011-09-14 10:32:51 +0200128 clkevt_periodic = true;
129 nmdk_clkevt_reset();
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100130 break;
131 case CLOCK_EVT_MODE_ONESHOT:
Jonas Aaberg2f73a062011-09-14 10:32:51 +0200132 clkevt_periodic = false;
Alessandro Rubinib102c012010-03-05 12:38:51 +0100133 break;
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100134 case CLOCK_EVT_MODE_SHUTDOWN:
135 case CLOCK_EVT_MODE_UNUSED:
Alessandro Rubinib102c012010-03-05 12:38:51 +0100136 writel(0, mtu_base + MTU_IMSC);
Linus Walleij29179472010-06-01 08:26:49 +0100137 /* disable timer */
Jonas Aaberg2f73a062011-09-14 10:32:51 +0200138 writel(0, mtu_base + MTU_CR(1));
Linus Walleij29179472010-06-01 08:26:49 +0100139 /* load some high default value */
140 writel(0xffffffff, mtu_base + MTU_LR(1));
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100141 break;
142 case CLOCK_EVT_MODE_RESUME:
143 break;
144 }
145}
146
Stephen Warren8726e962012-11-07 17:07:45 -0700147void nmdk_clksrc_reset(void)
148{
149 /* Disable */
150 writel(0, mtu_base + MTU_CR(0));
151
152 /* ClockSource: configure load and background-load, and fire it up */
153 writel(nmdk_cycle, mtu_base + MTU_LR(0));
154 writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
155
156 writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
157 mtu_base + MTU_CR(0));
158}
159
160static void nmdk_clkevt_resume(struct clock_event_device *cedev)
161{
162 nmdk_clkevt_reset();
163 nmdk_clksrc_reset();
164}
165
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100166static struct clock_event_device nmdk_clkevt = {
Alessandro Rubinib102c012010-03-05 12:38:51 +0100167 .name = "mtu_1",
Daniel Lezcano74adcbf2013-03-02 11:10:12 +0100168 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC |
169 CLOCK_EVT_FEAT_DYNIRQ,
Alessandro Rubinib102c012010-03-05 12:38:51 +0100170 .rating = 200,
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100171 .set_mode = nmdk_clkevt_mode,
Alessandro Rubinib102c012010-03-05 12:38:51 +0100172 .set_next_event = nmdk_clkevt_next,
Stephen Warren8726e962012-11-07 17:07:45 -0700173 .resume = nmdk_clkevt_resume,
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100174};
175
176/*
Alessandro Rubinib102c012010-03-05 12:38:51 +0100177 * IRQ Handler for timer 1 of the MTU block.
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100178 */
179static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
180{
Alessandro Rubinib102c012010-03-05 12:38:51 +0100181 struct clock_event_device *evdev = dev_id;
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100182
Alessandro Rubinib102c012010-03-05 12:38:51 +0100183 writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
184 evdev->event_handler(evdev);
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100185 return IRQ_HANDLED;
186}
187
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100188static struct irqaction nmdk_timer_irq = {
189 .name = "Nomadik Timer Tick",
190 .flags = IRQF_DISABLED | IRQF_TIMER,
191 .handler = nmdk_timer_interrupt,
Alessandro Rubinib102c012010-03-05 12:38:51 +0100192 .dev_id = &nmdk_clkevt,
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100193};
194
Rabin Vincentc7785ea2013-04-03 13:28:26 +0200195static void __init __nmdk_timer_init(void __iomem *base, int irq,
196 struct clk *pclk, struct clk *clk)
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100197{
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100198 unsigned long rate;
Linus Walleijba327b12010-05-26 07:38:54 +0100199
Linus Walleijb9576622012-01-11 09:46:59 +0100200 mtu_base = base;
Ulf Hansson16defa62012-10-24 14:13:41 +0200201
Rabin Vincentc7785ea2013-04-03 13:28:26 +0200202 BUG_ON(clk_prepare_enable(pclk));
203 BUG_ON(clk_prepare_enable(clk));
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100204
Alessandro Rubinib102c012010-03-05 12:38:51 +0100205 /*
Linus Walleija0719f52010-09-13 13:40:04 +0100206 * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
207 * for ux500.
208 * Use a divide-by-16 counter if the tick rate is more than 32MHz.
209 * At 32 MHz, the timer (with 32 bit counter) can be programmed
210 * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
211 * with 16 gives too low timer resolution.
Alessandro Rubinib102c012010-03-05 12:38:51 +0100212 */
Rabin Vincentc7785ea2013-04-03 13:28:26 +0200213 rate = clk_get_rate(clk);
Linus Walleija0719f52010-09-13 13:40:04 +0100214 if (rate > 32000000) {
Alessandro Rubinib102c012010-03-05 12:38:51 +0100215 rate /= 16;
Jonas Aaberg2f73a062011-09-14 10:32:51 +0200216 clk_prescale = MTU_CRn_PRESCALE_16;
Alessandro Rubinib102c012010-03-05 12:38:51 +0100217 } else {
Jonas Aaberg2f73a062011-09-14 10:32:51 +0200218 clk_prescale = MTU_CRn_PRESCALE_1;
Alessandro Rubinib102c012010-03-05 12:38:51 +0100219 }
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100220
Linus Walleij21366832012-10-18 11:12:31 +0200221 /* Cycles for periodic mode */
222 nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);
Jonas Aaberg2f73a062011-09-14 10:32:51 +0200223
224
Alessandro Rubinib102c012010-03-05 12:38:51 +0100225 /* Timer 0 is the free running clocksource */
Jonas Aaberg2f73a062011-09-14 10:32:51 +0200226 nmdk_clksrc_reset();
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100227
Russell Kingbfe45e02011-05-08 15:33:30 +0100228 if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
229 rate, 200, 32, clocksource_mmio_readl_down))
Alessandro Rubinib102c012010-03-05 12:38:51 +0100230 pr_err("timer: failed to initialize clock source %s\n",
Russell Kingbfe45e02011-05-08 15:33:30 +0100231 "mtu_0");
Marc Zyngier2f0778af2011-12-15 12:19:23 +0100232
Linus Walleijea7113f2013-04-20 16:09:17 +0200233#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
Marc Zyngier2f0778af2011-12-15 12:19:23 +0100234 setup_sched_clock(nomadik_read_sched_clock, 32, rate);
Mattias Wallincba13832011-05-27 10:29:25 +0200235#endif
Marc Zyngier2f0778af2011-12-15 12:19:23 +0100236
Linus Walleija3b86a62012-01-11 09:57:56 +0100237 /* Timer 1 is used for events, register irq and clockevents */
Linus Walleij08130692012-10-18 11:06:02 +0200238 setup_irq(irq, &nmdk_timer_irq);
Linus Walleija3b86a62012-01-11 09:57:56 +0100239 nmdk_clkevt.cpumask = cpumask_of(0);
Daniel Lezcano00f4e132013-02-22 16:44:30 +0100240 nmdk_clkevt.irq = irq;
Linus Walleija3b86a62012-01-11 09:57:56 +0100241 clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
Fabio Baltieri6f179b72012-12-04 11:10:44 +0100242
243 mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer;
244 mtu_delay_timer.freq = rate;
245 register_current_timer_delay(&mtu_delay_timer);
Alessandro Rubini28ad94e2009-07-02 19:06:47 +0100246}
Rabin Vincentc7785ea2013-04-03 13:28:26 +0200247
248void __init nmdk_timer_init(void __iomem *base, int irq)
249{
250 struct clk *clk0, *pclk0;
251
252 pclk0 = clk_get_sys("mtu0", "apb_pclk");
253 BUG_ON(IS_ERR(pclk0));
254 clk0 = clk_get_sys("mtu0", NULL);
255 BUG_ON(IS_ERR(clk0));
256
257 __nmdk_timer_init(base, irq, pclk0, clk0);
258}
259
Arnd Bergmann3c09f4d2013-05-31 17:49:28 +0200260static void __init nmdk_timer_of_init(struct device_node *node)
Rabin Vincentc7785ea2013-04-03 13:28:26 +0200261{
Rabin Vincentc7785ea2013-04-03 13:28:26 +0200262 struct clk *pclk;
263 struct clk *clk;
264 void __iomem *base;
265 int irq;
266
Rabin Vincentc7785ea2013-04-03 13:28:26 +0200267 base = of_iomap(node, 0);
268 if (!base)
269 panic("Can't remap registers");
270
271 pclk = of_clk_get_by_name(node, "apb_pclk");
272 if (IS_ERR(pclk))
273 panic("could not get apb_pclk");
274
275 clk = of_clk_get_by_name(node, "timclk");
276 if (IS_ERR(clk))
277 panic("could not get timclk");
278
279 irq = irq_of_parse_and_map(node, 0);
280 if (irq <= 0)
281 panic("Can't parse IRQ");
282
283 __nmdk_timer_init(base, irq, pclk, clk);
284}
285CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
286 nmdk_timer_of_init);