SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 1 | /* |
Andrew Victor | 9d04126 | 2007-02-05 11:42:07 +0100 | [diff] [blame] | 2 | * arch/arm/mach-at91/at91rm9200.c |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2005 SAN People |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | */ |
| 12 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 13 | #include <linux/module.h> |
| 14 | |
| 15 | #include <asm/mach/arch.h> |
| 16 | #include <asm/mach/map.h> |
Andrew Victor | 1f4fd0a | 2006-11-30 10:01:47 +0100 | [diff] [blame] | 17 | #include <asm/arch/at91rm9200.h> |
Andrew Victor | 55d8bae | 2006-11-30 17:16:43 +0100 | [diff] [blame] | 18 | #include <asm/arch/at91_pmc.h> |
| 19 | #include <asm/arch/at91_st.h> |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 20 | |
Andrew Victor | 10e8e1f | 2006-06-19 15:26:51 +0100 | [diff] [blame] | 21 | #include "generic.h" |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 22 | #include "clock.h" |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 23 | |
| 24 | static struct map_desc at91rm9200_io_desc[] __initdata = { |
| 25 | { |
| 26 | .virtual = AT91_VA_BASE_SYS, |
| 27 | .pfn = __phys_to_pfn(AT91_BASE_SYS), |
| 28 | .length = SZ_4K, |
| 29 | .type = MT_DEVICE, |
| 30 | }, { |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 31 | .virtual = AT91_VA_BASE_EMAC, |
Andrew Victor | 7272991 | 2006-09-27 09:44:11 +0100 | [diff] [blame] | 32 | .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC), |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 33 | .length = SZ_16K, |
| 34 | .type = MT_DEVICE, |
| 35 | }, { |
Andrew Victor | 05043d0 | 2006-12-01 11:51:19 +0100 | [diff] [blame] | 36 | .virtual = AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE, |
Andrew Victor | 7272991 | 2006-09-27 09:44:11 +0100 | [diff] [blame] | 37 | .pfn = __phys_to_pfn(AT91RM9200_SRAM_BASE), |
| 38 | .length = AT91RM9200_SRAM_SIZE, |
Andrew Victor | 10e8e1f | 2006-06-19 15:26:51 +0100 | [diff] [blame] | 39 | .type = MT_DEVICE, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 40 | }, |
| 41 | }; |
| 42 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 43 | /* -------------------------------------------------------------------- |
| 44 | * Clocks |
| 45 | * -------------------------------------------------------------------- */ |
| 46 | |
| 47 | /* |
| 48 | * The peripheral clocks. |
| 49 | */ |
| 50 | static struct clk udc_clk = { |
| 51 | .name = "udc_clk", |
| 52 | .pmc_mask = 1 << AT91RM9200_ID_UDP, |
| 53 | .type = CLK_TYPE_PERIPHERAL, |
| 54 | }; |
| 55 | static struct clk ohci_clk = { |
| 56 | .name = "ohci_clk", |
| 57 | .pmc_mask = 1 << AT91RM9200_ID_UHP, |
| 58 | .type = CLK_TYPE_PERIPHERAL, |
| 59 | }; |
| 60 | static struct clk ether_clk = { |
| 61 | .name = "ether_clk", |
| 62 | .pmc_mask = 1 << AT91RM9200_ID_EMAC, |
| 63 | .type = CLK_TYPE_PERIPHERAL, |
| 64 | }; |
| 65 | static struct clk mmc_clk = { |
| 66 | .name = "mci_clk", |
| 67 | .pmc_mask = 1 << AT91RM9200_ID_MCI, |
| 68 | .type = CLK_TYPE_PERIPHERAL, |
| 69 | }; |
| 70 | static struct clk twi_clk = { |
| 71 | .name = "twi_clk", |
| 72 | .pmc_mask = 1 << AT91RM9200_ID_TWI, |
| 73 | .type = CLK_TYPE_PERIPHERAL, |
| 74 | }; |
| 75 | static struct clk usart0_clk = { |
| 76 | .name = "usart0_clk", |
| 77 | .pmc_mask = 1 << AT91RM9200_ID_US0, |
| 78 | .type = CLK_TYPE_PERIPHERAL, |
| 79 | }; |
| 80 | static struct clk usart1_clk = { |
| 81 | .name = "usart1_clk", |
| 82 | .pmc_mask = 1 << AT91RM9200_ID_US1, |
| 83 | .type = CLK_TYPE_PERIPHERAL, |
| 84 | }; |
| 85 | static struct clk usart2_clk = { |
| 86 | .name = "usart2_clk", |
| 87 | .pmc_mask = 1 << AT91RM9200_ID_US2, |
| 88 | .type = CLK_TYPE_PERIPHERAL, |
| 89 | }; |
| 90 | static struct clk usart3_clk = { |
| 91 | .name = "usart3_clk", |
| 92 | .pmc_mask = 1 << AT91RM9200_ID_US3, |
| 93 | .type = CLK_TYPE_PERIPHERAL, |
| 94 | }; |
| 95 | static struct clk spi_clk = { |
| 96 | .name = "spi_clk", |
| 97 | .pmc_mask = 1 << AT91RM9200_ID_SPI, |
| 98 | .type = CLK_TYPE_PERIPHERAL, |
| 99 | }; |
| 100 | static struct clk pioA_clk = { |
| 101 | .name = "pioA_clk", |
| 102 | .pmc_mask = 1 << AT91RM9200_ID_PIOA, |
| 103 | .type = CLK_TYPE_PERIPHERAL, |
| 104 | }; |
| 105 | static struct clk pioB_clk = { |
| 106 | .name = "pioB_clk", |
| 107 | .pmc_mask = 1 << AT91RM9200_ID_PIOB, |
| 108 | .type = CLK_TYPE_PERIPHERAL, |
| 109 | }; |
| 110 | static struct clk pioC_clk = { |
| 111 | .name = "pioC_clk", |
| 112 | .pmc_mask = 1 << AT91RM9200_ID_PIOC, |
| 113 | .type = CLK_TYPE_PERIPHERAL, |
| 114 | }; |
| 115 | static struct clk pioD_clk = { |
| 116 | .name = "pioD_clk", |
| 117 | .pmc_mask = 1 << AT91RM9200_ID_PIOD, |
| 118 | .type = CLK_TYPE_PERIPHERAL, |
| 119 | }; |
Andrew Victor | e8788ba | 2007-05-02 17:14:57 +0100 | [diff] [blame] | 120 | static struct clk ssc0_clk = { |
| 121 | .name = "ssc0_clk", |
| 122 | .pmc_mask = 1 << AT91RM9200_ID_SSC0, |
| 123 | .type = CLK_TYPE_PERIPHERAL, |
| 124 | }; |
| 125 | static struct clk ssc1_clk = { |
| 126 | .name = "ssc1_clk", |
| 127 | .pmc_mask = 1 << AT91RM9200_ID_SSC1, |
| 128 | .type = CLK_TYPE_PERIPHERAL, |
| 129 | }; |
| 130 | static struct clk ssc2_clk = { |
| 131 | .name = "ssc2_clk", |
| 132 | .pmc_mask = 1 << AT91RM9200_ID_SSC2, |
| 133 | .type = CLK_TYPE_PERIPHERAL, |
| 134 | }; |
Andrew Victor | c177a1e | 2007-02-08 10:25:38 +0100 | [diff] [blame] | 135 | static struct clk tc0_clk = { |
| 136 | .name = "tc0_clk", |
| 137 | .pmc_mask = 1 << AT91RM9200_ID_TC0, |
| 138 | .type = CLK_TYPE_PERIPHERAL, |
| 139 | }; |
| 140 | static struct clk tc1_clk = { |
| 141 | .name = "tc1_clk", |
| 142 | .pmc_mask = 1 << AT91RM9200_ID_TC1, |
| 143 | .type = CLK_TYPE_PERIPHERAL, |
| 144 | }; |
| 145 | static struct clk tc2_clk = { |
| 146 | .name = "tc2_clk", |
| 147 | .pmc_mask = 1 << AT91RM9200_ID_TC2, |
| 148 | .type = CLK_TYPE_PERIPHERAL, |
| 149 | }; |
| 150 | static struct clk tc3_clk = { |
| 151 | .name = "tc3_clk", |
| 152 | .pmc_mask = 1 << AT91RM9200_ID_TC3, |
| 153 | .type = CLK_TYPE_PERIPHERAL, |
| 154 | }; |
| 155 | static struct clk tc4_clk = { |
| 156 | .name = "tc4_clk", |
| 157 | .pmc_mask = 1 << AT91RM9200_ID_TC4, |
| 158 | .type = CLK_TYPE_PERIPHERAL, |
| 159 | }; |
| 160 | static struct clk tc5_clk = { |
| 161 | .name = "tc5_clk", |
| 162 | .pmc_mask = 1 << AT91RM9200_ID_TC5, |
| 163 | .type = CLK_TYPE_PERIPHERAL, |
| 164 | }; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 165 | |
| 166 | static struct clk *periph_clocks[] __initdata = { |
| 167 | &pioA_clk, |
| 168 | &pioB_clk, |
| 169 | &pioC_clk, |
| 170 | &pioD_clk, |
| 171 | &usart0_clk, |
| 172 | &usart1_clk, |
| 173 | &usart2_clk, |
| 174 | &usart3_clk, |
| 175 | &mmc_clk, |
| 176 | &udc_clk, |
| 177 | &twi_clk, |
| 178 | &spi_clk, |
Andrew Victor | e8788ba | 2007-05-02 17:14:57 +0100 | [diff] [blame] | 179 | &ssc0_clk, |
| 180 | &ssc1_clk, |
| 181 | &ssc2_clk, |
Andrew Victor | c177a1e | 2007-02-08 10:25:38 +0100 | [diff] [blame] | 182 | &tc0_clk, |
| 183 | &tc1_clk, |
| 184 | &tc2_clk, |
| 185 | &tc3_clk, |
| 186 | &tc4_clk, |
| 187 | &tc5_clk, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 188 | &ohci_clk, |
| 189 | ðer_clk, |
| 190 | // irq0 .. irq6 |
| 191 | }; |
| 192 | |
| 193 | /* |
| 194 | * The four programmable clocks. |
| 195 | * You must configure pin multiplexing to bring these signals out. |
| 196 | */ |
| 197 | static struct clk pck0 = { |
| 198 | .name = "pck0", |
| 199 | .pmc_mask = AT91_PMC_PCK0, |
| 200 | .type = CLK_TYPE_PROGRAMMABLE, |
| 201 | .id = 0, |
| 202 | }; |
| 203 | static struct clk pck1 = { |
| 204 | .name = "pck1", |
| 205 | .pmc_mask = AT91_PMC_PCK1, |
| 206 | .type = CLK_TYPE_PROGRAMMABLE, |
| 207 | .id = 1, |
| 208 | }; |
| 209 | static struct clk pck2 = { |
| 210 | .name = "pck2", |
| 211 | .pmc_mask = AT91_PMC_PCK2, |
| 212 | .type = CLK_TYPE_PROGRAMMABLE, |
| 213 | .id = 2, |
| 214 | }; |
| 215 | static struct clk pck3 = { |
| 216 | .name = "pck3", |
| 217 | .pmc_mask = AT91_PMC_PCK3, |
| 218 | .type = CLK_TYPE_PROGRAMMABLE, |
| 219 | .id = 3, |
| 220 | }; |
| 221 | |
| 222 | static void __init at91rm9200_register_clocks(void) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 223 | { |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 224 | int i; |
| 225 | |
| 226 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) |
| 227 | clk_register(periph_clocks[i]); |
| 228 | |
| 229 | clk_register(&pck0); |
| 230 | clk_register(&pck1); |
| 231 | clk_register(&pck2); |
| 232 | clk_register(&pck3); |
| 233 | } |
| 234 | |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 235 | /* -------------------------------------------------------------------- |
| 236 | * GPIO |
| 237 | * -------------------------------------------------------------------- */ |
| 238 | |
| 239 | static struct at91_gpio_bank at91rm9200_gpio[] = { |
| 240 | { |
| 241 | .id = AT91RM9200_ID_PIOA, |
| 242 | .offset = AT91_PIOA, |
| 243 | .clock = &pioA_clk, |
| 244 | }, { |
| 245 | .id = AT91RM9200_ID_PIOB, |
| 246 | .offset = AT91_PIOB, |
| 247 | .clock = &pioB_clk, |
| 248 | }, { |
| 249 | .id = AT91RM9200_ID_PIOC, |
| 250 | .offset = AT91_PIOC, |
| 251 | .clock = &pioC_clk, |
| 252 | }, { |
| 253 | .id = AT91RM9200_ID_PIOD, |
| 254 | .offset = AT91_PIOD, |
| 255 | .clock = &pioD_clk, |
| 256 | } |
| 257 | }; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 258 | |
Andrew Victor | 1f4fd0a | 2006-11-30 10:01:47 +0100 | [diff] [blame] | 259 | static void at91rm9200_reset(void) |
| 260 | { |
| 261 | /* |
| 262 | * Perform a hardware reset with the use of the Watchdog timer. |
| 263 | */ |
| 264 | at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1); |
| 265 | at91_sys_write(AT91_ST_CR, AT91_ST_WDRST); |
| 266 | } |
| 267 | |
| 268 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 269 | /* -------------------------------------------------------------------- |
| 270 | * AT91RM9200 processor initialization |
| 271 | * -------------------------------------------------------------------- */ |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 272 | void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks) |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 273 | { |
| 274 | /* Map peripherals */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 275 | iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc)); |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 276 | |
Andrew Victor | 1f4fd0a | 2006-11-30 10:01:47 +0100 | [diff] [blame] | 277 | at91_arch_reset = at91rm9200_reset; |
| 278 | at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1) |
| 279 | | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3) |
| 280 | | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5) |
| 281 | | (1 << AT91RM9200_ID_IRQ6); |
| 282 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 283 | /* Init clock subsystem */ |
| 284 | at91_clock_init(main_clock); |
| 285 | |
| 286 | /* Register the processor-specific clocks */ |
| 287 | at91rm9200_register_clocks(); |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 288 | |
| 289 | /* Initialize GPIO subsystem */ |
| 290 | at91_gpio_init(at91rm9200_gpio, banks); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 291 | } |
| 292 | |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 293 | |
| 294 | /* -------------------------------------------------------------------- |
| 295 | * Interrupt initialization |
| 296 | * -------------------------------------------------------------------- */ |
| 297 | |
Andrew Victor | ba854e1 | 2006-07-05 17:22:52 +0100 | [diff] [blame] | 298 | /* |
| 299 | * The default interrupt priority levels (0 = lowest, 7 = highest). |
| 300 | */ |
| 301 | static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { |
| 302 | 7, /* Advanced Interrupt Controller (FIQ) */ |
| 303 | 7, /* System Peripherals */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 304 | 1, /* Parallel IO Controller A */ |
| 305 | 1, /* Parallel IO Controller B */ |
| 306 | 1, /* Parallel IO Controller C */ |
| 307 | 1, /* Parallel IO Controller D */ |
| 308 | 5, /* USART 0 */ |
| 309 | 5, /* USART 1 */ |
| 310 | 5, /* USART 2 */ |
| 311 | 5, /* USART 3 */ |
Andrew Victor | ba854e1 | 2006-07-05 17:22:52 +0100 | [diff] [blame] | 312 | 0, /* Multimedia Card Interface */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 313 | 2, /* USB Device Port */ |
| 314 | 6, /* Two-Wire Interface */ |
| 315 | 5, /* Serial Peripheral Interface */ |
| 316 | 4, /* Serial Synchronous Controller 0 */ |
| 317 | 4, /* Serial Synchronous Controller 1 */ |
| 318 | 4, /* Serial Synchronous Controller 2 */ |
Andrew Victor | ba854e1 | 2006-07-05 17:22:52 +0100 | [diff] [blame] | 319 | 0, /* Timer Counter 0 */ |
| 320 | 0, /* Timer Counter 1 */ |
| 321 | 0, /* Timer Counter 2 */ |
| 322 | 0, /* Timer Counter 3 */ |
| 323 | 0, /* Timer Counter 4 */ |
| 324 | 0, /* Timer Counter 5 */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 325 | 2, /* USB Host port */ |
Andrew Victor | ba854e1 | 2006-07-05 17:22:52 +0100 | [diff] [blame] | 326 | 3, /* Ethernet MAC */ |
| 327 | 0, /* Advanced Interrupt Controller (IRQ0) */ |
| 328 | 0, /* Advanced Interrupt Controller (IRQ1) */ |
| 329 | 0, /* Advanced Interrupt Controller (IRQ2) */ |
| 330 | 0, /* Advanced Interrupt Controller (IRQ3) */ |
| 331 | 0, /* Advanced Interrupt Controller (IRQ4) */ |
| 332 | 0, /* Advanced Interrupt Controller (IRQ5) */ |
| 333 | 0 /* Advanced Interrupt Controller (IRQ6) */ |
| 334 | }; |
| 335 | |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 336 | void __init at91rm9200_init_interrupts(unsigned int priority[NR_AIC_IRQS]) |
Andrew Victor | ba854e1 | 2006-07-05 17:22:52 +0100 | [diff] [blame] | 337 | { |
| 338 | if (!priority) |
| 339 | priority = at91rm9200_default_irq_priority; |
| 340 | |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 341 | /* Initialize the AIC interrupt controller */ |
Andrew Victor | ba854e1 | 2006-07-05 17:22:52 +0100 | [diff] [blame] | 342 | at91_aic_init(priority); |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 343 | |
| 344 | /* Enable GPIO interrupts */ |
| 345 | at91_gpio_irq_setup(); |
Andrew Victor | ba854e1 | 2006-07-05 17:22:52 +0100 | [diff] [blame] | 346 | } |