blob: 022e89ffec1da4bc8da86bf6ba8471634f4fdaad [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001#include <linux/serial_core.h>
Paul Mundte108b2c2006-09-27 16:32:13 +09002#include <asm/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07003#include <asm/gpio.h>
Markus Brunner3ea6bc32007-08-20 08:59:33 +09004
Linus Torvalds1da177e2005-04-16 15:20:36 -07005#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6#include <asm/regs306x.h>
7#endif
8#if defined(CONFIG_H8S2678)
9#include <asm/regs267x.h>
10#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070011
Magnus Damm0fbde952007-07-26 10:14:16 +090012#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7709)
Linus Torvalds1da177e2005-04-16 15:20:36 -070016# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
20# define SCIF0 0xA4400000
21# define SCIF2 0xA4410000
Paul Mundtb7a76e42006-02-01 03:06:06 -080022# define SCSMR_Ir 0xA44A0000
23# define IRDA_SCIF SCIF0
Linus Torvalds1da177e2005-04-16 15:20:36 -070024# define SCPCR 0xA4000116
25# define SCPDR 0xA4000136
26
27/* Set the clock source,
28 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
29 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
30 */
31# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
Yoshihiro Shimoda31a49c42007-12-26 11:45:06 +090032#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7721)
Markus Brunner3ea6bc32007-08-20 08:59:33 +090034# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
Paul Mundtfd88cac2009-01-09 16:32:08 +090035# define PORT_PTCR 0xA405011EUL
36# define PORT_PVCR 0xA4050122UL
37# define SCIF_ORER 0x0200 /* overrun error bit */
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#elif defined(CONFIG_SH_RTS7751R2D)
Matt Fleming7abc4042008-10-29 07:16:02 +000039# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
Linus Torvalds1da177e2005-04-16 15:20:36 -070040# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
41# define SCIF_ORER 0x0001 /* overrun error bit */
42# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
Paul Mundt05627482007-05-15 16:25:47 +090043#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
44 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
45 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
46 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
47 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
48 defined(CONFIG_CPU_SUBTYPE_SH7751R)
Linus Torvalds1da177e2005-04-16 15:20:36 -070049# define SCSPTR1 0xffe0001c /* 8 bit SCI */
50# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
51# define SCIF_ORER 0x0001 /* overrun error bit */
52# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
53 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
54 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
Linus Torvalds1da177e2005-04-16 15:20:36 -070055#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
Paul Mundtb7a76e42006-02-01 03:06:06 -080056# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
57# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
58# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
Linus Torvalds1da177e2005-04-16 15:20:36 -070059# define SCIF_ORER 0x0001 /* overrun error bit */
60# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
Paul Mundt2b1bd1a2007-06-20 18:27:10 +090061#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
Paul Mundte108b2c2006-09-27 16:32:13 +090062# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
Nobuhiro Iwamatsu9465a542007-03-27 18:13:51 +090063# define SCIF_ORER 0x0001 /* overrun error bit */
64# define PACR 0xa4050100
65# define PBCR 0xa4050102
66# define SCSCR_INIT(port) 0x3B
Paul Mundte108b2c2006-09-27 16:32:13 +090067#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
68# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
69# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
70# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
71# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
72# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
Paul Mundt41504c32006-12-11 20:28:03 +090073#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
Magnus Damm346b7462008-04-23 21:25:29 +090074# define PADR 0xA4050120
75# define PSDR 0xA405013e
76# define PWDR 0xA4050166
77# define PSCR 0xA405011E
Paul Mundt41504c32006-12-11 20:28:03 +090078# define SCIF_ORER 0x0001 /* overrun error bit */
79# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
Magnus Damm9109a302008-02-08 17:31:24 +090080#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
81# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
82# define SCSPTR0 SCPDR0
83# define SCIF_ORER 0x0001 /* overrun error bit */
84# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
Paul Mundt178dd0c2008-04-09 17:56:18 +090085#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
86# define SCSPTR0 0xa4050160
87# define SCSPTR1 0xa405013e
88# define SCSPTR2 0xa4050160
89# define SCSPTR3 0xa405013e
90# define SCSPTR4 0xa4050128
91# define SCSPTR5 0xa4050128
92# define SCIF_ORER 0x0001 /* overrun error bit */
93# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070094#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
Linus Torvalds1da177e2005-04-16 15:20:36 -070095# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
96# define SCIF_ORER 0x0001 /* overrun error bit */
97# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070098#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
Linus Torvalds1da177e2005-04-16 15:20:36 -070099# define SCIF_BASE_ADDR 0x01030000
100# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
101# define SCIF_PTR2_OFFS 0x0000020
102# define SCIF_LSR2_OFFS 0x0000024
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
104# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
Paul Mundtf9669182007-11-07 11:05:32 +0900105# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
109#elif defined(CONFIG_H8S2678)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
Yoshihiro Shimoda7d740a02008-01-07 14:40:07 +0900112#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
113# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
114# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
Nobuhiro Iwamatsuc63847a2008-06-06 17:04:08 +0900115# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
Yoshihiro Shimoda7d740a02008-01-07 14:40:07 +0900116# define SCIF_ORER 0x0001 /* overrun error bit */
Nobuhiro Iwamatsuc63847a2008-06-06 17:04:08 +0900117# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
Paul Mundtb7a76e42006-02-01 03:06:06 -0800118#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
119# define SCSPTR0 0xff923020 /* 16 bit SCIF */
120# define SCSPTR1 0xff924020 /* 16 bit SCIF */
121# define SCSPTR2 0xff925020 /* 16 bit SCIF */
122# define SCIF_ORER 0x0001 /* overrun error bit */
123# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
Paul Mundtb7a76e42006-02-01 03:06:06 -0800124#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
125# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
126# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
Paul Mundte108b2c2006-09-27 16:32:13 +0900127# define SCIF_ORER 0x0001 /* Overrun error bit */
Paul Mundtb7a76e42006-02-01 03:06:06 -0800128# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
Paul Mundt32351a22007-03-12 14:38:59 +0900129#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
130# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
131# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
132# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
133# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
134# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
135# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
Kuninori Morimoto34aeb432009-02-10 09:04:00 +0000136# define SCIF_ORER 0x0001 /* Overrun error bit */
Paul Mundt32351a22007-03-12 14:38:59 +0900137# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
Peter Griffin28259992008-11-28 22:48:20 +0900138#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
139 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
Paul Mundta8f67f42007-11-26 19:54:02 +0900140 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
141 defined(CONFIG_CPU_SUBTYPE_SH7263)
Yoshinori Sato9d4436a2006-11-05 15:40:13 +0900142# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
143# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
144# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
145# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
Peter Griffin28259992008-11-28 22:48:20 +0900146# if defined(CONFIG_CPU_SUBTYPE_SH7201)
147# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
148# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
149# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
150# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
151# endif
Yoshinori Sato9d4436a2006-11-05 15:40:13 +0900152# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
Yoshinori Sato9d4436a2006-11-05 15:40:13 +0900153#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
154# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
155# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
156# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
157# define SCIF_ORER 0x0001 /* overrun error bit */
158# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
Paul Mundt2b1bd1a2007-06-20 18:27:10 +0900159#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
160# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
161# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
162# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
163# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
164# define SCIF_ORER 0x0001 /* Overrun error bit */
165# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166#else
167# error CPU subtype not defined
168#endif
169
170/* SCSCR */
171#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
172#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
173#define SCI_CTRL_FLAGS_TE 0x20 /* all */
174#define SCI_CTRL_FLAGS_RE 0x10 /* all */
Paul Mundt05627482007-05-15 16:25:47 +0900175#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
176 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
177 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
Michael Trimarchia8884e32008-10-31 16:10:23 +0900178 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
Paul Mundt05627482007-05-15 16:25:47 +0900179 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
180 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
181 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
Nobuhiro Iwamatsuc63847a2008-06-06 17:04:08 +0900182 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
Paul Mundt05627482007-05-15 16:25:47 +0900183 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
Paul Mundt2b1bd1a2007-06-20 18:27:10 +0900184 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
185 defined(CONFIG_CPU_SUBTYPE_SHX3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
187#else
188#define SCI_CTRL_FLAGS_REIE 0
189#endif
190/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
191/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
192/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
193/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
194
195/* SCxSR SCI */
196#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
197#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
198#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
199#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
200#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
201#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
202/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
203/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
204
205#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
206
207/* SCxSR SCIF */
208#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
209#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
210#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
211#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
212#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
213#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
214#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
215#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
216
Markus Brunner3ea6bc32007-08-20 08:59:33 +0900217#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
Yoshihiro Shimoda31a49c42007-12-26 11:45:06 +0900218 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
219 defined(CONFIG_CPU_SUBTYPE_SH7721)
Nobuhiro Iwamatsuc63847a2008-06-06 17:04:08 +0900220# define SCIF_ORER 0x0200
221# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
222# define SCIF_RFDC_MASK 0x007f
223# define SCIF_TXROOM_MAX 64
224#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
225# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
226# define SCIF_RFDC_MASK 0x007f
227# define SCIF_TXROOM_MAX 64
228/* SH7763 SCIF2 support */
229# define SCIF2_RFDC_MASK 0x001f
230# define SCIF2_TXROOM_MAX 16
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231#else
Nobuhiro Iwamatsuc63847a2008-06-06 17:04:08 +0900232# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
233# define SCIF_RFDC_MASK 0x001f
234# define SCIF_TXROOM_MAX 16
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235#endif
236
Paul Mundtd830fa42008-12-16 19:29:38 +0900237#ifndef SCIF_ORER
238#define SCIF_ORER 0x0000
239#endif
240
Paul Mundt15c73aa2008-10-02 19:47:12 +0900241#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
242#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
243#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
244#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
245#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
246#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
247#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
Paul Mundtd830fa42008-12-16 19:29:38 +0900248#define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
Paul Mundt15c73aa2008-10-02 19:47:12 +0900249
Markus Brunner3ea6bc32007-08-20 08:59:33 +0900250#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
Yoshihiro Shimoda31a49c42007-12-26 11:45:06 +0900251 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
252 defined(CONFIG_CPU_SUBTYPE_SH7721)
Paul Mundt15c73aa2008-10-02 19:47:12 +0900253# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
254# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
255# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
256# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
259# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
260# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
261# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
262#endif
263
264/* SCFCR */
265#define SCFCR_RFRST 0x0002
266#define SCFCR_TFRST 0x0004
267#define SCFCR_TCRST 0x4000
268#define SCFCR_MCE 0x0008
269
270#define SCI_MAJOR 204
271#define SCI_MINOR_START 8
272
273/* Generic serial flags */
274#define SCI_RX_THROTTLE 0x0000001
275
276#define SCI_MAGIC 0xbabeface
277
278/*
279 * Events are used to schedule things to happen at timer-interrupt
280 * time, instead of at rs interrupt time.
281 */
282#define SCI_EVENT_WRITE_WAKEUP 0
283
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284#define SCI_IN(size, offset) \
Paul Mundtb7a76e42006-02-01 03:06:06 -0800285 if ((size) == 8) { \
Paul Mundt7ff731a2008-10-01 15:46:58 +0900286 return ioread8(port->membase + (offset)); \
Paul Mundtb7a76e42006-02-01 03:06:06 -0800287 } else { \
Paul Mundt7ff731a2008-10-01 15:46:58 +0900288 return ioread16(port->membase + (offset)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289 }
290#define SCI_OUT(size, offset, value) \
Paul Mundtb7a76e42006-02-01 03:06:06 -0800291 if ((size) == 8) { \
Paul Mundt7ff731a2008-10-01 15:46:58 +0900292 iowrite8(value, port->membase + (offset)); \
Magnus Damm3d2c2f32008-04-23 21:37:39 +0900293 } else if ((size) == 16) { \
Paul Mundt7ff731a2008-10-01 15:46:58 +0900294 iowrite16(value, port->membase + (offset)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295 }
296
297#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
298 static inline unsigned int sci_##name##_in(struct uart_port *port) \
299 { \
Yoshihiro Shimoda1a22f082008-11-11 12:19:05 +0900300 if (port->type == PORT_SCIF) { \
301 SCI_IN(scif_size, scif_offset) \
302 } else { /* PORT_SCI or PORT_SCIFA */ \
303 SCI_IN(sci_size, sci_offset); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304 } \
305 } \
306 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
307 { \
Yoshihiro Shimoda1a22f082008-11-11 12:19:05 +0900308 if (port->type == PORT_SCIF) { \
309 SCI_OUT(scif_size, scif_offset, value) \
310 } else { /* PORT_SCI or PORT_SCIFA */ \
311 SCI_OUT(sci_size, sci_offset, value); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312 } \
313 }
314
315#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
316 static inline unsigned int sci_##name##_in(struct uart_port *port) \
317 { \
Paul Mundtb7a76e42006-02-01 03:06:06 -0800318 SCI_IN(scif_size, scif_offset); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319 } \
320 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
321 { \
322 SCI_OUT(scif_size, scif_offset, value); \
323 }
324
325#define CPU_SCI_FNS(name, sci_offset, sci_size) \
326 static inline unsigned int sci_##name##_in(struct uart_port* port) \
327 { \
Paul Mundtb7a76e42006-02-01 03:06:06 -0800328 SCI_IN(sci_size, sci_offset); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329 } \
330 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
331 { \
332 SCI_OUT(sci_size, sci_offset, value); \
333 }
334
335#ifdef CONFIG_CPU_SH3
Nobuhiro Iwamatsu9465a542007-03-27 18:13:51 +0900336#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
337#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
338 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
339 h8_sci_offset, h8_sci_size) \
340 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
341#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
342 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
Markus Brunner3ea6bc32007-08-20 08:59:33 +0900343#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
Yoshihiro Shimoda31a49c42007-12-26 11:45:06 +0900344 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
345 defined(CONFIG_CPU_SUBTYPE_SH7721)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346#define SCIF_FNS(name, scif_offset, scif_size) \
347 CPU_SCIF_FNS(name, scif_offset, scif_size)
348#else
349#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
350 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
351 h8_sci_offset, h8_sci_size) \
352 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
353#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
354 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
355#endif
356#elif defined(__H8300H__) || defined(__H8300S__)
357#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
358 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
359 h8_sci_offset, h8_sci_size) \
360 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
361#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
Paul Mundt178dd0c2008-04-09 17:56:18 +0900362#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
363 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
364 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
365 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
366 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367#else
368#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
369 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
370 h8_sci_offset, h8_sci_size) \
371 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
372#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
373 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
374#endif
375
Markus Brunner3ea6bc32007-08-20 08:59:33 +0900376#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
Yoshihiro Shimoda31a49c42007-12-26 11:45:06 +0900377 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
378 defined(CONFIG_CPU_SUBTYPE_SH7721)
Nobuhiro Iwamatsu9465a542007-03-27 18:13:51 +0900379
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380SCIF_FNS(SCSMR, 0x00, 16)
381SCIF_FNS(SCBRR, 0x04, 8)
382SCIF_FNS(SCSCR, 0x08, 16)
383SCIF_FNS(SCTDSR, 0x0c, 8)
384SCIF_FNS(SCFER, 0x10, 16)
385SCIF_FNS(SCxSR, 0x14, 16)
386SCIF_FNS(SCFCR, 0x18, 16)
387SCIF_FNS(SCFDR, 0x1c, 16)
388SCIF_FNS(SCxTDR, 0x20, 8)
389SCIF_FNS(SCxRDR, 0x24, 8)
390SCIF_FNS(SCLSR, 0x24, 16)
Paul Mundt178dd0c2008-04-09 17:56:18 +0900391#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
392SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
393SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
394SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
395SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
396SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
397SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
Magnus Dammf6863592009-01-20 12:18:22 +0900398SCIx_FNS(SCSPTR, 0, 0, 0, 0)
Paul Mundt178dd0c2008-04-09 17:56:18 +0900399SCIF_FNS(SCTDSR, 0x0c, 8)
400SCIF_FNS(SCFER, 0x10, 16)
401SCIF_FNS(SCFCR, 0x18, 16)
402SCIF_FNS(SCFDR, 0x1c, 16)
403SCIF_FNS(SCLSR, 0x24, 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404#else
405/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
406/* name off sz off sz off sz off sz off sz*/
407SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
408SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
409SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
410SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
411SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
412SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
413SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
Paul Mundt32351a22007-03-12 14:38:59 +0900414#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
415 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
416 defined(CONFIG_CPU_SUBTYPE_SH7785)
Paul Mundtc2697962008-07-30 00:56:39 +0900417SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
Paul Mundtb7a76e42006-02-01 03:06:06 -0800418SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
419SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
420SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
421SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
Paul Mundtc2697962008-07-30 00:56:39 +0900422#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
Nobuhiro Iwamatsuc63847a2008-06-06 17:04:08 +0900423SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
424SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
Paul Mundtc2697962008-07-30 00:56:39 +0900425SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
426SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
427SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
428SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
429SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
Paul Mundtb7a76e42006-02-01 03:06:06 -0800430#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
Magnus Damm9b4e4662008-04-23 21:31:14 +0900432#if defined(CONFIG_CPU_SUBTYPE_SH7722)
433SCIF_FNS(SCSPTR, 0, 0, 0, 0)
434#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
Magnus Damm9b4e4662008-04-23 21:31:14 +0900436#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700437SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
438#endif
Paul Mundtb7a76e42006-02-01 03:06:06 -0800439#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700440#define sci_in(port, reg) sci_##reg##_in(port)
441#define sci_out(port, reg, value) sci_##reg##_out(port, value)
442
443/* H8/300 series SCI pins assignment */
444#if defined(__H8300H__) || defined(__H8300S__)
445static const struct __attribute__((packed)) {
446 int port; /* GPIO port no */
447 unsigned short rx,tx; /* GPIO bit no */
448} h8300_sci_pins[] = {
449#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
450 { /* SCI0 */
451 .port = H8300_GPIO_P9,
452 .rx = H8300_GPIO_B2,
453 .tx = H8300_GPIO_B0,
454 },
455 { /* SCI1 */
456 .port = H8300_GPIO_P9,
457 .rx = H8300_GPIO_B3,
458 .tx = H8300_GPIO_B1,
459 },
460 { /* SCI2 */
461 .port = H8300_GPIO_PB,
462 .rx = H8300_GPIO_B7,
463 .tx = H8300_GPIO_B6,
464 }
465#elif defined(CONFIG_H8S2678)
466 { /* SCI0 */
467 .port = H8300_GPIO_P3,
468 .rx = H8300_GPIO_B2,
469 .tx = H8300_GPIO_B0,
470 },
471 { /* SCI1 */
472 .port = H8300_GPIO_P3,
473 .rx = H8300_GPIO_B3,
474 .tx = H8300_GPIO_B1,
475 },
476 { /* SCI2 */
477 .port = H8300_GPIO_P5,
478 .rx = H8300_GPIO_B1,
479 .tx = H8300_GPIO_B0,
480 }
481#endif
482};
483#endif
484
Magnus Damm0fbde952007-07-26 10:14:16 +0900485#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
486 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
487 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
488 defined(CONFIG_CPU_SUBTYPE_SH7709)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489static inline int sci_rxd_in(struct uart_port *port)
490{
491 if (port->mapbase == 0xfffffe80)
492 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
493 if (port->mapbase == 0xa4000150)
494 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
495 if (port->mapbase == 0xa4000140)
496 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
497 return 1;
498}
499#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
500static inline int sci_rxd_in(struct uart_port *port)
501{
502 if (port->mapbase == SCIF0)
503 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
504 if (port->mapbase == SCIF2)
505 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
506 return 1;
507}
Nobuhiro Iwamatsu9465a542007-03-27 18:13:51 +0900508#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
Paul Mundte108b2c2006-09-27 16:32:13 +0900509static inline int sci_rxd_in(struct uart_port *port)
510{
Nobuhiro Iwamatsu9465a542007-03-27 18:13:51 +0900511 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
Paul Mundte108b2c2006-09-27 16:32:13 +0900512}
Yoshihiro Shimoda31a49c42007-12-26 11:45:06 +0900513#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
514 defined(CONFIG_CPU_SUBTYPE_SH7721)
Markus Brunner3ea6bc32007-08-20 08:59:33 +0900515static inline int sci_rxd_in(struct uart_port *port)
516{
517 if (port->mapbase == 0xa4430000)
518 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
519 else if (port->mapbase == 0xa4438000)
520 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
521 return 1;
522}
Paul Mundt05627482007-05-15 16:25:47 +0900523#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
524 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
525 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
526 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
527 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
Nobuhiro Iwamatsu961e9ff2008-10-29 13:33:45 +0900528 defined(CONFIG_CPU_SUBTYPE_SH7091)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700529static inline int sci_rxd_in(struct uart_port *port)
530{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700531 if (port->mapbase == 0xffe00000)
532 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533 if (port->mapbase == 0xffe80000)
534 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700535 return 1;
536}
Nobuhiro Iwamatsu961e9ff2008-10-29 13:33:45 +0900537#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
538static inline int sci_rxd_in(struct uart_port *port)
539{
540 if (port->mapbase == 0xffe80000)
541 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
542 return 1;
543}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
545static inline int sci_rxd_in(struct uart_port *port)
546{
547 if (port->mapbase == 0xfe600000)
548 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
549 if (port->mapbase == 0xfe610000)
550 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
551 if (port->mapbase == 0xfe620000)
552 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
Paul Mundt31388752006-12-08 14:26:19 +0900553 return 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700554}
Paul Mundte108b2c2006-09-27 16:32:13 +0900555#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
556static inline int sci_rxd_in(struct uart_port *port)
557{
558 if (port->mapbase == 0xffe00000)
559 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
560 if (port->mapbase == 0xffe10000)
561 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
562 if (port->mapbase == 0xffe20000)
563 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
564 if (port->mapbase == 0xffe30000)
565 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
566 return 1;
567}
Magnus Damm346b7462008-04-23 21:25:29 +0900568#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
Paul Mundt41504c32006-12-11 20:28:03 +0900569static inline int sci_rxd_in(struct uart_port *port)
570{
571 if (port->mapbase == 0xffe00000)
572 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
573 return 1;
574}
Magnus Damm346b7462008-04-23 21:25:29 +0900575#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
576static inline int sci_rxd_in(struct uart_port *port)
577{
578 if (port->mapbase == 0xffe00000)
579 return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
580 if (port->mapbase == 0xffe10000)
581 return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
582 if (port->mapbase == 0xffe20000)
583 return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
584
585 return 1;
586}
Paul Mundt178dd0c2008-04-09 17:56:18 +0900587#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
588static inline int sci_rxd_in(struct uart_port *port)
589{
590 if (port->mapbase == 0xffe00000)
591 return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
592 if (port->mapbase == 0xffe10000)
593 return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
594 if (port->mapbase == 0xffe20000)
595 return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
596 if (port->mapbase == 0xa4e30000)
597 return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
598 if (port->mapbase == 0xa4e40000)
599 return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
600 if (port->mapbase == 0xa4e50000)
601 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
602 return 1;
603}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
605static inline int sci_rxd_in(struct uart_port *port)
606{
Nobuhiro Iwamatsuaeffd542008-10-29 13:34:50 +0900607 return sci_in(port, SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700608}
609#elif defined(__H8300H__) || defined(__H8300S__)
610static inline int sci_rxd_in(struct uart_port *port)
611{
612 int ch = (port->mapbase - SMR0) >> 3;
613 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
614}
Yoshihiro Shimoda7d740a02008-01-07 14:40:07 +0900615#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
616static inline int sci_rxd_in(struct uart_port *port)
617{
618 if (port->mapbase == 0xffe00000)
619 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
620 if (port->mapbase == 0xffe08000)
621 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
Nobuhiro Iwamatsuc63847a2008-06-06 17:04:08 +0900622 if (port->mapbase == 0xffe10000)
623 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */
624
Yoshihiro Shimoda7d740a02008-01-07 14:40:07 +0900625 return 1;
626}
Paul Mundtb7a76e42006-02-01 03:06:06 -0800627#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
628static inline int sci_rxd_in(struct uart_port *port)
629{
630 if (port->mapbase == 0xff923000)
631 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
632 if (port->mapbase == 0xff924000)
633 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
634 if (port->mapbase == 0xff925000)
635 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
Paul Mundt31388752006-12-08 14:26:19 +0900636 return 1;
Paul Mundtb7a76e42006-02-01 03:06:06 -0800637}
638#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
639static inline int sci_rxd_in(struct uart_port *port)
640{
641 if (port->mapbase == 0xffe00000)
642 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
643 if (port->mapbase == 0xffe10000)
644 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
Paul Mundt31388752006-12-08 14:26:19 +0900645 return 1;
Paul Mundtb7a76e42006-02-01 03:06:06 -0800646}
Paul Mundt32351a22007-03-12 14:38:59 +0900647#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
648static inline int sci_rxd_in(struct uart_port *port)
649{
650 if (port->mapbase == 0xffea0000)
651 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
652 if (port->mapbase == 0xffeb0000)
653 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
654 if (port->mapbase == 0xffec0000)
655 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
656 if (port->mapbase == 0xffed0000)
657 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
658 if (port->mapbase == 0xffee0000)
659 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
660 if (port->mapbase == 0xffef0000)
661 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
662 return 1;
663}
Peter Griffin28259992008-11-28 22:48:20 +0900664#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
665 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
Paul Mundta8f67f42007-11-26 19:54:02 +0900666 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
667 defined(CONFIG_CPU_SUBTYPE_SH7263)
Yoshinori Sato9d4436a2006-11-05 15:40:13 +0900668static inline int sci_rxd_in(struct uart_port *port)
669{
670 if (port->mapbase == 0xfffe8000)
671 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
672 if (port->mapbase == 0xfffe8800)
673 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
674 if (port->mapbase == 0xfffe9000)
675 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
676 if (port->mapbase == 0xfffe9800)
677 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
Peter Griffin28259992008-11-28 22:48:20 +0900678#if defined(CONFIG_CPU_SUBTYPE_SH7201)
679 if (port->mapbase == 0xfffeA000)
680 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
681 if (port->mapbase == 0xfffeA800)
682 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
683 if (port->mapbase == 0xfffeB000)
684 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
685 if (port->mapbase == 0xfffeB800)
686 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
687#endif
Paul Mundt31388752006-12-08 14:26:19 +0900688 return 1;
Yoshinori Sato9d4436a2006-11-05 15:40:13 +0900689}
690#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
691static inline int sci_rxd_in(struct uart_port *port)
692{
693 if (port->mapbase == 0xf8400000)
694 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
695 if (port->mapbase == 0xf8410000)
696 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
697 if (port->mapbase == 0xf8420000)
698 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
Paul Mundt31388752006-12-08 14:26:19 +0900699 return 1;
Yoshinori Sato9d4436a2006-11-05 15:40:13 +0900700}
Paul Mundt2b1bd1a2007-06-20 18:27:10 +0900701#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
702static inline int sci_rxd_in(struct uart_port *port)
703{
704 if (port->mapbase == 0xffc30000)
705 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
706 if (port->mapbase == 0xffc40000)
707 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
708 if (port->mapbase == 0xffc50000)
709 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
710 if (port->mapbase == 0xffc60000)
711 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
Paul Mundt1760b7d72007-08-08 16:57:05 +0900712 return 1;
Paul Mundt2b1bd1a2007-06-20 18:27:10 +0900713}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700714#endif
715
716/*
717 * Values for the BitRate Register (SCBRR)
718 *
719 * The values are actually divisors for a frequency which can
720 * be internal to the SH3 (14.7456MHz) or derived from an external
721 * clock source. This driver assumes the internal clock is used;
722 * to support using an external clock source, config options or
723 * possibly command-line options would need to be added.
724 *
725 * Also, to support speeds below 2400 (why?) the lower 2 bits of
726 * the SCSMR register would also need to be set to non-zero values.
727 *
728 * -- Greg Banks 27Feb2000
729 *
730 * Answer: The SCBRR register is only eight bits, and the value in
731 * it gets larger with lower baud rates. At around 2400 (depending on
732 * the peripherial module clock) you run out of bits. However the
733 * lower two bits of SCSMR allow the module clock to be divided down,
734 * scaling the value which is needed in SCBRR.
735 *
736 * -- Stuart Menefy - 23 May 2000
737 *
738 * I meant, why would anyone bother with bitrates below 2400.
739 *
740 * -- Greg Banks - 7Jul2000
741 *
742 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
743 * tape reader as a console!
744 *
745 * -- Mitch Davis - 15 Jul 2000
746 */
747
Nobuhiro Iwamatsuc63847a2008-06-06 17:04:08 +0900748#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
Paul Mundt32351a22007-03-12 14:38:59 +0900749 defined(CONFIG_CPU_SUBTYPE_SH7785)
Paul Mundtb7a76e42006-02-01 03:06:06 -0800750#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
Markus Brunner3ea6bc32007-08-20 08:59:33 +0900751#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
Yoshihiro Shimoda31a49c42007-12-26 11:45:06 +0900752 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
753 defined(CONFIG_CPU_SUBTYPE_SH7721)
Paul Mundtb7a76e42006-02-01 03:06:06 -0800754#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
Paul Mundt178dd0c2008-04-09 17:56:18 +0900755#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
Nobuhiro Iwamatsuba1d2812008-10-03 17:37:31 +0900756static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
757{
758 if (port->type == PORT_SCIF)
759 return (clk+16*bps)/(32*bps)-1;
760 else
761 return ((clk*2)+16*bps)/(16*bps)-1;
762}
763#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
Paul Mundtb7a76e42006-02-01 03:06:06 -0800764#elif defined(__H8300H__) || defined(__H8300S__)
Paul Mundta2159b52008-10-02 19:09:13 +0900765#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
Paul Mundtb7a76e42006-02-01 03:06:06 -0800766#else /* Generic SH */
767#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700768#endif