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Rafał Miłecki8369ae32011-05-09 18:56:46 +02001/*
2 * Broadcom specific AMBA
3 * PCI Core
4 *
Hauke Mehrtens49dc9572012-01-31 00:03:35 +01005 * Copyright 2005, 2011, Broadcom Corporation
Michael Büscheb032b92011-07-04 20:50:05 +02006 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +01007 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
Rafał Miłecki8369ae32011-05-09 18:56:46 +02008 *
9 * Licensed under the GNU/GPL. See COPYING for details.
10 */
11
12#include "bcma_private.h"
Paul Gortmaker44a8e372011-07-27 21:21:04 -040013#include <linux/export.h>
Rafał Miłecki8369ae32011-05-09 18:56:46 +020014#include <linux/bcma/bcma.h>
15
16/**************************************************
17 * R/W ops.
18 **************************************************/
19
Hauke Mehrtens4b259a52012-01-31 00:03:33 +010020u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
Rafał Miłecki8369ae32011-05-09 18:56:46 +020021{
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010022 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
23 pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
24 return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020025}
26
Rafał Miłecki8369ae32011-05-09 18:56:46 +020027static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
28{
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010029 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
30 pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
31 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020032}
Rafał Miłecki8369ae32011-05-09 18:56:46 +020033
Hauke Mehrtens521deea2013-08-24 00:32:33 +020034static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
Rafał Miłecki8369ae32011-05-09 18:56:46 +020035{
Rafał Miłecki8369ae32011-05-09 18:56:46 +020036 u32 v;
37 int i;
38
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010039 v = BCMA_CORE_PCI_MDIODATA_START;
40 v |= BCMA_CORE_PCI_MDIODATA_WRITE;
41 v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
42 BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
43 v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
44 BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
45 v |= BCMA_CORE_PCI_MDIODATA_TA;
Rafał Miłecki8369ae32011-05-09 18:56:46 +020046 v |= (phy << 4);
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010047 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020048
49 udelay(10);
50 for (i = 0; i < 200; i++) {
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010051 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
52 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
Rafał Miłecki8369ae32011-05-09 18:56:46 +020053 break;
Rafał Miłecki1fd41a62012-09-25 10:17:22 +020054 usleep_range(1000, 2000);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020055 }
56}
57
Hauke Mehrtens521deea2013-08-24 00:32:33 +020058static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
Rafał Miłecki8369ae32011-05-09 18:56:46 +020059{
Rafał Miłecki8369ae32011-05-09 18:56:46 +020060 int max_retries = 10;
61 u16 ret = 0;
62 u32 v;
63 int i;
64
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010065 /* enable mdio access to SERDES */
66 v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
67 v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
68 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020069
70 if (pc->core->id.rev >= 10) {
71 max_retries = 200;
72 bcma_pcie_mdio_set_phy(pc, device);
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010073 v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
74 BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
75 v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
76 } else {
77 v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
78 v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020079 }
80
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010081 v = BCMA_CORE_PCI_MDIODATA_START;
82 v |= BCMA_CORE_PCI_MDIODATA_READ;
83 v |= BCMA_CORE_PCI_MDIODATA_TA;
84
85 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020086 /* Wait for the device to complete the transaction */
87 udelay(10);
Rafał Miłeckif1a9c1e2011-05-12 00:01:47 +020088 for (i = 0; i < max_retries; i++) {
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010089 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
90 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
Rafał Miłecki8369ae32011-05-09 18:56:46 +020091 udelay(10);
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010092 ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020093 break;
94 }
Rafał Miłecki1fd41a62012-09-25 10:17:22 +020095 usleep_range(1000, 2000);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020096 }
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +010097 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
Rafał Miłecki8369ae32011-05-09 18:56:46 +020098 return ret;
99}
100
Hauke Mehrtens521deea2013-08-24 00:32:33 +0200101static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200102 u8 address, u16 data)
103{
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200104 int max_retries = 10;
105 u32 v;
106 int i;
107
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +0100108 /* enable mdio access to SERDES */
109 v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
110 v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
111 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200112
113 if (pc->core->id.rev >= 10) {
114 max_retries = 200;
115 bcma_pcie_mdio_set_phy(pc, device);
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +0100116 v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
117 BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
118 v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
119 } else {
120 v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
121 v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200122 }
123
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +0100124 v = BCMA_CORE_PCI_MDIODATA_START;
125 v |= BCMA_CORE_PCI_MDIODATA_WRITE;
126 v |= BCMA_CORE_PCI_MDIODATA_TA;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200127 v |= data;
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +0100128 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200129 /* Wait for the device to complete the transaction */
130 udelay(10);
131 for (i = 0; i < max_retries; i++) {
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +0100132 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
133 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200134 break;
Rafał Miłecki1fd41a62012-09-25 10:17:22 +0200135 usleep_range(1000, 2000);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200136 }
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +0100137 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200138}
139
Hauke Mehrtens521deea2013-08-24 00:32:33 +0200140static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
141 u8 address, u16 data)
142{
143 bcma_pcie_mdio_write(pc, device, address, data);
144 return bcma_pcie_mdio_read(pc, device, address);
145}
146
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200147/**************************************************
Rafał Miłeckib5040752015-01-25 11:11:14 +0100148 * Early init.
149 **************************************************/
150
151static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc)
152{
153 struct bcma_device *core = pc->core;
154 u16 val16, core_index;
155 uint regoff;
156
157 regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET);
158 core_index = (u16)core->core_index;
159
160 val16 = pcicore_read16(pc, regoff);
161 if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT)
162 != core_index) {
163 val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) |
164 (val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK);
165 pcicore_write16(pc, regoff, val16);
166 }
167}
168
169/*
170 * Apply some early fixes required before accessing SPROM.
171 * See also si_pci_fixcfg.
172 */
173void bcma_core_pci_early_init(struct bcma_drv_pci *pc)
174{
175 if (pc->early_setup_done)
176 return;
177
178 pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
179 if (pc->hostmode)
180 goto out;
181
182 bcma_core_pci_fixcfg(pc);
183
184out:
185 pc->early_setup_done = true;
186}
187
188/**************************************************
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200189 * Workarounds.
190 **************************************************/
191
192static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
193{
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +0100194 u32 tmp;
195
196 tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
197 if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
198 return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
199 BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
200 else
201 return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200202}
203
204static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
205{
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200206 u16 tmp;
207
Hauke Mehrtens2be25ca2012-01-31 00:03:32 +0100208 bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
209 BCMA_CORE_PCI_SERDES_RX_CTRL,
210 bcma_pcicore_polarity_workaround(pc));
211 tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
212 BCMA_CORE_PCI_SERDES_PLL_CTRL);
213 if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
214 bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
215 BCMA_CORE_PCI_SERDES_PLL_CTRL,
216 tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200217}
218
Hauke Mehrtens2b2715b2012-04-29 02:18:52 +0200219/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
220/* Needs to happen when coming out of 'standby'/'hibernate' */
221static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc)
222{
223 u16 val16;
224 uint regoff;
225
226 regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG);
227
228 val16 = pcicore_read16(pc, regoff);
229
230 if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) {
231 val16 |= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST;
232 pcicore_write16(pc, regoff, val16);
233 }
234}
235
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200236/**************************************************
237 * Init.
238 **************************************************/
239
Greg Kroah-Hartman0f58a012012-12-21 15:12:59 -0800240static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200241{
242 bcma_pcicore_serdes_workaround(pc);
Hauke Mehrtens2b2715b2012-04-29 02:18:52 +0200243 bcma_core_pci_config_fixup(pc);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200244}
Rafał Miłecki1de520f2011-05-19 14:08:22 +0200245
Greg Kroah-Hartman0f58a012012-12-21 15:12:59 -0800246void bcma_core_pci_init(struct bcma_drv_pci *pc)
Rafał Miłecki9352f692011-07-05 19:48:26 +0200247{
Hauke Mehrtens517f43e2011-07-23 01:20:07 +0200248 if (pc->setup_done)
249 return;
250
Rafał Miłeckib5040752015-01-25 11:11:14 +0100251 bcma_core_pci_early_init(pc);
252
Hauke Mehrtens49dc9572012-01-31 00:03:35 +0100253 if (pc->hostmode)
Rafał Miłecki9352f692011-07-05 19:48:26 +0200254 bcma_core_pci_hostmode_init(pc);
Rafał Miłeckib5040752015-01-25 11:11:14 +0100255 else
Hauke Mehrtens49dc9572012-01-31 00:03:35 +0100256 bcma_core_pci_clientmode_init(pc);
Rafał Miłecki9352f692011-07-05 19:48:26 +0200257}
258
Arend van Spriel2bedea82013-09-25 12:11:02 +0200259void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
260{
261 struct bcma_drv_pci *pc;
262 u16 data;
263
264 if (bus->hosttype != BCMA_HOSTTYPE_PCI)
265 return;
266
267 pc = &bus->drv_pci[0];
268
269 if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
270 data = up ? 0x74 : 0x7C;
271 bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
272 BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
273 bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
274 BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
275 } else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
276 data = up ? 0x75 : 0x7D;
277 bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
278 BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
279 bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
280 BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
281 }
282}
283EXPORT_SYMBOL_GPL(bcma_core_pci_power_save);
284
Hauke Mehrtens780335a2013-08-24 00:32:32 +0200285static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
Hauke Mehrtens29f6b3d2012-04-29 02:18:50 +0200286{
287 u32 w;
288
289 w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
290 if (extend)
291 w |= BCMA_CORE_PCI_ASPMTIMER_EXTEND;
292 else
293 w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND;
294 bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
295 bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
296}
Hauke Mehrtenscfe51ec2013-08-24 00:32:30 +0200297
Rafał Miłecki41867212015-02-08 17:11:47 +0100298void bcma_core_pci_up(struct bcma_drv_pci *pc)
Hauke Mehrtenscfe51ec2013-08-24 00:32:30 +0200299{
Hauke Mehrtenscfe51ec2013-08-24 00:32:30 +0200300 bcma_core_pci_extend_L1timer(pc, true);
301}
Hauke Mehrtenscfe51ec2013-08-24 00:32:30 +0200302
Rafał Miłecki41867212015-02-08 17:11:47 +0100303void bcma_core_pci_down(struct bcma_drv_pci *pc)
Hauke Mehrtenscfe51ec2013-08-24 00:32:30 +0200304{
Hauke Mehrtenscfe51ec2013-08-24 00:32:30 +0200305 bcma_core_pci_extend_L1timer(pc, false);
306}