Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
| 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 4 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 6 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the |
| 10 | * "Software"), to deal in the Software without restriction, including |
| 11 | * without limitation the rights to use, copy, modify, merge, publish, |
| 12 | * distribute, sub license, and/or sell copies of the Software, and to |
| 13 | * permit persons to whom the Software is furnished to do so, subject to |
| 14 | * the following conditions: |
| 15 | * |
| 16 | * The above copyright notice and this permission notice (including the |
| 17 | * next paragraph) shall be included in all copies or substantial portions |
| 18 | * of the Software. |
| 19 | * |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 27 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 28 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | |
| 30 | #ifndef _I915_DRV_H_ |
| 31 | #define _I915_DRV_H_ |
| 32 | |
Chris Wilson | e9b73c6 | 2012-12-03 21:03:14 +0000 | [diff] [blame] | 33 | #include <uapi/drm/i915_drm.h> |
| 34 | |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 35 | #include "i915_reg.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include "intel_bios.h" |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 37 | #include "intel_ringbuffer.h" |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 38 | #include <linux/io-mapping.h> |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 39 | #include <linux/i2c.h> |
Daniel Vetter | c167a6f | 2012-02-28 00:43:09 +0100 | [diff] [blame] | 40 | #include <linux/i2c-algo-bit.h> |
Daniel Vetter | 0ade638 | 2010-08-24 22:18:41 +0200 | [diff] [blame] | 41 | #include <drm/intel-gtt.h> |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 42 | #include <linux/backlight.h> |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 43 | #include <linux/intel-iommu.h> |
Daniel Vetter | 742cbee | 2012-04-27 15:17:39 +0200 | [diff] [blame] | 44 | #include <linux/kref.h> |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 45 | #include <linux/pm_qos.h> |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 46 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | /* General customization: |
| 48 | */ |
| 49 | |
| 50 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." |
| 51 | |
| 52 | #define DRIVER_NAME "i915" |
| 53 | #define DRIVER_DESC "Intel Graphics" |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 54 | #define DRIVER_DATE "20080730" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 56 | enum pipe { |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 57 | INVALID_PIPE = -1, |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 58 | PIPE_A = 0, |
| 59 | PIPE_B, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 60 | PIPE_C, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 61 | _PIPE_EDP, |
| 62 | I915_MAX_PIPES = _PIPE_EDP |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 63 | }; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 64 | #define pipe_name(p) ((p) + 'A') |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 65 | |
Paulo Zanoni | a5c961d | 2012-10-24 15:59:34 -0200 | [diff] [blame] | 66 | enum transcoder { |
| 67 | TRANSCODER_A = 0, |
| 68 | TRANSCODER_B, |
| 69 | TRANSCODER_C, |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 70 | TRANSCODER_EDP, |
| 71 | I915_MAX_TRANSCODERS |
Paulo Zanoni | a5c961d | 2012-10-24 15:59:34 -0200 | [diff] [blame] | 72 | }; |
| 73 | #define transcoder_name(t) ((t) + 'A') |
| 74 | |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 75 | enum plane { |
| 76 | PLANE_A = 0, |
| 77 | PLANE_B, |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 78 | PLANE_C, |
Jesse Barnes | 8082400 | 2009-09-10 15:28:06 -0700 | [diff] [blame] | 79 | }; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 80 | #define plane_name(p) ((p) + 'A') |
Keith Packard | 5244021 | 2008-11-18 09:30:25 -0800 | [diff] [blame] | 81 | |
Damien Lespiau | d615a16 | 2014-03-03 17:31:48 +0000 | [diff] [blame] | 82 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
Ville Syrjälä | 06da8da | 2013-04-17 17:48:51 +0300 | [diff] [blame] | 83 | |
Eugeni Dodonov | 2b13952 | 2012-03-29 12:32:22 -0300 | [diff] [blame] | 84 | enum port { |
| 85 | PORT_A = 0, |
| 86 | PORT_B, |
| 87 | PORT_C, |
| 88 | PORT_D, |
| 89 | PORT_E, |
| 90 | I915_MAX_PORTS |
| 91 | }; |
| 92 | #define port_name(p) ((p) + 'A') |
| 93 | |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 94 | #define I915_NUM_PHYS_VLV 1 |
| 95 | |
| 96 | enum dpio_channel { |
| 97 | DPIO_CH0, |
| 98 | DPIO_CH1 |
| 99 | }; |
| 100 | |
| 101 | enum dpio_phy { |
| 102 | DPIO_PHY0, |
| 103 | DPIO_PHY1 |
| 104 | }; |
| 105 | |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 106 | enum intel_display_power_domain { |
| 107 | POWER_DOMAIN_PIPE_A, |
| 108 | POWER_DOMAIN_PIPE_B, |
| 109 | POWER_DOMAIN_PIPE_C, |
| 110 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, |
| 111 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, |
| 112 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, |
| 113 | POWER_DOMAIN_TRANSCODER_A, |
| 114 | POWER_DOMAIN_TRANSCODER_B, |
| 115 | POWER_DOMAIN_TRANSCODER_C, |
Imre Deak | f52e353 | 2013-10-16 17:25:48 +0300 | [diff] [blame] | 116 | POWER_DOMAIN_TRANSCODER_EDP, |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 117 | POWER_DOMAIN_PORT_DDI_A_2_LANES, |
| 118 | POWER_DOMAIN_PORT_DDI_A_4_LANES, |
| 119 | POWER_DOMAIN_PORT_DDI_B_2_LANES, |
| 120 | POWER_DOMAIN_PORT_DDI_B_4_LANES, |
| 121 | POWER_DOMAIN_PORT_DDI_C_2_LANES, |
| 122 | POWER_DOMAIN_PORT_DDI_C_4_LANES, |
| 123 | POWER_DOMAIN_PORT_DDI_D_2_LANES, |
| 124 | POWER_DOMAIN_PORT_DDI_D_4_LANES, |
| 125 | POWER_DOMAIN_PORT_DSI, |
| 126 | POWER_DOMAIN_PORT_CRT, |
| 127 | POWER_DOMAIN_PORT_OTHER, |
Ville Syrjälä | cdf8dd7 | 2013-09-16 17:38:30 +0300 | [diff] [blame] | 128 | POWER_DOMAIN_VGA, |
Imre Deak | fbeeaa2 | 2013-11-25 17:15:28 +0200 | [diff] [blame] | 129 | POWER_DOMAIN_AUDIO, |
Imre Deak | baa7070 | 2013-10-25 17:36:48 +0300 | [diff] [blame] | 130 | POWER_DOMAIN_INIT, |
Imre Deak | bddc764 | 2013-10-16 17:25:49 +0300 | [diff] [blame] | 131 | |
| 132 | POWER_DOMAIN_NUM, |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 133 | }; |
| 134 | |
| 135 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) |
| 136 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ |
| 137 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) |
Imre Deak | f52e353 | 2013-10-16 17:25:48 +0300 | [diff] [blame] | 138 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
| 139 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ |
| 140 | (tran) + POWER_DOMAIN_TRANSCODER_A) |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 141 | |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 142 | enum hpd_pin { |
| 143 | HPD_NONE = 0, |
| 144 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ |
| 145 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
| 146 | HPD_CRT, |
| 147 | HPD_SDVO_B, |
| 148 | HPD_SDVO_C, |
| 149 | HPD_PORT_B, |
| 150 | HPD_PORT_C, |
| 151 | HPD_PORT_D, |
| 152 | HPD_NUM_PINS |
| 153 | }; |
| 154 | |
Chris Wilson | 2a2d548 | 2012-12-03 11:49:06 +0000 | [diff] [blame] | 155 | #define I915_GEM_GPU_DOMAINS \ |
| 156 | (I915_GEM_DOMAIN_RENDER | \ |
| 157 | I915_GEM_DOMAIN_SAMPLER | \ |
| 158 | I915_GEM_DOMAIN_COMMAND | \ |
| 159 | I915_GEM_DOMAIN_INSTRUCTION | \ |
| 160 | I915_GEM_DOMAIN_VERTEX) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 161 | |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 162 | #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
Damien Lespiau | d615a16 | 2014-03-03 17:31:48 +0000 | [diff] [blame] | 163 | #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++) |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 164 | |
Daniel Vetter | 6c2b7c12 | 2012-07-05 09:50:24 +0200 | [diff] [blame] | 165 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
| 166 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ |
| 167 | if ((intel_encoder)->base.crtc == (__crtc)) |
| 168 | |
Jesse Barnes | 53f5e3c | 2014-02-07 12:48:15 -0800 | [diff] [blame] | 169 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
| 170 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ |
| 171 | if ((intel_connector)->base.encoder == (__encoder)) |
| 172 | |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 173 | struct drm_i915_private; |
| 174 | |
Daniel Vetter | e2b7826 | 2013-06-07 23:10:03 +0200 | [diff] [blame] | 175 | enum intel_dpll_id { |
| 176 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ |
| 177 | /* real shared dpll ids must be >= 0 */ |
| 178 | DPLL_ID_PCH_PLL_A, |
| 179 | DPLL_ID_PCH_PLL_B, |
| 180 | }; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 181 | #define I915_NUM_PLLS 2 |
| 182 | |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 183 | struct intel_dpll_hw_state { |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 184 | uint32_t dpll; |
Daniel Vetter | 8bcc279 | 2013-06-05 13:34:28 +0200 | [diff] [blame] | 185 | uint32_t dpll_md; |
Daniel Vetter | 66e985c | 2013-06-05 13:34:20 +0200 | [diff] [blame] | 186 | uint32_t fp0; |
| 187 | uint32_t fp1; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 188 | }; |
| 189 | |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 190 | struct intel_shared_dpll { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 191 | int refcount; /* count of number of CRTCs sharing this PLL */ |
| 192 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
| 193 | bool on; /* is the PLL actually active? Disabled during modeset */ |
Daniel Vetter | 46edb02 | 2013-06-05 13:34:12 +0200 | [diff] [blame] | 194 | const char *name; |
| 195 | /* should match the index in the dev_priv->shared_dplls array */ |
| 196 | enum intel_dpll_id id; |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 197 | struct intel_dpll_hw_state hw_state; |
Daniel Vetter | 15bdd4c | 2013-06-05 13:34:23 +0200 | [diff] [blame] | 198 | void (*mode_set)(struct drm_i915_private *dev_priv, |
| 199 | struct intel_shared_dpll *pll); |
Daniel Vetter | e7b903d | 2013-06-05 13:34:14 +0200 | [diff] [blame] | 200 | void (*enable)(struct drm_i915_private *dev_priv, |
| 201 | struct intel_shared_dpll *pll); |
| 202 | void (*disable)(struct drm_i915_private *dev_priv, |
| 203 | struct intel_shared_dpll *pll); |
Daniel Vetter | 5358901 | 2013-06-05 13:34:16 +0200 | [diff] [blame] | 204 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
| 205 | struct intel_shared_dpll *pll, |
| 206 | struct intel_dpll_hw_state *hw_state); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 207 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 208 | |
Daniel Vetter | e69d0bc | 2012-11-29 15:59:36 +0100 | [diff] [blame] | 209 | /* Used by dp and fdi links */ |
| 210 | struct intel_link_m_n { |
| 211 | uint32_t tu; |
| 212 | uint32_t gmch_m; |
| 213 | uint32_t gmch_n; |
| 214 | uint32_t link_m; |
| 215 | uint32_t link_n; |
| 216 | }; |
| 217 | |
| 218 | void intel_link_compute_m_n(int bpp, int nlanes, |
| 219 | int pixel_clock, int link_clock, |
| 220 | struct intel_link_m_n *m_n); |
| 221 | |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 222 | struct intel_ddi_plls { |
| 223 | int spll_refcount; |
| 224 | int wrpll1_refcount; |
| 225 | int wrpll2_refcount; |
| 226 | }; |
| 227 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 228 | /* Interface history: |
| 229 | * |
| 230 | * 1.1: Original. |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 231 | * 1.2: Add Power Management |
| 232 | * 1.3: Add vblank support |
Dave Airlie | de227f5 | 2006-01-25 15:31:43 +1100 | [diff] [blame] | 233 | * 1.4: Fix cmdbuffer path, add heap destroy |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 234 | * 1.5: Add vblank pipe configuration |
=?utf-8?q?Michel_D=C3=A4nzer?= | 2228ed6 | 2006-10-25 01:05:09 +1000 | [diff] [blame] | 235 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
| 236 | * - Support vertical blank on secondary display pipe |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 237 | */ |
| 238 | #define DRIVER_MAJOR 1 |
=?utf-8?q?Michel_D=C3=A4nzer?= | 2228ed6 | 2006-10-25 01:05:09 +1000 | [diff] [blame] | 239 | #define DRIVER_MINOR 6 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 240 | #define DRIVER_PATCHLEVEL 0 |
| 241 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 242 | #define WATCH_LISTS 0 |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 243 | #define WATCH_GTT 0 |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 244 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 245 | #define I915_GEM_PHYS_CURSOR_0 1 |
| 246 | #define I915_GEM_PHYS_CURSOR_1 2 |
| 247 | #define I915_GEM_PHYS_OVERLAY_REGS 3 |
| 248 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) |
| 249 | |
| 250 | struct drm_i915_gem_phys_object { |
| 251 | int id; |
| 252 | struct page **page_list; |
| 253 | drm_dma_handle_t *handle; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 254 | struct drm_i915_gem_object *cur_obj; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 255 | }; |
| 256 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 257 | struct opregion_header; |
| 258 | struct opregion_acpi; |
| 259 | struct opregion_swsci; |
| 260 | struct opregion_asle; |
| 261 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 262 | struct intel_opregion { |
Ben Widawsky | 5bc4418 | 2012-04-16 14:07:42 -0700 | [diff] [blame] | 263 | struct opregion_header __iomem *header; |
| 264 | struct opregion_acpi __iomem *acpi; |
| 265 | struct opregion_swsci __iomem *swsci; |
Jani Nikula | ebde53c | 2013-09-02 10:38:59 +0300 | [diff] [blame] | 266 | u32 swsci_gbda_sub_functions; |
| 267 | u32 swsci_sbcb_sub_functions; |
Ben Widawsky | 5bc4418 | 2012-04-16 14:07:42 -0700 | [diff] [blame] | 268 | struct opregion_asle __iomem *asle; |
| 269 | void __iomem *vbt; |
Chris Wilson | 01fe9db | 2011-01-16 19:37:30 +0000 | [diff] [blame] | 270 | u32 __iomem *lid_state; |
Jani Nikula | 91a60f2 | 2013-10-31 18:55:48 +0200 | [diff] [blame] | 271 | struct work_struct asle_work; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 272 | }; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 273 | #define OPREGION_SIZE (8*1024) |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 274 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 275 | struct intel_overlay; |
| 276 | struct intel_overlay_error_state; |
| 277 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 278 | struct drm_i915_master_private { |
| 279 | drm_local_map_t *sarea; |
| 280 | struct _drm_i915_sarea *sarea_priv; |
| 281 | }; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 282 | #define I915_FENCE_REG_NONE -1 |
Ville Syrjälä | 42b5aea | 2013-04-09 13:02:47 +0300 | [diff] [blame] | 283 | #define I915_MAX_NUM_FENCES 32 |
| 284 | /* 32 fences + sign bit for FENCE_REG_NONE */ |
| 285 | #define I915_MAX_NUM_FENCE_BITS 6 |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 286 | |
| 287 | struct drm_i915_fence_reg { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 288 | struct list_head lru_list; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 289 | struct drm_i915_gem_object *obj; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 290 | int pin_count; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 291 | }; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 292 | |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 293 | struct sdvo_device_mapping { |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 294 | u8 initialized; |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 295 | u8 dvo_port; |
| 296 | u8 slave_addr; |
| 297 | u8 dvo_wiring; |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 298 | u8 i2c_pin; |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 299 | u8 ddc_pin; |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 300 | }; |
| 301 | |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 302 | struct intel_display_error_state; |
| 303 | |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 304 | struct drm_i915_error_state { |
Daniel Vetter | 742cbee | 2012-04-27 15:17:39 +0200 | [diff] [blame] | 305 | struct kref ref; |
Ben Widawsky | 585b028 | 2014-01-30 00:19:37 -0800 | [diff] [blame] | 306 | struct timeval time; |
| 307 | |
Mika Kuoppala | cb38300 | 2014-02-25 17:11:25 +0200 | [diff] [blame] | 308 | char error_msg[128]; |
Mika Kuoppala | 48b031e | 2014-02-25 17:11:27 +0200 | [diff] [blame] | 309 | u32 reset_count; |
Mika Kuoppala | 62d5d69 | 2014-02-25 17:11:28 +0200 | [diff] [blame] | 310 | u32 suspend_count; |
Mika Kuoppala | cb38300 | 2014-02-25 17:11:25 +0200 | [diff] [blame] | 311 | |
Ben Widawsky | 585b028 | 2014-01-30 00:19:37 -0800 | [diff] [blame] | 312 | /* Generic register state */ |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 313 | u32 eir; |
| 314 | u32 pgtbl_er; |
Ben Widawsky | be998e2 | 2012-04-26 16:03:00 -0700 | [diff] [blame] | 315 | u32 ier; |
Ben Widawsky | b9a3906 | 2012-06-04 14:42:52 -0700 | [diff] [blame] | 316 | u32 ccid; |
Chris Wilson | 0f3b684 | 2013-01-15 12:05:55 +0000 | [diff] [blame] | 317 | u32 derrmr; |
| 318 | u32 forcewake; |
Ben Widawsky | 585b028 | 2014-01-30 00:19:37 -0800 | [diff] [blame] | 319 | u32 error; /* gen6+ */ |
| 320 | u32 err_int; /* gen7 */ |
| 321 | u32 done_reg; |
Ben Widawsky | 91ec5d1 | 2014-01-30 00:19:39 -0800 | [diff] [blame] | 322 | u32 gac_eco; |
| 323 | u32 gam_ecochk; |
| 324 | u32 gab_ctl; |
| 325 | u32 gfx_mode; |
Ben Widawsky | 585b028 | 2014-01-30 00:19:37 -0800 | [diff] [blame] | 326 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 327 | u32 pipestat[I915_MAX_PIPES]; |
Ben Widawsky | 585b028 | 2014-01-30 00:19:37 -0800 | [diff] [blame] | 328 | u64 fence[I915_MAX_NUM_FENCES]; |
| 329 | struct intel_overlay_error_state *overlay; |
| 330 | struct intel_display_error_state *display; |
| 331 | |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 332 | struct drm_i915_error_ring { |
Chris Wilson | 372fbb8 | 2014-01-27 13:52:34 +0000 | [diff] [blame] | 333 | bool valid; |
Ben Widawsky | 362b8af | 2014-01-30 00:19:38 -0800 | [diff] [blame] | 334 | /* Software tracked state */ |
| 335 | bool waiting; |
| 336 | int hangcheck_score; |
| 337 | enum intel_ring_hangcheck_action hangcheck_action; |
| 338 | int num_requests; |
| 339 | |
| 340 | /* our own tracking of ring head and tail */ |
| 341 | u32 cpu_ring_head; |
| 342 | u32 cpu_ring_tail; |
| 343 | |
| 344 | u32 semaphore_seqno[I915_NUM_RINGS - 1]; |
| 345 | |
| 346 | /* Register state */ |
| 347 | u32 tail; |
| 348 | u32 head; |
| 349 | u32 ctl; |
| 350 | u32 hws; |
| 351 | u32 ipeir; |
| 352 | u32 ipehr; |
| 353 | u32 instdone; |
| 354 | u32 acthd; |
| 355 | u32 bbstate; |
| 356 | u32 instpm; |
| 357 | u32 instps; |
| 358 | u32 seqno; |
| 359 | u64 bbaddr; |
| 360 | u32 fault_reg; |
| 361 | u32 faddr; |
| 362 | u32 rc_psmi; /* sleep state */ |
| 363 | u32 semaphore_mboxes[I915_NUM_RINGS - 1]; |
| 364 | |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 365 | struct drm_i915_error_object { |
| 366 | int page_count; |
| 367 | u32 gtt_offset; |
| 368 | u32 *pages[0]; |
Chris Wilson | ab0e7ff | 2014-02-25 17:11:24 +0200 | [diff] [blame] | 369 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
Ben Widawsky | 362b8af | 2014-01-30 00:19:38 -0800 | [diff] [blame] | 370 | |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 371 | struct drm_i915_error_request { |
| 372 | long jiffies; |
| 373 | u32 seqno; |
Chris Wilson | ee4f42b | 2012-02-15 11:25:38 +0000 | [diff] [blame] | 374 | u32 tail; |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 375 | } *requests; |
Ben Widawsky | 6c7a01e | 2014-01-30 00:19:40 -0800 | [diff] [blame] | 376 | |
| 377 | struct { |
| 378 | u32 gfx_mode; |
| 379 | union { |
| 380 | u64 pdp[4]; |
| 381 | u32 pp_dir_base; |
| 382 | }; |
| 383 | } vm_info; |
Chris Wilson | ab0e7ff | 2014-02-25 17:11:24 +0200 | [diff] [blame] | 384 | |
| 385 | pid_t pid; |
| 386 | char comm[TASK_COMM_LEN]; |
Chris Wilson | 52d39a2 | 2012-02-15 11:25:37 +0000 | [diff] [blame] | 387 | } ring[I915_NUM_RINGS]; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 388 | struct drm_i915_error_buffer { |
Chris Wilson | a779e5a | 2011-01-09 21:07:49 +0000 | [diff] [blame] | 389 | u32 size; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 390 | u32 name; |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 391 | u32 rseqno, wseqno; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 392 | u32 gtt_offset; |
| 393 | u32 read_domains; |
| 394 | u32 write_domain; |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 395 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
Chris Wilson | 9df3079 | 2010-02-18 10:24:56 +0000 | [diff] [blame] | 396 | s32 pinned:2; |
| 397 | u32 tiling:2; |
| 398 | u32 dirty:1; |
| 399 | u32 purgeable:1; |
Daniel Vetter | 5d1333f | 2012-02-16 11:03:29 +0100 | [diff] [blame] | 400 | s32 ring:4; |
Chris Wilson | f56383c | 2013-09-25 10:23:19 +0100 | [diff] [blame] | 401 | u32 cache_level:3; |
Ben Widawsky | 95f5301 | 2013-07-31 17:00:15 -0700 | [diff] [blame] | 402 | } **active_bo, **pinned_bo; |
Ben Widawsky | 6c7a01e | 2014-01-30 00:19:40 -0800 | [diff] [blame] | 403 | |
Ben Widawsky | 95f5301 | 2013-07-31 17:00:15 -0700 | [diff] [blame] | 404 | u32 *active_bo_count, *pinned_bo_count; |
Jesse Barnes | 63eeaf3 | 2009-06-18 16:56:52 -0700 | [diff] [blame] | 405 | }; |
| 406 | |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 407 | struct intel_connector; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 408 | struct intel_crtc_config; |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 409 | struct intel_plane_config; |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 410 | struct intel_crtc; |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 411 | struct intel_limit; |
| 412 | struct dpll; |
Daniel Vetter | b8cecdf | 2013-03-27 00:44:50 +0100 | [diff] [blame] | 413 | |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 414 | struct drm_i915_display_funcs { |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 415 | bool (*fbc_enabled)(struct drm_device *dev); |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 416 | void (*enable_fbc)(struct drm_crtc *crtc); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 417 | void (*disable_fbc)(struct drm_device *dev); |
| 418 | int (*get_display_clock_speed)(struct drm_device *dev); |
| 419 | int (*get_fifo_size)(struct drm_device *dev, int plane); |
Daniel Vetter | ee9300b | 2013-06-03 22:40:22 +0200 | [diff] [blame] | 420 | /** |
| 421 | * find_dpll() - Find the best values for the PLL |
| 422 | * @limit: limits for the PLL |
| 423 | * @crtc: current CRTC |
| 424 | * @target: target frequency in kHz |
| 425 | * @refclk: reference clock frequency in kHz |
| 426 | * @match_clock: if provided, @best_clock P divider must |
| 427 | * match the P divider from @match_clock |
| 428 | * used for LVDS downclocking |
| 429 | * @best_clock: best PLL values found |
| 430 | * |
| 431 | * Returns true on success, false on failure. |
| 432 | */ |
| 433 | bool (*find_dpll)(const struct intel_limit *limit, |
| 434 | struct drm_crtc *crtc, |
| 435 | int target, int refclk, |
| 436 | struct dpll *match_clock, |
| 437 | struct dpll *best_clock); |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 438 | void (*update_wm)(struct drm_crtc *crtc); |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 439 | void (*update_sprite_wm)(struct drm_plane *plane, |
| 440 | struct drm_crtc *crtc, |
Paulo Zanoni | 4c4ff43 | 2013-05-24 11:59:17 -0300 | [diff] [blame] | 441 | uint32_t sprite_width, int pixel_size, |
Ville Syrjälä | bdd57d0 | 2013-07-05 11:57:13 +0300 | [diff] [blame] | 442 | bool enable, bool scaled); |
Daniel Vetter | 47fab73 | 2012-10-26 10:58:18 +0200 | [diff] [blame] | 443 | void (*modeset_global_resources)(struct drm_device *dev); |
Daniel Vetter | 0e8ffe1 | 2013-03-28 10:42:00 +0100 | [diff] [blame] | 444 | /* Returns the active state of the crtc, and if the crtc is active, |
| 445 | * fills out the pipe-config with the hw state. */ |
| 446 | bool (*get_pipe_config)(struct intel_crtc *, |
| 447 | struct intel_crtc_config *); |
Jesse Barnes | 46f297f | 2014-03-07 08:57:48 -0800 | [diff] [blame] | 448 | void (*get_plane_config)(struct intel_crtc *, |
| 449 | struct intel_plane_config *); |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 450 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
Eric Anholt | f564048e | 2011-03-30 13:01:02 -0700 | [diff] [blame] | 451 | int x, int y, |
| 452 | struct drm_framebuffer *old_fb); |
Daniel Vetter | 76e5a89 | 2012-06-29 22:39:33 +0200 | [diff] [blame] | 453 | void (*crtc_enable)(struct drm_crtc *crtc); |
| 454 | void (*crtc_disable)(struct drm_crtc *crtc); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 455 | void (*off)(struct drm_crtc *crtc); |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 456 | void (*write_eld)(struct drm_connector *connector, |
Jani Nikula | 3442705 | 2013-10-16 12:34:47 +0300 | [diff] [blame] | 457 | struct drm_crtc *crtc, |
| 458 | struct drm_display_mode *mode); |
Jesse Barnes | 674cf96 | 2011-04-28 14:27:04 -0700 | [diff] [blame] | 459 | void (*fdi_link_train)(struct drm_crtc *crtc); |
Jesse Barnes | 6067aae | 2011-04-28 15:04:31 -0700 | [diff] [blame] | 460 | void (*init_clock_gating)(struct drm_device *dev); |
Jesse Barnes | 8c9f3aa | 2011-06-16 09:19:13 -0700 | [diff] [blame] | 461 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
| 462 | struct drm_framebuffer *fb, |
Keith Packard | ed8d197 | 2013-07-22 18:49:58 -0700 | [diff] [blame] | 463 | struct drm_i915_gem_object *obj, |
| 464 | uint32_t flags); |
Matt Roper | 262ca2b | 2014-03-18 17:22:55 -0700 | [diff] [blame] | 465 | int (*update_primary_plane)(struct drm_crtc *crtc, |
| 466 | struct drm_framebuffer *fb, |
| 467 | int x, int y); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 468 | void (*hpd_irq_setup)(struct drm_device *dev); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 469 | /* clock updates for mode set */ |
| 470 | /* cursor updates */ |
| 471 | /* render clock increase/decrease */ |
| 472 | /* display clock increase/decrease */ |
| 473 | /* pll clock increase/decrease */ |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 474 | |
| 475 | int (*setup_backlight)(struct intel_connector *connector); |
Jani Nikula | 7bd688c | 2013-11-08 16:48:56 +0200 | [diff] [blame] | 476 | uint32_t (*get_backlight)(struct intel_connector *connector); |
| 477 | void (*set_backlight)(struct intel_connector *connector, |
| 478 | uint32_t level); |
| 479 | void (*disable_backlight)(struct intel_connector *connector); |
| 480 | void (*enable_backlight)(struct intel_connector *connector); |
Jesse Barnes | e70236a | 2009-09-21 10:42:27 -0700 | [diff] [blame] | 481 | }; |
| 482 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 483 | struct intel_uncore_funcs { |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 484 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
| 485 | int fw_engine); |
| 486 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
| 487 | int fw_engine); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 488 | |
| 489 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
| 490 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
| 491 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
| 492 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); |
| 493 | |
| 494 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, |
| 495 | uint8_t val, bool trace); |
| 496 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, |
| 497 | uint16_t val, bool trace); |
| 498 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, |
| 499 | uint32_t val, bool trace); |
| 500 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, |
| 501 | uint64_t val, bool trace); |
Chris Wilson | 990bbda | 2012-07-02 11:51:02 -0300 | [diff] [blame] | 502 | }; |
| 503 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 504 | struct intel_uncore { |
| 505 | spinlock_t lock; /** lock is also taken in irq contexts. */ |
| 506 | |
| 507 | struct intel_uncore_funcs funcs; |
| 508 | |
| 509 | unsigned fifo_count; |
| 510 | unsigned forcewake_count; |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 511 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 512 | unsigned fw_rendercount; |
| 513 | unsigned fw_mediacount; |
| 514 | |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 515 | struct timer_list force_wake_timer; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 516 | }; |
| 517 | |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 518 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
| 519 | func(is_mobile) sep \ |
| 520 | func(is_i85x) sep \ |
| 521 | func(is_i915g) sep \ |
| 522 | func(is_i945gm) sep \ |
| 523 | func(is_g33) sep \ |
| 524 | func(need_gfx_hws) sep \ |
| 525 | func(is_g4x) sep \ |
| 526 | func(is_pineview) sep \ |
| 527 | func(is_broadwater) sep \ |
| 528 | func(is_crestline) sep \ |
| 529 | func(is_ivybridge) sep \ |
| 530 | func(is_valleyview) sep \ |
| 531 | func(is_haswell) sep \ |
Ben Widawsky | b833d68 | 2013-08-23 16:00:07 -0700 | [diff] [blame] | 532 | func(is_preliminary) sep \ |
Damien Lespiau | 79fc46d | 2013-04-23 16:37:17 +0100 | [diff] [blame] | 533 | func(has_fbc) sep \ |
| 534 | func(has_pipe_cxsr) sep \ |
| 535 | func(has_hotplug) sep \ |
| 536 | func(cursor_needs_physical) sep \ |
| 537 | func(has_overlay) sep \ |
| 538 | func(overlay_needs_physical) sep \ |
| 539 | func(supports_tv) sep \ |
Damien Lespiau | dd93be5 | 2013-04-22 18:40:39 +0100 | [diff] [blame] | 540 | func(has_llc) sep \ |
Damien Lespiau | 30568c4 | 2013-04-22 18:40:41 +0100 | [diff] [blame] | 541 | func(has_ddi) sep \ |
| 542 | func(has_fpga_dbg) |
Daniel Vetter | c96ea64 | 2012-08-08 22:01:51 +0200 | [diff] [blame] | 543 | |
Damien Lespiau | a587f77 | 2013-04-22 18:40:38 +0100 | [diff] [blame] | 544 | #define DEFINE_FLAG(name) u8 name:1 |
| 545 | #define SEP_SEMICOLON ; |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 546 | |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 547 | struct intel_device_info { |
Ville Syrjälä | 10fce67 | 2013-01-24 15:29:28 +0200 | [diff] [blame] | 548 | u32 display_mmio_offset; |
Ben Widawsky | 7eb552a | 2013-03-13 14:05:41 -0700 | [diff] [blame] | 549 | u8 num_pipes:3; |
Damien Lespiau | d615a16 | 2014-03-03 17:31:48 +0000 | [diff] [blame] | 550 | u8 num_sprites[I915_MAX_PIPES]; |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 551 | u8 gen; |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 552 | u8 ring_mask; /* Rings supported by the HW */ |
Damien Lespiau | a587f77 | 2013-04-22 18:40:38 +0100 | [diff] [blame] | 553 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
Antti Koskipaa | a57c774 | 2014-02-04 14:22:24 +0200 | [diff] [blame] | 554 | /* Register offsets for the various display pipes and transcoders */ |
| 555 | int pipe_offsets[I915_MAX_TRANSCODERS]; |
| 556 | int trans_offsets[I915_MAX_TRANSCODERS]; |
| 557 | int dpll_offsets[I915_MAX_PIPES]; |
| 558 | int dpll_md_offsets[I915_MAX_PIPES]; |
| 559 | int palette_offsets[I915_MAX_PIPES]; |
Kristian Høgsberg | cfdf1fa | 2009-12-16 15:16:16 -0500 | [diff] [blame] | 560 | }; |
| 561 | |
Damien Lespiau | a587f77 | 2013-04-22 18:40:38 +0100 | [diff] [blame] | 562 | #undef DEFINE_FLAG |
| 563 | #undef SEP_SEMICOLON |
| 564 | |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 565 | enum i915_cache_level { |
| 566 | I915_CACHE_NONE = 0, |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 567 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
| 568 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc |
| 569 | caches, eg sampler/render caches, and the |
| 570 | large Last-Level-Cache. LLC is coherent with |
| 571 | the CPU, but L3 is only visible to the GPU. */ |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 572 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 573 | }; |
| 574 | |
Kenneth Graunke | 2d04bef | 2013-04-22 00:53:49 -0700 | [diff] [blame] | 575 | typedef uint32_t gen6_gtt_pte_t; |
| 576 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 577 | /** |
| 578 | * A VMA represents a GEM BO that is bound into an address space. Therefore, a |
| 579 | * VMA's presence cannot be guaranteed before binding, or after unbinding the |
| 580 | * object into/from the address space. |
| 581 | * |
| 582 | * To make things as simple as possible (ie. no refcounting), a VMA's lifetime |
| 583 | * will always be <= an objects lifetime. So object refcounting should cover us. |
| 584 | */ |
| 585 | struct i915_vma { |
| 586 | struct drm_mm_node node; |
| 587 | struct drm_i915_gem_object *obj; |
| 588 | struct i915_address_space *vm; |
| 589 | |
| 590 | /** This object's place on the active/inactive lists */ |
| 591 | struct list_head mm_list; |
| 592 | |
| 593 | struct list_head vma_link; /* Link in the object's VMA list */ |
| 594 | |
| 595 | /** This vma's place in the batchbuffer or on the eviction list */ |
| 596 | struct list_head exec_list; |
| 597 | |
| 598 | /** |
| 599 | * Used for performing relocations during execbuffer insertion. |
| 600 | */ |
| 601 | struct hlist_node exec_node; |
| 602 | unsigned long exec_handle; |
| 603 | struct drm_i915_gem_exec_object2 *exec_entry; |
| 604 | |
| 605 | /** |
| 606 | * How many users have pinned this object in GTT space. The following |
| 607 | * users can each hold at most one reference: pwrite/pread, pin_ioctl |
| 608 | * (via user_pin_count), execbuffer (objects are not allowed multiple |
| 609 | * times for the same batchbuffer), and the framebuffer code. When |
| 610 | * switching/pageflipping, the framebuffer code has at most two buffers |
| 611 | * pinned per crtc. |
| 612 | * |
| 613 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 |
| 614 | * bits with absolutely no headroom. So use 4 bits. */ |
| 615 | unsigned int pin_count:4; |
| 616 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
| 617 | |
| 618 | /** Unmap an object from an address space. This usually consists of |
| 619 | * setting the valid PTE entries to a reserved scratch page. */ |
| 620 | void (*unbind_vma)(struct i915_vma *vma); |
| 621 | /* Map an object into an address space with the given cache flags. */ |
| 622 | #define GLOBAL_BIND (1<<0) |
| 623 | void (*bind_vma)(struct i915_vma *vma, |
| 624 | enum i915_cache_level cache_level, |
| 625 | u32 flags); |
| 626 | }; |
| 627 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 628 | struct i915_address_space { |
Ben Widawsky | 93bd864 | 2013-07-16 16:50:06 -0700 | [diff] [blame] | 629 | struct drm_mm mm; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 630 | struct drm_device *dev; |
Ben Widawsky | a7bbbd6 | 2013-07-16 16:50:07 -0700 | [diff] [blame] | 631 | struct list_head global_link; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 632 | unsigned long start; /* Start offset always 0 for dri2 */ |
| 633 | size_t total; /* size addr space maps (ex. 2GB for ggtt) */ |
| 634 | |
| 635 | struct { |
| 636 | dma_addr_t addr; |
| 637 | struct page *page; |
| 638 | } scratch; |
| 639 | |
Ben Widawsky | 5cef07e | 2013-07-16 16:50:08 -0700 | [diff] [blame] | 640 | /** |
| 641 | * List of objects currently involved in rendering. |
| 642 | * |
| 643 | * Includes buffers having the contents of their GPU caches |
| 644 | * flushed, not necessarily primitives. last_rendering_seqno |
| 645 | * represents when the rendering involved will be completed. |
| 646 | * |
| 647 | * A reference is held on the buffer while on this list. |
| 648 | */ |
| 649 | struct list_head active_list; |
| 650 | |
| 651 | /** |
| 652 | * LRU list of objects which are not in the ringbuffer and |
| 653 | * are ready to unbind, but are still in the GTT. |
| 654 | * |
| 655 | * last_rendering_seqno is 0 while an object is in this list. |
| 656 | * |
| 657 | * A reference is not held on the buffer while on this list, |
| 658 | * as merely being GTT-bound shouldn't prevent its being |
| 659 | * freed, and we'll pull it off the list in the free path. |
| 660 | */ |
| 661 | struct list_head inactive_list; |
| 662 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 663 | /* FIXME: Need a more generic return type */ |
| 664 | gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, |
Ben Widawsky | b35b380 | 2013-10-16 09:18:21 -0700 | [diff] [blame] | 665 | enum i915_cache_level level, |
| 666 | bool valid); /* Create a valid PTE */ |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 667 | void (*clear_range)(struct i915_address_space *vm, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 668 | uint64_t start, |
| 669 | uint64_t length, |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 670 | bool use_scratch); |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 671 | void (*insert_entries)(struct i915_address_space *vm, |
| 672 | struct sg_table *st, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 673 | uint64_t start, |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 674 | enum i915_cache_level cache_level); |
| 675 | void (*cleanup)(struct i915_address_space *vm); |
| 676 | }; |
| 677 | |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 678 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
| 679 | * Graphics Virtual Address into a Physical Address. In addition to the normal |
| 680 | * collateral associated with any va->pa translations GEN hardware also has a |
| 681 | * portion of the GTT which can be mapped by the CPU and remain both coherent |
| 682 | * and correct (in cases like swizzling). That region is referred to as GMADR in |
| 683 | * the spec. |
| 684 | */ |
| 685 | struct i915_gtt { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 686 | struct i915_address_space base; |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 687 | size_t stolen_size; /* Total size of stolen memory */ |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 688 | |
| 689 | unsigned long mappable_end; /* End offset that we can CPU map */ |
| 690 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ |
| 691 | phys_addr_t mappable_base; /* PA of our GMADR */ |
| 692 | |
| 693 | /** "Graphics Stolen Memory" holds the global PTEs */ |
| 694 | void __iomem *gsm; |
Ben Widawsky | a81cc00 | 2013-01-18 12:30:31 -0800 | [diff] [blame] | 695 | |
| 696 | bool do_idle_maps; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 697 | |
Ben Widawsky | 911bdf0 | 2013-06-27 16:30:23 -0700 | [diff] [blame] | 698 | int mtrr; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 699 | |
| 700 | /* global gtt ops */ |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 701 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 702 | size_t *stolen, phys_addr_t *mappable_base, |
| 703 | unsigned long *mappable_end); |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 704 | }; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 705 | #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 706 | |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 707 | #define GEN8_LEGACY_PDPS 4 |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 708 | struct i915_hw_ppgtt { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 709 | struct i915_address_space base; |
Ben Widawsky | c7c48df | 2013-12-06 14:11:15 -0800 | [diff] [blame] | 710 | struct kref ref; |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 711 | struct drm_mm_node node; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 712 | unsigned num_pd_entries; |
Ben Widawsky | 5abbcca | 2014-02-21 13:06:34 -0800 | [diff] [blame] | 713 | unsigned num_pd_pages; /* gen8+ */ |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 714 | union { |
| 715 | struct page **pt_pages; |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 716 | struct page **gen8_pt_pages[GEN8_LEGACY_PDPS]; |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 717 | }; |
| 718 | struct page *pd_pages; |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 719 | union { |
| 720 | uint32_t pd_offset; |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 721 | dma_addr_t pd_dma_addr[GEN8_LEGACY_PDPS]; |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 722 | }; |
| 723 | union { |
| 724 | dma_addr_t *pt_dma_addr; |
| 725 | dma_addr_t *gen8_pt_dma_addr[4]; |
| 726 | }; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 727 | |
Ben Widawsky | a3d67d2 | 2013-12-06 14:11:06 -0800 | [diff] [blame] | 728 | int (*enable)(struct i915_hw_ppgtt *ppgtt); |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 729 | int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, |
| 730 | struct intel_ring_buffer *ring, |
| 731 | bool synchronous); |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 732 | void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 733 | }; |
| 734 | |
Mika Kuoppala | e59ec13 | 2013-06-12 12:35:28 +0300 | [diff] [blame] | 735 | struct i915_ctx_hang_stats { |
| 736 | /* This context had batch pending when hang was declared */ |
| 737 | unsigned batch_pending; |
| 738 | |
| 739 | /* This context had batch active when hang was declared */ |
| 740 | unsigned batch_active; |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 741 | |
| 742 | /* Time when this context was last blamed for a GPU reset */ |
| 743 | unsigned long guilty_ts; |
| 744 | |
| 745 | /* This context is banned to submit more work */ |
| 746 | bool banned; |
Mika Kuoppala | e59ec13 | 2013-06-12 12:35:28 +0300 | [diff] [blame] | 747 | }; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 748 | |
| 749 | /* This must match up with the value previously used for execbuf2.rsvd1. */ |
| 750 | #define DEFAULT_CONTEXT_ID 0 |
| 751 | struct i915_hw_context { |
Mika Kuoppala | dce3271 | 2013-04-30 13:30:33 +0300 | [diff] [blame] | 752 | struct kref ref; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 753 | int id; |
Ben Widawsky | e055684 | 2012-06-04 14:42:46 -0700 | [diff] [blame] | 754 | bool is_initialized; |
Ben Widawsky | 3ccfd19 | 2013-09-18 19:03:18 -0700 | [diff] [blame] | 755 | uint8_t remap_slice; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 756 | struct drm_i915_file_private *file_priv; |
Ben Widawsky | 0009e46 | 2013-12-06 14:11:02 -0800 | [diff] [blame] | 757 | struct intel_ring_buffer *last_ring; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 758 | struct drm_i915_gem_object *obj; |
Mika Kuoppala | e59ec13 | 2013-06-12 12:35:28 +0300 | [diff] [blame] | 759 | struct i915_ctx_hang_stats hang_stats; |
Ben Widawsky | c7c48df | 2013-12-06 14:11:15 -0800 | [diff] [blame] | 760 | struct i915_address_space *vm; |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 761 | |
| 762 | struct list_head link; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 763 | }; |
| 764 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 765 | struct i915_fbc { |
| 766 | unsigned long size; |
| 767 | unsigned int fb_id; |
| 768 | enum plane plane; |
| 769 | int y; |
| 770 | |
| 771 | struct drm_mm_node *compressed_fb; |
| 772 | struct drm_mm_node *compressed_llb; |
| 773 | |
| 774 | struct intel_fbc_work { |
| 775 | struct delayed_work work; |
| 776 | struct drm_crtc *crtc; |
| 777 | struct drm_framebuffer *fb; |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 778 | } *fbc_work; |
| 779 | |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 780 | enum no_fbc_reason { |
| 781 | FBC_OK, /* FBC is enabled */ |
| 782 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 783 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
| 784 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ |
| 785 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ |
| 786 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ |
| 787 | FBC_BAD_PLANE, /* fbc not supported on plane */ |
| 788 | FBC_NOT_TILED, /* buffer not tiled */ |
| 789 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
| 790 | FBC_MODULE_PARAM, |
| 791 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ |
| 792 | } no_fbc_reason; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 793 | }; |
| 794 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 795 | struct i915_psr { |
| 796 | bool sink_support; |
| 797 | bool source_ok; |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 798 | }; |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 799 | |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 800 | enum intel_pch { |
Paulo Zanoni | f035083 | 2012-07-03 18:48:16 -0300 | [diff] [blame] | 801 | PCH_NONE = 0, /* No PCH present */ |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 802 | PCH_IBX, /* Ibexpeak PCH */ |
| 803 | PCH_CPT, /* Cougarpoint PCH */ |
Eugeni Dodonov | eb877eb | 2012-03-29 12:32:20 -0300 | [diff] [blame] | 804 | PCH_LPT, /* Lynxpoint PCH */ |
Ben Widawsky | 40c7ead | 2013-04-05 13:12:40 -0700 | [diff] [blame] | 805 | PCH_NOP, |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 806 | }; |
| 807 | |
Paulo Zanoni | 988d6ee | 2012-12-01 12:04:24 -0200 | [diff] [blame] | 808 | enum intel_sbi_destination { |
| 809 | SBI_ICLK, |
| 810 | SBI_MPHY, |
| 811 | }; |
| 812 | |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 813 | #define QUIRK_PIPEA_FORCE (1<<0) |
Keith Packard | 435793d | 2011-07-12 14:56:22 -0700 | [diff] [blame] | 814 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
Carsten Emde | 4dca20e | 2012-03-15 15:56:26 +0100 | [diff] [blame] | 815 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
Jesse Barnes | b690e96 | 2010-07-19 13:53:12 -0700 | [diff] [blame] | 816 | |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 817 | struct intel_fbdev; |
Chris Wilson | 1630fe7 | 2011-07-08 12:22:42 +0100 | [diff] [blame] | 818 | struct intel_fbc_work; |
Dave Airlie | 3865167 | 2010-03-30 05:34:13 +0000 | [diff] [blame] | 819 | |
Daniel Vetter | c2b9152 | 2012-02-14 22:37:19 +0100 | [diff] [blame] | 820 | struct intel_gmbus { |
| 821 | struct i2c_adapter adapter; |
Chris Wilson | f2ce9fa | 2012-11-10 15:58:21 +0000 | [diff] [blame] | 822 | u32 force_bit; |
Daniel Vetter | c2b9152 | 2012-02-14 22:37:19 +0100 | [diff] [blame] | 823 | u32 reg0; |
Daniel Vetter | 36c785f | 2012-02-14 22:37:22 +0100 | [diff] [blame] | 824 | u32 gpio_reg; |
Daniel Vetter | c167a6f | 2012-02-28 00:43:09 +0100 | [diff] [blame] | 825 | struct i2c_algo_bit_data bit_algo; |
Daniel Vetter | c2b9152 | 2012-02-14 22:37:19 +0100 | [diff] [blame] | 826 | struct drm_i915_private *dev_priv; |
| 827 | }; |
| 828 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 829 | struct i915_suspend_saved_registers { |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 830 | u8 saveLBB; |
| 831 | u32 saveDSPACNTR; |
| 832 | u32 saveDSPBCNTR; |
Keith Packard | e948e99 | 2008-05-07 12:27:53 +1000 | [diff] [blame] | 833 | u32 saveDSPARB; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 834 | u32 savePIPEACONF; |
| 835 | u32 savePIPEBCONF; |
| 836 | u32 savePIPEASRC; |
| 837 | u32 savePIPEBSRC; |
| 838 | u32 saveFPA0; |
| 839 | u32 saveFPA1; |
| 840 | u32 saveDPLL_A; |
| 841 | u32 saveDPLL_A_MD; |
| 842 | u32 saveHTOTAL_A; |
| 843 | u32 saveHBLANK_A; |
| 844 | u32 saveHSYNC_A; |
| 845 | u32 saveVTOTAL_A; |
| 846 | u32 saveVBLANK_A; |
| 847 | u32 saveVSYNC_A; |
| 848 | u32 saveBCLRPAT_A; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 849 | u32 saveTRANSACONF; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 850 | u32 saveTRANS_HTOTAL_A; |
| 851 | u32 saveTRANS_HBLANK_A; |
| 852 | u32 saveTRANS_HSYNC_A; |
| 853 | u32 saveTRANS_VTOTAL_A; |
| 854 | u32 saveTRANS_VBLANK_A; |
| 855 | u32 saveTRANS_VSYNC_A; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 856 | u32 savePIPEASTAT; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 857 | u32 saveDSPASTRIDE; |
| 858 | u32 saveDSPASIZE; |
| 859 | u32 saveDSPAPOS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 860 | u32 saveDSPAADDR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 861 | u32 saveDSPASURF; |
| 862 | u32 saveDSPATILEOFF; |
| 863 | u32 savePFIT_PGM_RATIOS; |
Jesse Barnes | 0eb96d6 | 2009-10-14 12:33:41 -0700 | [diff] [blame] | 864 | u32 saveBLC_HIST_CTL; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 865 | u32 saveBLC_PWM_CTL; |
| 866 | u32 saveBLC_PWM_CTL2; |
Jesse Barnes | 07bf139 | 2013-10-31 18:55:50 +0200 | [diff] [blame] | 867 | u32 saveBLC_HIST_CTL_B; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 868 | u32 saveBLC_CPU_PWM_CTL; |
| 869 | u32 saveBLC_CPU_PWM_CTL2; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 870 | u32 saveFPB0; |
| 871 | u32 saveFPB1; |
| 872 | u32 saveDPLL_B; |
| 873 | u32 saveDPLL_B_MD; |
| 874 | u32 saveHTOTAL_B; |
| 875 | u32 saveHBLANK_B; |
| 876 | u32 saveHSYNC_B; |
| 877 | u32 saveVTOTAL_B; |
| 878 | u32 saveVBLANK_B; |
| 879 | u32 saveVSYNC_B; |
| 880 | u32 saveBCLRPAT_B; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 881 | u32 saveTRANSBCONF; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 882 | u32 saveTRANS_HTOTAL_B; |
| 883 | u32 saveTRANS_HBLANK_B; |
| 884 | u32 saveTRANS_HSYNC_B; |
| 885 | u32 saveTRANS_VTOTAL_B; |
| 886 | u32 saveTRANS_VBLANK_B; |
| 887 | u32 saveTRANS_VSYNC_B; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 888 | u32 savePIPEBSTAT; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 889 | u32 saveDSPBSTRIDE; |
| 890 | u32 saveDSPBSIZE; |
| 891 | u32 saveDSPBPOS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 892 | u32 saveDSPBADDR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 893 | u32 saveDSPBSURF; |
| 894 | u32 saveDSPBTILEOFF; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 895 | u32 saveVGA0; |
| 896 | u32 saveVGA1; |
| 897 | u32 saveVGA_PD; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 898 | u32 saveVGACNTRL; |
| 899 | u32 saveADPA; |
| 900 | u32 saveLVDS; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 901 | u32 savePP_ON_DELAYS; |
| 902 | u32 savePP_OFF_DELAYS; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 903 | u32 saveDVOA; |
| 904 | u32 saveDVOB; |
| 905 | u32 saveDVOC; |
| 906 | u32 savePP_ON; |
| 907 | u32 savePP_OFF; |
| 908 | u32 savePP_CONTROL; |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 909 | u32 savePP_DIVISOR; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 910 | u32 savePFIT_CONTROL; |
| 911 | u32 save_palette_a[256]; |
| 912 | u32 save_palette_b[256]; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 913 | u32 saveFBC_CONTROL; |
Jesse Barnes | 0da3ea1 | 2008-02-20 09:39:58 +1000 | [diff] [blame] | 914 | u32 saveIER; |
| 915 | u32 saveIIR; |
| 916 | u32 saveIMR; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 917 | u32 saveDEIER; |
| 918 | u32 saveDEIMR; |
| 919 | u32 saveGTIER; |
| 920 | u32 saveGTIMR; |
| 921 | u32 saveFDI_RXA_IMR; |
| 922 | u32 saveFDI_RXB_IMR; |
Keith Packard | 1f84e55 | 2008-02-16 19:19:29 -0800 | [diff] [blame] | 923 | u32 saveCACHE_MODE_0; |
Keith Packard | 1f84e55 | 2008-02-16 19:19:29 -0800 | [diff] [blame] | 924 | u32 saveMI_ARB_STATE; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 925 | u32 saveSWF0[16]; |
| 926 | u32 saveSWF1[16]; |
| 927 | u32 saveSWF2[3]; |
| 928 | u8 saveMSR; |
| 929 | u8 saveSR[8]; |
Jesse Barnes | 123f794 | 2008-02-07 11:15:20 -0800 | [diff] [blame] | 930 | u8 saveGR[25]; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 931 | u8 saveAR_INDEX; |
Jesse Barnes | a59e122 | 2008-05-07 12:25:46 +1000 | [diff] [blame] | 932 | u8 saveAR[21]; |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 933 | u8 saveDACMASK; |
Jesse Barnes | a59e122 | 2008-05-07 12:25:46 +1000 | [diff] [blame] | 934 | u8 saveCR[37]; |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 935 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
Eric Anholt | 1fd1c62 | 2009-06-03 07:26:58 +0000 | [diff] [blame] | 936 | u32 saveCURACNTR; |
| 937 | u32 saveCURAPOS; |
| 938 | u32 saveCURABASE; |
| 939 | u32 saveCURBCNTR; |
| 940 | u32 saveCURBPOS; |
| 941 | u32 saveCURBBASE; |
| 942 | u32 saveCURSIZE; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 943 | u32 saveDP_B; |
| 944 | u32 saveDP_C; |
| 945 | u32 saveDP_D; |
| 946 | u32 savePIPEA_GMCH_DATA_M; |
| 947 | u32 savePIPEB_GMCH_DATA_M; |
| 948 | u32 savePIPEA_GMCH_DATA_N; |
| 949 | u32 savePIPEB_GMCH_DATA_N; |
| 950 | u32 savePIPEA_DP_LINK_M; |
| 951 | u32 savePIPEB_DP_LINK_M; |
| 952 | u32 savePIPEA_DP_LINK_N; |
| 953 | u32 savePIPEB_DP_LINK_N; |
Zhenyu Wang | 4204878 | 2009-10-21 15:27:01 +0800 | [diff] [blame] | 954 | u32 saveFDI_RXA_CTL; |
| 955 | u32 saveFDI_TXA_CTL; |
| 956 | u32 saveFDI_RXB_CTL; |
| 957 | u32 saveFDI_TXB_CTL; |
| 958 | u32 savePFA_CTL_1; |
| 959 | u32 savePFB_CTL_1; |
| 960 | u32 savePFA_WIN_SZ; |
| 961 | u32 savePFB_WIN_SZ; |
| 962 | u32 savePFA_WIN_POS; |
| 963 | u32 savePFB_WIN_POS; |
Zhenyu Wang | 5586c8b | 2009-11-06 02:13:02 +0000 | [diff] [blame] | 964 | u32 savePCH_DREF_CONTROL; |
| 965 | u32 saveDISP_ARB_CTL; |
| 966 | u32 savePIPEA_DATA_M1; |
| 967 | u32 savePIPEA_DATA_N1; |
| 968 | u32 savePIPEA_LINK_M1; |
| 969 | u32 savePIPEA_LINK_N1; |
| 970 | u32 savePIPEB_DATA_M1; |
| 971 | u32 savePIPEB_DATA_N1; |
| 972 | u32 savePIPEB_LINK_M1; |
| 973 | u32 savePIPEB_LINK_N1; |
Matthew Garrett | b5b72e8 | 2010-02-02 18:30:47 +0000 | [diff] [blame] | 974 | u32 saveMCHBAR_RENDER_STANDBY; |
Adam Jackson | cda2bb7 | 2011-07-26 16:53:06 -0400 | [diff] [blame] | 975 | u32 savePCH_PORT_HOTPLUG; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 976 | }; |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 977 | |
| 978 | struct intel_gen6_power_mgmt { |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 979 | /* work and pm_iir are protected by dev_priv->irq_lock */ |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 980 | struct work_struct work; |
| 981 | u32 pm_iir; |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 982 | |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 983 | u8 cur_delay; |
| 984 | u8 min_delay; |
| 985 | u8 max_delay; |
Jesse Barnes | 52ceb90 | 2013-04-23 10:09:26 -0700 | [diff] [blame] | 986 | u8 rpe_delay; |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 987 | u8 rp1_delay; |
| 988 | u8 rp0_delay; |
Ben Widawsky | 31c7738 | 2013-04-05 14:29:22 -0700 | [diff] [blame] | 989 | u8 hw_max; |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 990 | |
Deepak S | 2754436 | 2014-01-27 21:35:05 +0530 | [diff] [blame] | 991 | bool rp_up_masked; |
| 992 | bool rp_down_masked; |
| 993 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 994 | int last_adj; |
| 995 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; |
| 996 | |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 997 | bool enabled; |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 998 | struct delayed_work delayed_resume_work; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 999 | |
| 1000 | /* |
| 1001 | * Protects RPS/RC6 register access and PCU communication. |
| 1002 | * Must be taken after struct_mutex if nested. |
| 1003 | */ |
| 1004 | struct mutex hw_lock; |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 1005 | }; |
| 1006 | |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 1007 | /* defined intel_pm.c */ |
| 1008 | extern spinlock_t mchdev_lock; |
| 1009 | |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 1010 | struct intel_ilk_power_mgmt { |
| 1011 | u8 cur_delay; |
| 1012 | u8 min_delay; |
| 1013 | u8 max_delay; |
| 1014 | u8 fmax; |
| 1015 | u8 fstart; |
| 1016 | |
| 1017 | u64 last_count1; |
| 1018 | unsigned long last_time1; |
| 1019 | unsigned long chipset_power; |
| 1020 | u64 last_count2; |
| 1021 | struct timespec last_time2; |
| 1022 | unsigned long gfx_power; |
| 1023 | u8 corr; |
| 1024 | |
| 1025 | int c_m; |
| 1026 | int r_t; |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 1027 | |
| 1028 | struct drm_i915_gem_object *pwrctx; |
| 1029 | struct drm_i915_gem_object *renderctx; |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 1030 | }; |
| 1031 | |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 1032 | struct drm_i915_private; |
| 1033 | struct i915_power_well; |
| 1034 | |
| 1035 | struct i915_power_well_ops { |
| 1036 | /* |
| 1037 | * Synchronize the well's hw state to match the current sw state, for |
| 1038 | * example enable/disable it based on the current refcount. Called |
| 1039 | * during driver init and resume time, possibly after first calling |
| 1040 | * the enable/disable handlers. |
| 1041 | */ |
| 1042 | void (*sync_hw)(struct drm_i915_private *dev_priv, |
| 1043 | struct i915_power_well *power_well); |
| 1044 | /* |
| 1045 | * Enable the well and resources that depend on it (for example |
| 1046 | * interrupts located on the well). Called after the 0->1 refcount |
| 1047 | * transition. |
| 1048 | */ |
| 1049 | void (*enable)(struct drm_i915_private *dev_priv, |
| 1050 | struct i915_power_well *power_well); |
| 1051 | /* |
| 1052 | * Disable the well and resources that depend on it. Called after |
| 1053 | * the 1->0 refcount transition. |
| 1054 | */ |
| 1055 | void (*disable)(struct drm_i915_private *dev_priv, |
| 1056 | struct i915_power_well *power_well); |
| 1057 | /* Returns the hw enabled state. */ |
| 1058 | bool (*is_enabled)(struct drm_i915_private *dev_priv, |
| 1059 | struct i915_power_well *power_well); |
| 1060 | }; |
| 1061 | |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 1062 | /* Power well structure for haswell */ |
| 1063 | struct i915_power_well { |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 1064 | const char *name; |
Imre Deak | 6f3ef5d | 2013-11-25 17:15:30 +0200 | [diff] [blame] | 1065 | bool always_on; |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 1066 | /* power well enable/disable usage count */ |
| 1067 | int count; |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 1068 | unsigned long domains; |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 1069 | unsigned long data; |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 1070 | const struct i915_power_well_ops *ops; |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 1071 | }; |
| 1072 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 1073 | struct i915_power_domains { |
Imre Deak | baa7070 | 2013-10-25 17:36:48 +0300 | [diff] [blame] | 1074 | /* |
| 1075 | * Power wells needed for initialization at driver init and suspend |
| 1076 | * time are on. They are kept on until after the first modeset. |
| 1077 | */ |
| 1078 | bool init_power_on; |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 1079 | int power_well_count; |
Imre Deak | baa7070 | 2013-10-25 17:36:48 +0300 | [diff] [blame] | 1080 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 1081 | struct mutex lock; |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 1082 | int domain_use_count[POWER_DOMAIN_NUM]; |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 1083 | struct i915_power_well *power_wells; |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 1084 | }; |
| 1085 | |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 1086 | struct i915_dri1_state { |
| 1087 | unsigned allow_batchbuffer : 1; |
| 1088 | u32 __iomem *gfx_hws_cpu_addr; |
| 1089 | |
| 1090 | unsigned int cpp; |
| 1091 | int back_offset; |
| 1092 | int front_offset; |
| 1093 | int current_page; |
| 1094 | int page_flipping; |
| 1095 | |
| 1096 | uint32_t counter; |
| 1097 | }; |
| 1098 | |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 1099 | struct i915_ums_state { |
| 1100 | /** |
| 1101 | * Flag if the X Server, and thus DRM, is not currently in |
| 1102 | * control of the device. |
| 1103 | * |
| 1104 | * This is set between LeaveVT and EnterVT. It needs to be |
| 1105 | * replaced with a semaphore. It also needs to be |
| 1106 | * transitioned away from for kernel modesetting. |
| 1107 | */ |
| 1108 | int mm_suspended; |
| 1109 | }; |
| 1110 | |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1111 | #define MAX_L3_SLICES 2 |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1112 | struct intel_l3_parity { |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1113 | u32 *remap_info[MAX_L3_SLICES]; |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1114 | struct work_struct error_work; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 1115 | int which_slice; |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1116 | }; |
| 1117 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1118 | struct i915_gem_mm { |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1119 | /** Memory allocator for GTT stolen memory */ |
| 1120 | struct drm_mm stolen; |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1121 | /** List of all objects in gtt_space. Used to restore gtt |
| 1122 | * mappings on resume */ |
| 1123 | struct list_head bound_list; |
| 1124 | /** |
| 1125 | * List of objects which are not bound to the GTT (thus |
| 1126 | * are idle and not used by the GPU) but still have |
| 1127 | * (presumably uncached) pages still attached. |
| 1128 | */ |
| 1129 | struct list_head unbound_list; |
| 1130 | |
| 1131 | /** Usable portion of the GTT for GEM */ |
| 1132 | unsigned long stolen_base; /* limited to low memory (32-bit) */ |
| 1133 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1134 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
| 1135 | struct i915_hw_ppgtt *aliasing_ppgtt; |
| 1136 | |
| 1137 | struct shrinker inactive_shrinker; |
| 1138 | bool shrinker_no_lock_stealing; |
| 1139 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1140 | /** LRU list of objects with fence regs on them. */ |
| 1141 | struct list_head fence_list; |
| 1142 | |
| 1143 | /** |
| 1144 | * We leave the user IRQ off as much as possible, |
| 1145 | * but this means that requests will finish and never |
| 1146 | * be retired once the system goes idle. Set a timer to |
| 1147 | * fire periodically while the ring is running. When it |
| 1148 | * fires, go retire requests. |
| 1149 | */ |
| 1150 | struct delayed_work retire_work; |
| 1151 | |
| 1152 | /** |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1153 | * When we detect an idle GPU, we want to turn on |
| 1154 | * powersaving features. So once we see that there |
| 1155 | * are no more requests outstanding and no more |
| 1156 | * arrive within a small period of time, we fire |
| 1157 | * off the idle_work. |
| 1158 | */ |
| 1159 | struct delayed_work idle_work; |
| 1160 | |
| 1161 | /** |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1162 | * Are we in a non-interruptible section of code like |
| 1163 | * modesetting? |
| 1164 | */ |
| 1165 | bool interruptible; |
| 1166 | |
Chris Wilson | f62a007 | 2014-02-21 17:55:39 +0000 | [diff] [blame] | 1167 | /** |
| 1168 | * Is the GPU currently considered idle, or busy executing userspace |
| 1169 | * requests? Whilst idle, we attempt to power down the hardware and |
| 1170 | * display clocks. In order to reduce the effect on performance, there |
| 1171 | * is a slight delay before we do so. |
| 1172 | */ |
| 1173 | bool busy; |
| 1174 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1175 | /** Bit 6 swizzling required for X tiling */ |
| 1176 | uint32_t bit_6_swizzle_x; |
| 1177 | /** Bit 6 swizzling required for Y tiling */ |
| 1178 | uint32_t bit_6_swizzle_y; |
| 1179 | |
| 1180 | /* storage for physical objects */ |
| 1181 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; |
| 1182 | |
| 1183 | /* accounting, useful for userland debugging */ |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 1184 | spinlock_t object_stat_lock; |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1185 | size_t object_memory; |
| 1186 | u32 object_count; |
| 1187 | }; |
| 1188 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1189 | struct drm_i915_error_state_buf { |
| 1190 | unsigned bytes; |
| 1191 | unsigned size; |
| 1192 | int err; |
| 1193 | u8 *buf; |
| 1194 | loff_t start; |
| 1195 | loff_t pos; |
| 1196 | }; |
| 1197 | |
Mika Kuoppala | fc16b48 | 2013-06-06 15:18:39 +0300 | [diff] [blame] | 1198 | struct i915_error_state_file_priv { |
| 1199 | struct drm_device *dev; |
| 1200 | struct drm_i915_error_state *error; |
| 1201 | }; |
| 1202 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1203 | struct i915_gpu_error { |
| 1204 | /* For hangcheck timer */ |
| 1205 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
| 1206 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 1207 | /* Hang gpu twice in this window and your context gets banned */ |
| 1208 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) |
| 1209 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1210 | struct timer_list hangcheck_timer; |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1211 | |
| 1212 | /* For reset and error_state handling. */ |
| 1213 | spinlock_t lock; |
| 1214 | /* Protected by the above dev->gpu_error.lock. */ |
| 1215 | struct drm_i915_error_state *first_error; |
| 1216 | struct work_struct work; |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1217 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1218 | |
| 1219 | unsigned long missed_irq_rings; |
| 1220 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1221 | /** |
Mika Kuoppala | 2ac0f45 | 2013-11-12 14:44:19 +0200 | [diff] [blame] | 1222 | * State variable controlling the reset flow and count |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1223 | * |
Mika Kuoppala | 2ac0f45 | 2013-11-12 14:44:19 +0200 | [diff] [blame] | 1224 | * This is a counter which gets incremented when reset is triggered, |
| 1225 | * and again when reset has been handled. So odd values (lowest bit set) |
| 1226 | * means that reset is in progress and even values that |
| 1227 | * (reset_counter >> 1):th reset was successfully completed. |
| 1228 | * |
| 1229 | * If reset is not completed succesfully, the I915_WEDGE bit is |
| 1230 | * set meaning that hardware is terminally sour and there is no |
| 1231 | * recovery. All waiters on the reset_queue will be woken when |
| 1232 | * that happens. |
| 1233 | * |
| 1234 | * This counter is used by the wait_seqno code to notice that reset |
| 1235 | * event happened and it needs to restart the entire ioctl (since most |
| 1236 | * likely the seqno it waited for won't ever signal anytime soon). |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1237 | * |
| 1238 | * This is important for lock-free wait paths, where no contended lock |
| 1239 | * naturally enforces the correct ordering between the bail-out of the |
| 1240 | * waiter and the gpu reset work code. |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1241 | */ |
| 1242 | atomic_t reset_counter; |
| 1243 | |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1244 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
Mika Kuoppala | 2ac0f45 | 2013-11-12 14:44:19 +0200 | [diff] [blame] | 1245 | #define I915_WEDGED (1 << 31) |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 1246 | |
| 1247 | /** |
| 1248 | * Waitqueue to signal when the reset has completed. Used by clients |
| 1249 | * that wait for dev_priv->mm.wedged to settle. |
| 1250 | */ |
| 1251 | wait_queue_head_t reset_queue; |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 1252 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1253 | /* For gpu hang simulation. */ |
| 1254 | unsigned int stop_rings; |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1255 | |
| 1256 | /* For missed irq/seqno simulation. */ |
| 1257 | unsigned int test_irq_rings; |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1258 | }; |
| 1259 | |
Zhang Rui | b8efb17 | 2013-02-05 15:41:53 +0800 | [diff] [blame] | 1260 | enum modeset_restore { |
| 1261 | MODESET_ON_LID_OPEN, |
| 1262 | MODESET_DONE, |
| 1263 | MODESET_SUSPENDED, |
| 1264 | }; |
| 1265 | |
Paulo Zanoni | 6acab15 | 2013-09-12 17:06:24 -0300 | [diff] [blame] | 1266 | struct ddi_vbt_port_info { |
| 1267 | uint8_t hdmi_level_shift; |
Paulo Zanoni | 311a209 | 2013-09-12 17:12:18 -0300 | [diff] [blame] | 1268 | |
| 1269 | uint8_t supports_dvi:1; |
| 1270 | uint8_t supports_hdmi:1; |
| 1271 | uint8_t supports_dp:1; |
Paulo Zanoni | 6acab15 | 2013-09-12 17:06:24 -0300 | [diff] [blame] | 1272 | }; |
| 1273 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1274 | struct intel_vbt_data { |
| 1275 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
| 1276 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
| 1277 | |
| 1278 | /* Feature bits */ |
| 1279 | unsigned int int_tv_support:1; |
| 1280 | unsigned int lvds_dither:1; |
| 1281 | unsigned int lvds_vbt:1; |
| 1282 | unsigned int int_crt_support:1; |
| 1283 | unsigned int lvds_use_ssc:1; |
| 1284 | unsigned int display_clock_mode:1; |
| 1285 | unsigned int fdi_rx_polarity_inverted:1; |
| 1286 | int lvds_ssc_freq; |
| 1287 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ |
| 1288 | |
| 1289 | /* eDP */ |
| 1290 | int edp_rate; |
| 1291 | int edp_lanes; |
| 1292 | int edp_preemphasis; |
| 1293 | int edp_vswing; |
| 1294 | bool edp_initialized; |
| 1295 | bool edp_support; |
| 1296 | int edp_bpp; |
| 1297 | struct edp_power_seq edp_pps; |
| 1298 | |
Jani Nikula | f00076d | 2013-12-14 20:38:29 -0200 | [diff] [blame] | 1299 | struct { |
| 1300 | u16 pwm_freq_hz; |
| 1301 | bool active_low_pwm; |
| 1302 | } backlight; |
| 1303 | |
Shobhit Kumar | d17c544 | 2013-08-27 15:12:25 +0300 | [diff] [blame] | 1304 | /* MIPI DSI */ |
| 1305 | struct { |
| 1306 | u16 panel_id; |
| 1307 | } dsi; |
| 1308 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1309 | int crt_ddc_pin; |
| 1310 | |
| 1311 | int child_dev_num; |
Paulo Zanoni | 768f69c | 2013-09-11 18:02:47 -0300 | [diff] [blame] | 1312 | union child_device_config *child_dev; |
Paulo Zanoni | 6acab15 | 2013-09-12 17:06:24 -0300 | [diff] [blame] | 1313 | |
| 1314 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1315 | }; |
| 1316 | |
Ville Syrjälä | 77c122b | 2013-08-06 22:24:04 +0300 | [diff] [blame] | 1317 | enum intel_ddb_partitioning { |
| 1318 | INTEL_DDB_PART_1_2, |
| 1319 | INTEL_DDB_PART_5_6, /* IVB+ */ |
| 1320 | }; |
| 1321 | |
Ville Syrjälä | 1fd527c | 2013-08-06 22:24:05 +0300 | [diff] [blame] | 1322 | struct intel_wm_level { |
| 1323 | bool enable; |
| 1324 | uint32_t pri_val; |
| 1325 | uint32_t spr_val; |
| 1326 | uint32_t cur_val; |
| 1327 | uint32_t fbc_val; |
| 1328 | }; |
| 1329 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1330 | struct ilk_wm_values { |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 1331 | uint32_t wm_pipe[3]; |
| 1332 | uint32_t wm_lp[3]; |
| 1333 | uint32_t wm_lp_spr[3]; |
| 1334 | uint32_t wm_linetime[3]; |
| 1335 | bool enable_fbc_wm; |
| 1336 | enum intel_ddb_partitioning partitioning; |
| 1337 | }; |
| 1338 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1339 | /* |
| 1340 | * This struct tracks the state needed for the Package C8+ feature. |
| 1341 | * |
Paulo Zanoni | a8a8bd5 | 2014-03-07 20:08:05 -0300 | [diff] [blame] | 1342 | * TODO: we're merging the Package C8+ feature with the runtime PM support. To |
| 1343 | * avoid having to update the documentation at each patch of the series, we'll |
| 1344 | * do a final update at the end. |
| 1345 | * |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1346 | * Package states C8 and deeper are really deep PC states that can only be |
| 1347 | * reached when all the devices on the system allow it, so even if the graphics |
| 1348 | * device allows PC8+, it doesn't mean the system will actually get to these |
| 1349 | * states. |
| 1350 | * |
| 1351 | * Our driver only allows PC8+ when all the outputs are disabled, the power well |
| 1352 | * is disabled and the GPU is idle. When these conditions are met, we manually |
| 1353 | * do the other conditions: disable the interrupts, clocks and switch LCPLL |
| 1354 | * refclk to Fclk. |
| 1355 | * |
| 1356 | * When we really reach PC8 or deeper states (not just when we allow it) we lose |
| 1357 | * the state of some registers, so when we come back from PC8+ we need to |
| 1358 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't |
| 1359 | * need to take care of the registers kept by RC6. |
| 1360 | * |
| 1361 | * The interrupt disabling is part of the requirements. We can only leave the |
| 1362 | * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we |
| 1363 | * can lock the machine. |
| 1364 | * |
| 1365 | * Ideally every piece of our code that needs PC8+ disabled would call |
| 1366 | * hsw_disable_package_c8, which would increment disable_count and prevent the |
| 1367 | * system from reaching PC8+. But we don't have a symmetric way to do this for |
Paulo Zanoni | 86c4ec0 | 2014-02-21 13:52:24 -0300 | [diff] [blame] | 1368 | * everything, so we have the requirements_met variable. When we switch |
| 1369 | * requirements_met to true we decrease disable_count, and increase it in the |
| 1370 | * opposite case. The requirements_met variable is true when all the CRTCs, |
| 1371 | * encoders and the power well are disabled. |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1372 | * |
| 1373 | * In addition to everything, we only actually enable PC8+ if disable_count |
| 1374 | * stays at zero for at least some seconds. This is implemented with the |
| 1375 | * enable_work variable. We do this so we don't enable/disable PC8 dozens of |
| 1376 | * consecutive times when all screens are disabled and some background app |
| 1377 | * queries the state of our connectors, or we have some application constantly |
| 1378 | * waking up to use the GPU. Only after the enable_work function actually |
| 1379 | * enables PC8+ the "enable" variable will become true, which means that it can |
| 1380 | * be false even if disable_count is 0. |
| 1381 | * |
| 1382 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and |
| 1383 | * goes back to false exactly before we reenable the IRQs. We use this variable |
| 1384 | * to check if someone is trying to enable/disable IRQs while they're supposed |
| 1385 | * to be disabled. This shouldn't happen and we'll print some error messages in |
| 1386 | * case it happens, but if it actually happens we'll also update the variables |
| 1387 | * inside struct regsave so when we restore the IRQs they will contain the |
| 1388 | * latest expected values. |
| 1389 | * |
| 1390 | * For more, read "Display Sequences for Package C8" on our documentation. |
| 1391 | */ |
| 1392 | struct i915_package_c8 { |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1393 | bool irqs_disabled; |
| 1394 | /* Only true after the delayed work task actually enables it. */ |
| 1395 | bool enabled; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1396 | struct mutex lock; |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1397 | |
| 1398 | struct { |
| 1399 | uint32_t deimr; |
| 1400 | uint32_t sdeimr; |
| 1401 | uint32_t gtimr; |
| 1402 | uint32_t gtier; |
| 1403 | uint32_t gen6_pmimr; |
| 1404 | } regsave; |
| 1405 | }; |
| 1406 | |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1407 | struct i915_runtime_pm { |
| 1408 | bool suspended; |
| 1409 | }; |
| 1410 | |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 1411 | enum intel_pipe_crc_source { |
| 1412 | INTEL_PIPE_CRC_SOURCE_NONE, |
| 1413 | INTEL_PIPE_CRC_SOURCE_PLANE1, |
| 1414 | INTEL_PIPE_CRC_SOURCE_PLANE2, |
| 1415 | INTEL_PIPE_CRC_SOURCE_PF, |
Daniel Vetter | 5b3a856 | 2013-10-16 22:55:48 +0200 | [diff] [blame] | 1416 | INTEL_PIPE_CRC_SOURCE_PIPE, |
Daniel Vetter | 3d099a0 | 2013-10-16 22:55:58 +0200 | [diff] [blame] | 1417 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
| 1418 | INTEL_PIPE_CRC_SOURCE_TV, |
| 1419 | INTEL_PIPE_CRC_SOURCE_DP_B, |
| 1420 | INTEL_PIPE_CRC_SOURCE_DP_C, |
| 1421 | INTEL_PIPE_CRC_SOURCE_DP_D, |
Daniel Vetter | 46a1918 | 2013-11-01 10:50:20 +0100 | [diff] [blame] | 1422 | INTEL_PIPE_CRC_SOURCE_AUTO, |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 1423 | INTEL_PIPE_CRC_SOURCE_MAX, |
| 1424 | }; |
| 1425 | |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1426 | struct intel_pipe_crc_entry { |
Damien Lespiau | ac2300d | 2013-10-15 18:55:30 +0100 | [diff] [blame] | 1427 | uint32_t frame; |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1428 | uint32_t crc[5]; |
| 1429 | }; |
| 1430 | |
Damien Lespiau | b2c88f5 | 2013-10-15 18:55:29 +0100 | [diff] [blame] | 1431 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1432 | struct intel_pipe_crc { |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1433 | spinlock_t lock; |
| 1434 | bool opened; /* exclusive access to the result file */ |
Damien Lespiau | e5f75ac | 2013-10-15 18:55:34 +0100 | [diff] [blame] | 1435 | struct intel_pipe_crc_entry *entries; |
Daniel Vetter | 926321d | 2013-10-16 13:30:34 +0200 | [diff] [blame] | 1436 | enum intel_pipe_crc_source source; |
Damien Lespiau | d538bbd | 2013-10-21 14:29:30 +0100 | [diff] [blame] | 1437 | int head, tail; |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 1438 | wait_queue_head_t wq; |
Shuang He | 8bf1e9f | 2013-10-15 18:55:27 +0100 | [diff] [blame] | 1439 | }; |
| 1440 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1441 | typedef struct drm_i915_private { |
| 1442 | struct drm_device *dev; |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 1443 | struct kmem_cache *slab; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1444 | |
Damien Lespiau | 5c969aa | 2014-02-07 19:12:48 +0000 | [diff] [blame] | 1445 | const struct intel_device_info info; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1446 | |
| 1447 | int relative_constants_mode; |
| 1448 | |
| 1449 | void __iomem *regs; |
| 1450 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1451 | struct intel_uncore uncore; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1452 | |
| 1453 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; |
| 1454 | |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1455 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1456 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
| 1457 | * controller on different i2c buses. */ |
| 1458 | struct mutex gmbus_mutex; |
| 1459 | |
| 1460 | /** |
| 1461 | * Base address of the gmbus and gpio block. |
| 1462 | */ |
| 1463 | uint32_t gpio_mmio_base; |
| 1464 | |
Daniel Vetter | 28c70f1 | 2012-12-01 13:53:45 +0100 | [diff] [blame] | 1465 | wait_queue_head_t gmbus_wait_queue; |
| 1466 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1467 | struct pci_dev *bridge_dev; |
| 1468 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 1469 | uint32_t last_seqno, next_seqno; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1470 | |
| 1471 | drm_dma_handle_t *status_page_dmah; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1472 | struct resource mch_res; |
| 1473 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1474 | /* protects the irq masks */ |
| 1475 | spinlock_t irq_lock; |
| 1476 | |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 1477 | bool display_irqs_enabled; |
| 1478 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 1479 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
| 1480 | struct pm_qos_request pm_qos; |
| 1481 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1482 | /* DPIO indirect register protection */ |
Daniel Vetter | 0915300 | 2012-12-12 14:06:44 +0100 | [diff] [blame] | 1483 | struct mutex dpio_lock; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1484 | |
| 1485 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
Ben Widawsky | abd58f0 | 2013-11-02 21:07:09 -0700 | [diff] [blame] | 1486 | union { |
| 1487 | u32 irq_mask; |
| 1488 | u32 de_irq_mask[I915_MAX_PIPES]; |
| 1489 | }; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1490 | u32 gt_irq_mask; |
Paulo Zanoni | 605cd25 | 2013-08-06 18:57:15 -0300 | [diff] [blame] | 1491 | u32 pm_irq_mask; |
Imre Deak | 91d181d | 2014-02-10 18:42:49 +0200 | [diff] [blame] | 1492 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1493 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1494 | struct work_struct hotplug_work; |
Daniel Vetter | 52d7ece | 2012-12-01 21:03:22 +0100 | [diff] [blame] | 1495 | bool enable_hotplug_processing; |
Egbert Eich | b543fb0 | 2013-04-16 13:36:54 +0200 | [diff] [blame] | 1496 | struct { |
| 1497 | unsigned long hpd_last_jiffies; |
| 1498 | int hpd_cnt; |
| 1499 | enum { |
| 1500 | HPD_ENABLED = 0, |
| 1501 | HPD_DISABLED = 1, |
| 1502 | HPD_MARK_DISABLED = 2 |
| 1503 | } hpd_mark; |
| 1504 | } hpd_stats[HPD_NUM_PINS]; |
Egbert Eich | 142e239 | 2013-04-11 15:57:57 +0200 | [diff] [blame] | 1505 | u32 hpd_event_bits; |
Egbert Eich | ac4c16c | 2013-04-16 13:36:58 +0200 | [diff] [blame] | 1506 | struct timer_list hotplug_reenable_timer; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1507 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 1508 | struct i915_fbc fbc; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1509 | struct intel_opregion opregion; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 1510 | struct intel_vbt_data vbt; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1511 | |
| 1512 | /* overlay */ |
| 1513 | struct intel_overlay *overlay; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1514 | |
Jani Nikula | 58c6877 | 2013-11-08 16:48:54 +0200 | [diff] [blame] | 1515 | /* backlight registers and fields in struct intel_panel */ |
| 1516 | spinlock_t backlight_lock; |
Jani Nikula | 31ad8ec | 2013-04-02 15:48:09 +0300 | [diff] [blame] | 1517 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1518 | /* LVDS info */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1519 | bool no_aux_handshake; |
| 1520 | |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1521 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
| 1522 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ |
| 1523 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
| 1524 | |
| 1525 | unsigned int fsb_freq, mem_freq, is_ddr3; |
| 1526 | |
Daniel Vetter | 645416f | 2013-09-02 16:22:25 +0200 | [diff] [blame] | 1527 | /** |
| 1528 | * wq - Driver workqueue for GEM. |
| 1529 | * |
| 1530 | * NOTE: Work items scheduled here are not allowed to grab any modeset |
| 1531 | * locks, for otherwise the flushing done in the pageflip code will |
| 1532 | * result in deadlocks. |
| 1533 | */ |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1534 | struct workqueue_struct *wq; |
| 1535 | |
| 1536 | /* Display functions */ |
| 1537 | struct drm_i915_display_funcs display; |
| 1538 | |
| 1539 | /* PCH chipset type */ |
| 1540 | enum intel_pch pch_type; |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 1541 | unsigned short pch_id; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1542 | |
| 1543 | unsigned long quirks; |
| 1544 | |
Zhang Rui | b8efb17 | 2013-02-05 15:41:53 +0800 | [diff] [blame] | 1545 | enum modeset_restore modeset_restore; |
| 1546 | struct mutex modeset_restore_lock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1547 | |
Ben Widawsky | a7bbbd6 | 2013-07-16 16:50:07 -0700 | [diff] [blame] | 1548 | struct list_head vm_list; /* Global list of all address spaces */ |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1549 | struct i915_gtt gtt; /* VMA representing the global address space */ |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1550 | |
Daniel Vetter | 4b5aed6 | 2012-11-14 17:14:03 +0100 | [diff] [blame] | 1551 | struct i915_gem_mm mm; |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 1552 | |
Daniel Vetter | 8781342 | 2012-05-02 11:49:32 +0200 | [diff] [blame] | 1553 | /* Kernel Modesetting */ |
| 1554 | |
yakui_zhao | 9b9d172 | 2009-05-31 17:17:17 +0800 | [diff] [blame] | 1555 | struct sdvo_device_mapping sdvo_mappings[2]; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1556 | |
Damien Lespiau | 76c4ac0 | 2014-02-07 19:12:52 +0000 | [diff] [blame] | 1557 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
| 1558 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 1559 | wait_queue_head_t pending_flip_queue; |
| 1560 | |
Daniel Vetter | c459787 | 2013-10-21 21:04:07 +0200 | [diff] [blame] | 1561 | #ifdef CONFIG_DEBUG_FS |
| 1562 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; |
| 1563 | #endif |
| 1564 | |
Daniel Vetter | e72f9fb | 2013-06-05 13:34:06 +0200 | [diff] [blame] | 1565 | int num_shared_dpll; |
| 1566 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; |
Paulo Zanoni | 6441ab5 | 2012-10-05 12:05:58 -0300 | [diff] [blame] | 1567 | struct intel_ddi_plls ddi_plls; |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1568 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 1569 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1570 | /* Reclocking support */ |
| 1571 | bool render_reclock_avail; |
| 1572 | bool lvds_downclock_avail; |
Zhao Yakui | 18f9ed1 | 2009-11-20 03:24:16 +0000 | [diff] [blame] | 1573 | /* indicates the reduced downclock for LVDS*/ |
| 1574 | int lvds_downclock; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1575 | u16 orig_clock; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1576 | |
Zhenyu Wang | c4804411 | 2009-12-17 14:48:43 +0800 | [diff] [blame] | 1577 | bool mchbar_need_disable; |
Jesse Barnes | f97108d | 2010-01-29 11:27:07 -0800 | [diff] [blame] | 1578 | |
Daniel Vetter | a4da4fa | 2012-11-02 19:55:07 +0100 | [diff] [blame] | 1579 | struct intel_l3_parity l3_parity; |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1580 | |
Ben Widawsky | 5912450 | 2013-07-04 11:02:05 -0700 | [diff] [blame] | 1581 | /* Cannot be determined by PCIID. You must always read a register. */ |
| 1582 | size_t ellc_size; |
| 1583 | |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1584 | /* gen6+ rps state */ |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 1585 | struct intel_gen6_power_mgmt rps; |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 1586 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 1587 | /* ilk-only ips/rps state. Everything in here is protected by the global |
| 1588 | * mchdev_lock in intel_pm.c */ |
Daniel Vetter | c85aa88 | 2012-11-02 19:55:03 +0100 | [diff] [blame] | 1589 | struct intel_ilk_power_mgmt ips; |
Jesse Barnes | b5e50c3 | 2010-02-05 12:42:41 -0800 | [diff] [blame] | 1590 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 1591 | struct i915_power_domains power_domains; |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 1592 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1593 | struct i915_psr psr; |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1594 | |
Daniel Vetter | 99584db | 2012-11-14 17:14:04 +0100 | [diff] [blame] | 1595 | struct i915_gpu_error gpu_error; |
Chris Wilson | ae681d9 | 2010-10-01 14:57:56 +0100 | [diff] [blame] | 1596 | |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 1597 | struct drm_i915_gem_object *vlv_pctx; |
| 1598 | |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1599 | #ifdef CONFIG_DRM_I915_FBDEV |
Dave Airlie | 8be48d9 | 2010-03-30 05:34:14 +0000 | [diff] [blame] | 1600 | /* list of fbdev register on this device */ |
| 1601 | struct intel_fbdev *fbdev; |
Daniel Vetter | 4520f53 | 2013-10-09 09:18:51 +0200 | [diff] [blame] | 1602 | #endif |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 1603 | |
Jesse Barnes | 073f34d | 2012-11-02 11:13:59 -0700 | [diff] [blame] | 1604 | /* |
| 1605 | * The console may be contended at resume, but we don't |
| 1606 | * want it to block on it. |
| 1607 | */ |
| 1608 | struct work_struct console_resume_work; |
| 1609 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 1610 | struct drm_property *broadcast_rgb_property; |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 1611 | struct drm_property *force_audio_property; |
Ben Widawsky | e368919 | 2012-05-25 16:56:22 -0700 | [diff] [blame] | 1612 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 1613 | uint32_t hw_context_size; |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 1614 | struct list_head context_list; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1615 | |
Damien Lespiau | 3e68320 | 2012-12-11 18:48:29 +0000 | [diff] [blame] | 1616 | u32 fdi_rx_config; |
Paulo Zanoni | 68d18ad | 2012-12-01 12:04:26 -0200 | [diff] [blame] | 1617 | |
Daniel Vetter | 842f1c8 | 2014-03-10 10:01:44 +0100 | [diff] [blame] | 1618 | u32 suspend_count; |
Daniel Vetter | f4c956a | 2012-11-02 19:55:02 +0100 | [diff] [blame] | 1619 | struct i915_suspend_saved_registers regfile; |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 1620 | |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 1621 | struct { |
| 1622 | /* |
| 1623 | * Raw watermark latency values: |
| 1624 | * in 0.1us units for WM0, |
| 1625 | * in 0.5us units for WM1+. |
| 1626 | */ |
| 1627 | /* primary */ |
| 1628 | uint16_t pri_latency[5]; |
| 1629 | /* sprite */ |
| 1630 | uint16_t spr_latency[5]; |
| 1631 | /* cursor */ |
| 1632 | uint16_t cur_latency[5]; |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 1633 | |
| 1634 | /* current hardware state */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1635 | struct ilk_wm_values hw; |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 1636 | } wm; |
| 1637 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1638 | struct i915_package_c8 pc8; |
| 1639 | |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 1640 | struct i915_runtime_pm pm; |
| 1641 | |
Daniel Vetter | 231f42a | 2012-11-02 19:55:05 +0100 | [diff] [blame] | 1642 | /* Old dri1 support infrastructure, beware the dragons ya fools entering |
| 1643 | * here! */ |
| 1644 | struct i915_dri1_state dri1; |
Daniel Vetter | db1b76c | 2013-07-09 16:51:37 +0200 | [diff] [blame] | 1645 | /* Old ums support infrastructure, same warning applies. */ |
| 1646 | struct i915_ums_state ums; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1647 | } drm_i915_private_t; |
| 1648 | |
Chris Wilson | 2c1792a | 2013-08-01 18:39:55 +0100 | [diff] [blame] | 1649 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
| 1650 | { |
| 1651 | return dev->dev_private; |
| 1652 | } |
| 1653 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 1654 | /* Iterate over initialised rings */ |
| 1655 | #define for_each_ring(ring__, dev_priv__, i__) \ |
| 1656 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ |
| 1657 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) |
| 1658 | |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 1659 | enum hdmi_force_audio { |
| 1660 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ |
| 1661 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ |
| 1662 | HDMI_AUDIO_AUTO, /* trust EDID */ |
| 1663 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ |
| 1664 | }; |
| 1665 | |
Daniel Vetter | 190d6cd | 2013-07-04 13:06:28 +0200 | [diff] [blame] | 1666 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 1667 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1668 | struct drm_i915_gem_object_ops { |
| 1669 | /* Interface between the GEM object and its backing storage. |
| 1670 | * get_pages() is called once prior to the use of the associated set |
| 1671 | * of pages before to binding them into the GTT, and put_pages() is |
| 1672 | * called after we no longer need them. As we expect there to be |
| 1673 | * associated cost with migrating pages between the backing storage |
| 1674 | * and making them available for the GPU (e.g. clflush), we may hold |
| 1675 | * onto the pages after they are no longer referenced by the GPU |
| 1676 | * in case they may be used again shortly (for example migrating the |
| 1677 | * pages to a different memory domain within the GTT). put_pages() |
| 1678 | * will therefore most likely be called when the object itself is |
| 1679 | * being released or under memory pressure (where we attempt to |
| 1680 | * reap pages for the shrinker). |
| 1681 | */ |
| 1682 | int (*get_pages)(struct drm_i915_gem_object *); |
| 1683 | void (*put_pages)(struct drm_i915_gem_object *); |
| 1684 | }; |
| 1685 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1686 | struct drm_i915_gem_object { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 1687 | struct drm_gem_object base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1688 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 1689 | const struct drm_i915_gem_object_ops *ops; |
| 1690 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 1691 | /** List of VMAs backed by this object */ |
| 1692 | struct list_head vma_list; |
| 1693 | |
Chris Wilson | c1ad11f | 2012-11-15 11:32:21 +0000 | [diff] [blame] | 1694 | /** Stolen memory for this object, instead of being backed by shmem. */ |
| 1695 | struct drm_mm_node *stolen; |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 1696 | struct list_head global_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1697 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1698 | struct list_head ring_list; |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 1699 | /** Used in execbuf to temporarily hold a ref */ |
| 1700 | struct list_head obj_exec_link; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1701 | |
| 1702 | /** |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 1703 | * This is set if the object is on the active lists (has pending |
| 1704 | * rendering and so a non-zero seqno), and is not set if it i s on |
| 1705 | * inactive (ready to be unbound) list. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1706 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1707 | unsigned int active:1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1708 | |
| 1709 | /** |
| 1710 | * This is set if the object has been written to since last bound |
| 1711 | * to the GTT |
| 1712 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1713 | unsigned int dirty:1; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1714 | |
| 1715 | /** |
| 1716 | * Fence register bits (if any) for this object. Will be set |
| 1717 | * as needed when mapped into the GTT. |
| 1718 | * Protected by dev->struct_mutex. |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1719 | */ |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 1720 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1721 | |
| 1722 | /** |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1723 | * Advice: are the backing pages purgeable? |
| 1724 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1725 | unsigned int madv:2; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1726 | |
| 1727 | /** |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1728 | * Current tiling mode for the object. |
| 1729 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1730 | unsigned int tiling_mode:2; |
Chris Wilson | 5d82e3e | 2012-04-21 16:23:23 +0100 | [diff] [blame] | 1731 | /** |
| 1732 | * Whether the tiling parameters for the currently associated fence |
| 1733 | * register have changed. Note that for the purposes of tracking |
| 1734 | * tiling changes we also treat the unfenced register, the register |
| 1735 | * slot that the object occupies whilst it executes a fenced |
| 1736 | * command (such as BLT on gen2/3), as a "fence". |
| 1737 | */ |
| 1738 | unsigned int fence_dirty:1; |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1739 | |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1740 | /** |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1741 | * Is the object at the current location in the gtt mappable and |
| 1742 | * fenceable? Used to avoid costly recalculations. |
| 1743 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1744 | unsigned int map_and_fenceable:1; |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 1745 | |
| 1746 | /** |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1747 | * Whether the current gtt mapping needs to be mappable (and isn't just |
| 1748 | * mappable by accident). Track pin and fault separate for a more |
| 1749 | * accurate mappable working set. |
| 1750 | */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1751 | unsigned int fault_mappable:1; |
| 1752 | unsigned int pin_mappable:1; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 1753 | unsigned int pin_display:1; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1754 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1755 | /* |
| 1756 | * Is the GPU currently using a fence to access this buffer, |
| 1757 | */ |
| 1758 | unsigned int pending_fenced_gpu_access:1; |
| 1759 | unsigned int fenced_gpu_access:1; |
| 1760 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 1761 | unsigned int cache_level:3; |
Chris Wilson | 93dfb40 | 2011-03-29 16:59:50 -0700 | [diff] [blame] | 1762 | |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 1763 | unsigned int has_aliasing_ppgtt_mapping:1; |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 1764 | unsigned int has_global_gtt_mapping:1; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1765 | unsigned int has_dma_mapping:1; |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 1766 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1767 | struct sg_table *pages; |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 1768 | int pages_pin_count; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1769 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1770 | /* prime dma-buf support */ |
Dave Airlie | 9a70cc2 | 2012-05-22 13:09:21 +0100 | [diff] [blame] | 1771 | void *dma_buf_vmapping; |
| 1772 | int vmapping_count; |
| 1773 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1774 | struct intel_ring_buffer *ring; |
| 1775 | |
Chris Wilson | 1c293ea | 2012-04-17 15:31:27 +0100 | [diff] [blame] | 1776 | /** Breadcrumb of last rendering to the buffer. */ |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 1777 | uint32_t last_read_seqno; |
| 1778 | uint32_t last_write_seqno; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 1779 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
| 1780 | uint32_t last_fenced_seqno; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1781 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 1782 | /** Current tiling stride for the object, if it's tiled. */ |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1783 | uint32_t stride; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1784 | |
Daniel Vetter | 80075d4 | 2013-10-09 21:23:52 +0200 | [diff] [blame] | 1785 | /** References from framebuffers, locks out tiling changes. */ |
| 1786 | unsigned long framebuffer_references; |
| 1787 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1788 | /** Record of address bit 17 of each page at last unbind. */ |
Chris Wilson | d312ec2 | 2010-06-06 15:40:22 +0100 | [diff] [blame] | 1789 | unsigned long *bit_17; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1790 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1791 | /** User space pin count and filp owning the pin */ |
Daniel Vetter | aa5f802 | 2013-10-10 14:46:37 +0200 | [diff] [blame] | 1792 | unsigned long user_pin_count; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1793 | struct drm_file *pin_filp; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1794 | |
| 1795 | /** for phy allocated objects */ |
| 1796 | struct drm_i915_gem_phys_object *phys_obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1797 | }; |
| 1798 | |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 1799 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1800 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1801 | /** |
| 1802 | * Request queue structure. |
| 1803 | * |
| 1804 | * The request queue allows us to note sequence numbers that have been emitted |
| 1805 | * and may be associated with active buffers to be retired. |
| 1806 | * |
| 1807 | * By keeping this list, we can avoid having to do questionable |
| 1808 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate |
| 1809 | * an emission time with seqnos for tracking how far ahead of the GPU we are. |
| 1810 | */ |
| 1811 | struct drm_i915_gem_request { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1812 | /** On Which ring this request was generated */ |
| 1813 | struct intel_ring_buffer *ring; |
| 1814 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1815 | /** GEM sequence number associated with this request. */ |
| 1816 | uint32_t seqno; |
| 1817 | |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 1818 | /** Position in the ringbuffer of the start of the request */ |
| 1819 | u32 head; |
| 1820 | |
| 1821 | /** Position in the ringbuffer of the end of the request */ |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1822 | u32 tail; |
| 1823 | |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 1824 | /** Context related to this request */ |
| 1825 | struct i915_hw_context *ctx; |
| 1826 | |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 1827 | /** Batch buffer related to this request if any */ |
| 1828 | struct drm_i915_gem_object *batch_obj; |
| 1829 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1830 | /** Time at which this request was emitted, in jiffies. */ |
| 1831 | unsigned long emitted_jiffies; |
| 1832 | |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1833 | /** global list entry for this request */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1834 | struct list_head list; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1835 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1836 | struct drm_i915_file_private *file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1837 | /** file_priv list entry for this request */ |
| 1838 | struct list_head client_list; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1839 | }; |
| 1840 | |
| 1841 | struct drm_i915_file_private { |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1842 | struct drm_i915_private *dev_priv; |
Chris Wilson | ab0e7ff | 2014-02-25 17:11:24 +0200 | [diff] [blame] | 1843 | struct drm_file *file; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1844 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1845 | struct { |
Luis R. Rodriguez | 99057c8 | 2012-11-29 12:45:06 -0800 | [diff] [blame] | 1846 | spinlock_t lock; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1847 | struct list_head request_list; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1848 | struct delayed_work idle_work; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1849 | } mm; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 1850 | struct idr context_idr; |
Mika Kuoppala | e59ec13 | 2013-06-12 12:35:28 +0300 | [diff] [blame] | 1851 | |
Ben Widawsky | 0eea67e | 2013-12-06 14:11:19 -0800 | [diff] [blame] | 1852 | struct i915_hw_context *private_default_ctx; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1853 | atomic_t rps_wait_boost; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1854 | }; |
| 1855 | |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 1856 | /* |
| 1857 | * A command that requires special handling by the command parser. |
| 1858 | */ |
| 1859 | struct drm_i915_cmd_descriptor { |
| 1860 | /* |
| 1861 | * Flags describing how the command parser processes the command. |
| 1862 | * |
| 1863 | * CMD_DESC_FIXED: The command has a fixed length if this is set, |
| 1864 | * a length mask if not set |
| 1865 | * CMD_DESC_SKIP: The command is allowed but does not follow the |
| 1866 | * standard length encoding for the opcode range in |
| 1867 | * which it falls |
| 1868 | * CMD_DESC_REJECT: The command is never allowed |
| 1869 | * CMD_DESC_REGISTER: The command should be checked against the |
| 1870 | * register whitelist for the appropriate ring |
| 1871 | * CMD_DESC_MASTER: The command is allowed if the submitting process |
| 1872 | * is the DRM master |
| 1873 | */ |
| 1874 | u32 flags; |
| 1875 | #define CMD_DESC_FIXED (1<<0) |
| 1876 | #define CMD_DESC_SKIP (1<<1) |
| 1877 | #define CMD_DESC_REJECT (1<<2) |
| 1878 | #define CMD_DESC_REGISTER (1<<3) |
| 1879 | #define CMD_DESC_BITMASK (1<<4) |
| 1880 | #define CMD_DESC_MASTER (1<<5) |
| 1881 | |
| 1882 | /* |
| 1883 | * The command's unique identification bits and the bitmask to get them. |
| 1884 | * This isn't strictly the opcode field as defined in the spec and may |
| 1885 | * also include type, subtype, and/or subop fields. |
| 1886 | */ |
| 1887 | struct { |
| 1888 | u32 value; |
| 1889 | u32 mask; |
| 1890 | } cmd; |
| 1891 | |
| 1892 | /* |
| 1893 | * The command's length. The command is either fixed length (i.e. does |
| 1894 | * not include a length field) or has a length field mask. The flag |
| 1895 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has |
| 1896 | * a length mask. All command entries in a command table must include |
| 1897 | * length information. |
| 1898 | */ |
| 1899 | union { |
| 1900 | u32 fixed; |
| 1901 | u32 mask; |
| 1902 | } length; |
| 1903 | |
| 1904 | /* |
| 1905 | * Describes where to find a register address in the command to check |
| 1906 | * against the ring's register whitelist. Only valid if flags has the |
| 1907 | * CMD_DESC_REGISTER bit set. |
| 1908 | */ |
| 1909 | struct { |
| 1910 | u32 offset; |
| 1911 | u32 mask; |
| 1912 | } reg; |
| 1913 | |
| 1914 | #define MAX_CMD_DESC_BITMASKS 3 |
| 1915 | /* |
| 1916 | * Describes command checks where a particular dword is masked and |
| 1917 | * compared against an expected value. If the command does not match |
| 1918 | * the expected value, the parser rejects it. Only valid if flags has |
| 1919 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero |
| 1920 | * are valid. |
| 1921 | */ |
| 1922 | struct { |
| 1923 | u32 offset; |
| 1924 | u32 mask; |
| 1925 | u32 expected; |
| 1926 | } bits[MAX_CMD_DESC_BITMASKS]; |
| 1927 | }; |
| 1928 | |
| 1929 | /* |
| 1930 | * A table of commands requiring special handling by the command parser. |
| 1931 | * |
| 1932 | * Each ring has an array of tables. Each table consists of an array of command |
| 1933 | * descriptors, which must be sorted with command opcodes in ascending order. |
| 1934 | */ |
| 1935 | struct drm_i915_cmd_table { |
| 1936 | const struct drm_i915_cmd_descriptor *table; |
| 1937 | int count; |
| 1938 | }; |
| 1939 | |
Damien Lespiau | 5c969aa | 2014-02-07 19:12:48 +0000 | [diff] [blame] | 1940 | #define INTEL_INFO(dev) (&to_i915(dev)->info) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1941 | |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1942 | #define IS_I830(dev) ((dev)->pdev->device == 0x3577) |
| 1943 | #define IS_845G(dev) ((dev)->pdev->device == 0x2562) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1944 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1945 | #define IS_I865G(dev) ((dev)->pdev->device == 0x2572) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1946 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1947 | #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592) |
| 1948 | #define IS_I945G(dev) ((dev)->pdev->device == 0x2772) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1949 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
| 1950 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) |
| 1951 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1952 | #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1953 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1954 | #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001) |
| 1955 | #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1956 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
| 1957 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1958 | #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046) |
Jesse Barnes | 4b65177 | 2011-04-28 14:33:09 -0700 | [diff] [blame] | 1959 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1960 | #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \ |
| 1961 | (dev)->pdev->device == 0x0152 || \ |
| 1962 | (dev)->pdev->device == 0x015a) |
| 1963 | #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \ |
| 1964 | (dev)->pdev->device == 0x0106 || \ |
| 1965 | (dev)->pdev->device == 0x010A) |
Jesse Barnes | 70a3eb7 | 2012-03-28 13:39:21 -0700 | [diff] [blame] | 1966 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
Eugeni Dodonov | 4cae9ae | 2012-03-29 12:32:18 -0300 | [diff] [blame] | 1967 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
Paulo Zanoni | 4e8058a | 2013-11-02 21:07:31 -0700 | [diff] [blame] | 1968 | #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1969 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
Paulo Zanoni | ed1c9e2 | 2013-08-12 14:34:08 -0300 | [diff] [blame] | 1970 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1971 | ((dev)->pdev->device & 0xFF00) == 0x0C00) |
Ben Widawsky | 5dd8c4c | 2013-11-08 10:20:06 -0800 | [diff] [blame] | 1972 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
| 1973 | (((dev)->pdev->device & 0xf) == 0x2 || \ |
| 1974 | ((dev)->pdev->device & 0xf) == 0x6 || \ |
| 1975 | ((dev)->pdev->device & 0xf) == 0xe)) |
| 1976 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1977 | ((dev)->pdev->device & 0xFF00) == 0x0A00) |
Ben Widawsky | 5dd8c4c | 2013-11-08 10:20:06 -0800 | [diff] [blame] | 1978 | #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
Rodrigo Vivi | 9435373 | 2013-08-28 16:45:46 -0300 | [diff] [blame] | 1979 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
Ville Syrjälä | ffbab09b | 2013-10-04 14:53:40 +0300 | [diff] [blame] | 1980 | ((dev)->pdev->device & 0x00F0) == 0x0020) |
Ben Widawsky | b833d68 | 2013-08-23 16:00:07 -0700 | [diff] [blame] | 1981 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1982 | |
Jesse Barnes | 8543669 | 2011-04-06 12:11:14 -0700 | [diff] [blame] | 1983 | /* |
| 1984 | * The genX designation typically refers to the render engine, so render |
| 1985 | * capability related checks should use IS_GEN, while display and other checks |
| 1986 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular |
| 1987 | * chips, etc.). |
| 1988 | */ |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1989 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
| 1990 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) |
| 1991 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) |
| 1992 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) |
| 1993 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) |
Jesse Barnes | 8543669 | 2011-04-06 12:11:14 -0700 | [diff] [blame] | 1994 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
Ben Widawsky | d298084 | 2013-11-02 21:06:59 -0700 | [diff] [blame] | 1995 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1996 | |
Ben Widawsky | 73ae478 | 2013-10-15 10:02:57 -0700 | [diff] [blame] | 1997 | #define RENDER_RING (1<<RCS) |
| 1998 | #define BSD_RING (1<<VCS) |
| 1999 | #define BLT_RING (1<<BCS) |
| 2000 | #define VEBOX_RING (1<<VECS) |
| 2001 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
| 2002 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
| 2003 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 2004 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 2005 | #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2006 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
| 2007 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 2008 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
Ben Widawsky | 246cbfb | 2013-12-06 14:11:14 -0800 | [diff] [blame] | 2009 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) |
Ben Widawsky | c5dc5ce | 2014-01-27 23:07:00 -0800 | [diff] [blame] | 2010 | #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) \ |
| 2011 | && !IS_BROADWELL(dev)) |
| 2012 | #define USES_PPGTT(dev) intel_enable_ppgtt(dev, false) |
Ben Widawsky | 7e0d96b | 2013-12-06 14:11:26 -0800 | [diff] [blame] | 2013 | #define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true) |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 2014 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2015 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2016 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
| 2017 | |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2018 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
| 2019 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) |
Daniel Vetter | 4e6b788 | 2014-02-07 16:33:20 +0100 | [diff] [blame] | 2020 | /* |
| 2021 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts |
| 2022 | * even when in MSI mode. This results in spurious interrupt warnings if the |
| 2023 | * legacy irq no. is shared with another device. The kernel then disables that |
| 2024 | * interrupt source and so prevents the other device from working properly. |
| 2025 | */ |
| 2026 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) |
| 2027 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 2028 | |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2029 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
| 2030 | * rows, which changed the alignment requirements and fence programming. |
| 2031 | */ |
| 2032 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ |
| 2033 | IS_I915GM(dev))) |
| 2034 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) |
| 2035 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
| 2036 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2037 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
| 2038 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2039 | |
| 2040 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) |
| 2041 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 2042 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2043 | |
Ben Widawsky | 2a114cc | 2013-11-02 21:07:47 -0700 | [diff] [blame] | 2044 | #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) |
Damien Lespiau | f5adf94 | 2013-06-24 18:29:34 +0100 | [diff] [blame] | 2045 | |
Damien Lespiau | dd93be5 | 2013-04-22 18:40:39 +0100 | [diff] [blame] | 2046 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
Damien Lespiau | 30568c4 | 2013-04-22 18:40:41 +0100 | [diff] [blame] | 2047 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
Ben Widawsky | ed8546a | 2013-11-04 22:45:05 -0800 | [diff] [blame] | 2048 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Chris Wilson | 7c6c265 | 2013-11-18 18:32:37 -0800 | [diff] [blame] | 2049 | #define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */ |
Paulo Zanoni | df4547d | 2013-12-13 15:22:32 -0200 | [diff] [blame] | 2050 | #define HAS_RUNTIME_PM(dev) (IS_HASWELL(dev)) |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 2051 | |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 2052 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
| 2053 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
| 2054 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
| 2055 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
| 2056 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 |
| 2057 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 |
| 2058 | |
Chris Wilson | 2c1792a | 2013-08-01 18:39:55 +0100 | [diff] [blame] | 2059 | #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) |
Eugeni Dodonov | eb877eb | 2012-03-29 12:32:20 -0300 | [diff] [blame] | 2060 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2061 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
| 2062 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) |
Ben Widawsky | 40c7ead | 2013-04-05 13:12:40 -0700 | [diff] [blame] | 2063 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
Paulo Zanoni | 45e6e3a | 2012-07-03 15:57:32 -0300 | [diff] [blame] | 2064 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2065 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 2066 | /* DPF == dynamic parity feature */ |
| 2067 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
| 2068 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) |
Ben Widawsky | e1ef7cc | 2012-07-24 20:47:31 -0700 | [diff] [blame] | 2069 | |
Ben Widawsky | c8735b0 | 2012-09-07 19:43:39 -0700 | [diff] [blame] | 2070 | #define GT_FREQUENCY_MULTIPLIER 50 |
| 2071 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2072 | #include "i915_trace.h" |
| 2073 | |
Rob Clark | baa7094 | 2013-08-02 13:27:49 -0400 | [diff] [blame] | 2074 | extern const struct drm_ioctl_desc i915_ioctls[]; |
Dave Airlie | b3a8363 | 2005-09-30 18:37:36 +1000 | [diff] [blame] | 2075 | extern int i915_max_ioctl; |
| 2076 | |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 2077 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
| 2078 | extern int i915_resume(struct drm_device *dev); |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 2079 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
| 2080 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); |
| 2081 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 2082 | /* i915_params.c */ |
| 2083 | struct i915_params { |
| 2084 | int modeset; |
| 2085 | int panel_ignore_lid; |
| 2086 | unsigned int powersave; |
| 2087 | int semaphores; |
| 2088 | unsigned int lvds_downclock; |
| 2089 | int lvds_channel_mode; |
| 2090 | int panel_use_ssc; |
| 2091 | int vbt_sdvo_panel_type; |
| 2092 | int enable_rc6; |
| 2093 | int enable_fbc; |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 2094 | int enable_ppgtt; |
| 2095 | int enable_psr; |
| 2096 | unsigned int preliminary_hw_support; |
| 2097 | int disable_power_well; |
| 2098 | int enable_ips; |
Damien Lespiau | e5aa654 | 2014-02-07 19:12:53 +0000 | [diff] [blame] | 2099 | int invert_brightness; |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 2100 | int enable_cmd_parser; |
Damien Lespiau | e5aa654 | 2014-02-07 19:12:53 +0000 | [diff] [blame] | 2101 | /* leave bools at the end to not create holes */ |
| 2102 | bool enable_hangcheck; |
| 2103 | bool fastboot; |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 2104 | bool prefault_disable; |
| 2105 | bool reset; |
Damien Lespiau | a0bae57 | 2014-02-10 17:20:55 +0000 | [diff] [blame] | 2106 | bool disable_display; |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 2107 | }; |
| 2108 | extern struct i915_params i915 __read_mostly; |
| 2109 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2110 | /* i915_dma.c */ |
Daniel Vetter | d05c617 | 2012-04-26 23:28:09 +0200 | [diff] [blame] | 2111 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 2112 | extern void i915_kernel_lost_context(struct drm_device * dev); |
Dave Airlie | 22eae94 | 2005-11-10 22:16:34 +1100 | [diff] [blame] | 2113 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
Jesse Barnes | ba8bbcf | 2007-11-22 14:14:14 +1000 | [diff] [blame] | 2114 | extern int i915_driver_unload(struct drm_device *); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2115 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 2116 | extern void i915_driver_lastclose(struct drm_device * dev); |
Eric Anholt | 6c340ea | 2007-08-25 20:23:09 +1000 | [diff] [blame] | 2117 | extern void i915_driver_preclose(struct drm_device *dev, |
| 2118 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2119 | extern void i915_driver_postclose(struct drm_device *dev, |
| 2120 | struct drm_file *file_priv); |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 2121 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 2122 | #ifdef CONFIG_COMPAT |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 2123 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
| 2124 | unsigned long arg); |
Ben Widawsky | c43b563 | 2012-04-16 14:07:40 -0700 | [diff] [blame] | 2125 | #endif |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2126 | extern int i915_emit_box(struct drm_device *dev, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 2127 | struct drm_clip_rect *box, |
| 2128 | int DR1, int DR4); |
Ben Widawsky | 8e96d9c | 2012-06-04 14:42:56 -0700 | [diff] [blame] | 2129 | extern int intel_gpu_reset(struct drm_device *dev); |
Daniel Vetter | d4b8bb2 | 2012-04-27 15:17:44 +0200 | [diff] [blame] | 2130 | extern int i915_reset(struct drm_device *dev); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 2131 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
| 2132 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); |
| 2133 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); |
| 2134 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); |
| 2135 | |
Jesse Barnes | 073f34d | 2012-11-02 11:13:59 -0700 | [diff] [blame] | 2136 | extern void intel_console_resume(struct work_struct *work); |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 2137 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2138 | /* i915_irq.c */ |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 2139 | void i915_queue_hangcheck(struct drm_device *dev); |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 2140 | __printf(3, 4) |
| 2141 | void i915_handle_error(struct drm_device *dev, bool wedged, |
| 2142 | const char *fmt, ...); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2143 | |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 2144 | void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir, |
| 2145 | int new_delay); |
Jesse Barnes | f71d4af | 2011-06-28 13:00:41 -0700 | [diff] [blame] | 2146 | extern void intel_irq_init(struct drm_device *dev); |
Daniel Vetter | 20afbda | 2012-12-11 14:05:07 +0100 | [diff] [blame] | 2147 | extern void intel_hpd_init(struct drm_device *dev); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 2148 | |
| 2149 | extern void intel_uncore_sanitize(struct drm_device *dev); |
| 2150 | extern void intel_uncore_early_sanitize(struct drm_device *dev); |
| 2151 | extern void intel_uncore_init(struct drm_device *dev); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 2152 | extern void intel_uncore_check_errors(struct drm_device *dev); |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 2153 | extern void intel_uncore_fini(struct drm_device *dev); |
Jesse Barnes | b1f14ad | 2011-04-06 12:13:38 -0700 | [diff] [blame] | 2154 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 2155 | void |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 2156 | i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, |
| 2157 | u32 status_mask); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 2158 | |
| 2159 | void |
Imre Deak | 755e901 | 2014-02-10 18:42:47 +0200 | [diff] [blame] | 2160 | i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, |
| 2161 | u32 status_mask); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 2162 | |
Imre Deak | f8b79e5 | 2014-03-04 19:23:07 +0200 | [diff] [blame] | 2163 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
| 2164 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); |
| 2165 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2166 | /* i915_gem.c */ |
| 2167 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 2168 | struct drm_file *file_priv); |
| 2169 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 2170 | struct drm_file *file_priv); |
| 2171 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 2172 | struct drm_file *file_priv); |
| 2173 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 2174 | struct drm_file *file_priv); |
| 2175 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 2176 | struct drm_file *file_priv); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2177 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 2178 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2179 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 2180 | struct drm_file *file_priv); |
| 2181 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 2182 | struct drm_file *file_priv); |
| 2183 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 2184 | struct drm_file *file_priv); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 2185 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 2186 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2187 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 2188 | struct drm_file *file_priv); |
| 2189 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 2190 | struct drm_file *file_priv); |
| 2191 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 2192 | struct drm_file *file_priv); |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 2193 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
| 2194 | struct drm_file *file); |
| 2195 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
| 2196 | struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2197 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 2198 | struct drm_file *file_priv); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2199 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 2200 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2201 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 2202 | struct drm_file *file_priv); |
| 2203 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 2204 | struct drm_file *file_priv); |
| 2205 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
| 2206 | struct drm_file *file_priv); |
| 2207 | int i915_gem_get_tiling(struct drm_device *dev, void *data, |
| 2208 | struct drm_file *file_priv); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 2209 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 2210 | struct drm_file *file_priv); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 2211 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
| 2212 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2213 | void i915_gem_load(struct drm_device *dev); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 2214 | void *i915_gem_object_alloc(struct drm_device *dev); |
| 2215 | void i915_gem_object_free(struct drm_i915_gem_object *obj); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2216 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 2217 | const struct drm_i915_gem_object_ops *ops); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2218 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
| 2219 | size_t size); |
Ben Widawsky | 7e0d96b | 2013-12-06 14:11:26 -0800 | [diff] [blame] | 2220 | void i915_init_vm(struct drm_i915_private *dev_priv, |
| 2221 | struct i915_address_space *vm); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2222 | void i915_gem_free_object(struct drm_gem_object *obj); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 2223 | void i915_gem_vma_destroy(struct i915_vma *vma); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 2224 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 2225 | #define PIN_MAPPABLE 0x1 |
| 2226 | #define PIN_NONBLOCK 0x2 |
Daniel Vetter | bf3d149 | 2014-02-14 14:01:12 +0100 | [diff] [blame] | 2227 | #define PIN_GLOBAL 0x4 |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2228 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 2229 | struct i915_address_space *vm, |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2230 | uint32_t alignment, |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 2231 | unsigned flags); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 2232 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2233 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
Paulo Zanoni | 48018a5 | 2013-12-13 15:22:31 -0200 | [diff] [blame] | 2234 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2235 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2236 | void i915_gem_lastclose(struct drm_device *dev); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2237 | |
Brad Volkin | 4c914c0 | 2014-02-18 10:15:45 -0800 | [diff] [blame] | 2238 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
| 2239 | int *needs_clflush); |
| 2240 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2241 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2242 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
| 2243 | { |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 2244 | struct sg_page_iter sg_iter; |
Chris Wilson | 1cf8378 | 2012-10-10 12:11:52 +0100 | [diff] [blame] | 2245 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 2246 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 2247 | return sg_page_iter_page(&sg_iter); |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 2248 | |
| 2249 | return NULL; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2250 | } |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 2251 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
| 2252 | { |
| 2253 | BUG_ON(obj->pages == NULL); |
| 2254 | obj->pages_pin_count++; |
| 2255 | } |
| 2256 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) |
| 2257 | { |
| 2258 | BUG_ON(obj->pages_pin_count == 0); |
| 2259 | obj->pages_pin_count--; |
| 2260 | } |
| 2261 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 2262 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2263 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 2264 | struct intel_ring_buffer *to); |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2265 | void i915_vma_move_to_active(struct i915_vma *vma, |
| 2266 | struct intel_ring_buffer *ring); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2267 | int i915_gem_dumb_create(struct drm_file *file_priv, |
| 2268 | struct drm_device *dev, |
| 2269 | struct drm_mode_create_dumb *args); |
| 2270 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
| 2271 | uint32_t handle, uint64_t *offset); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 2272 | /** |
| 2273 | * Returns true if seq1 is later than seq2. |
| 2274 | */ |
| 2275 | static inline bool |
| 2276 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
| 2277 | { |
| 2278 | return (int32_t)(seq1 - seq2) >= 0; |
| 2279 | } |
| 2280 | |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2281 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
| 2282 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); |
Chris Wilson | 06d9813 | 2012-04-17 15:31:24 +0100 | [diff] [blame] | 2283 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 2284 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2285 | |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2286 | static inline bool |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2287 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
| 2288 | { |
| 2289 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2290 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2291 | dev_priv->fence_regs[obj->fence_reg].pin_count++; |
Chris Wilson | 9a5a53b | 2012-03-22 15:10:00 +0000 | [diff] [blame] | 2292 | return true; |
| 2293 | } else |
| 2294 | return false; |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2295 | } |
| 2296 | |
| 2297 | static inline void |
| 2298 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) |
| 2299 | { |
| 2300 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
| 2301 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | b8c3af7 | 2013-06-12 11:29:47 +0100 | [diff] [blame] | 2302 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); |
Chris Wilson | 1690e1e | 2011-12-14 13:57:08 +0100 | [diff] [blame] | 2303 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
| 2304 | } |
| 2305 | } |
| 2306 | |
Chris Wilson | 8d9fc7f | 2014-02-25 17:11:23 +0200 | [diff] [blame] | 2307 | struct drm_i915_gem_request * |
| 2308 | i915_gem_find_active_request(struct intel_ring_buffer *ring); |
| 2309 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2310 | bool i915_gem_retire_requests(struct drm_device *dev); |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 2311 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
Daniel Vetter | d6b2c79 | 2012-07-04 22:54:13 +0200 | [diff] [blame] | 2312 | bool interruptible); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2313 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
| 2314 | { |
| 2315 | return unlikely(atomic_read(&error->reset_counter) |
Mika Kuoppala | 2ac0f45 | 2013-11-12 14:44:19 +0200 | [diff] [blame] | 2316 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2317 | } |
| 2318 | |
| 2319 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) |
| 2320 | { |
Mika Kuoppala | 2ac0f45 | 2013-11-12 14:44:19 +0200 | [diff] [blame] | 2321 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
| 2322 | } |
| 2323 | |
| 2324 | static inline u32 i915_reset_count(struct i915_gpu_error *error) |
| 2325 | { |
| 2326 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 2327 | } |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2328 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 2329 | void i915_gem_reset(struct drm_device *dev); |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 2330 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 2331 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 2332 | int __must_check i915_gem_init(struct drm_device *dev); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 2333 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 2334 | int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 2335 | void i915_gem_init_swizzling(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2336 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 2337 | int __must_check i915_gpu_idle(struct drm_device *dev); |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 2338 | int __must_check i915_gem_suspend(struct drm_device *dev); |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2339 | int __i915_add_request(struct intel_ring_buffer *ring, |
| 2340 | struct drm_file *file, |
Mika Kuoppala | 7d736f4 | 2013-06-12 15:01:39 +0300 | [diff] [blame] | 2341 | struct drm_i915_gem_object *batch_obj, |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 2342 | u32 *seqno); |
| 2343 | #define i915_add_request(ring, seqno) \ |
Dan Carpenter | 854c94a | 2013-06-18 10:29:58 +0300 | [diff] [blame] | 2344 | __i915_add_request(ring, NULL, NULL, seqno) |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 2345 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
| 2346 | uint32_t seqno); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2347 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2348 | int __must_check |
| 2349 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
| 2350 | bool write); |
| 2351 | int __must_check |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 2352 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
| 2353 | int __must_check |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 2354 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 2355 | u32 alignment, |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 2356 | struct intel_ring_buffer *pipelined); |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 2357 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 2358 | int i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2359 | struct drm_i915_gem_object *obj, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 2360 | int id, |
| 2361 | int align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 2362 | void i915_gem_detach_phys_object(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2363 | struct drm_i915_gem_object *obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 2364 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 2365 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2366 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2367 | |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 2368 | uint32_t |
Imre Deak | 0fa8779 | 2013-01-07 21:47:35 +0200 | [diff] [blame] | 2369 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); |
| 2370 | uint32_t |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 2371 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
| 2372 | int tiling_mode, bool fenced); |
Chris Wilson | 467cffb | 2011-03-07 10:42:03 +0000 | [diff] [blame] | 2373 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 2374 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 2375 | enum i915_cache_level cache_level); |
| 2376 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 2377 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
| 2378 | struct dma_buf *dma_buf); |
| 2379 | |
| 2380 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, |
| 2381 | struct drm_gem_object *gem_obj, int flags); |
| 2382 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 2383 | void i915_gem_restore_fences(struct drm_device *dev); |
| 2384 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2385 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
| 2386 | struct i915_address_space *vm); |
| 2387 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
| 2388 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
| 2389 | struct i915_address_space *vm); |
| 2390 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
| 2391 | struct i915_address_space *vm); |
| 2392 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
| 2393 | struct i915_address_space *vm); |
Ben Widawsky | accfef2 | 2013-08-14 11:38:35 +0200 | [diff] [blame] | 2394 | struct i915_vma * |
| 2395 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
| 2396 | struct i915_address_space *vm); |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 2397 | |
| 2398 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 2399 | static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) { |
| 2400 | struct i915_vma *vma; |
| 2401 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
| 2402 | if (vma->pin_count > 0) |
| 2403 | return true; |
| 2404 | return false; |
| 2405 | } |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 2406 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2407 | /* Some GGTT VM helpers */ |
| 2408 | #define obj_to_ggtt(obj) \ |
| 2409 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
| 2410 | static inline bool i915_is_ggtt(struct i915_address_space *vm) |
| 2411 | { |
| 2412 | struct i915_address_space *ggtt = |
| 2413 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; |
| 2414 | return vm == ggtt; |
| 2415 | } |
| 2416 | |
| 2417 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
| 2418 | { |
| 2419 | return i915_gem_obj_bound(obj, obj_to_ggtt(obj)); |
| 2420 | } |
| 2421 | |
| 2422 | static inline unsigned long |
| 2423 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) |
| 2424 | { |
| 2425 | return i915_gem_obj_offset(obj, obj_to_ggtt(obj)); |
| 2426 | } |
| 2427 | |
| 2428 | static inline unsigned long |
| 2429 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) |
| 2430 | { |
| 2431 | return i915_gem_obj_size(obj, obj_to_ggtt(obj)); |
| 2432 | } |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 2433 | |
| 2434 | static inline int __must_check |
| 2435 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, |
| 2436 | uint32_t alignment, |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 2437 | unsigned flags) |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 2438 | { |
Daniel Vetter | bf3d149 | 2014-02-14 14:01:12 +0100 | [diff] [blame] | 2439 | return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL); |
Ben Widawsky | c37e220 | 2013-07-31 16:59:58 -0700 | [diff] [blame] | 2440 | } |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 2441 | |
Daniel Vetter | b287110 | 2014-02-14 14:01:19 +0100 | [diff] [blame] | 2442 | static inline int |
| 2443 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) |
| 2444 | { |
| 2445 | return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); |
| 2446 | } |
| 2447 | |
| 2448 | void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj); |
| 2449 | |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 2450 | /* i915_gem_context.c */ |
Ben Widawsky | 0eea67e | 2013-12-06 14:11:19 -0800 | [diff] [blame] | 2451 | #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base) |
Ben Widawsky | 8245be3 | 2013-11-06 13:56:29 -0200 | [diff] [blame] | 2452 | int __must_check i915_gem_context_init(struct drm_device *dev); |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 2453 | void i915_gem_context_fini(struct drm_device *dev); |
Ben Widawsky | acce9ff | 2013-12-06 14:11:03 -0800 | [diff] [blame] | 2454 | void i915_gem_context_reset(struct drm_device *dev); |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 2455 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 2456 | int i915_gem_context_enable(struct drm_i915_private *dev_priv); |
Ben Widawsky | 254f965 | 2012-06-04 14:42:42 -0700 | [diff] [blame] | 2457 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
Ben Widawsky | e055684 | 2012-06-04 14:42:46 -0700 | [diff] [blame] | 2458 | int i915_switch_context(struct intel_ring_buffer *ring, |
Ben Widawsky | 41bde55 | 2013-12-06 14:11:21 -0800 | [diff] [blame] | 2459 | struct drm_file *file, struct i915_hw_context *to); |
| 2460 | struct i915_hw_context * |
| 2461 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); |
Mika Kuoppala | dce3271 | 2013-04-30 13:30:33 +0300 | [diff] [blame] | 2462 | void i915_gem_context_free(struct kref *ctx_ref); |
| 2463 | static inline void i915_gem_context_reference(struct i915_hw_context *ctx) |
| 2464 | { |
Ben Widawsky | c482972 | 2013-12-06 14:11:20 -0800 | [diff] [blame] | 2465 | if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev)) |
| 2466 | kref_get(&ctx->ref); |
Mika Kuoppala | dce3271 | 2013-04-30 13:30:33 +0300 | [diff] [blame] | 2467 | } |
| 2468 | |
| 2469 | static inline void i915_gem_context_unreference(struct i915_hw_context *ctx) |
| 2470 | { |
Ben Widawsky | c482972 | 2013-12-06 14:11:20 -0800 | [diff] [blame] | 2471 | if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev)) |
| 2472 | kref_put(&ctx->ref, i915_gem_context_free); |
Mika Kuoppala | dce3271 | 2013-04-30 13:30:33 +0300 | [diff] [blame] | 2473 | } |
| 2474 | |
Mika Kuoppala | 3fac897 | 2014-01-30 16:05:48 +0200 | [diff] [blame] | 2475 | static inline bool i915_gem_context_is_default(const struct i915_hw_context *c) |
| 2476 | { |
| 2477 | return c->id == DEFAULT_CONTEXT_ID; |
| 2478 | } |
| 2479 | |
Ben Widawsky | 8462481 | 2012-06-04 14:42:54 -0700 | [diff] [blame] | 2480 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
| 2481 | struct drm_file *file); |
| 2482 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, |
| 2483 | struct drm_file *file); |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 2484 | |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2485 | /* i915_gem_evict.c */ |
Ben Widawsky | f6cd1f1 | 2013-07-31 17:00:11 -0700 | [diff] [blame] | 2486 | int __must_check i915_gem_evict_something(struct drm_device *dev, |
| 2487 | struct i915_address_space *vm, |
| 2488 | int min_size, |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2489 | unsigned alignment, |
| 2490 | unsigned cache_level, |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 2491 | unsigned flags); |
Ben Widawsky | 68c8c17 | 2013-09-11 14:57:50 -0700 | [diff] [blame] | 2492 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2493 | int i915_gem_evict_everything(struct drm_device *dev); |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2494 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2495 | /* i915_gem_gtt.c */ |
| 2496 | void i915_check_and_clear_faults(struct drm_device *dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2497 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev); |
| 2498 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2499 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2500 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
| 2501 | void i915_gem_init_global_gtt(struct drm_device *dev); |
| 2502 | void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, |
| 2503 | unsigned long mappable_end, unsigned long end); |
| 2504 | int i915_gem_gtt_init(struct drm_device *dev); |
| 2505 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
| 2506 | { |
| 2507 | if (INTEL_INFO(dev)->gen < 6) |
| 2508 | intel_gtt_chipset_flush(); |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 2509 | } |
Ben Widawsky | 246cbfb | 2013-12-06 14:11:14 -0800 | [diff] [blame] | 2510 | int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); |
Daniel Vetter | 93a25a9 | 2014-03-06 09:40:43 +0100 | [diff] [blame] | 2511 | bool intel_enable_ppgtt(struct drm_device *dev, bool full); |
Ben Widawsky | 246cbfb | 2013-12-06 14:11:14 -0800 | [diff] [blame] | 2512 | |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 2513 | /* i915_gem_stolen.c */ |
| 2514 | int i915_gem_init_stolen(struct drm_device *dev); |
Chris Wilson | 11be49e | 2012-11-15 11:32:20 +0000 | [diff] [blame] | 2515 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); |
| 2516 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 2517 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
Chris Wilson | 0104fdb | 2012-11-15 11:32:26 +0000 | [diff] [blame] | 2518 | struct drm_i915_gem_object * |
| 2519 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); |
Chris Wilson | 866d12b | 2013-02-19 13:31:37 -0800 | [diff] [blame] | 2520 | struct drm_i915_gem_object * |
| 2521 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, |
| 2522 | u32 stolen_offset, |
| 2523 | u32 gtt_offset, |
| 2524 | u32 size); |
Chris Wilson | 0104fdb | 2012-11-15 11:32:26 +0000 | [diff] [blame] | 2525 | void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); |
Chris Wilson | 9797fbf | 2012-04-24 15:47:39 +0100 | [diff] [blame] | 2526 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2527 | /* i915_gem_tiling.c */ |
Chris Wilson | 2c1792a | 2013-08-01 18:39:55 +0100 | [diff] [blame] | 2528 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
Chris Wilson | e9b73c6 | 2012-12-03 21:03:14 +0000 | [diff] [blame] | 2529 | { |
| 2530 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
| 2531 | |
| 2532 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
| 2533 | obj->tiling_mode != I915_TILING_NONE; |
| 2534 | } |
| 2535 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2536 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
| 2537 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
| 2538 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); |
| 2539 | |
| 2540 | /* i915_gem_debug.c */ |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2541 | #if WATCH_LISTS |
| 2542 | int i915_verify_lists(struct drm_device *dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2543 | #else |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2544 | #define i915_verify_lists(dev) 0 |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2545 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2546 | |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2547 | /* i915_debugfs.c */ |
Ben Gamari | 27c202a | 2009-07-01 22:26:52 -0400 | [diff] [blame] | 2548 | int i915_debugfs_init(struct drm_minor *minor); |
| 2549 | void i915_debugfs_cleanup(struct drm_minor *minor); |
Daniel Vetter | f8c168f | 2013-10-16 11:49:58 +0200 | [diff] [blame] | 2550 | #ifdef CONFIG_DEBUG_FS |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2551 | void intel_display_crc_init(struct drm_device *dev); |
| 2552 | #else |
Daniel Vetter | f8c168f | 2013-10-16 11:49:58 +0200 | [diff] [blame] | 2553 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
Damien Lespiau | 0714442 | 2013-10-15 18:55:40 +0100 | [diff] [blame] | 2554 | #endif |
Mika Kuoppala | 84734a0 | 2013-07-12 16:50:57 +0300 | [diff] [blame] | 2555 | |
| 2556 | /* i915_gpu_error.c */ |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 2557 | __printf(2, 3) |
| 2558 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); |
Mika Kuoppala | fc16b48 | 2013-06-06 15:18:39 +0300 | [diff] [blame] | 2559 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
| 2560 | const struct i915_error_state_file_priv *error); |
Mika Kuoppala | 4dc955f | 2013-06-06 15:18:41 +0300 | [diff] [blame] | 2561 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
| 2562 | size_t count, loff_t pos); |
| 2563 | static inline void i915_error_state_buf_release( |
| 2564 | struct drm_i915_error_state_buf *eb) |
| 2565 | { |
| 2566 | kfree(eb->buf); |
| 2567 | } |
Mika Kuoppala | 5817446 | 2014-02-25 17:11:26 +0200 | [diff] [blame] | 2568 | void i915_capture_error_state(struct drm_device *dev, bool wedge, |
| 2569 | const char *error_msg); |
Mika Kuoppala | 84734a0 | 2013-07-12 16:50:57 +0300 | [diff] [blame] | 2570 | void i915_error_state_get(struct drm_device *dev, |
| 2571 | struct i915_error_state_file_priv *error_priv); |
| 2572 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); |
| 2573 | void i915_destroy_error_state(struct drm_device *dev); |
| 2574 | |
| 2575 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); |
| 2576 | const char *i915_cache_level_str(int type); |
Ben Gamari | 2017263 | 2009-02-17 20:08:50 -0500 | [diff] [blame] | 2577 | |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 2578 | /* i915_cmd_parser.c */ |
| 2579 | void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring); |
| 2580 | bool i915_needs_cmd_parser(struct intel_ring_buffer *ring); |
| 2581 | int i915_parse_cmds(struct intel_ring_buffer *ring, |
| 2582 | struct drm_i915_gem_object *batch_obj, |
| 2583 | u32 batch_start_offset, |
| 2584 | bool is_master); |
| 2585 | |
Jesse Barnes | 317c35d | 2008-08-25 15:11:06 -0700 | [diff] [blame] | 2586 | /* i915_suspend.c */ |
| 2587 | extern int i915_save_state(struct drm_device *dev); |
| 2588 | extern int i915_restore_state(struct drm_device *dev); |
| 2589 | |
Daniel Vetter | d8157a3 | 2013-01-25 17:53:20 +0100 | [diff] [blame] | 2590 | /* i915_ums.c */ |
| 2591 | void i915_save_display_reg(struct drm_device *dev); |
| 2592 | void i915_restore_display_reg(struct drm_device *dev); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 2593 | |
Ben Widawsky | 0136db58 | 2012-04-10 21:17:01 -0700 | [diff] [blame] | 2594 | /* i915_sysfs.c */ |
| 2595 | void i915_setup_sysfs(struct drm_device *dev_priv); |
| 2596 | void i915_teardown_sysfs(struct drm_device *dev_priv); |
| 2597 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2598 | /* intel_i2c.c */ |
| 2599 | extern int intel_setup_gmbus(struct drm_device *dev); |
| 2600 | extern void intel_teardown_gmbus(struct drm_device *dev); |
Jan-Simon Möller | 8f375e1 | 2013-05-06 14:52:08 +0200 | [diff] [blame] | 2601 | static inline bool intel_gmbus_is_port_valid(unsigned port) |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 2602 | { |
Daniel Kurtz | 2ed06c9 | 2012-03-28 02:36:15 +0800 | [diff] [blame] | 2603 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 2604 | } |
| 2605 | |
| 2606 | extern struct i2c_adapter *intel_gmbus_get_adapter( |
| 2607 | struct drm_i915_private *dev_priv, unsigned port); |
Chris Wilson | e957d77 | 2010-09-24 12:52:03 +0100 | [diff] [blame] | 2608 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
| 2609 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); |
Jan-Simon Möller | 8f375e1 | 2013-05-06 14:52:08 +0200 | [diff] [blame] | 2610 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
Chris Wilson | b8232e9 | 2010-09-28 16:41:32 +0100 | [diff] [blame] | 2611 | { |
| 2612 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; |
| 2613 | } |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2614 | extern void intel_i2c_reset(struct drm_device *dev); |
| 2615 | |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 2616 | /* intel_opregion.c */ |
Jani Nikula | 9c4b0a6 | 2013-08-30 19:40:30 +0300 | [diff] [blame] | 2617 | struct intel_encoder; |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 2618 | #ifdef CONFIG_ACPI |
Lv Zheng | 27d50c8 | 2013-12-06 16:52:05 +0800 | [diff] [blame] | 2619 | extern int intel_opregion_setup(struct drm_device *dev); |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 2620 | extern void intel_opregion_init(struct drm_device *dev); |
| 2621 | extern void intel_opregion_fini(struct drm_device *dev); |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 2622 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
Jani Nikula | 9c4b0a6 | 2013-08-30 19:40:30 +0300 | [diff] [blame] | 2623 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
| 2624 | bool enable); |
Jani Nikula | ecbc5cf | 2013-08-30 19:40:31 +0300 | [diff] [blame] | 2625 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
| 2626 | pci_power_t state); |
Len Brown | 65e082c | 2008-10-24 17:18:10 -0400 | [diff] [blame] | 2627 | #else |
Lv Zheng | 27d50c8 | 2013-12-06 16:52:05 +0800 | [diff] [blame] | 2628 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } |
Chris Wilson | 44834a6 | 2010-08-19 16:09:23 +0100 | [diff] [blame] | 2629 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
| 2630 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } |
Chris Wilson | 3b61796 | 2010-08-24 09:02:58 +0100 | [diff] [blame] | 2631 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
Jani Nikula | 9c4b0a6 | 2013-08-30 19:40:30 +0300 | [diff] [blame] | 2632 | static inline int |
| 2633 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) |
| 2634 | { |
| 2635 | return 0; |
| 2636 | } |
Jani Nikula | ecbc5cf | 2013-08-30 19:40:31 +0300 | [diff] [blame] | 2637 | static inline int |
| 2638 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) |
| 2639 | { |
| 2640 | return 0; |
| 2641 | } |
Len Brown | 65e082c | 2008-10-24 17:18:10 -0400 | [diff] [blame] | 2642 | #endif |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 2643 | |
Jesse Barnes | 723bfd7 | 2010-10-07 16:01:13 -0700 | [diff] [blame] | 2644 | /* intel_acpi.c */ |
| 2645 | #ifdef CONFIG_ACPI |
| 2646 | extern void intel_register_dsm_handler(void); |
| 2647 | extern void intel_unregister_dsm_handler(void); |
| 2648 | #else |
| 2649 | static inline void intel_register_dsm_handler(void) { return; } |
| 2650 | static inline void intel_unregister_dsm_handler(void) { return; } |
| 2651 | #endif /* CONFIG_ACPI */ |
| 2652 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2653 | /* modesetting */ |
Daniel Vetter | f817586 | 2012-04-10 15:50:11 +0200 | [diff] [blame] | 2654 | extern void intel_modeset_init_hw(struct drm_device *dev); |
Imre Deak | 7d708ee | 2013-04-17 14:04:50 +0300 | [diff] [blame] | 2655 | extern void intel_modeset_suspend_hw(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2656 | extern void intel_modeset_init(struct drm_device *dev); |
Chris Wilson | 2c7111d | 2011-03-29 10:40:27 +0100 | [diff] [blame] | 2657 | extern void intel_modeset_gem_init(struct drm_device *dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2658 | extern void intel_modeset_cleanup(struct drm_device *dev); |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 2659 | extern void intel_connector_unregister(struct intel_connector *); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 2660 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
Daniel Vetter | 45e2b5f | 2012-11-23 18:16:34 +0100 | [diff] [blame] | 2661 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
| 2662 | bool force_restore); |
Daniel Vetter | 44cec74 | 2013-01-25 17:53:21 +0100 | [diff] [blame] | 2663 | extern void i915_redisable_vga(struct drm_device *dev); |
Imre Deak | 0409875 | 2014-02-18 00:02:16 +0200 | [diff] [blame] | 2664 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
Adam Jackson | ee5382a | 2010-04-23 11:17:39 -0400 | [diff] [blame] | 2665 | extern bool intel_fbc_enabled(struct drm_device *dev); |
Chris Wilson | 43a9539 | 2011-07-08 12:22:36 +0100 | [diff] [blame] | 2666 | extern void intel_disable_fbc(struct drm_device *dev); |
Jesse Barnes | 7648fa9 | 2010-05-20 14:28:11 -0700 | [diff] [blame] | 2667 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
Paulo Zanoni | dde86e2 | 2012-12-01 12:04:25 -0200 | [diff] [blame] | 2668 | extern void intel_init_pch_refclk(struct drm_device *dev); |
Jesse Barnes | 3b8d8d9 | 2010-12-17 14:19:02 -0800 | [diff] [blame] | 2669 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 2670 | extern void valleyview_set_rps(struct drm_device *dev, u8 val); |
| 2671 | extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); |
| 2672 | extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2673 | extern void intel_detect_pch(struct drm_device *dev); |
| 2674 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); |
Ben Widawsky | 0136db58 | 2012-04-10 21:17:01 -0700 | [diff] [blame] | 2675 | extern int intel_enable_rc6(const struct drm_device *dev); |
Zhenyu Wang | 3bad078 | 2010-04-07 16:15:53 +0800 | [diff] [blame] | 2676 | |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 2677 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
Ben Widawsky | c0c7bab | 2012-07-12 11:01:05 -0700 | [diff] [blame] | 2678 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
| 2679 | struct drm_file *file); |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 2680 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
| 2681 | struct drm_file *file); |
Jesse Barnes | 575155a | 2012-03-28 13:39:37 -0700 | [diff] [blame] | 2682 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 2683 | /* overlay */ |
| 2684 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 2685 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
| 2686 | struct intel_overlay_error_state *error); |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 2687 | |
| 2688 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 2689 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
Chris Wilson | c4a1d9e | 2010-11-21 13:12:35 +0000 | [diff] [blame] | 2690 | struct drm_device *dev, |
| 2691 | struct intel_display_error_state *error); |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 2692 | |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 2693 | /* On SNB platform, before reading ring registers forcewake bit |
| 2694 | * must be set to prevent GT core from power down and stale values being |
| 2695 | * returned. |
| 2696 | */ |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 2697 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); |
| 2698 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); |
Paulo Zanoni | e998c40 | 2014-02-21 13:52:26 -0300 | [diff] [blame] | 2699 | void assert_force_wake_inactive(struct drm_i915_private *dev_priv); |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 2700 | |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 2701 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
| 2702 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 2703 | |
| 2704 | /* intel_sideband.c */ |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 2705 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); |
| 2706 | void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); |
| 2707 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
Jani Nikula | e9f882a | 2013-08-27 15:12:14 +0300 | [diff] [blame] | 2708 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
| 2709 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
| 2710 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
| 2711 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
| 2712 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); |
| 2713 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
Jesse Barnes | f341915 | 2013-11-04 11:52:44 -0800 | [diff] [blame] | 2714 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
| 2715 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
Jani Nikula | e9f882a | 2013-08-27 15:12:14 +0300 | [diff] [blame] | 2716 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
| 2717 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 2718 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
| 2719 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); |
Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame] | 2720 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
| 2721 | enum intel_sbi_destination destination); |
| 2722 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, |
| 2723 | enum intel_sbi_destination destination); |
Shobhit Kumar | e9fe51c | 2013-12-10 12:14:55 +0530 | [diff] [blame] | 2724 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
| 2725 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 2726 | |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 2727 | int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); |
| 2728 | int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 2729 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 2730 | void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); |
| 2731 | void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); |
| 2732 | |
| 2733 | #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ |
| 2734 | (((reg) >= 0x2000 && (reg) < 0x4000) ||\ |
| 2735 | ((reg) >= 0x5000 && (reg) < 0x8000) ||\ |
| 2736 | ((reg) >= 0xB000 && (reg) < 0x12000) ||\ |
| 2737 | ((reg) >= 0x2E000 && (reg) < 0x30000)) |
| 2738 | |
| 2739 | #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\ |
| 2740 | (((reg) >= 0x12000 && (reg) < 0x14000) ||\ |
| 2741 | ((reg) >= 0x22000 && (reg) < 0x24000) ||\ |
| 2742 | ((reg) >= 0x30000 && (reg) < 0x40000)) |
| 2743 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 2744 | #define FORCEWAKE_RENDER (1 << 0) |
| 2745 | #define FORCEWAKE_MEDIA (1 << 1) |
| 2746 | #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA) |
| 2747 | |
| 2748 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 2749 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
| 2750 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 2751 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 2752 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) |
| 2753 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) |
| 2754 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) |
| 2755 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 2756 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 2757 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) |
| 2758 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) |
| 2759 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) |
| 2760 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) |
Keith Packard | 5f75377 | 2010-11-22 09:24:22 +0000 | [diff] [blame] | 2761 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 2762 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
| 2763 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 2764 | |
| 2765 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
| 2766 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) |
| 2767 | |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 2768 | /* "Broadcast RGB" property */ |
| 2769 | #define INTEL_BROADCAST_RGB_AUTO 0 |
| 2770 | #define INTEL_BROADCAST_RGB_FULL 1 |
| 2771 | #define INTEL_BROADCAST_RGB_LIMITED 2 |
Yuanhan Liu | ba4f01a | 2010-11-08 17:09:41 +0800 | [diff] [blame] | 2772 | |
Ville Syrjälä | 766aa1c | 2013-01-25 21:44:46 +0200 | [diff] [blame] | 2773 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
| 2774 | { |
| 2775 | if (HAS_PCH_SPLIT(dev)) |
| 2776 | return CPU_VGACNTRL; |
| 2777 | else if (IS_VALLEYVIEW(dev)) |
| 2778 | return VLV_VGACNTRL; |
| 2779 | else |
| 2780 | return VGACNTRL; |
| 2781 | } |
| 2782 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 2783 | static inline void __user *to_user_ptr(u64 address) |
| 2784 | { |
| 2785 | return (void __user *)(uintptr_t)address; |
| 2786 | } |
| 2787 | |
Imre Deak | df97729 | 2013-05-21 20:03:17 +0300 | [diff] [blame] | 2788 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
| 2789 | { |
| 2790 | unsigned long j = msecs_to_jiffies(m); |
| 2791 | |
| 2792 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
| 2793 | } |
| 2794 | |
| 2795 | static inline unsigned long |
| 2796 | timespec_to_jiffies_timeout(const struct timespec *value) |
| 2797 | { |
| 2798 | unsigned long j = timespec_to_jiffies(value); |
| 2799 | |
| 2800 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); |
| 2801 | } |
| 2802 | |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 2803 | /* |
| 2804 | * If you need to wait X milliseconds between events A and B, but event B |
| 2805 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of |
| 2806 | * when event A happened, then just before event B you call this function and |
| 2807 | * pass the timestamp as the first argument, and X as the second argument. |
| 2808 | */ |
| 2809 | static inline void |
| 2810 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) |
| 2811 | { |
Imre Deak | ec5e0cf | 2014-01-29 13:25:40 +0200 | [diff] [blame] | 2812 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 2813 | |
| 2814 | /* |
| 2815 | * Don't re-read the value of "jiffies" every time since it may change |
| 2816 | * behind our back and break the math. |
| 2817 | */ |
| 2818 | tmp_jiffies = jiffies; |
| 2819 | target_jiffies = timestamp_jiffies + |
| 2820 | msecs_to_jiffies_timeout(to_wait_ms); |
| 2821 | |
| 2822 | if (time_after(target_jiffies, tmp_jiffies)) { |
Imre Deak | ec5e0cf | 2014-01-29 13:25:40 +0200 | [diff] [blame] | 2823 | remaining_jiffies = target_jiffies - tmp_jiffies; |
| 2824 | while (remaining_jiffies) |
| 2825 | remaining_jiffies = |
| 2826 | schedule_timeout_uninterruptible(remaining_jiffies); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 2827 | } |
| 2828 | } |
| 2829 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2830 | #endif |