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Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001/* bnx2x_hsi.h: Broadcom Everest network driver.
2 *
Eliezer Tamirf1410642008-02-28 11:51:50 -08003 * Copyright (c) 2007-2008 Broadcom Corporation
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10
Eliezer Tamirf1410642008-02-28 11:51:50 -080011#define PORT_0 0
12#define PORT_1 1
13#define PORT_MAX 2
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020014
15/****************************************************************************
16 * Shared HW configuration *
17 ****************************************************************************/
18struct shared_hw_cfg { /* NVRAM Offset */
19 /* Up to 16 bytes of NULL-terminated string */
20 u8 part_num[16]; /* 0x104 */
21
22 u32 config; /* 0x114 */
23#define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
24#define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
25#define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
26#define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
27#define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
28
29#define SHARED_HW_CFG_PORT_SWAP 0x00000004
30
31#define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
32
33#define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
34#define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
35 /* Whatever MFW found in NVM
36 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
37#define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
38#define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
39#define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
40#define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
41 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
42 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
43#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
44 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
45 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
46#define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
47 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
48 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
49#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
50
51#define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
52#define SHARED_HW_CFG_LED_MODE_SHIFT 16
53#define SHARED_HW_CFG_LED_MAC1 0x00000000
54#define SHARED_HW_CFG_LED_PHY1 0x00010000
55#define SHARED_HW_CFG_LED_PHY2 0x00020000
56#define SHARED_HW_CFG_LED_PHY3 0x00030000
57#define SHARED_HW_CFG_LED_MAC2 0x00040000
58#define SHARED_HW_CFG_LED_PHY4 0x00050000
59#define SHARED_HW_CFG_LED_PHY5 0x00060000
60#define SHARED_HW_CFG_LED_PHY6 0x00070000
61#define SHARED_HW_CFG_LED_MAC3 0x00080000
62#define SHARED_HW_CFG_LED_PHY7 0x00090000
63#define SHARED_HW_CFG_LED_PHY9 0x000a0000
64#define SHARED_HW_CFG_LED_PHY11 0x000b0000
65#define SHARED_HW_CFG_LED_MAC4 0x000c0000
66#define SHARED_HW_CFG_LED_PHY8 0x000d0000
67
68#define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
69#define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
70#define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
71#define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
72#define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
73#define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
74#define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
75#define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
76
77 u32 config2; /* 0x118 */
78 /* one time auto detect grace period (in sec) */
79#define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
80#define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
81
82#define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
83
84 /* The default value for the core clock is 250MHz and it is
85 achieved by setting the clock change to 4 */
86#define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
87#define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
88
89#define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
90#define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
91
Eliezer Tamirf1410642008-02-28 11:51:50 -080092#define SHARED_HW_CFG_HIDE_PORT1 0x00002000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +020093
94 u32 power_dissipated; /* 0x11c */
95#define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
96#define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
97
98#define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
99#define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
100#define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
101#define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
102#define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
103#define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
104
105 u32 ump_nc_si_config; /* 0x120 */
106#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
107#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
108#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
109#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
110#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
111#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
112
113#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
114#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
115
116#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
117#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
118#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
119#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
120
121 u32 board; /* 0x124 */
122#define SHARED_HW_CFG_BOARD_TYPE_MASK 0x0000ffff
123#define SHARED_HW_CFG_BOARD_TYPE_SHIFT 0
124#define SHARED_HW_CFG_BOARD_TYPE_NONE 0x00000000
125#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1000 0x00000001
126#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1001 0x00000002
127#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G 0x00000003
128#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1004G 0x00000004
129#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1007G 0x00000005
130#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1015G 0x00000006
131#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1020G 0x00000007
132#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008
Eliezer Tamirf1410642008-02-28 11:51:50 -0800133#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G 0x00000009
134#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G 0x0000000a
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700135#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1023G 0x0000000b
136#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1033G 0x0000000c
137#define SHARED_HW_CFG_BOARD_TYPE_BCM957711T1101 0x0000000d
138#define SHARED_HW_CFG_BOARD_TYPE_BCM957711ET1201 0x0000000e
139#define SHARED_HW_CFG_BOARD_TYPE_BCM957711A1133G 0x0000000f
140#define SHARED_HW_CFG_BOARD_TYPE_BCM957711EA1233G 0x00000010
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200141
142#define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000
143#define SHARED_HW_CFG_BOARD_VER_SHIFT 16
144#define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0xf0000000
145#define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 28
146#define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0x0f000000
147#define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 24
148#define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
149#define SHARED_HW_CFG_BOARD_REV_SHIFT 16
150
151 u32 reserved; /* 0x128 */
152
153};
154
Eliezer Tamirf1410642008-02-28 11:51:50 -0800155
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200156/****************************************************************************
157 * Port HW configuration *
158 ****************************************************************************/
Eliezer Tamirf1410642008-02-28 11:51:50 -0800159struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200160
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200161 u32 pci_id;
162#define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
163#define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
164
165 u32 pci_sub_id;
166#define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
167#define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
168
169 u32 power_dissipated;
170#define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
171#define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
172#define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
173#define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
174#define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
175#define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
176#define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
177#define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
178
179 u32 power_consumed;
180#define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
181#define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
182#define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
183#define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
184#define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
185#define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
186#define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
187#define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
188
189 u32 mac_upper;
190#define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
191#define PORT_HW_CFG_UPPERMAC_SHIFT 0
192 u32 mac_lower;
193
194 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */
195 u32 iscsi_mac_lower;
196
197 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */
198 u32 rdma_mac_lower;
199
200 u32 serdes_config;
201 /* for external PHY, or forced mode or during AN */
202#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
203#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 16
204
205#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0x0000ffff
206#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 0
207
208 u16 serdes_tx_driver_pre_emphasis[16];
209 u16 serdes_rx_driver_equalizer[16];
210
211 u32 xgxs_config_lane0;
212 u32 xgxs_config_lane1;
213 u32 xgxs_config_lane2;
214 u32 xgxs_config_lane3;
215 /* for external PHY, or forced mode or during AN */
216#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
217#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT 16
218
219#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK 0x0000ffff
220#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT 0
221
222 u16 xgxs_tx_driver_pre_emphasis_lane0[16];
223 u16 xgxs_tx_driver_pre_emphasis_lane1[16];
224 u16 xgxs_tx_driver_pre_emphasis_lane2[16];
225 u16 xgxs_tx_driver_pre_emphasis_lane3[16];
226
227 u16 xgxs_rx_driver_equalizer_lane0[16];
228 u16 xgxs_rx_driver_equalizer_lane1[16];
229 u16 xgxs_rx_driver_equalizer_lane2[16];
230 u16 xgxs_rx_driver_equalizer_lane3[16];
231
232 u32 lane_config;
233#define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
234#define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
235#define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
236#define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
237#define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
238#define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
239#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
240#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
241 /* AN and forced */
242#define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
243 /* forced only */
244#define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
245 /* forced only */
246#define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
247 /* forced only */
248#define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
249
250 u32 external_phy_config;
251#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
252#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
253#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
254#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
255#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
256
257#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
258#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
259
260#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
261#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
262#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
263#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
264#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
265#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
266#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
267#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
268#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276 0x00000600
269#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
Eliezer Tamirf1410642008-02-28 11:51:50 -0800270#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
271#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200272#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
273
274#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
275#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
276
277 u32 speed_capability_mask;
278#define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
279#define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
280#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
281#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
282#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
283#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
284#define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
285#define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
286#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
287#define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000
288#define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000
289#define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000
290#define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000
291#define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000
292#define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
293
294#define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
295#define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
296#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
297#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
298#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
299#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
300#define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
301#define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
302#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
303#define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080
304#define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100
305#define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200
306#define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400
307#define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800
308#define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
309
310 u32 reserved[2];
311
312};
313
Eliezer Tamirf1410642008-02-28 11:51:50 -0800314
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200315/****************************************************************************
316 * Shared Feature configuration *
317 ****************************************************************************/
318struct shared_feat_cfg { /* NVRAM Offset */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800319
320 u32 config; /* 0x450 */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200321#define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700322#define SHARED_FEATURE_MF_MODE_DISABLED 0x00000100
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200323
324};
325
326
327/****************************************************************************
328 * Port Feature configuration *
329 ****************************************************************************/
Eliezer Tamirf1410642008-02-28 11:51:50 -0800330struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
331
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200332 u32 config;
333#define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
334#define PORT_FEATURE_BAR1_SIZE_SHIFT 0
335#define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
336#define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
337#define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
338#define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
339#define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
340#define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
341#define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
342#define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
343#define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
344#define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
345#define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
346#define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
347#define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
348#define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
349#define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
350#define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
351#define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
352#define PORT_FEATURE_BAR2_SIZE_SHIFT 4
353#define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
354#define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
355#define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
356#define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
357#define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
358#define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
359#define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
360#define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
361#define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
362#define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
363#define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
364#define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
365#define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
366#define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
367#define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
368#define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
369#define PORT_FEATURE_EN_SIZE_MASK 0x07000000
370#define PORT_FEATURE_EN_SIZE_SHIFT 24
371#define PORT_FEATURE_WOL_ENABLED 0x01000000
372#define PORT_FEATURE_MBA_ENABLED 0x02000000
373#define PORT_FEATURE_MFW_ENABLED 0x04000000
374
375 u32 wol_config;
376 /* Default is used when driver sets to "auto" mode */
377#define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
378#define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
379#define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
380#define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
381#define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
382#define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
383#define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
384#define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
385#define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
386
387 u32 mba_config;
388#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003
389#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
390#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
391#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
392#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
393#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
394#define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
395#define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
396#define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
397#define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
398#define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
399#define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
400#define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
401#define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
402#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
403#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
404#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
405#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
406#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
407#define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
408#define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
409#define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
410#define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
411#define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
412#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
413#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
414#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
415#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
416#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
417#define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
418#define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
419#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
420#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
421#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
422#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
423#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
424#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
425#define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
426#define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
427#define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
428#define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
429#define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
430#define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
431#define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
432#define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
433#define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
434#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
435#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000
436#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000
437#define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000
438#define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000
439#define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000
440#define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000
441#define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000
442
443 u32 bmc_config;
444#define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
445#define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
446
447 u32 mba_vlan_cfg;
448#define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
449#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
450#define PORT_FEATURE_MBA_VLAN_EN 0x00010000
451
452 u32 resource_cfg;
453#define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
454#define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
455#define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
456#define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
457#define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
458
459 u32 smbus_config;
460 /* Obsolete */
461#define PORT_FEATURE_SMBUS_EN 0x00000001
462#define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
463#define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
464
Eliezer Tamirf1410642008-02-28 11:51:50 -0800465 u32 reserved1;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200466
467 u32 link_config; /* Used as HW defaults for the driver */
468#define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
469#define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
470 /* (forced) low speed switch (< 10G) */
471#define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
472 /* (forced) high speed switch (>= 10G) */
473#define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
474#define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
475#define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
476
477#define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
478#define PORT_FEATURE_LINK_SPEED_SHIFT 16
479#define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
480#define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
481#define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
482#define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
483#define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
484#define PORT_FEATURE_LINK_SPEED_1G 0x00050000
485#define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
486#define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
487#define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000
488#define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000
489#define PORT_FEATURE_LINK_SPEED_12G 0x000a0000
490#define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000
491#define PORT_FEATURE_LINK_SPEED_13G 0x000c0000
492#define PORT_FEATURE_LINK_SPEED_15G 0x000d0000
493#define PORT_FEATURE_LINK_SPEED_16G 0x000e0000
494
495#define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
496#define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
497#define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
498#define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
499#define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
500#define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
501#define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
502
503 /* The default for MCP link configuration,
504 uses the same defines as link_config */
505 u32 mfw_wol_link_cfg;
506
507 u32 reserved[19];
508
509};
510
511
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700512/****************************************************************************
513 * Device Information *
514 ****************************************************************************/
515struct dev_info { /* size */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800516
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700517 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800518
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700519 struct shared_hw_cfg shared_hw_config; /* 40 */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800520
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700521 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800522
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700523 struct shared_feat_cfg shared_feature_config; /* 4 */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800524
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700525 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800526
527};
528
529
530#define FUNC_0 0
531#define FUNC_1 1
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700532#define FUNC_2 2
533#define FUNC_3 3
534#define FUNC_4 4
535#define FUNC_5 5
536#define FUNC_6 6
537#define FUNC_7 7
Eliezer Tamirf1410642008-02-28 11:51:50 -0800538#define E1_FUNC_MAX 2
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700539#define E1H_FUNC_MAX 8
540
541#define VN_0 0
542#define VN_1 1
543#define VN_2 2
544#define VN_3 3
545#define E1VN_MAX 1
546#define E1HVN_MAX 4
Eliezer Tamirf1410642008-02-28 11:51:50 -0800547
548
549/* This value (in milliseconds) determines the frequency of the driver
550 * issuing the PULSE message code. The firmware monitors this periodic
551 * pulse to determine when to switch to an OS-absent mode. */
552#define DRV_PULSE_PERIOD_MS 250
553
554/* This value (in milliseconds) determines how long the driver should
555 * wait for an acknowledgement from the firmware before timing out. Once
556 * the firmware has timed out, the driver will assume there is no firmware
557 * running and there won't be any firmware-driver synchronization during a
558 * driver reset. */
559#define FW_ACK_TIME_OUT_MS 5000
560
561#define FW_ACK_POLL_TIME_MS 1
562
563#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
564
565/* LED Blink rate that will achieve ~15.9Hz */
566#define LED_BLINK_RATE_VAL 480
567
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200568/****************************************************************************
Eliezer Tamirf1410642008-02-28 11:51:50 -0800569 * Driver <-> FW Mailbox *
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200570 ****************************************************************************/
Eliezer Tamirf1410642008-02-28 11:51:50 -0800571struct drv_port_mb {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200572
Eliezer Tamirf1410642008-02-28 11:51:50 -0800573 u32 link_status;
574 /* Driver should update this field on any link change event */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200575
Eliezer Tamirf1410642008-02-28 11:51:50 -0800576#define LINK_STATUS_LINK_FLAG_MASK 0x00000001
577#define LINK_STATUS_LINK_UP 0x00000001
578#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
579#define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
580#define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
581#define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
582#define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
583#define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
584#define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
585#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
586#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
587#define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
588#define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
589#define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
590#define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
591#define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
592#define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
593#define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1)
594#define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1)
595#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1)
596#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1)
597#define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1)
598#define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1)
599#define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1)
600#define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1)
601#define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1)
602#define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200603
Eliezer Tamirf1410642008-02-28 11:51:50 -0800604#define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
605#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200606
Eliezer Tamirf1410642008-02-28 11:51:50 -0800607#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
608#define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
609#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200610
Eliezer Tamirf1410642008-02-28 11:51:50 -0800611#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
612#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
613#define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
614#define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
615#define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
616#define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
617#define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
618
619#define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
620#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
621
622#define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
623#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
624
625#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
626#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
627#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
628#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
629#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
630
631#define LINK_STATUS_SERDES_LINK 0x00100000
632
633#define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
634#define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
635#define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
636#define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000
637#define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000
638#define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000
639#define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
640#define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
641
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700642 u32 port_stx;
643
644 u32 reserved[2];
Eliezer Tamirf1410642008-02-28 11:51:50 -0800645
646};
647
648
649struct drv_func_mb {
650
651 u32 drv_mb_header;
652#define DRV_MSG_CODE_MASK 0xffff0000
653#define DRV_MSG_CODE_LOAD_REQ 0x10000000
654#define DRV_MSG_CODE_LOAD_DONE 0x11000000
655#define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
656#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
657#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
658#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
659#define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
660#define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
661#define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
662#define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
663#define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
664#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
665#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
666
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700667#define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
668#define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
669#define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
670#define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
671
Eliezer Tamirf1410642008-02-28 11:51:50 -0800672#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
673
674 u32 drv_mb_param;
675
676 u32 fw_mb_header;
677#define FW_MSG_CODE_MASK 0xffff0000
678#define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
679#define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
680#define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
681#define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
682#define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
683#define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
684#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
685#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
686#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
687#define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
688#define FW_MSG_CODE_DIAG_REFUSE 0x50200000
689#define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
690#define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
691#define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
692#define FW_MSG_CODE_GET_KEY_DONE 0x80100000
693#define FW_MSG_CODE_NO_KEY 0x80f00000
694#define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
695#define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
696#define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
697#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
698#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
699#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
700
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700701#define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
702#define FW_MSG_CODE_LIC_RESPONSE 0xff020000
703#define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
704#define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
705
Eliezer Tamirf1410642008-02-28 11:51:50 -0800706#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
707
708 u32 fw_mb_param;
709
710 u32 drv_pulse_mb;
711#define DRV_PULSE_SEQ_MASK 0x00007fff
712#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
713 /* The system time is in the format of
714 * (year-2001)*12*32 + month*32 + day. */
715#define DRV_PULSE_ALWAYS_ALIVE 0x00008000
716 /* Indicate to the firmware not to go into the
717 * OS-absent when it is not getting driver pulse.
718 * This is used for debugging as well for PXE(MBA). */
719
720 u32 mcp_pulse_mb;
721#define MCP_PULSE_SEQ_MASK 0x00007fff
722#define MCP_PULSE_ALWAYS_ALIVE 0x00008000
723 /* Indicates to the driver not to assert due to lack
724 * of MCP response */
725#define MCP_EVENT_MASK 0xffff0000
726#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
727
728 u32 iscsi_boot_signature;
729 u32 iscsi_boot_block_offset;
730
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700731 u32 drv_status;
732#define DRV_STATUS_PMF 0x00000001
733
734 u32 virt_mac_upper;
735#define VIRT_MAC_SIGN_MASK 0xffff0000
736#define VIRT_MAC_SIGNATURE 0x564d0000
737 u32 virt_mac_lower;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200738
739};
740
741
742/****************************************************************************
743 * Management firmware state *
744 ****************************************************************************/
Eliezer Tamirf1410642008-02-28 11:51:50 -0800745/* Allocate 440 bytes for management firmware */
746#define MGMTFW_STATE_WORD_SIZE 110
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200747
748struct mgmtfw_state {
749 u32 opaque[MGMTFW_STATE_WORD_SIZE];
750};
751
752
753/****************************************************************************
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700754 * Multi-Function configuration *
755 ****************************************************************************/
756struct shared_mf_cfg {
757
758 u32 clp_mb;
759#define SHARED_MF_CLP_SET_DEFAULT 0x00000000
760 /* set by CLP */
761#define SHARED_MF_CLP_EXIT 0x00000001
762 /* set by MCP */
763#define SHARED_MF_CLP_EXIT_DONE 0x00010000
764
765};
766
767struct port_mf_cfg {
768
769 u32 dynamic_cfg; /* device control channel */
770#define PORT_MF_CFG_OUTER_VLAN_TAG_MASK 0x0000ffff
771#define PORT_MF_CFG_OUTER_VLAN_TAG_SHIFT 0
772#define PORT_MF_CFG_DYNAMIC_CFG_ENABLED 0x00010000
773#define PORT_MF_CFG_DYNAMIC_CFG_DEFAULT 0x00000000
774
775 u32 reserved[3];
776
777};
778
779struct func_mf_cfg {
780
781 u32 config;
782 /* E/R/I/D */
783 /* function 0 of each port cannot be hidden */
784#define FUNC_MF_CFG_FUNC_HIDE 0x00000001
785
786#define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007
787#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
788#define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
789#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
790#define FUNC_MF_CFG_PROTOCOL_DEFAULT\
791 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
792
793#define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
794
795 /* PRI */
796 /* 0 - low priority, 3 - high priority */
797#define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
798#define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
799#define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
800
801 /* MINBW, MAXBW */
802 /* value range - 0..100, increments in 100Mbps */
803#define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
804#define FUNC_MF_CFG_MIN_BW_SHIFT 16
805#define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
806#define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
807#define FUNC_MF_CFG_MAX_BW_SHIFT 24
808#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
809
810 u32 mac_upper; /* MAC */
811#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
812#define FUNC_MF_CFG_UPPERMAC_SHIFT 0
813#define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
814 u32 mac_lower;
815#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
816
817 u32 e1hov_tag; /* VNI */
818#define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
819#define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
820#define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
821
822 u32 reserved[2];
823
824};
825
826struct mf_cfg {
827
828 struct shared_mf_cfg shared_mf_config;
829 struct port_mf_cfg port_mf_config[PORT_MAX];
830#if defined(b710)
831 struct func_mf_cfg func_mf_config[E1_FUNC_MAX];
832#else
833 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
834#endif
835
836};
837
838
839/****************************************************************************
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200840 * Shared Memory Region *
841 ****************************************************************************/
842struct shmem_region { /* SharedMem Offset (size) */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800843
844 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
845#define SHR_MEM_FORMAT_REV_ID ('A'<<24)
846#define SHR_MEM_FORMAT_REV_MASK 0xff000000
847 /* validity bits */
848#define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
849#define SHR_MEM_VALIDITY_MB 0x00200000
850#define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
851#define SHR_MEM_VALIDITY_RESERVED 0x00000007
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200852 /* One licensing bit should be set */
853#define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
854#define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
855#define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
856#define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
Eliezer Tamirf1410642008-02-28 11:51:50 -0800857 /* Active MFW */
858#define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
859#define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
860#define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
861#define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
862#define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
863#define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200864
Eliezer Tamirf1410642008-02-28 11:51:50 -0800865 struct dev_info dev_info; /* 0x8 (0x438) */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200866
Eliezer Tamirf1410642008-02-28 11:51:50 -0800867 u8 reserved[52*PORT_MAX];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200868
869 /* FW information (for internal FW use) */
Eliezer Tamirf1410642008-02-28 11:51:50 -0800870 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
871 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200872
Eliezer Tamirf1410642008-02-28 11:51:50 -0800873 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
Eilon Greensteinad8d3942008-06-23 20:29:02 -0700874 struct drv_func_mb func_mb[E1H_FUNC_MAX];
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700875
876 struct mf_cfg mf_cfg;
Eliezer Tamirf1410642008-02-28 11:51:50 -0800877
878}; /* 0x6dc */
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200879
880
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700881
882
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200883#define BCM_5710_FW_MAJOR_VERSION 4
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700884#define BCM_5710_FW_MINOR_VERSION 5
885#define BCM_5710_FW_REVISION_VERSION 1
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200886#define BCM_5710_FW_COMPILE_FLAGS 1
887
888
889/*
890 * attention bits
891 */
892struct atten_def_status_block {
893 u32 attn_bits;
894 u32 attn_bits_ack;
895#if defined(__BIG_ENDIAN)
896 u16 attn_bits_index;
897 u8 reserved0;
898 u8 status_block_id;
899#elif defined(__LITTLE_ENDIAN)
900 u8 status_block_id;
901 u8 reserved0;
902 u16 attn_bits_index;
903#endif
904 u32 reserved1;
905};
906
907
908/*
909 * common data for all protocols
910 */
911struct doorbell_hdr {
912 u8 header;
913#define DOORBELL_HDR_RX (0x1<<0)
914#define DOORBELL_HDR_RX_SHIFT 0
915#define DOORBELL_HDR_DB_TYPE (0x1<<1)
916#define DOORBELL_HDR_DB_TYPE_SHIFT 1
917#define DOORBELL_HDR_DPM_SIZE (0x3<<2)
918#define DOORBELL_HDR_DPM_SIZE_SHIFT 2
919#define DOORBELL_HDR_CONN_TYPE (0xF<<4)
920#define DOORBELL_HDR_CONN_TYPE_SHIFT 4
921};
922
923/*
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700924 * doorbell message sent to the chip
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200925 */
926struct doorbell {
927#if defined(__BIG_ENDIAN)
928 u16 zero_fill2;
929 u8 zero_fill1;
930 struct doorbell_hdr header;
931#elif defined(__LITTLE_ENDIAN)
932 struct doorbell_hdr header;
933 u8 zero_fill1;
934 u16 zero_fill2;
935#endif
936};
937
938
939/*
940 * IGU driver acknowlegement register
941 */
942struct igu_ack_register {
943#if defined(__BIG_ENDIAN)
944 u16 sb_id_and_flags;
945#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
946#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
947#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
948#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
949#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
950#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
951#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
952#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
953#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
954#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
955 u16 status_block_index;
956#elif defined(__LITTLE_ENDIAN)
957 u16 status_block_index;
958 u16 sb_id_and_flags;
959#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
960#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
961#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
962#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
963#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
964#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
965#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
966#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
967#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
968#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
969#endif
970};
971
972
973/*
974 * Parser parsing flags field
975 */
976struct parsing_flags {
977 u16 flags;
978#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
979#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
Eilon Greenstein34f80b02008-06-23 20:33:01 -0700980#define PARSING_FLAGS_VLAN (0x1<<1)
981#define PARSING_FLAGS_VLAN_SHIFT 1
982#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
983#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +0200984#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
985#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
986#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
987#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
988#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
989#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
990#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
991#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
992#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
993#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
994#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
995#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
996#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
997#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
998#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
999#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
1000#define PARSING_FLAGS_LLC_SNAP (0x1<<13)
1001#define PARSING_FLAGS_LLC_SNAP_SHIFT 13
1002#define PARSING_FLAGS_RESERVED0 (0x3<<14)
1003#define PARSING_FLAGS_RESERVED0_SHIFT 14
1004};
1005
1006
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001007struct regpair {
1008 u32 lo;
1009 u32 hi;
1010};
1011
1012
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001013/*
1014 * dmae command structure
1015 */
1016struct dmae_command {
1017 u32 opcode;
1018#define DMAE_COMMAND_SRC (0x1<<0)
1019#define DMAE_COMMAND_SRC_SHIFT 0
1020#define DMAE_COMMAND_DST (0x3<<1)
1021#define DMAE_COMMAND_DST_SHIFT 1
1022#define DMAE_COMMAND_C_DST (0x1<<3)
1023#define DMAE_COMMAND_C_DST_SHIFT 3
1024#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
1025#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
1026#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
1027#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
1028#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
1029#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
1030#define DMAE_COMMAND_ENDIANITY (0x3<<9)
1031#define DMAE_COMMAND_ENDIANITY_SHIFT 9
1032#define DMAE_COMMAND_PORT (0x1<<11)
1033#define DMAE_COMMAND_PORT_SHIFT 11
1034#define DMAE_COMMAND_CRC_RESET (0x1<<12)
1035#define DMAE_COMMAND_CRC_RESET_SHIFT 12
1036#define DMAE_COMMAND_SRC_RESET (0x1<<13)
1037#define DMAE_COMMAND_SRC_RESET_SHIFT 13
1038#define DMAE_COMMAND_DST_RESET (0x1<<14)
1039#define DMAE_COMMAND_DST_RESET_SHIFT 14
Eilon Greensteinad8d3942008-06-23 20:29:02 -07001040#define DMAE_COMMAND_E1HVN (0x3<<15)
1041#define DMAE_COMMAND_E1HVN_SHIFT 15
1042#define DMAE_COMMAND_RESERVED0 (0x7FFF<<17)
1043#define DMAE_COMMAND_RESERVED0_SHIFT 17
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001044 u32 src_addr_lo;
1045 u32 src_addr_hi;
1046 u32 dst_addr_lo;
1047 u32 dst_addr_hi;
1048#if defined(__BIG_ENDIAN)
1049 u16 reserved1;
1050 u16 len;
1051#elif defined(__LITTLE_ENDIAN)
1052 u16 len;
1053 u16 reserved1;
1054#endif
1055 u32 comp_addr_lo;
1056 u32 comp_addr_hi;
1057 u32 comp_val;
1058 u32 crc32;
1059 u32 crc32_c;
1060#if defined(__BIG_ENDIAN)
1061 u16 crc16_c;
1062 u16 crc16;
1063#elif defined(__LITTLE_ENDIAN)
1064 u16 crc16;
1065 u16 crc16_c;
1066#endif
1067#if defined(__BIG_ENDIAN)
1068 u16 reserved2;
1069 u16 crc_t10;
1070#elif defined(__LITTLE_ENDIAN)
1071 u16 crc_t10;
1072 u16 reserved2;
1073#endif
1074#if defined(__BIG_ENDIAN)
1075 u16 xsum8;
1076 u16 xsum16;
1077#elif defined(__LITTLE_ENDIAN)
1078 u16 xsum16;
1079 u16 xsum8;
1080#endif
1081};
1082
1083
1084struct double_regpair {
1085 u32 regpair0_lo;
1086 u32 regpair0_hi;
1087 u32 regpair1_lo;
1088 u32 regpair1_hi;
1089};
1090
1091
1092/*
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001093 * The eth storm context of Ustorm (configuration part)
1094 */
1095struct ustorm_eth_st_context_config {
1096#if defined(__BIG_ENDIAN)
1097 u8 flags;
1098#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1099#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1100#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1101#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1102#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1103#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1104#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1105#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1106#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
1107#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
1108 u8 status_block_id;
1109 u8 clientId;
1110 u8 sb_index_numbers;
1111#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1112#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1113#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1114#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1115#elif defined(__LITTLE_ENDIAN)
1116 u8 sb_index_numbers;
1117#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF<<0)
1118#define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1119#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF<<4)
1120#define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1121 u8 clientId;
1122 u8 status_block_id;
1123 u8 flags;
1124#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1<<0)
1125#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1126#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1<<1)
1127#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1128#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1<<2)
1129#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1130#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING (0x1<<3)
1131#define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING_SHIFT 3
1132#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF<<4)
1133#define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
1134#endif
1135#if defined(__BIG_ENDIAN)
1136 u16 bd_buff_size;
1137 u16 mc_alignment_size;
1138#elif defined(__LITTLE_ENDIAN)
1139 u16 mc_alignment_size;
1140 u16 bd_buff_size;
1141#endif
1142#if defined(__BIG_ENDIAN)
1143 u8 __local_sge_prod;
1144 u8 __local_bd_prod;
1145 u16 sge_buff_size;
1146#elif defined(__LITTLE_ENDIAN)
1147 u16 sge_buff_size;
1148 u8 __local_bd_prod;
1149 u8 __local_sge_prod;
1150#endif
1151#if defined(__BIG_ENDIAN)
1152 u16 __bd_cons;
1153 u16 __sge_cons;
1154#elif defined(__LITTLE_ENDIAN)
1155 u16 __sge_cons;
1156 u16 __bd_cons;
1157#endif
1158 u32 bd_page_base_lo;
1159 u32 bd_page_base_hi;
1160 u32 sge_page_base_lo;
1161 u32 sge_page_base_hi;
1162};
1163
1164/*
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001165 * The eth Rx Buffer Descriptor
1166 */
1167struct eth_rx_bd {
1168 u32 addr_lo;
1169 u32 addr_hi;
1170};
1171
1172/*
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001173 * The eth Rx SGE Descriptor
1174 */
1175struct eth_rx_sge {
1176 u32 addr_lo;
1177 u32 addr_hi;
1178};
1179
1180/*
1181 * Local BDs and SGEs rings (in ETH)
1182 */
1183struct eth_local_rx_rings {
1184 struct eth_rx_bd __local_bd_ring[16];
1185 struct eth_rx_sge __local_sge_ring[12];
1186};
1187
1188/*
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001189 * The eth storm context of Ustorm
1190 */
1191struct ustorm_eth_st_context {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001192 struct ustorm_eth_st_context_config common;
1193 struct eth_local_rx_rings __rings;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001194};
1195
1196/*
1197 * The eth storm context of Tstorm
1198 */
1199struct tstorm_eth_st_context {
1200 u32 __reserved0[28];
1201};
1202
1203/*
1204 * The eth aggregative context section of Xstorm
1205 */
1206struct xstorm_eth_extra_ag_context_section {
1207#if defined(__BIG_ENDIAN)
1208 u8 __tcp_agg_vars1;
1209 u8 __reserved50;
1210 u16 __mss;
1211#elif defined(__LITTLE_ENDIAN)
1212 u16 __mss;
1213 u8 __reserved50;
1214 u8 __tcp_agg_vars1;
1215#endif
1216 u32 __snd_nxt;
1217 u32 __tx_wnd;
1218 u32 __snd_una;
1219 u32 __reserved53;
1220#if defined(__BIG_ENDIAN)
1221 u8 __agg_val8_th;
1222 u8 __agg_val8;
1223 u16 __tcp_agg_vars2;
1224#elif defined(__LITTLE_ENDIAN)
1225 u16 __tcp_agg_vars2;
1226 u8 __agg_val8;
1227 u8 __agg_val8_th;
1228#endif
1229 u32 __reserved58;
1230 u32 __reserved59;
1231 u32 __reserved60;
1232 u32 __reserved61;
1233#if defined(__BIG_ENDIAN)
1234 u16 __agg_val7_th;
1235 u16 __agg_val7;
1236#elif defined(__LITTLE_ENDIAN)
1237 u16 __agg_val7;
1238 u16 __agg_val7_th;
1239#endif
1240#if defined(__BIG_ENDIAN)
1241 u8 __tcp_agg_vars5;
1242 u8 __tcp_agg_vars4;
1243 u8 __tcp_agg_vars3;
1244 u8 __reserved62;
1245#elif defined(__LITTLE_ENDIAN)
1246 u8 __reserved62;
1247 u8 __tcp_agg_vars3;
1248 u8 __tcp_agg_vars4;
1249 u8 __tcp_agg_vars5;
1250#endif
1251 u32 __tcp_agg_vars6;
1252#if defined(__BIG_ENDIAN)
1253 u16 __agg_misc6;
1254 u16 __tcp_agg_vars7;
1255#elif defined(__LITTLE_ENDIAN)
1256 u16 __tcp_agg_vars7;
1257 u16 __agg_misc6;
1258#endif
1259 u32 __agg_val10;
1260 u32 __agg_val10_th;
1261#if defined(__BIG_ENDIAN)
1262 u16 __reserved3;
1263 u8 __reserved2;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001264 u8 __da_only_cnt;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001265#elif defined(__LITTLE_ENDIAN)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001266 u8 __da_only_cnt;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001267 u8 __reserved2;
1268 u16 __reserved3;
1269#endif
1270};
1271
1272/*
1273 * The eth aggregative context of Xstorm
1274 */
1275struct xstorm_eth_ag_context {
1276#if defined(__BIG_ENDIAN)
1277 u16 __bd_prod;
1278 u8 __agg_vars1;
1279 u8 __state;
1280#elif defined(__LITTLE_ENDIAN)
1281 u8 __state;
1282 u8 __agg_vars1;
1283 u16 __bd_prod;
1284#endif
1285#if defined(__BIG_ENDIAN)
1286 u8 cdu_reserved;
1287 u8 __agg_vars4;
1288 u8 __agg_vars3;
1289 u8 __agg_vars2;
1290#elif defined(__LITTLE_ENDIAN)
1291 u8 __agg_vars2;
1292 u8 __agg_vars3;
1293 u8 __agg_vars4;
1294 u8 cdu_reserved;
1295#endif
1296 u32 __more_packets_to_send;
1297#if defined(__BIG_ENDIAN)
1298 u16 __agg_vars5;
1299 u16 __agg_val4_th;
1300#elif defined(__LITTLE_ENDIAN)
1301 u16 __agg_val4_th;
1302 u16 __agg_vars5;
1303#endif
1304 struct xstorm_eth_extra_ag_context_section __extra_section;
1305#if defined(__BIG_ENDIAN)
1306 u16 __agg_vars7;
1307 u8 __agg_val3_th;
1308 u8 __agg_vars6;
1309#elif defined(__LITTLE_ENDIAN)
1310 u8 __agg_vars6;
1311 u8 __agg_val3_th;
1312 u16 __agg_vars7;
1313#endif
1314#if defined(__BIG_ENDIAN)
1315 u16 __agg_val11_th;
1316 u16 __agg_val11;
1317#elif defined(__LITTLE_ENDIAN)
1318 u16 __agg_val11;
1319 u16 __agg_val11_th;
1320#endif
1321#if defined(__BIG_ENDIAN)
1322 u8 __reserved1;
1323 u8 __agg_val6_th;
1324 u16 __agg_val9;
1325#elif defined(__LITTLE_ENDIAN)
1326 u16 __agg_val9;
1327 u8 __agg_val6_th;
1328 u8 __reserved1;
1329#endif
1330#if defined(__BIG_ENDIAN)
1331 u16 __agg_val2_th;
1332 u16 __agg_val2;
1333#elif defined(__LITTLE_ENDIAN)
1334 u16 __agg_val2;
1335 u16 __agg_val2_th;
1336#endif
1337 u32 __agg_vars8;
1338#if defined(__BIG_ENDIAN)
1339 u16 __agg_misc0;
1340 u16 __agg_val4;
1341#elif defined(__LITTLE_ENDIAN)
1342 u16 __agg_val4;
1343 u16 __agg_misc0;
1344#endif
1345#if defined(__BIG_ENDIAN)
1346 u8 __agg_val3;
1347 u8 __agg_val6;
1348 u8 __agg_val5_th;
1349 u8 __agg_val5;
1350#elif defined(__LITTLE_ENDIAN)
1351 u8 __agg_val5;
1352 u8 __agg_val5_th;
1353 u8 __agg_val6;
1354 u8 __agg_val3;
1355#endif
1356#if defined(__BIG_ENDIAN)
1357 u16 __agg_misc1;
1358 u16 __bd_ind_max_val;
1359#elif defined(__LITTLE_ENDIAN)
1360 u16 __bd_ind_max_val;
1361 u16 __agg_misc1;
1362#endif
1363 u32 __reserved57;
1364 u32 __agg_misc4;
1365 u32 __agg_misc5;
1366};
1367
1368/*
1369 * The eth aggregative context section of Tstorm
1370 */
1371struct tstorm_eth_extra_ag_context_section {
1372 u32 __agg_val1;
1373#if defined(__BIG_ENDIAN)
1374 u8 __tcp_agg_vars2;
1375 u8 __agg_val3;
1376 u16 __agg_val2;
1377#elif defined(__LITTLE_ENDIAN)
1378 u16 __agg_val2;
1379 u8 __agg_val3;
1380 u8 __tcp_agg_vars2;
1381#endif
1382#if defined(__BIG_ENDIAN)
1383 u16 __agg_val5;
1384 u8 __agg_val6;
1385 u8 __tcp_agg_vars3;
1386#elif defined(__LITTLE_ENDIAN)
1387 u8 __tcp_agg_vars3;
1388 u8 __agg_val6;
1389 u16 __agg_val5;
1390#endif
1391 u32 __reserved63;
1392 u32 __reserved64;
1393 u32 __reserved65;
1394 u32 __reserved66;
1395 u32 __reserved67;
1396 u32 __tcp_agg_vars1;
1397 u32 __reserved61;
1398 u32 __reserved62;
1399 u32 __reserved2;
1400};
1401
1402/*
1403 * The eth aggregative context of Tstorm
1404 */
1405struct tstorm_eth_ag_context {
1406#if defined(__BIG_ENDIAN)
1407 u16 __reserved54;
1408 u8 __agg_vars1;
1409 u8 __state;
1410#elif defined(__LITTLE_ENDIAN)
1411 u8 __state;
1412 u8 __agg_vars1;
1413 u16 __reserved54;
1414#endif
1415#if defined(__BIG_ENDIAN)
1416 u16 __agg_val4;
1417 u16 __agg_vars2;
1418#elif defined(__LITTLE_ENDIAN)
1419 u16 __agg_vars2;
1420 u16 __agg_val4;
1421#endif
1422 struct tstorm_eth_extra_ag_context_section __extra_section;
1423};
1424
1425/*
1426 * The eth aggregative context of Cstorm
1427 */
1428struct cstorm_eth_ag_context {
1429 u32 __agg_vars1;
1430#if defined(__BIG_ENDIAN)
1431 u8 __aux1_th;
1432 u8 __aux1_val;
1433 u16 __agg_vars2;
1434#elif defined(__LITTLE_ENDIAN)
1435 u16 __agg_vars2;
1436 u8 __aux1_val;
1437 u8 __aux1_th;
1438#endif
1439 u32 __num_of_treated_packet;
1440 u32 __last_packet_treated;
1441#if defined(__BIG_ENDIAN)
1442 u16 __reserved58;
1443 u16 __reserved57;
1444#elif defined(__LITTLE_ENDIAN)
1445 u16 __reserved57;
1446 u16 __reserved58;
1447#endif
1448#if defined(__BIG_ENDIAN)
1449 u8 __reserved62;
1450 u8 __reserved61;
1451 u8 __reserved60;
1452 u8 __reserved59;
1453#elif defined(__LITTLE_ENDIAN)
1454 u8 __reserved59;
1455 u8 __reserved60;
1456 u8 __reserved61;
1457 u8 __reserved62;
1458#endif
1459#if defined(__BIG_ENDIAN)
1460 u16 __reserved64;
1461 u16 __reserved63;
1462#elif defined(__LITTLE_ENDIAN)
1463 u16 __reserved63;
1464 u16 __reserved64;
1465#endif
1466 u32 __reserved65;
1467#if defined(__BIG_ENDIAN)
1468 u16 __agg_vars3;
1469 u16 __rq_inv_cnt;
1470#elif defined(__LITTLE_ENDIAN)
1471 u16 __rq_inv_cnt;
1472 u16 __agg_vars3;
1473#endif
1474#if defined(__BIG_ENDIAN)
1475 u16 __packet_index_th;
1476 u16 __packet_index;
1477#elif defined(__LITTLE_ENDIAN)
1478 u16 __packet_index;
1479 u16 __packet_index_th;
1480#endif
1481};
1482
1483/*
1484 * The eth aggregative context of Ustorm
1485 */
1486struct ustorm_eth_ag_context {
1487#if defined(__BIG_ENDIAN)
1488 u8 __aux_counter_flags;
1489 u8 __agg_vars2;
1490 u8 __agg_vars1;
1491 u8 __state;
1492#elif defined(__LITTLE_ENDIAN)
1493 u8 __state;
1494 u8 __agg_vars1;
1495 u8 __agg_vars2;
1496 u8 __aux_counter_flags;
1497#endif
1498#if defined(__BIG_ENDIAN)
1499 u8 cdu_usage;
1500 u8 __agg_misc2;
1501 u16 __agg_misc1;
1502#elif defined(__LITTLE_ENDIAN)
1503 u16 __agg_misc1;
1504 u8 __agg_misc2;
1505 u8 cdu_usage;
1506#endif
1507 u32 __agg_misc4;
1508#if defined(__BIG_ENDIAN)
1509 u8 __agg_val3_th;
1510 u8 __agg_val3;
1511 u16 __agg_misc3;
1512#elif defined(__LITTLE_ENDIAN)
1513 u16 __agg_misc3;
1514 u8 __agg_val3;
1515 u8 __agg_val3_th;
1516#endif
1517 u32 __agg_val1;
1518 u32 __agg_misc4_th;
1519#if defined(__BIG_ENDIAN)
1520 u16 __agg_val2_th;
1521 u16 __agg_val2;
1522#elif defined(__LITTLE_ENDIAN)
1523 u16 __agg_val2;
1524 u16 __agg_val2_th;
1525#endif
1526#if defined(__BIG_ENDIAN)
1527 u16 __reserved2;
1528 u8 __decision_rules;
1529 u8 __decision_rule_enable_bits;
1530#elif defined(__LITTLE_ENDIAN)
1531 u8 __decision_rule_enable_bits;
1532 u8 __decision_rules;
1533 u16 __reserved2;
1534#endif
1535};
1536
1537/*
1538 * Timers connection context
1539 */
1540struct timers_block_context {
1541 u32 __reserved_0;
1542 u32 __reserved_1;
1543 u32 __reserved_2;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001544 u32 flags;
1545#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
1546#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
1547#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
1548#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
1549#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
1550#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001551};
1552
1553/*
1554 * structure for easy accessability to assembler
1555 */
1556struct eth_tx_bd_flags {
1557 u8 as_bitfield;
1558#define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
1559#define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
1560#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
1561#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
1562#define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2)
1563#define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2
1564#define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
1565#define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
1566#define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
1567#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
1568#define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
1569#define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
1570#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
1571#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
1572#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
1573#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
1574};
1575
1576/*
1577 * The eth Tx Buffer Descriptor
1578 */
1579struct eth_tx_bd {
1580 u32 addr_lo;
1581 u32 addr_hi;
1582 u16 nbd;
1583 u16 nbytes;
1584 u16 vlan;
1585 struct eth_tx_bd_flags bd_flags;
1586 u8 general_data;
1587#define ETH_TX_BD_HDR_NBDS (0x3F<<0)
1588#define ETH_TX_BD_HDR_NBDS_SHIFT 0
1589#define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
1590#define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
1591};
1592
1593/*
1594 * Tx parsing BD structure for ETH,Relevant in START
1595 */
1596struct eth_tx_parse_bd {
1597 u8 global_data;
1598#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
1599#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
1600#define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
1601#define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
1602#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
1603#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
1604#define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
1605#define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
1606#define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
1607#define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
1608 u8 tcp_flags;
1609#define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
1610#define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
1611#define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
1612#define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
1613#define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
1614#define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
1615#define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
1616#define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
1617#define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
1618#define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
1619#define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
1620#define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
1621#define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
1622#define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
1623#define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
1624#define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
1625 u8 ip_hlen;
1626 s8 cs_offset;
1627 u16 total_hlen;
1628 u16 lso_mss;
1629 u16 tcp_pseudo_csum;
1630 u16 ip_id;
1631 u32 tcp_send_seq;
1632};
1633
1634/*
1635 * The last BD in the BD memory will hold a pointer to the next BD memory
1636 */
1637struct eth_tx_next_bd {
1638 u32 addr_lo;
1639 u32 addr_hi;
1640 u8 reserved[8];
1641};
1642
1643/*
1644 * union for 3 Bd types
1645 */
1646union eth_tx_bd_types {
1647 struct eth_tx_bd reg_bd;
1648 struct eth_tx_parse_bd parse_bd;
1649 struct eth_tx_next_bd next_bd;
1650};
1651
1652/*
1653 * The eth storm context of Xstorm
1654 */
1655struct xstorm_eth_st_context {
1656 u32 tx_bd_page_base_lo;
1657 u32 tx_bd_page_base_hi;
1658#if defined(__BIG_ENDIAN)
1659 u16 tx_bd_cons;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001660 u8 statistics_data;
1661#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1662#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1663#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1664#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001665 u8 __local_tx_bd_prod;
1666#elif defined(__LITTLE_ENDIAN)
1667 u8 __local_tx_bd_prod;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001668 u8 statistics_data;
1669#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F<<0)
1670#define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
1671#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1<<7)
1672#define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001673 u16 tx_bd_cons;
1674#endif
1675 u32 db_data_addr_lo;
1676 u32 db_data_addr_hi;
1677 u32 __pkt_cons;
1678 u32 __gso_next;
1679 u32 is_eth_conn_1b;
1680 union eth_tx_bd_types __bds[13];
1681};
1682
1683/*
1684 * The eth storm context of Cstorm
1685 */
1686struct cstorm_eth_st_context {
1687#if defined(__BIG_ENDIAN)
1688 u16 __reserved0;
1689 u8 sb_index_number;
1690 u8 status_block_id;
1691#elif defined(__LITTLE_ENDIAN)
1692 u8 status_block_id;
1693 u8 sb_index_number;
1694 u16 __reserved0;
1695#endif
1696 u32 __reserved1[3];
1697};
1698
1699/*
1700 * Ethernet connection context
1701 */
1702struct eth_context {
1703 struct ustorm_eth_st_context ustorm_st_context;
1704 struct tstorm_eth_st_context tstorm_st_context;
1705 struct xstorm_eth_ag_context xstorm_ag_context;
1706 struct tstorm_eth_ag_context tstorm_ag_context;
1707 struct cstorm_eth_ag_context cstorm_ag_context;
1708 struct ustorm_eth_ag_context ustorm_ag_context;
1709 struct timers_block_context timers_context;
1710 struct xstorm_eth_st_context xstorm_st_context;
1711 struct cstorm_eth_st_context cstorm_st_context;
1712};
1713
1714
1715/*
1716 * ethernet doorbell
1717 */
1718struct eth_tx_doorbell {
1719#if defined(__BIG_ENDIAN)
1720 u16 npackets;
1721 u8 params;
1722#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
1723#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
1724#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
1725#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
1726#define ETH_TX_DOORBELL_SPARE (0x1<<7)
1727#define ETH_TX_DOORBELL_SPARE_SHIFT 7
1728 struct doorbell_hdr hdr;
1729#elif defined(__LITTLE_ENDIAN)
1730 struct doorbell_hdr hdr;
1731 u8 params;
1732#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
1733#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
1734#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
1735#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
1736#define ETH_TX_DOORBELL_SPARE (0x1<<7)
1737#define ETH_TX_DOORBELL_SPARE_SHIFT 7
1738 u16 npackets;
1739#endif
1740};
1741
1742
1743/*
1744 * ustorm status block
1745 */
1746struct ustorm_def_status_block {
1747 u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
1748 u16 status_block_index;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001749 u8 func;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001750 u8 status_block_id;
1751 u32 __flags;
1752};
1753
1754/*
1755 * cstorm status block
1756 */
1757struct cstorm_def_status_block {
1758 u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
1759 u16 status_block_index;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001760 u8 func;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001761 u8 status_block_id;
1762 u32 __flags;
1763};
1764
1765/*
1766 * xstorm status block
1767 */
1768struct xstorm_def_status_block {
1769 u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
1770 u16 status_block_index;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001771 u8 func;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001772 u8 status_block_id;
1773 u32 __flags;
1774};
1775
1776/*
1777 * tstorm status block
1778 */
1779struct tstorm_def_status_block {
1780 u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
1781 u16 status_block_index;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001782 u8 func;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001783 u8 status_block_id;
1784 u32 __flags;
1785};
1786
1787/*
1788 * host status block
1789 */
1790struct host_def_status_block {
1791 struct atten_def_status_block atten_status_block;
1792 struct ustorm_def_status_block u_def_status_block;
1793 struct cstorm_def_status_block c_def_status_block;
1794 struct xstorm_def_status_block x_def_status_block;
1795 struct tstorm_def_status_block t_def_status_block;
1796};
1797
1798
1799/*
1800 * ustorm status block
1801 */
1802struct ustorm_status_block {
1803 u16 index_values[HC_USTORM_SB_NUM_INDICES];
1804 u16 status_block_index;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001805 u8 func;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001806 u8 status_block_id;
1807 u32 __flags;
1808};
1809
1810/*
1811 * cstorm status block
1812 */
1813struct cstorm_status_block {
1814 u16 index_values[HC_CSTORM_SB_NUM_INDICES];
1815 u16 status_block_index;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001816 u8 func;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001817 u8 status_block_id;
1818 u32 __flags;
1819};
1820
1821/*
1822 * host status block
1823 */
1824struct host_status_block {
1825 struct ustorm_status_block u_status_block;
1826 struct cstorm_status_block c_status_block;
1827};
1828
1829
1830/*
1831 * The data for RSS setup ramrod
1832 */
1833struct eth_client_setup_ramrod_data {
1834 u32 client_id_5b;
1835 u8 is_rdma_1b;
1836 u8 reserved0;
1837 u16 reserved1;
1838};
1839
1840
1841/*
1842 * L2 dynamic host coalescing init parameters
1843 */
1844struct eth_dynamic_hc_config {
1845 u32 threshold[3];
1846 u8 hc_timeout[4];
1847};
1848
1849
1850/*
1851 * regular eth FP CQE parameters struct
1852 */
1853struct eth_fast_path_rx_cqe {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001854 u8 type_error_flags;
1855#define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
1856#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
1857#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
1858#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
1859#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
1860#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
1861#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
1862#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
1863#define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
1864#define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
1865#define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
1866#define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
1867#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
1868#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001869 u8 status_flags;
1870#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
1871#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
1872#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
1873#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
1874#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
1875#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
1876#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
1877#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
1878#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
1879#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
1880#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
1881#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
1882 u8 placement_offset;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001883 u8 queue_index;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001884 u32 rss_hash_result;
1885 u16 vlan_tag;
1886 u16 pkt_len;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001887 u16 len_on_bd;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001888 struct parsing_flags pars_flags;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001889 u16 sgl[8];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001890};
1891
1892
1893/*
1894 * The data for RSS setup ramrod
1895 */
1896struct eth_halt_ramrod_data {
1897 u32 client_id_5b;
1898 u32 reserved0;
1899};
1900
1901
1902/*
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001903 * The data for statistics query ramrod
1904 */
1905struct eth_query_ramrod_data {
1906#if defined(__BIG_ENDIAN)
1907 u8 reserved0;
1908 u8 collect_port_1b;
1909 u16 drv_counter;
1910#elif defined(__LITTLE_ENDIAN)
1911 u16 drv_counter;
1912 u8 collect_port_1b;
1913 u8 reserved0;
1914#endif
1915 u32 ctr_id_vector;
1916};
1917
1918
1919/*
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001920 * Place holder for ramrods protocol specific data
1921 */
1922struct ramrod_data {
1923 u32 data_lo;
1924 u32 data_hi;
1925};
1926
1927/*
1928 * union for ramrod data for ethernet protocol (CQE) (force size of 16 bits)
1929 */
1930union eth_ramrod_data {
1931 struct ramrod_data general;
1932};
1933
1934
1935/*
1936 * Rx Last BD in page (in ETH)
1937 */
1938struct eth_rx_bd_next_page {
1939 u32 addr_lo;
1940 u32 addr_hi;
1941 u8 reserved[8];
1942};
1943
1944
1945/*
1946 * Eth Rx Cqe structure- general structure for ramrods
1947 */
1948struct common_ramrod_eth_rx_cqe {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001949 u8 ramrod_type;
1950#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
1951#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
1952#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x7F<<1)
1953#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 1
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001954 u8 conn_type_3b;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001955 u16 reserved1;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001956 u32 conn_and_cmd_data;
1957#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
1958#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
1959#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
1960#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
1961 struct ramrod_data protocol_data;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001962 u32 reserved2[4];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001963};
1964
1965/*
1966 * Rx Last CQE in page (in ETH)
1967 */
1968struct eth_rx_cqe_next_page {
1969 u32 addr_lo;
1970 u32 addr_hi;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07001971 u32 reserved[6];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02001972};
1973
1974/*
1975 * union for all eth rx cqe types (fix their sizes)
1976 */
1977union eth_rx_cqe {
1978 struct eth_fast_path_rx_cqe fast_path_cqe;
1979 struct common_ramrod_eth_rx_cqe ramrod_cqe;
1980 struct eth_rx_cqe_next_page next_page_cqe;
1981};
1982
1983
1984/*
1985 * common data for all protocols
1986 */
1987struct spe_hdr {
1988 u32 conn_and_cmd_data;
1989#define SPE_HDR_CID (0xFFFFFF<<0)
1990#define SPE_HDR_CID_SHIFT 0
1991#define SPE_HDR_CMD_ID (0xFF<<24)
1992#define SPE_HDR_CMD_ID_SHIFT 24
1993 u16 type;
1994#define SPE_HDR_CONN_TYPE (0xFF<<0)
1995#define SPE_HDR_CONN_TYPE_SHIFT 0
1996#define SPE_HDR_COMMON_RAMROD (0xFF<<8)
1997#define SPE_HDR_COMMON_RAMROD_SHIFT 8
1998 u16 reserved;
1999};
2000
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002001/*
2002 * ethernet slow path element
2003 */
2004union eth_specific_data {
2005 u8 protocol_data[8];
2006 struct regpair mac_config_addr;
2007 struct eth_client_setup_ramrod_data client_setup_ramrod_data;
2008 struct eth_halt_ramrod_data halt_ramrod_data;
2009 struct regpair leading_cqe_addr;
2010 struct regpair update_data_addr;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002011 struct eth_query_ramrod_data query_ramrod_data;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002012};
2013
2014/*
2015 * ethernet slow path element
2016 */
2017struct eth_spe {
2018 struct spe_hdr hdr;
2019 union eth_specific_data data;
2020};
2021
2022
2023/*
2024 * doorbell data in host memory
2025 */
2026struct eth_tx_db_data {
2027 u32 packets_prod;
2028 u16 bds_prod;
2029 u16 reserved;
2030};
2031
2032
2033/*
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002034 * Common configuration parameters per function in Tstorm
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002035 */
2036struct tstorm_eth_function_common_config {
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002037#if defined(__BIG_ENDIAN)
2038 u8 leading_client_id;
2039 u8 rss_result_mask;
2040 u16 config_flags;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002041#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2042#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2043#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2044#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2045#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2046#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2047#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2048#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2049#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4)
2050#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
2051#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
2052#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002053#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6)
2054#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6
2055#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7)
2056#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002057#elif defined(__LITTLE_ENDIAN)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002058 u16 config_flags;
2059#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2060#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2061#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2062#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2063#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2064#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2065#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2066#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2067#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE (0x1<<4)
2068#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
2069#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
2070#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
2071#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1<<6)
2072#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 6
2073#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1FF<<7)
2074#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 7
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002075 u8 rss_result_mask;
2076 u8 leading_client_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002077#endif
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002078 u16 vlan_id[2];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002079};
2080
2081/*
2082 * parameters for eth update ramrod
2083 */
2084struct eth_update_ramrod_data {
2085 struct tstorm_eth_function_common_config func_config;
2086 u8 indirectionTable[128];
2087};
2088
2089
2090/*
2091 * MAC filtering configuration command header
2092 */
2093struct mac_configuration_hdr {
2094 u8 length_6b;
2095 u8 offset;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002096 u16 client_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002097 u32 reserved1;
2098};
2099
2100/*
2101 * MAC address in list for ramrod
2102 */
2103struct tstorm_cam_entry {
2104 u16 lsb_mac_addr;
2105 u16 middle_mac_addr;
2106 u16 msb_mac_addr;
2107 u16 flags;
2108#define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
2109#define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
2110#define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
2111#define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
2112#define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
2113#define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
2114};
2115
2116/*
2117 * MAC filtering: CAM target table entry
2118 */
2119struct tstorm_cam_target_table_entry {
2120 u8 flags;
2121#define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
2122#define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
2123#define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
2124#define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
2125#define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
2126#define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
2127#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
2128#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
2129#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
2130#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
2131 u8 client_id;
2132 u16 vlan_id;
2133};
2134
2135/*
2136 * MAC address in list for ramrod
2137 */
2138struct mac_configuration_entry {
2139 struct tstorm_cam_entry cam_entry;
2140 struct tstorm_cam_target_table_entry target_table_entry;
2141};
2142
2143/*
2144 * MAC filtering configuration command
2145 */
2146struct mac_configuration_cmd {
2147 struct mac_configuration_hdr hdr;
2148 struct mac_configuration_entry config_table[64];
2149};
2150
2151
2152/*
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002153 * MAC address in list for ramrod
2154 */
2155struct mac_configuration_entry_e1h {
2156 u16 lsb_mac_addr;
2157 u16 middle_mac_addr;
2158 u16 msb_mac_addr;
2159 u16 vlan_id;
2160 u16 e1hov_id;
2161 u8 client_id;
2162 u8 flags;
2163#define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1<<0)
2164#define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
2165#define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1<<1)
2166#define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
2167#define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1<<2)
2168#define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
2169#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0 (0x1F<<3)
2170#define MAC_CONFIGURATION_ENTRY_E1H_RESERVED0_SHIFT 3
2171};
2172
2173/*
2174 * MAC filtering configuration command
2175 */
2176struct mac_configuration_cmd_e1h {
2177 struct mac_configuration_hdr hdr;
2178 struct mac_configuration_entry_e1h config_table[32];
2179};
2180
2181
2182/*
2183 * approximate-match multicast filtering for E1H per function in Tstorm
2184 */
2185struct tstorm_eth_approximate_match_multicast_filtering {
2186 u32 mcast_add_hash_bit_array[8];
2187};
2188
2189
2190/*
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002191 * Configuration parameters per client in Tstorm
2192 */
2193struct tstorm_eth_client_config {
2194#if defined(__BIG_ENDIAN)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002195 u8 max_sges_for_packet;
2196 u8 statistics_counter_id;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002197 u16 mtu;
2198#elif defined(__LITTLE_ENDIAN)
2199 u16 mtu;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002200 u8 statistics_counter_id;
2201 u8 max_sges_for_packet;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002202#endif
2203#if defined(__BIG_ENDIAN)
2204 u16 drop_flags;
2205#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2206#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2207#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2208#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002209#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2210#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2211#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2212#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2213#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2214#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002215 u16 config_flags;
2216#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
2217#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
2218#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
2219#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002220#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2)
2221#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2
2222#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3)
2223#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002224#elif defined(__LITTLE_ENDIAN)
2225 u16 config_flags;
2226#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
2227#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
2228#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
2229#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002230#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING (0x1<<2)
2231#define TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING_SHIFT 2
2232#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x1FFF<<3)
2233#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 3
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002234 u16 drop_flags;
2235#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
2236#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2237#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
2238#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002239#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<2)
2240#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2241#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<3)
2242#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2243#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0xFFF<<4)
2244#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002245#endif
2246};
2247
2248
2249/*
2250 * MAC filtering configuration parameters per port in Tstorm
2251 */
2252struct tstorm_eth_mac_filter_config {
2253 u32 ucast_drop_all;
2254 u32 ucast_accept_all;
2255 u32 mcast_drop_all;
2256 u32 mcast_accept_all;
2257 u32 bcast_drop_all;
2258 u32 bcast_accept_all;
2259 u32 strict_vlan;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002260 u32 vlan_filter[2];
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002261 u32 reserved;
2262};
2263
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002264
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002265/*
2266 * Three RX producers for ETH
2267 */
2268struct tstorm_eth_rx_producers {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002269#if defined(__BIG_ENDIAN)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002270 u16 bd_prod;
2271 u16 cqe_prod;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002272#elif defined(__LITTLE_ENDIAN)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002273 u16 cqe_prod;
2274 u16 bd_prod;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002275#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002276#if defined(__BIG_ENDIAN)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002277 u16 reserved;
2278 u16 sge_prod;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002279#elif defined(__LITTLE_ENDIAN)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002280 u16 sge_prod;
2281 u16 reserved;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002282#endif
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002283};
2284
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002285
2286/*
2287 * common flag to indicate existance of TPA.
2288 */
2289struct tstorm_eth_tpa_exist {
2290#if defined(__BIG_ENDIAN)
2291 u16 reserved1;
2292 u8 reserved0;
2293 u8 tpa_exist;
2294#elif defined(__LITTLE_ENDIAN)
2295 u8 tpa_exist;
2296 u8 reserved0;
2297 u16 reserved1;
2298#endif
2299 u32 reserved2;
2300};
2301
2302
2303/*
2304 * per-port SAFC demo variables
2305 */
2306struct cmng_flags_per_port {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002307 u8 con_number[NUM_OF_PROTOCOLS];
2308#if defined(__BIG_ENDIAN)
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002309 u8 fairness_enable;
2310 u8 rate_shaping_enable;
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002311 u8 cmng_protocol_enable;
2312 u8 cmng_vn_enable;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002313#elif defined(__LITTLE_ENDIAN)
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002314 u8 cmng_vn_enable;
2315 u8 cmng_protocol_enable;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002316 u8 rate_shaping_enable;
2317 u8 fairness_enable;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002318#endif
2319};
2320
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002321
2322/*
2323 * per-port rate shaping variables
2324 */
2325struct rate_shaping_vars_per_port {
2326 u32 rs_periodic_timeout;
2327 u32 rs_threshold;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002328};
2329
2330
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002331/*
2332 * per-port fairness variables
2333 */
2334struct fairness_vars_per_port {
2335 u32 upper_bound;
2336 u32 fair_threshold;
2337 u32 fairness_timeout;
2338};
2339
2340
2341/*
2342 * per-port SAFC variables
2343 */
2344struct safc_struct_per_port {
2345#if defined(__BIG_ENDIAN)
2346 u16 __reserved0;
2347 u8 cur_cos_types;
2348 u8 safc_timeout_usec;
2349#elif defined(__LITTLE_ENDIAN)
2350 u8 safc_timeout_usec;
2351 u8 cur_cos_types;
2352 u16 __reserved0;
2353#endif
2354 u8 cos_to_protocol[MAX_COS_NUMBER];
2355};
2356
2357
2358/*
2359 * Per-port congestion management variables
2360 */
2361struct cmng_struct_per_port {
2362 struct rate_shaping_vars_per_port rs_vars;
2363 struct fairness_vars_per_port fair_vars;
2364 struct safc_struct_per_port safc_vars;
2365 struct cmng_flags_per_port flags;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002366};
2367
2368
2369/*
2370 * Common statistics collected by the Xstorm (per port)
2371 */
2372struct xstorm_common_stats {
2373 struct regpair total_sent_bytes;
2374 u32 total_sent_pkts;
2375 u32 unicast_pkts_sent;
2376 struct regpair unicast_bytes_sent;
2377 struct regpair multicast_bytes_sent;
2378 u32 multicast_pkts_sent;
2379 u32 broadcast_pkts_sent;
2380 struct regpair broadcast_bytes_sent;
2381 struct regpair done;
2382};
2383
2384/*
2385 * Protocol-common statistics collected by the Tstorm (per client)
2386 */
2387struct tstorm_per_client_stats {
2388 struct regpair total_rcv_bytes;
2389 struct regpair rcv_unicast_bytes;
2390 struct regpair rcv_broadcast_bytes;
2391 struct regpair rcv_multicast_bytes;
2392 struct regpair rcv_error_bytes;
2393 u32 checksum_discard;
2394 u32 packets_too_big_discard;
2395 u32 total_rcv_pkts;
2396 u32 rcv_unicast_pkts;
2397 u32 rcv_broadcast_pkts;
2398 u32 rcv_multicast_pkts;
2399 u32 no_buff_discard;
2400 u32 ttl0_discard;
2401 u32 mac_discard;
2402 u32 reserved;
2403};
2404
2405/*
2406 * Protocol-common statistics collected by the Tstorm (per port)
2407 */
2408struct tstorm_common_stats {
2409 struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
2410 u32 mac_filter_discard;
2411 u32 xxoverflow_discard;
2412 u32 brb_truncate_discard;
2413 u32 reserved;
2414 struct regpair done;
2415};
2416
2417/*
2418 * Eth statistics query sturcture for the eth_stats_quesry ramrod
2419 */
2420struct eth_stats_query {
2421 struct xstorm_common_stats xstorm_common;
2422 struct tstorm_common_stats tstorm_common;
2423};
2424
2425
2426/*
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002427 * per-vnic fairness variables
2428 */
2429struct fairness_vars_per_vn {
2430 u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
2431 u32 vn_credit_delta;
2432 u32 __reserved0;
2433};
2434
2435
2436/*
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002437 * FW version stored in the Xstorm RAM
2438 */
2439struct fw_version {
2440#if defined(__BIG_ENDIAN)
2441 u16 patch;
2442 u8 primary;
2443 u8 client;
2444#elif defined(__LITTLE_ENDIAN)
2445 u8 client;
2446 u8 primary;
2447 u16 patch;
2448#endif
2449 u32 flags;
2450#define FW_VERSION_OPTIMIZED (0x1<<0)
2451#define FW_VERSION_OPTIMIZED_SHIFT 0
2452#define FW_VERSION_BIG_ENDIEN (0x1<<1)
2453#define FW_VERSION_BIG_ENDIEN_SHIFT 1
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002454#define FW_VERSION_CHIP_VERSION (0x3<<2)
2455#define FW_VERSION_CHIP_VERSION_SHIFT 2
2456#define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
2457#define __FW_VERSION_RESERVED_SHIFT 4
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002458};
2459
2460
2461/*
2462 * FW version stored in first line of pram
2463 */
2464struct pram_fw_version {
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002465 u8 client;
2466 u8 primary;
2467 u16 patch;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002468 u8 flags;
2469#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
2470#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
2471#define PRAM_FW_VERSION_STORM_ID (0x3<<1)
2472#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
2473#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
2474#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
Eilon Greenstein34f80b02008-06-23 20:33:01 -07002475#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
2476#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
2477#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
2478#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
2479};
2480
2481
2482/*
2483 * a single rate shaping counter. can be used as protocol or vnic counter
2484 */
2485struct rate_shaping_counter {
2486 u32 quota;
2487#if defined(__BIG_ENDIAN)
2488 u16 __reserved0;
2489 u16 rate;
2490#elif defined(__LITTLE_ENDIAN)
2491 u16 rate;
2492 u16 __reserved0;
2493#endif
2494};
2495
2496
2497/*
2498 * per-vnic rate shaping variables
2499 */
2500struct rate_shaping_vars_per_vn {
2501 struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
2502 struct rate_shaping_counter vn_counter;
Eliezer Tamira2fbb9e2007-11-15 20:09:02 +02002503};
2504
2505
2506/*
2507 * The send queue element
2508 */
2509struct slow_path_element {
2510 struct spe_hdr hdr;
2511 u8 protocol_data[8];
2512};
2513
2514
2515/*
2516 * eth/toe flags that indicate if to query
2517 */
2518struct stats_indication_flags {
2519 u32 collect_eth;
2520 u32 collect_toe;
2521};
2522
2523